1 /* $OpenBSD: vpci.c,v 1.12 2012/10/29 23:25:48 kettenis Exp $ */ 2 /* 3 * Copyright (c) 2008 Mark Kettenis <kettenis@openbsd.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/param.h> 19 #include <sys/device.h> 20 #include <sys/errno.h> 21 #include <sys/malloc.h> 22 #include <sys/systm.h> 23 24 #include <uvm/uvm_extern.h> 25 26 #define _SPARC_BUS_DMA_PRIVATE 27 #include <machine/bus.h> 28 #include <machine/autoconf.h> 29 #include <machine/hypervisor.h> 30 #include <machine/openfirm.h> 31 32 #include <dev/pci/pcivar.h> 33 #include <dev/pci/pcireg.h> 34 35 #include <sparc64/dev/viommuvar.h> 36 #include <sparc64/dev/msivar.h> 37 38 extern struct sparc_pci_chipset _sparc_pci_chipset; 39 40 struct vpci_msi_msg { 41 uint32_t mm_version; 42 uint8_t mm_reserved[3]; 43 uint8_t mm_type; 44 uint64_t mm_sysino; 45 uint64_t mm_reserved1; 46 uint64_t mm_stick; 47 uint16_t mm_reserved2[3]; 48 uint16_t mm_reqid; 49 uint64_t mm_addr; 50 uint64_t mm_data; 51 uint64_t mm_reserved3; 52 }; 53 54 struct vpci_range { 55 u_int32_t cspace; 56 u_int32_t child_hi; 57 u_int32_t child_lo; 58 u_int32_t phys_hi; 59 u_int32_t phys_lo; 60 u_int32_t size_hi; 61 u_int32_t size_lo; 62 }; 63 64 struct vpci_pbm { 65 struct vpci_softc *vp_sc; 66 uint64_t vp_devhandle; 67 68 struct vpci_range *vp_range; 69 pci_chipset_tag_t vp_pc; 70 int vp_nrange; 71 72 bus_space_tag_t vp_memt; 73 bus_space_tag_t vp_iot; 74 bus_dma_tag_t vp_dmat; 75 struct iommu_state vp_is; 76 77 struct msi_eq *vp_meq; 78 bus_addr_t vp_msiaddr; 79 int vp_msinum; 80 struct intrhand **vp_msi; 81 82 int vp_flags; 83 }; 84 85 struct vpci_softc { 86 struct device sc_dv; 87 bus_dma_tag_t sc_dmat; 88 bus_space_tag_t sc_bust; 89 int sc_node; 90 }; 91 92 int vpci_match(struct device *, void *, void *); 93 void vpci_attach(struct device *, struct device *, void *); 94 void vpci_init_iommu(struct vpci_softc *, struct vpci_pbm *); 95 void vpci_init_msi(struct vpci_softc *, struct vpci_pbm *); 96 int vpci_print(void *, const char *); 97 98 pci_chipset_tag_t vpci_alloc_chipset(struct vpci_pbm *, int, 99 pci_chipset_tag_t); 100 bus_space_tag_t vpci_alloc_mem_tag(struct vpci_pbm *); 101 bus_space_tag_t vpci_alloc_io_tag(struct vpci_pbm *); 102 bus_space_tag_t vpci_alloc_bus_tag(struct vpci_pbm *, const char *, 103 int, int, int); 104 bus_dma_tag_t vpci_alloc_dma_tag(struct vpci_pbm *); 105 106 int vpci_conf_size(pci_chipset_tag_t, pcitag_t); 107 pcireg_t vpci_conf_read(pci_chipset_tag_t, pcitag_t, int); 108 void vpci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 109 110 int vpci_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 111 int vpci_bus_map(bus_space_tag_t, bus_space_tag_t, bus_addr_t, 112 bus_size_t, int, bus_space_handle_t *); 113 paddr_t vpci_bus_mmap(bus_space_tag_t, bus_space_tag_t, bus_addr_t, off_t, 114 int, int); 115 void *vpci_intr_establish(bus_space_tag_t, bus_space_tag_t, int, int, int, 116 int (*)(void *), void *, const char *); 117 void vpci_intr_ack(struct intrhand *); 118 void vpci_msi_ack(struct intrhand *); 119 120 int vpci_msi_eq_intr(void *); 121 122 int vpci_dmamap_create(bus_dma_tag_t, bus_dma_tag_t, bus_size_t, int, 123 bus_size_t, bus_size_t, int, bus_dmamap_t *); 124 void vpci_dmamap_destroy(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 125 int vpci_dmamap_load(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 126 void *, bus_size_t, struct proc *, int); 127 void vpci_dmamap_unload(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 128 int vpci_dmamem_alloc(bus_dma_tag_t, bus_dma_tag_t, bus_size_t, 129 bus_size_t, bus_size_t, bus_dma_segment_t *, int, int *, int); 130 int vpci_dmamem_map(bus_dma_tag_t, bus_dma_tag_t, bus_dma_segment_t *, 131 int, size_t, caddr_t *, int); 132 void vpci_dmamem_unmap(bus_dma_tag_t, bus_dma_tag_t, caddr_t, size_t); 133 134 int 135 vpci_match(struct device *parent, void *match, void *aux) 136 { 137 struct mainbus_attach_args *ma = aux; 138 char compat[32]; 139 140 if (strcmp(ma->ma_name, "pci") != 0) 141 return (0); 142 143 if (OF_getprop(ma->ma_node, "compatible", compat, sizeof(compat)) == -1) 144 return (0); 145 146 if (strcmp(compat, "SUNW,sun4v-pci") == 0) 147 return (1); 148 149 return (0); 150 } 151 152 void 153 vpci_attach(struct device *parent, struct device *self, void *aux) 154 { 155 struct vpci_softc *sc = (struct vpci_softc *)self; 156 struct mainbus_attach_args *ma = aux; 157 struct pcibus_attach_args pba; 158 struct vpci_pbm *pbm; 159 int *busranges = NULL, nranges; 160 161 sc->sc_dmat = ma->ma_dmatag; 162 sc->sc_bust = ma->ma_bustag; 163 sc->sc_node = ma->ma_node; 164 165 pbm = malloc(sizeof(*pbm), M_DEVBUF, M_NOWAIT | M_ZERO); 166 if (pbm == NULL) 167 panic("vpci: can't alloc vpci pbm"); 168 169 pbm->vp_sc = sc; 170 pbm->vp_devhandle = (ma->ma_reg[0].ur_paddr >> 32) & 0x0fffffff; 171 172 if (getprop(ma->ma_node, "ranges", sizeof(struct vpci_range), 173 &pbm->vp_nrange, (void **)&pbm->vp_range)) 174 panic("vpci: can't get ranges"); 175 176 if (getprop(ma->ma_node, "bus-range", sizeof(int), &nranges, 177 (void **)&busranges)) 178 panic("vpci: can't get bus-range"); 179 180 printf(": bus %d to %d, ", busranges[0], busranges[1]); 181 182 pbm->vp_memt = vpci_alloc_mem_tag(pbm); 183 pbm->vp_iot = vpci_alloc_io_tag(pbm); 184 pbm->vp_dmat = vpci_alloc_dma_tag(pbm); 185 186 pbm->vp_pc = vpci_alloc_chipset(pbm, ma->ma_node, &_sparc_pci_chipset); 187 pbm->vp_pc->bustag = pbm->vp_memt; 188 189 vpci_init_iommu(sc, pbm); 190 vpci_init_msi(sc, pbm); 191 192 bzero(&pba, sizeof(pba)); 193 pba.pba_busname = "pci"; 194 pba.pba_domain = pci_ndomains++; 195 pba.pba_bus = busranges[0]; 196 pba.pba_pc = pbm->vp_pc; 197 pba.pba_flags = pbm->vp_flags; 198 pba.pba_dmat = pbm->vp_dmat; 199 pba.pba_memt = pbm->vp_memt; 200 pba.pba_iot = pbm->vp_iot; 201 pba.pba_pc->conf_size = vpci_conf_size; 202 pba.pba_pc->conf_read = vpci_conf_read; 203 pba.pba_pc->conf_write = vpci_conf_write; 204 pba.pba_pc->intr_map = vpci_intr_map; 205 206 free(busranges, M_DEVBUF); 207 208 config_found(&sc->sc_dv, &pba, vpci_print); 209 } 210 211 void 212 vpci_init_iommu(struct vpci_softc *sc, struct vpci_pbm *pbm) 213 { 214 struct iommu_state *is = &pbm->vp_is; 215 int tsbsize = 8; 216 u_int32_t iobase = 0x80000000; 217 char *name; 218 219 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 220 if (name == NULL) 221 panic("couldn't malloc iommu name"); 222 snprintf(name, 32, "%s dvma", sc->sc_dv.dv_xname); 223 224 viommu_init(name, is, tsbsize, iobase); 225 is->is_devhandle = pbm->vp_devhandle; 226 } 227 228 void 229 vpci_init_msi(struct vpci_softc *sc, struct vpci_pbm *pbm) 230 { 231 u_int32_t msi_addr_range[3]; 232 u_int32_t msi_eq_devino[3] = { 0, 36, 24 }; 233 uint64_t sysino; 234 int msis, msi_eq_size; 235 int64_t err; 236 237 if (OF_getprop(sc->sc_node, "msi-address-ranges", 238 msi_addr_range, sizeof(msi_addr_range)) <= 0) 239 return; 240 pbm->vp_msiaddr = msi_addr_range[1]; 241 pbm->vp_msiaddr |= ((bus_addr_t)msi_addr_range[0]) << 32; 242 243 msis = getpropint(sc->sc_node, "#msi", 256); 244 pbm->vp_msi = malloc(msis * sizeof(*pbm->vp_msi), 245 M_DEVBUF, M_NOWAIT | M_ZERO); 246 if (pbm->vp_msi == NULL) 247 return; 248 249 msi_eq_size = getpropint(sc->sc_node, "msi-eq-size", 256); 250 pbm->vp_meq = msi_eq_alloc(sc->sc_dmat, msi_eq_size); 251 if (pbm->vp_meq == NULL) 252 goto free_table; 253 254 err = hv_pci_msiq_conf(pbm->vp_devhandle, 0, 255 pbm->vp_meq->meq_map->dm_segs[0].ds_addr, 256 pbm->vp_meq->meq_nentries); 257 if (err != H_EOK) 258 goto free_queue; 259 260 OF_getprop(sc->sc_node, "msi-eq-to-devino", 261 msi_eq_devino, sizeof(msi_eq_devino)); 262 err = hv_intr_devino_to_sysino(pbm->vp_devhandle, 263 msi_eq_devino[2], &sysino); 264 if (err != H_EOK) 265 goto disable_queue; 266 267 if (vpci_intr_establish(sc->sc_bust, sc->sc_bust, sysino, 268 IPL_HIGH, 0, vpci_msi_eq_intr, pbm, sc->sc_dv.dv_xname) == NULL) 269 goto disable_queue; 270 271 err = hv_pci_msiq_setvalid(pbm->vp_devhandle, 0, PCI_MSIQ_VALID); 272 if (err != H_EOK) 273 panic("vpci: can't enable msi eq"); 274 275 pbm->vp_flags |= PCI_FLAGS_MSI_ENABLED; 276 return; 277 278 disable_queue: 279 hv_pci_msiq_conf(pbm->vp_devhandle, 0, 0, 0); 280 free_queue: 281 msi_eq_free(sc->sc_dmat, pbm->vp_meq); 282 free_table: 283 free(pbm->vp_msi, M_DEVBUF); 284 } 285 286 int 287 vpci_print(void *aux, const char *p) 288 { 289 if (p == NULL) 290 return (UNCONF); 291 return (QUIET); 292 } 293 294 int 295 vpci_conf_size(pci_chipset_tag_t pc, pcitag_t tag) 296 { 297 return PCIE_CONFIG_SPACE_SIZE; 298 } 299 300 pcireg_t 301 vpci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 302 { 303 struct vpci_pbm *pbm = pc->cookie; 304 uint64_t error_flag, data; 305 306 hv_pci_config_get(pbm->vp_devhandle, PCITAG_OFFSET(tag), reg, 4, 307 &error_flag, &data); 308 309 return (error_flag ? (pcireg_t)~0 : data); 310 } 311 312 void 313 vpci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 314 { 315 struct vpci_pbm *pbm = pc->cookie; 316 uint64_t error_flag; 317 318 hv_pci_config_put(pbm->vp_devhandle, PCITAG_OFFSET(tag), reg, 4, 319 data, &error_flag); 320 } 321 322 /* 323 * Bus-specific interrupt mapping 324 */ 325 int 326 vpci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 327 { 328 struct vpci_pbm *pbm = pa->pa_pc->cookie; 329 uint64_t devhandle = pbm->vp_devhandle; 330 uint64_t devino = INTINO(*ihp); 331 uint64_t sysino; 332 int err; 333 334 if (*ihp != (pci_intr_handle_t)-1) { 335 err = hv_intr_devino_to_sysino(devhandle, devino, &sysino); 336 if (err != H_EOK) 337 return (-1); 338 339 KASSERT(sysino == INTVEC(sysino)); 340 *ihp = sysino; 341 return (0); 342 } 343 344 return (-1); 345 } 346 347 bus_space_tag_t 348 vpci_alloc_mem_tag(struct vpci_pbm *pp) 349 { 350 return (vpci_alloc_bus_tag(pp, "mem", 351 0x02, /* 32-bit mem space (where's the #define???) */ 352 ASI_PRIMARY, ASI_PRIMARY_LITTLE)); 353 } 354 355 bus_space_tag_t 356 vpci_alloc_io_tag(struct vpci_pbm *pp) 357 { 358 return (vpci_alloc_bus_tag(pp, "io", 359 0x01, /* IO space (where's the #define???) */ 360 ASI_PRIMARY, ASI_PRIMARY_LITTLE)); 361 } 362 363 bus_space_tag_t 364 vpci_alloc_bus_tag(struct vpci_pbm *pbm, const char *name, int ss, 365 int asi, int sasi) 366 { 367 struct vpci_softc *sc = pbm->vp_sc; 368 struct sparc_bus_space_tag *bt; 369 370 bt = malloc(sizeof(*bt), M_DEVBUF, M_NOWAIT | M_ZERO); 371 if (bt == NULL) 372 panic("vpci: could not allocate bus tag"); 373 374 snprintf(bt->name, sizeof(bt->name), "%s-pbm_%s(%d/%2.2x)", 375 sc->sc_dv.dv_xname, name, ss, asi); 376 377 bt->cookie = pbm; 378 bt->parent = sc->sc_bust; 379 bt->default_type = ss; 380 bt->asi = asi; 381 bt->sasi = sasi; 382 bt->sparc_bus_map = vpci_bus_map; 383 bt->sparc_bus_mmap = vpci_bus_mmap; 384 bt->sparc_intr_establish = vpci_intr_establish; 385 return (bt); 386 } 387 388 bus_dma_tag_t 389 vpci_alloc_dma_tag(struct vpci_pbm *pbm) 390 { 391 struct vpci_softc *sc = pbm->vp_sc; 392 bus_dma_tag_t dt, pdt = sc->sc_dmat; 393 394 dt = malloc(sizeof(*dt), M_DEVBUF, M_NOWAIT | M_ZERO); 395 if (dt == NULL) 396 panic("vpci: could not alloc dma tag"); 397 398 dt->_cookie = pbm; 399 dt->_parent = pdt; 400 dt->_dmamap_create = vpci_dmamap_create; 401 dt->_dmamap_destroy = viommu_dvmamap_destroy; 402 dt->_dmamap_load = viommu_dvmamap_load; 403 dt->_dmamap_load_raw = viommu_dvmamap_load_raw; 404 dt->_dmamap_unload = viommu_dvmamap_unload; 405 dt->_dmamap_sync = viommu_dvmamap_sync; 406 dt->_dmamem_alloc = viommu_dvmamem_alloc; 407 dt->_dmamem_free = viommu_dvmamem_free; 408 return (dt); 409 } 410 411 pci_chipset_tag_t 412 vpci_alloc_chipset(struct vpci_pbm *pbm, int node, pci_chipset_tag_t pc) 413 { 414 pci_chipset_tag_t npc; 415 416 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 417 if (npc == NULL) 418 panic("vpci: could not allocate pci_chipset_tag_t"); 419 memcpy(npc, pc, sizeof *pc); 420 npc->cookie = pbm; 421 npc->rootnode = node; 422 return (npc); 423 } 424 425 #define BUS_DMA_FIND_PARENT(t, fn) \ 426 if (t->_parent == NULL) \ 427 panic("null bus_dma parent (" #fn ")"); \ 428 for (t = t->_parent; t->fn == NULL; t = t->_parent) \ 429 if (t->_parent == NULL) \ 430 panic("no bus_dma " #fn " located"); 431 432 int 433 vpci_dmamap_create(bus_dma_tag_t t, bus_dma_tag_t t0, bus_size_t size, 434 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 435 bus_dmamap_t *dmamap) 436 { 437 struct vpci_pbm *vp = t->_cookie; 438 439 return (viommu_dvmamap_create(t, t0, &vp->vp_is, size, nsegments, 440 maxsegsz, boundary, flags, dmamap)); 441 } 442 443 int 444 vpci_bus_map(bus_space_tag_t t, bus_space_tag_t t0, bus_addr_t offset, 445 bus_size_t size, int flags, bus_space_handle_t *hp) 446 { 447 struct vpci_pbm *pbm = t->cookie; 448 int i, ss = t->default_type; 449 450 if (t->parent == 0 || t->parent->sparc_bus_map == 0) 451 panic("vpci_bus_map: invalid parent"); 452 453 if (flags & BUS_SPACE_MAP_PROMADDRESS) { 454 return ((*t->parent->sparc_bus_map) 455 (t, t0, offset, size, flags, hp)); 456 } 457 458 for (i = 0; i < pbm->vp_nrange; i++) { 459 bus_addr_t paddr; 460 461 if (((pbm->vp_range[i].cspace >> 24) & 0x03) != ss) 462 continue; 463 464 paddr = pbm->vp_range[i].phys_lo + offset; 465 paddr |= ((bus_addr_t)pbm->vp_range[i].phys_hi) << 32; 466 return ((*t->parent->sparc_bus_map) 467 (t, t0, paddr, size, flags, hp)); 468 } 469 470 return (EINVAL); 471 } 472 473 paddr_t 474 vpci_bus_mmap(bus_space_tag_t t, bus_space_tag_t t0, bus_addr_t paddr, 475 off_t off, int prot, int flags) 476 { 477 bus_addr_t offset = paddr; 478 struct vpci_pbm *pbm = t->cookie; 479 int i, ss = t->default_type; 480 481 if (t->parent == 0 || t->parent->sparc_bus_mmap == 0) 482 panic("vpci_bus_mmap: invalid parent"); 483 484 for (i = 0; i < pbm->vp_nrange; i++) { 485 bus_addr_t paddr; 486 487 if (((pbm->vp_range[i].cspace >> 24) & 0x03) != ss) 488 continue; 489 490 paddr = pbm->vp_range[i].phys_lo + offset; 491 paddr |= ((bus_addr_t)pbm->vp_range[i].phys_hi) << 32; 492 return ((*t->parent->sparc_bus_mmap) 493 (t, t0, paddr, off, prot, flags)); 494 } 495 496 return (-1); 497 } 498 499 void * 500 vpci_intr_establish(bus_space_tag_t t, bus_space_tag_t t0, int ihandle, 501 int level, int flags, int (*handler)(void *), void *arg, const char *what) 502 { 503 struct vpci_pbm *pbm = t->cookie; 504 uint64_t sysino = INTVEC(ihandle); 505 struct intrhand *ih; 506 int err; 507 508 ih = bus_intr_allocate(t0, handler, arg, ihandle, level, 509 NULL, NULL, what); 510 if (ih == NULL) 511 return (NULL); 512 513 if (ihandle & PCI_INTR_MSI) { 514 pci_chipset_tag_t pc = pbm->vp_pc; 515 pcitag_t tag = ihandle & ~PCI_INTR_MSI; 516 int msinum = pbm->vp_msinum++; 517 518 if (ih->ih_name) 519 evcount_attach(&ih->ih_count, ih->ih_name, NULL); 520 else 521 evcount_attach(&ih->ih_count, "unknown", NULL); 522 523 ih->ih_ack = vpci_msi_ack; 524 525 pbm->vp_msi[msinum] = ih; 526 ih->ih_number = msinum; 527 528 pci_msi_enable(pc, tag, pbm->vp_msiaddr, msinum); 529 530 err = hv_pci_msi_setmsiq(pbm->vp_devhandle, msinum, 0, 0); 531 if (err != H_EOK) { 532 printf("pci_msi_setmsiq: err %ld\n", err); 533 return (NULL); 534 } 535 536 err = hv_pci_msi_setvalid(pbm->vp_devhandle, msinum, PCI_MSI_VALID); 537 if (err != H_EOK) { 538 printf("pci_msi_setvalid: err %ld\n", err); 539 return (NULL); 540 } 541 542 return (ih); 543 } 544 545 intr_establish(ih->ih_pil, ih); 546 ih->ih_ack = vpci_intr_ack; 547 548 err = hv_intr_settarget(sysino, cpus->ci_upaid); 549 if (err != H_EOK) 550 return (NULL); 551 552 /* Clear pending interrupts. */ 553 err = hv_intr_setstate(sysino, INTR_IDLE); 554 if (err != H_EOK) 555 return (NULL); 556 557 err = hv_intr_setenabled(sysino, INTR_ENABLED); 558 if (err != H_EOK) 559 return (NULL); 560 561 return (ih); 562 } 563 564 void 565 vpci_intr_ack(struct intrhand *ih) 566 { 567 hv_intr_setstate(ih->ih_number, INTR_IDLE); 568 } 569 570 void 571 vpci_msi_ack(struct intrhand *ih) 572 { 573 } 574 575 int 576 vpci_msi_eq_intr(void *arg) 577 { 578 struct vpci_pbm *pbm = arg; 579 struct msi_eq *meq = pbm->vp_meq; 580 struct vpci_msi_msg *msg; 581 uint64_t head, tail; 582 struct intrhand *ih; 583 int msinum; 584 int err; 585 586 err = hv_pci_msiq_gethead(pbm->vp_devhandle, 0, &head); 587 if (err != H_EOK) 588 printf("%s: hv_pci_msiq_gethead: %d\n", __func__, err); 589 590 err = hv_pci_msiq_gettail(pbm->vp_devhandle, 0, &tail); 591 if (err != H_EOK) 592 printf("%s: hv_pci_msiq_gettail: %d\n", __func__, err); 593 594 if (head == tail) 595 return (0); 596 597 while (head != tail) { 598 msg = (struct vpci_msi_msg *)(meq->meq_va + head); 599 600 if (msg->mm_type == 0) 601 break; 602 msg->mm_type = 0; 603 604 msinum = msg->mm_data; 605 ih = pbm->vp_msi[msinum]; 606 err = hv_pci_msi_setstate(pbm->vp_devhandle, 607 msinum, PCI_MSISTATE_IDLE); 608 if (err != H_EOK) 609 printf("%s: hv_pci_msiq_setstate: %d\n", __func__, err); 610 611 send_softint(-1, ih->ih_pil, ih); 612 613 head += sizeof(struct vpci_msi_msg); 614 head &= ((meq->meq_nentries * sizeof(struct vpci_msi_msg)) - 1); 615 } 616 617 err = hv_pci_msiq_sethead(pbm->vp_devhandle, 0, head); 618 if (err != H_EOK) 619 printf("%s: pci_msiq_sethead: %d\n", __func__, err); 620 621 return (1); 622 } 623 624 const struct cfattach vpci_ca = { 625 sizeof(struct vpci_softc), vpci_match, vpci_attach 626 }; 627 628 struct cfdriver vpci_cd = { 629 NULL, "vpci", DV_DULL 630 }; 631