1 /* $OpenBSD: fpu_emu.h,v 1.3 2001/10/05 17:43:09 jason Exp $ */ 2 /* $NetBSD: fpu_emu.h,v 1.4 2000/08/03 18:32:07 eeh Exp $ */ 3 4 /* 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This software was developed by the Computer Systems Engineering group 9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 10 * contributed to Berkeley. 11 * 12 * All advertising materials mentioning features or use of this software 13 * must display the following acknowledgement: 14 * This product includes software developed by the University of 15 * California, Lawrence Berkeley Laboratory. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. All advertising materials mentioning features or use of this software 26 * must display the following acknowledgement: 27 * This product includes software developed by the University of 28 * California, Berkeley and its contributors. 29 * 4. Neither the name of the University nor the names of its contributors 30 * may be used to endorse or promote products derived from this software 31 * without specific prior written permission. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 43 * SUCH DAMAGE. 44 * 45 * @(#)fpu_emu.h 8.1 (Berkeley) 6/11/93 46 */ 47 48 /* 49 * Floating point emulator (tailored for SPARC, but structurally 50 * machine-independent). 51 * 52 * Floating point numbers are carried around internally in an `expanded' 53 * or `unpacked' form consisting of: 54 * - sign 55 * - unbiased exponent 56 * - mantissa (`1.' + 112-bit fraction + guard + round) 57 * - sticky bit 58 * Any implied `1' bit is inserted, giving a 113-bit mantissa that is 59 * always nonzero. Additional low-order `guard' and `round' bits are 60 * scrunched in, making the entire mantissa 115 bits long. This is divided 61 * into four 32-bit words, with `spare' bits left over in the upper part 62 * of the top word (the high bits of fp_mant[0]). An internal `exploded' 63 * number is thus kept within the half-open interval [1.0,2.0) (but see 64 * the `number classes' below). This holds even for denormalized numbers: 65 * when we explode an external denorm, we normalize it, introducing low-order 66 * zero bits, so that the rest of the code always sees normalized values. 67 * 68 * Note that a number of our algorithms use the `spare' bits at the top. 69 * The most demanding algorithm---the one for sqrt---depends on two such 70 * bits, so that it can represent values up to (but not including) 8.0, 71 * and then it needs a carry on top of that, so that we need three `spares'. 72 * 73 * The sticky-word is 32 bits so that we can use `OR' operators to goosh 74 * whole words from the mantissa into it. 75 * 76 * All operations are done in this internal extended precision. According 77 * to Hennesey & Patterson, Appendix A, rounding can be repeated---that is, 78 * it is OK to do a+b in extended precision and then round the result to 79 * single precision---provided single, double, and extended precisions are 80 * `far enough apart' (they always are), but we will try to avoid any such 81 * extra work where possible. 82 */ 83 struct fpn { 84 int fp_class; /* see below */ 85 int fp_sign; /* 0 => positive, 1 => negative */ 86 int fp_exp; /* exponent (unbiased) */ 87 int fp_sticky; /* nonzero bits lost at right end */ 88 u_int fp_mant[4]; /* 115-bit mantissa */ 89 }; 90 91 #define FP_NMANT 115 /* total bits in mantissa (incl g,r) */ 92 #define FP_NG 2 /* number of low-order guard bits */ 93 #define FP_LG ((FP_NMANT - 1) & 31) /* log2(1.0) for fp_mant[0] */ 94 #define FP_LG2 ((FP_NMANT - 1) & 63) /* log2(1.0) for fp_mant[0] and fp_mant[1] */ 95 #define FP_QUIETBIT (1 << (FP_LG - 1)) /* Quiet bit in NaNs (0.5) */ 96 #define FP_1 (1 << FP_LG) /* 1.0 in fp_mant[0] */ 97 #define FP_2 (1 << (FP_LG + 1)) /* 2.0 in fp_mant[0] */ 98 99 /* 100 * Number classes. Since zero, Inf, and NaN cannot be represented using 101 * the above layout, we distinguish these from other numbers via a class. 102 * In addition, to make computation easier and to follow Appendix N of 103 * the SPARC Version 8 standard, we give each kind of NaN a separate class. 104 */ 105 #define FPC_SNAN -2 /* signalling NaN (sign irrelevant) */ 106 #define FPC_QNAN -1 /* quiet NaN (sign irrelevant) */ 107 #define FPC_ZERO 0 /* zero (sign matters) */ 108 #define FPC_NUM 1 /* number (sign matters) */ 109 #define FPC_INF 2 /* infinity (sign matters) */ 110 111 #define ISNAN(fp) ((fp)->fp_class < 0) 112 #define ISZERO(fp) ((fp)->fp_class == 0) 113 #define ISINF(fp) ((fp)->fp_class == FPC_INF) 114 115 /* 116 * ORDER(x,y) `sorts' a pair of `fpn *'s so that the right operand (y) points 117 * to the `more significant' operand for our purposes. Appendix N says that 118 * the result of a computation involving two numbers are: 119 * 120 * If both are SNaN: operand 2, converted to Quiet 121 * If only one is SNaN: the SNaN operand, converted to Quiet 122 * If both are QNaN: operand 2 123 * If only one is QNaN: the QNaN operand 124 * 125 * In addition, in operations with an Inf operand, the result is usually 126 * Inf. The class numbers are carefully arranged so that if 127 * (unsigned)class(op1) > (unsigned)class(op2) 128 * then op1 is the one we want; otherwise op2 is the one we want. 129 */ 130 #define ORDER(x, y) { \ 131 if ((u_int)(x)->fp_class > (u_int)(y)->fp_class) \ 132 SWAP(x, y); \ 133 } 134 #define SWAP(x, y) { \ 135 register struct fpn *swap; \ 136 swap = (x), (x) = (y), (y) = swap; \ 137 } 138 139 /* 140 * Emulator state. 141 */ 142 struct fpemu { 143 #ifndef SUN4U 144 struct fpstate *fe_fpstate; /* registers, etc */ 145 #else /* SUN4U */ 146 struct fpstate64 *fe_fpstate; /* registers, etc */ 147 #endif /* SUN4U */ 148 int fe_fsr; /* fsr copy (modified during op) */ 149 int fe_cx; /* exceptions */ 150 struct fpn fe_f1; /* operand 1 */ 151 struct fpn fe_f2; /* operand 2, if required */ 152 struct fpn fe_f3; /* available storage for result */ 153 }; 154 155 /* 156 * Arithmetic functions. 157 * Each of these may modify its inputs (f1,f2) and/or the temporary. 158 * Each returns a pointer to the result and/or sets exceptions. 159 */ 160 struct fpn *fpu_add(struct fpemu *); 161 #define fpu_sub(fe) ((fe)->fe_f2.fp_sign ^= 1, fpu_add(fe)) 162 struct fpn *fpu_mul(struct fpemu *); 163 struct fpn *fpu_div(struct fpemu *); 164 struct fpn *fpu_sqrt(struct fpemu *); 165 166 /* 167 * Other functions. 168 */ 169 170 /* Perform a compare instruction (with or without unordered exception). */ 171 void fpu_compare(struct fpemu *, int); 172 173 /* Build a new Quiet NaN (sign=0, frac=all 1's). */ 174 struct fpn *fpu_newnan(struct fpemu *); 175 176 /* 177 * Shift a number right some number of bits, taking care of round/sticky. 178 * Note that the result is probably not a well-formed number (it will lack 179 * the normal 1-bit mant[0]&FP_1). 180 */ 181 int fpu_shr(struct fpn *, int); 182 183 void fpu_explode(struct fpemu *, struct fpn *, int, int); 184 void fpu_implode(struct fpemu *, struct fpn *, int, u_int *); 185 186 #ifdef DEBUG 187 #define FPE_INSN 0x1 188 #define FPE_REG 0x2 189 #define FPE_STATE 0x4 190 extern int fpe_debug; 191 void fpu_dumpfpn(struct fpn *); 192 void fpu_dumpstate(struct fpstate64 *); 193 #define DPRINTF(x, y) if (fpe_debug & (x)) printf y 194 #define DUMPFPN(x, f) if (fpe_debug & (x)) fpu_dumpfpn((f)) 195 #define DUMPSTATE(x, s) if (fpe_debug & (x)) fpu_dumpstate((s)) 196 #else 197 #define DPRINTF(x, y) 198 #define DUMPFPN(x, f) 199 #define DUMPSTATE(x, s) 200 #endif 201