1 /* $OpenBSD: bus.h,v 1.36 2022/10/16 01:22:39 jsg Exp $ */ 2 /* $NetBSD: bus.h,v 1.31 2001/09/21 15:30:41 wiz Exp $ */ 3 4 /*- 5 * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1997-1999, 2001 Eduardo E. Horvath. All rights reserved. 36 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 37 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 #ifndef _MACHINE_BUS_H_ 67 #define _MACHINE_BUS_H_ 68 69 #include <sys/atomic.h> 70 71 #ifdef _KERNEL 72 73 /* 74 * Debug hooks 75 */ 76 77 #define BSDB_ACCESS 0x01 78 #define BSDB_MAP 0x02 79 #define BSDB_ASSERT 0x04 80 #define BSDB_MAPDETAIL 0x08 81 #define BSDB_ALL_ACCESS 0x10 82 extern int bus_space_debug; 83 84 #define BSHDB_ACCESS 0x01 85 #define BSHDB_NO_ACCESS 0x02 86 87 #if defined(BUS_SPACE_DEBUG) 88 #ifndef _MACHINE_BUS_H_ 89 #include <sys/systm.h> 90 #endif 91 #define BUS_SPACE_PRINTF(l, s) do { \ 92 if(bus_space_debug & (l)) printf s; \ 93 } while(0) 94 #define BUS_SPACE_TRACE(t, h, s) do { \ 95 if ( (((bus_space_debug & BSDB_ALL_ACCESS) != 0) && \ 96 (((h).bh_flags & BSHDB_NO_ACCESS) == 0)) || \ 97 (((bus_space_debug & BSDB_ACCESS) != 0) && \ 98 (((h).bh_flags & BSHDB_ACCESS) != 0))) \ 99 printf s; \ 100 } while(0) 101 #define BUS_SPACE_SET_FLAGS(t, h, f) ((h).bh_flags |= (f)) 102 #define BUS_SPACE_CLEAR_FLAGS(t, h, f) ((h).bh_flags &= ~(f)) 103 #define BUS_SPACE_FLAG_DECL(s) int s 104 #define BUS_SPACE_SAVE_FLAGS(t, h, s) (s = (h).bh_flags) 105 #define BUS_SPACE_RESTORE_FLAGS(t, h, s) (s = (h).bh_flags) 106 #define BUS_SPACE_ASSERT(t, h, o, n) do { \ 107 if (bus_space_debug & BSDB_ASSERT) \ 108 bus_space_assert(t, &(h), o, n); \ 109 } while(0) 110 #else /* BUS_SPACE_DEBUG */ 111 #define BUS_SPACE_PRINTF(l, s) 112 #define BUS_SPACE_TRACE(t, h, s) 113 #define BUS_SPACE_SET_FLAGS(t, h, f) 114 #define BUS_SPACE_CLEAR_FLAGS(t, h, f) 115 #define BUS_SPACE_FLAG_DECL(s) 116 #define BUS_SPACE_SAVE_FLAGS(t, h, s) 117 #define BUS_SPACE_RESTORE_FLAGS(t, h, s) 118 #define BUS_SPACE_ASSERT(t, h, o, n) 119 #endif /* BUS_SPACE_DEBUG */ 120 121 122 /* 123 * UPA and SBus spaces are non-cached and big endian 124 * (except for RAM and PROM) 125 * 126 * PCI spaces are non-cached and little endian 127 */ 128 129 enum bus_type { 130 UPA_BUS_SPACE, 131 SBUS_BUS_SPACE, 132 PCI_CONFIG_BUS_SPACE, 133 PCI_IO_BUS_SPACE, 134 PCI_MEMORY_BUS_SPACE, 135 LAST_BUS_SPACE 136 }; 137 /* For backwards compatibility */ 138 #define SPARC_BUS_SPACE UPA_BUS_SPACE 139 140 /* 141 * Bus address and size types 142 */ 143 typedef const struct sparc_bus_space_tag *bus_space_tag_t; 144 typedef u_long bus_addr_t; 145 typedef u_long bus_size_t; 146 147 148 typedef struct _bus_space_handle { 149 paddr_t bh_ptr; 150 #ifdef BUS_SPACE_DEBUG 151 bus_space_tag_t bh_tag; 152 bus_size_t bh_size; 153 int bh_flags; 154 #endif 155 } bus_space_handle_t; 156 157 /* For buses which have an iospace. */ 158 #define BUS_ADDR_IOSPACE(x) ((x)>>32) 159 #define BUS_ADDR_PADDR(x) ((x)&0xffffffff) 160 #define BUS_ADDR(io, pa) ((((bus_addr_t)io)<<32)|(pa)) 161 162 /* 163 * Access methods for bus resources and address space. 164 */ 165 166 struct sparc_bus_space_tag { 167 void *cookie; 168 bus_space_tag_t parent; 169 enum bus_type default_type; 170 u_int8_t asi; 171 u_int8_t sasi; 172 char name[32]; 173 174 int (*sparc_bus_alloc)(bus_space_tag_t, 175 bus_space_tag_t, 176 bus_addr_t, bus_addr_t, 177 bus_size_t, bus_size_t, bus_size_t, 178 int, bus_addr_t *, bus_space_handle_t *); 179 180 void (*sparc_bus_free)(bus_space_tag_t, 181 bus_space_tag_t, 182 bus_space_handle_t, bus_size_t); 183 184 int (*sparc_bus_map)(bus_space_tag_t, 185 bus_space_tag_t, 186 bus_addr_t, bus_size_t, 187 int, bus_space_handle_t *); 188 189 int (*sparc_bus_protect)(bus_space_tag_t, 190 bus_space_tag_t, 191 bus_space_handle_t, bus_size_t, int); 192 193 int (*sparc_bus_unmap)(bus_space_tag_t, 194 bus_space_tag_t, 195 bus_space_handle_t, bus_size_t); 196 197 int (*sparc_bus_subregion)(bus_space_tag_t, 198 bus_space_tag_t, 199 bus_space_handle_t, bus_size_t, 200 bus_size_t, bus_space_handle_t *); 201 202 paddr_t (*sparc_bus_mmap)(bus_space_tag_t, 203 bus_space_tag_t, 204 bus_addr_t, off_t, int, int); 205 206 void *(*sparc_intr_establish)(bus_space_tag_t, 207 bus_space_tag_t, 208 int, int, int, 209 int (*)(void *), void *, 210 const char *); 211 void *(*sparc_intr_establish_cpu)(bus_space_tag_t, 212 bus_space_tag_t, 213 int, int, int, 214 struct cpu_info *, 215 int (*)(void *), void *, 216 const char *); 217 218 bus_addr_t (*sparc_bus_addr)(bus_space_tag_t, 219 bus_space_tag_t, bus_space_handle_t); 220 }; 221 222 /* 223 * Bus space function prototypes. 224 */ 225 int bus_space_alloc( 226 bus_space_tag_t, 227 bus_addr_t, /* reg start */ 228 bus_addr_t, /* reg end */ 229 bus_size_t, /* size */ 230 bus_size_t, /* alignment */ 231 bus_size_t, /* boundary */ 232 int, /* flags */ 233 bus_addr_t *, 234 bus_space_handle_t *); 235 void bus_space_free( 236 bus_space_tag_t, 237 bus_space_handle_t, 238 bus_size_t); 239 int bus_space_map( 240 bus_space_tag_t, 241 bus_addr_t, 242 bus_size_t, 243 int, /*flags*/ 244 bus_space_handle_t *); 245 int bus_space_protect( 246 bus_space_tag_t, 247 bus_space_handle_t, 248 bus_size_t, 249 int); /*flags*/ 250 int bus_space_unmap( 251 bus_space_tag_t, 252 bus_space_handle_t, 253 bus_size_t); 254 int bus_space_subregion( 255 bus_space_tag_t, 256 bus_space_handle_t, 257 bus_size_t, 258 bus_size_t, 259 bus_space_handle_t *); 260 static void bus_space_barrier( 261 bus_space_tag_t, 262 bus_space_handle_t, 263 bus_size_t, 264 bus_size_t, 265 int); 266 paddr_t bus_space_mmap( 267 bus_space_tag_t, 268 bus_addr_t, /*addr*/ 269 off_t, /*offset*/ 270 int, /*prot*/ 271 int); /*flags*/ 272 void *bus_intr_establish( 273 bus_space_tag_t, 274 int, /*bus-specific intr*/ 275 int, /*device class level, 276 see machine/intr.h*/ 277 int, /*flags*/ 278 int (*)(void *), /*handler*/ 279 void *, /*handler arg*/ 280 const char *); /*what*/ 281 void *bus_intr_establish_cpu( 282 bus_space_tag_t, 283 int, /*bus-specific intr*/ 284 int, /*device class level, 285 see machine/intr.h*/ 286 int, /*flags*/ 287 struct cpu_info *, /*cpu*/ 288 int (*)(void *), /*handler*/ 289 void *, /*handler arg*/ 290 const char *); /*what*/ 291 void *bus_intr_allocate( 292 bus_space_tag_t, 293 int (*)(void *), /*handler*/ 294 void *, /*handler arg*/ 295 int, /*number*/ 296 int, /*pil*/ 297 volatile u_int64_t *, /*map*/ 298 volatile u_int64_t *, /*clr*/ 299 const char *); /*what*/ 300 void bus_intr_free(void *); 301 void bus_space_render_tag( 302 bus_space_tag_t, 303 char *, 304 size_t); 305 void *bus_space_vaddr( 306 bus_space_tag_t, 307 bus_space_handle_t); 308 309 #ifdef BUS_SPACE_DEBUG 310 void bus_space_assert(bus_space_tag_t, 311 const bus_space_handle_t *, 312 bus_size_t, int); 313 void bus_space_render_tag(bus_space_tag_t, char*, size_t); 314 #endif /* BUS_SPACE_DEBUG */ 315 316 317 #define _BS_PRECALL(t,f) \ 318 while (t->f == NULL) \ 319 t = t->parent; 320 #define _BS_POSTCALL 321 322 #define _BS_CALL(t,f) \ 323 (*(t)->f) 324 325 /* flags for bus_space_barrier() */ 326 #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */ 327 #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */ 328 329 static inline void 330 bus_space_barrier(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, 331 bus_size_t s, int f) 332 { 333 #ifdef notyet 334 switch (f) { 335 case (BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE): 336 __membar("#LoadLoad|#StoreStore"); 337 break; 338 case BUS_SPACE_BARRIER_READ: 339 membar("#LoadLoad"); 340 break; 341 case BUS_SPACE_BARRIER_WRITE: 342 membar("#StoreStore"); 343 break; 344 default: 345 break; 346 } 347 #else 348 __membar("#Sync"); 349 #endif 350 } 351 352 #include <sparc64/sparc64/busop.h> 353 354 /* flags for bus space map functions */ 355 #define BUS_SPACE_MAP_CACHEABLE 0x0001 356 #define BUS_SPACE_MAP_LINEAR 0x0002 357 #define BUS_SPACE_MAP_READONLY 0x0004 358 #define BUS_SPACE_MAP_PREFETCHABLE 0x0008 359 #define BUS_SPACE_MAP_PROMADDRESS 0x0010 360 #define BUS_SPACE_MAP_BUS1 0x0100 /* placeholders for bus functions... */ 361 #define BUS_SPACE_MAP_BUS2 0x0200 362 #define BUS_SPACE_MAP_BUS3 0x0400 363 #define BUS_SPACE_MAP_BUS4 0x0800 364 365 366 /* flags for bus_intr_establish() */ 367 #define BUS_INTR_ESTABLISH_MPSAFE 0x0001 368 #define BUS_INTR_ESTABLISH_SOFTINTR 0x0002 369 370 /* 371 * Flags used in various bus DMA methods. 372 */ 373 #define BUS_DMA_WAITOK 0x0000 /* safe to sleep (pseudo-flag) */ 374 #define BUS_DMA_NOWAIT 0x0001 /* not safe to sleep */ 375 #define BUS_DMA_ALLOCNOW 0x0002 /* perform resource allocation now */ 376 #define BUS_DMA_COHERENT 0x0004 /* hint: map memory DMA coherent */ 377 #define BUS_DMA_NOWRITE 0x0008 /* I suppose the following two should default on */ 378 #define BUS_DMA_BUS1 0x0010 /* placeholders for bus functions... */ 379 #define BUS_DMA_BUS2 0x0020 380 #define BUS_DMA_BUS3 0x0040 381 #define BUS_DMA_BUS4 0x0080 382 #define BUS_DMA_STREAMING 0x0100 /* hint: sequential, unidirectional */ 383 #define BUS_DMA_READ 0x0200 /* mapping is device -> memory only */ 384 #define BUS_DMA_WRITE 0x0400 /* mapping is memory -> device only */ 385 #define BUS_DMA_ZERO 0x0800 /* zero memory in dmamem_alloc */ 386 #define BUS_DMA_OVERRUN 0x1000 /* tolerate DMA overruns */ 387 #define BUS_DMA_64BIT 0x2000 /* device handles 64bit dva */ 388 389 #define BUS_DMA_NOCACHE BUS_DMA_BUS1 390 #define BUS_DMA_DVMA BUS_DMA_BUS2 /* Don't bother with alignment */ 391 #define BUS_DMA_24BIT BUS_DMA_BUS3 /* 24bit device */ 392 393 #define BUS_DMA_RAW BUS_DMA_STREAMING 394 395 /* Forwards needed by prototypes below. */ 396 struct mbuf; 397 struct uio; 398 399 /* 400 * Operations performed by bus_dmamap_sync(). 401 */ 402 #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */ 403 #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */ 404 #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */ 405 #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */ 406 407 typedef struct sparc_bus_dma_tag *bus_dma_tag_t; 408 typedef struct sparc_bus_dmamap *bus_dmamap_t; 409 410 /* 411 * bus_dma_segment_t 412 * 413 * Describes a single contiguous DMA transaction. Values 414 * are suitable for programming into DMA registers. 415 */ 416 struct sparc_bus_dma_segment { 417 bus_addr_t ds_addr; /* DVMA address */ 418 bus_size_t ds_len; /* length of transfer */ 419 /* 420 * The following is to support bus_dmamem_alloc()'s 421 * odd interface. Only the values in the first 422 * segment are used. This means that 3/5ths of 423 * most segments are useless space (and mbufs use 1024 424 * segments). 425 */ 426 bus_size_t _ds_boundary; /* don't cross this */ 427 bus_size_t _ds_align; /* align to this */ 428 void *_ds_mlist; /* XXX - dmamap_alloc'ed pages */ 429 }; 430 typedef struct sparc_bus_dma_segment bus_dma_segment_t; 431 432 433 /* 434 * bus_dma_tag_t 435 * 436 * A machine-dependent opaque type describing the implementation of 437 * DMA for a given bus. 438 */ 439 struct sparc_bus_dma_tag { 440 void *_cookie; /* cookie used in the guts */ 441 struct sparc_bus_dma_tag* _parent; 442 443 /* 444 * DMA mapping methods. 445 */ 446 int (*_dmamap_create)(bus_dma_tag_t, bus_dma_tag_t, bus_size_t, 447 int, bus_size_t, bus_size_t, int, bus_dmamap_t *); 448 void (*_dmamap_destroy)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 449 int (*_dmamap_load)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 450 void *, bus_size_t, struct proc *, int); 451 int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dma_tag_t, 452 bus_dmamap_t, struct mbuf *, int); 453 int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 454 struct uio *, int); 455 int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 456 bus_dma_segment_t *, int, bus_size_t, int); 457 void (*_dmamap_unload)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 458 void (*_dmamap_sync)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 459 bus_addr_t, bus_size_t, int); 460 461 /* 462 * DMA memory utility functions. 463 */ 464 int (*_dmamem_alloc)(bus_dma_tag_t, bus_dma_tag_t, bus_size_t, 465 bus_size_t, bus_size_t, bus_dma_segment_t *, int, int *, 466 int); 467 void (*_dmamem_free)(bus_dma_tag_t, bus_dma_tag_t, 468 bus_dma_segment_t *, int); 469 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_tag_t, 470 bus_dma_segment_t *, int, size_t, caddr_t *, int); 471 void (*_dmamem_unmap)(bus_dma_tag_t, bus_dma_tag_t, caddr_t, 472 size_t); 473 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_tag_t, 474 bus_dma_segment_t *, int, off_t, int, int); 475 }; 476 477 #define _BD_PRECALL(t,f) \ 478 while (t->f == NULL) { \ 479 t = t->_parent; \ 480 } 481 #define _BD_CALL(t,f) \ 482 (*(t)->f) 483 #define _BD_POSTCALL 484 485 static inline int 486 bus_dmamap_create(bus_dma_tag_t t, bus_size_t s, int n, bus_size_t m, 487 bus_size_t b, int f, bus_dmamap_t *p) 488 { 489 int r; 490 const bus_dma_tag_t t0 = t; 491 _BD_PRECALL(t, _dmamap_create); 492 r = _BD_CALL(t, _dmamap_create)(t, t0, s, n, m, b, f, p); 493 _BD_POSTCALL; 494 return (r); 495 } 496 static inline void 497 bus_dmamap_destroy(bus_dma_tag_t t, bus_dmamap_t p) 498 { 499 const bus_dma_tag_t t0 = t; 500 _BD_PRECALL(t, _dmamap_destroy); 501 _BD_CALL(t, _dmamap_destroy)(t, t0, p); 502 _BD_POSTCALL; 503 } 504 static inline int 505 bus_dmamap_load(bus_dma_tag_t t, bus_dmamap_t m, void *b, bus_size_t s, 506 struct proc *p, int f) 507 { 508 const bus_dma_tag_t t0 = t; 509 int r; 510 _BD_PRECALL(t, _dmamap_load); 511 r = _BD_CALL(t, _dmamap_load)(t, t0, m, b, s, p, f); 512 _BD_POSTCALL; 513 return (r); 514 } 515 static inline int 516 bus_dmamap_load_mbuf(bus_dma_tag_t t, bus_dmamap_t m, struct mbuf *b, 517 int f) 518 { 519 const bus_dma_tag_t t0 = t; 520 int r; 521 _BD_PRECALL(t, _dmamap_load_mbuf); 522 r = _BD_CALL(t, _dmamap_load_mbuf)(t, t0, m, b, f); 523 _BD_POSTCALL; 524 return (r); 525 } 526 static inline int 527 bus_dmamap_load_uio(bus_dma_tag_t t, bus_dmamap_t m, struct uio * u, int f) 528 { 529 const bus_dma_tag_t t0 = t; 530 int r; 531 _BD_PRECALL(t, _dmamap_load_uio); 532 r = _BD_CALL(t, _dmamap_load_uio)(t, t0, m, u, f); 533 _BD_POSTCALL; 534 return (r); 535 } 536 static inline int 537 bus_dmamap_load_raw(bus_dma_tag_t t, bus_dmamap_t m, bus_dma_segment_t *sg, 538 int n, bus_size_t s, int f) 539 { 540 const bus_dma_tag_t t0 = t; 541 int r; 542 _BD_PRECALL(t, _dmamap_load_raw); 543 r = _BD_CALL(t, _dmamap_load_raw)(t, t0, m, sg, n, s, f); 544 _BD_POSTCALL; 545 return (r); 546 } 547 static inline void 548 bus_dmamap_unload(bus_dma_tag_t t, bus_dmamap_t p) 549 { 550 const bus_dma_tag_t t0 = t; 551 _BD_PRECALL(t, _dmamap_unload); 552 _BD_CALL(t, _dmamap_unload)(t, t0, p); 553 _BD_POSTCALL; 554 } 555 static inline void 556 bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t p, bus_addr_t o, bus_size_t l, 557 int ops) 558 { 559 const bus_dma_tag_t t0 = t; 560 _BD_PRECALL(t, _dmamap_sync); 561 _BD_CALL(t, _dmamap_sync)(t, t0, p, o, l, ops); 562 _BD_POSTCALL; 563 } 564 static inline int 565 bus_dmamem_alloc(bus_dma_tag_t t, bus_size_t s, bus_size_t a, bus_size_t b, 566 bus_dma_segment_t *sg, int n, int *r, int f) 567 { 568 const bus_dma_tag_t t0 = t; 569 int ret; 570 _BD_PRECALL(t, _dmamem_alloc); 571 ret = _BD_CALL(t, _dmamem_alloc)(t, t0, s, a, b, sg, n, r, f); 572 _BD_POSTCALL; 573 return (ret); 574 } 575 static inline void 576 bus_dmamem_free(bus_dma_tag_t t, bus_dma_segment_t *sg, int n) 577 { 578 const bus_dma_tag_t t0 = t; 579 _BD_PRECALL(t, _dmamem_free); 580 _BD_CALL(t, _dmamem_free)(t, t0, sg, n); 581 _BD_POSTCALL; 582 } 583 static inline int 584 bus_dmamem_map(bus_dma_tag_t t, bus_dma_segment_t *sg, int n, size_t s, 585 caddr_t *k, int f) 586 { 587 const bus_dma_tag_t t0 = t; 588 int r; 589 _BD_PRECALL(t, _dmamem_map); 590 r = _BD_CALL(t, _dmamem_map)(t, t0, sg, n, s, k, f); 591 _BD_POSTCALL; 592 return (r); 593 } 594 static inline void 595 bus_dmamem_unmap(bus_dma_tag_t t, caddr_t k, size_t s) 596 { 597 const bus_dma_tag_t t0 = t; 598 _BD_PRECALL(t, _dmamem_unmap); 599 _BD_CALL(t, _dmamem_unmap)(t, t0, k, s); 600 _BD_POSTCALL; 601 } 602 static inline paddr_t 603 bus_dmamem_mmap(bus_dma_tag_t t, bus_dma_segment_t *sg, int n, off_t o, int p, 604 int f) 605 { 606 const bus_dma_tag_t t0 = t; 607 int r; 608 _BD_PRECALL(t, _dmamem_mmap); 609 r = _BD_CALL(t, _dmamem_mmap)(t, t0, sg, n, o, p, f); 610 _BD_POSTCALL; 611 return (r); 612 } 613 614 /* 615 * bus_dmamap_t 616 * 617 * Describes a DMA mapping. 618 */ 619 struct sparc_bus_dmamap { 620 /* 621 * PRIVATE MEMBERS: not for use by machine-independent code. 622 */ 623 bus_addr_t _dm_dvmastart; /* start and size of allocated */ 624 bus_size_t _dm_dvmasize; /* DVMA segment for this map */ 625 626 bus_size_t _dm_size; /* largest DMA transfer mappable */ 627 bus_size_t _dm_maxsegsz; /* largest possible segment */ 628 bus_size_t _dm_boundary; /* don't cross this */ 629 int _dm_segcnt; /* number of segs this map can map */ 630 int _dm_flags; /* misc. flags */ 631 #define _DM_TYPE_LOAD 0 632 #define _DM_TYPE_SEGS 1 633 #define _DM_TYPE_UIO 2 634 #define _DM_TYPE_MBUF 3 635 int _dm_type; /* mapping type: raw, uio, mbuf, etc */ 636 void *_dm_source; /* source mbuf/uio/etc. for unload */ 637 638 void *_dm_cookie; /* cookie for bus-specific functions */ 639 640 /* 641 * PUBLIC MEMBERS: these are used by machine-independent code. 642 */ 643 bus_size_t dm_mapsize; /* size of the mapping */ 644 int dm_nsegs; /* # valid segments in mapping */ 645 646 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 647 }; 648 649 #endif /* _KERNEL */ 650 651 #endif /* _MACHINE_BUS_H_ */ 652 653