1 /* $OpenBSD: atareg.h,v 1.7 2003/02/25 19:21:14 grange Exp $ */ 2 /* $NetBSD: atareg.h,v 1.5 1999/01/18 20:06:24 bouyer Exp $ */ 3 4 #ifndef __DEV_ATA_ATAREG_H__ 5 #define __DEV_ATA_ATAREG_H__ 6 7 /* 8 * Drive parameter structure for ATA/ATAPI. 9 * Bit fields: WDC_* : common to ATA/ATAPI 10 * ATA_* : ATA only 11 * ATAPI_* : ATAPI only. 12 */ 13 struct ataparams { 14 /* drive info */ 15 u_int16_t atap_config; /* 0: general configuration */ 16 #define WDC_CFG_ATAPI_MASK 0xc000 17 #define WDC_CFG_ATAPI 0x8000 18 #define ATA_CFG_REMOVABLE 0x0080 19 #define ATA_CFG_FIXED 0x0040 20 #define ATAPI_CFG_TYPE_MASK 0x1f00 21 #define ATAPI_CFG_TYPE(x) (((x) & ATAPI_CFG_TYPE_MASK) >> 8) 22 #define ATAPI_CFG_TYPE_DIRECT 0x00 23 #define ATAPI_CFG_TYPE_SEQUENTIAL 0x01 24 #define ATAPI_CFG_TYPE_CDROM 0x05 25 #define ATAPI_CFG_TYPE_OPTICAL 0x07 26 #define ATAPI_CFG_TYPE_NODEVICE 0x1F 27 #define ATAPI_CFG_REMOV 0x0080 28 #define ATAPI_CFG_DRQ_MASK 0x0060 29 #define ATAPI_CFG_STD_DRQ 0x0000 30 #define ATAPI_CFG_IRQ_DRQ 0x0020 31 #define ATAPI_CFG_ACCEL_DRQ 0x0040 32 #define ATAPI_CFG_CMD_MASK 0x0003 33 #define ATAPI_CFG_CMD_12 0x0000 34 #define ATAPI_CFG_CMD_16 0x0001 35 /* words 1-9 are ATA only */ 36 u_int16_t atap_cylinders; /* 1: # of non-removable cylinders */ 37 u_int16_t __reserved1; 38 u_int16_t atap_heads; /* 3: # of heads */ 39 u_int16_t __retired1[2]; /* 4-5: # of unform. bytes/track */ 40 u_int16_t atap_sectors; /* 6: # of sectors */ 41 u_int16_t __retired2[3]; 42 43 u_int8_t atap_serial[20]; /* 10-19: serial number */ 44 u_int16_t __retired3[2]; 45 u_int16_t __obsolete1; 46 u_int8_t atap_revision[8]; /* 23-26: firmware revision */ 47 u_int8_t atap_model[40]; /* 27-46: model number */ 48 u_int16_t atap_multi; /* 47: maximum sectors per irq (ATA) */ 49 u_int16_t __reserved2; 50 u_int16_t atap_capabilities1; /* 49: capability flags */ 51 #define WDC_CAP_IORDY 0x0800 52 #define WDC_CAP_IORDY_DSBL 0x0400 53 #define WDC_CAP_LBA 0x0200 54 #define WDC_CAP_DMA 0x0100 55 #define ATA_CAP_STBY 0x2000 56 #define ATAPI_CAP_INTERL_DMA 0x8000 57 #define ATAPI_CAP_CMD_QUEUE 0x4000 58 #define ATAPI_CAP_OVERLP 0x2000 59 #define ATAPI_CAP_ATA_RST 0x1000 60 u_int16_t atap_capabilities2; /* 50: capability flags (ATA) */ 61 #if BYTE_ORDER == LITTLE_ENDIAN 62 u_int8_t __junk2; 63 u_int8_t atap_oldpiotiming; /* 51: old PIO timing mode */ 64 u_int8_t __junk3; 65 u_int8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */ 66 #else 67 u_int8_t atap_oldpiotiming; /* 51: old PIO timing mode */ 68 u_int8_t __junk2; 69 u_int8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */ 70 u_int8_t __junk3; 71 #endif 72 u_int16_t atap_extensions; /* 53: extentions supported */ 73 #define WDC_EXT_UDMA_MODES 0x0004 74 #define WDC_EXT_MODES 0x0002 75 #define WDC_EXT_GEOM 0x0001 76 /* words 54-62 are ATA only */ 77 u_int16_t atap_curcylinders; /* 54: current logical cyliners */ 78 u_int16_t atap_curheads; /* 55: current logical heads */ 79 u_int16_t atap_cursectors; /* 56: current logical sectors/tracks */ 80 u_int16_t atap_curcapacity[2]; /* 57-58: current capacity */ 81 u_int16_t atap_curmulti; /* 59: current multi-sector setting */ 82 #define WDC_MULTI_VALID 0x0100 83 #define WDC_MULTI_MASK 0x00ff 84 u_int16_t atap_capacity[2]; /* 60-61: total capacity (LBA only) */ 85 u_int16_t __retired4; 86 #if BYTE_ORDER == LITTLE_ENDIAN 87 u_int8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */ 88 u_int8_t atap_dmamode_act; /* multiword DMA mode active */ 89 u_int8_t atap_piomode_supp; /* 64: PIO mode supported */ 90 u_int8_t __junk4; 91 #else 92 u_int8_t atap_dmamode_act; /* multiword DMA mode active */ 93 u_int8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */ 94 u_int8_t __junk4; 95 u_int8_t atap_piomode_supp; /* 64: PIO mode supported */ 96 #endif 97 u_int16_t atap_dmatiming_mimi; /* 65: minimum DMA cycle time */ 98 u_int16_t atap_dmatiming_recom; /* 66: recomended DMA cycle time */ 99 u_int16_t atap_piotiming; /* 67: mini PIO cycle time without FC */ 100 u_int16_t atap_piotiming_iordy; /* 68: mini PIO cycle time with IORDY FC */ 101 u_int16_t __reserved3[2]; 102 /* words 71-72 are ATAPI only */ 103 u_int16_t atap_pkt_br; /* 71: time (ns) to bus release */ 104 u_int16_t atap_pkt_bsyclr; /* 72: tme to clear BSY after service */ 105 u_int16_t __reserved4[2]; 106 u_int16_t atap_queuedepth; /* 75: */ 107 #define WDC_QUEUE_DEPTH_MASK 0x1f 108 u_int16_t __reserved5[4]; 109 u_int16_t atap_ata_major; /* 80: Major version number */ 110 #define WDC_VER_ATA1 0x0002 111 #define WDC_VER_ATA2 0x0004 112 #define WDC_VER_ATA3 0x0008 113 #define WDC_VER_ATA4 0x0010 114 #define WDC_VER_ATA5 0x0020 115 #define WDC_VER_ATA6 0x0040 116 #define WDC_VER_ATA7 0x0080 117 #define WDC_VER_ATA8 0x0100 118 #define WDC_VER_ATA9 0x0200 119 #define WDC_VER_ATA10 0x0400 120 #define WDC_VER_ATA11 0x0800 121 #define WDC_VER_ATA12 0x1000 122 #define WDC_VER_ATA13 0x2000 123 #define WDC_VER_ATA14 0x4000 124 u_int16_t atap_ata_minor; /* 81: Minor version number */ 125 u_int16_t atap_cmd_set1; /* 82: command set supported */ 126 #define WDC_CMD1_NOP 0x4000 127 #define WDC_CMD1_RB 0x2000 128 #define WDC_CMD1_WB 0x1000 129 #define WDC_CMD1_HPA 0x0400 130 #define WDC_CMD1_DVRST 0x0200 131 #define WDC_CMD1_SRV 0x0100 132 #define WDC_CMD1_RLSE 0x0080 133 #define WDC_CMD1_AHEAD 0x0040 134 #define WDC_CMD1_CACHE 0x0020 135 #define WDC_CMD1_PKT 0x0010 136 #define WDC_CMD1_PM 0x0008 137 #define WDC_CMD1_REMOV 0x0004 138 #define WDC_CMD1_SEC 0x0002 139 #define WDC_CMD1_SMART 0x0001 140 u_int16_t atap_cmd_set2; /* 83: command set supported */ 141 #define ATAPI_CMD2_FCE 0x2000 /* Flush Cache Ext supported */ 142 #define ATAPI_CMD2_FC 0x1000 /* Flush Cache supported */ 143 #define ATAPI_CMD2_DCO 0x0800 /* Device Configuration Overlay supported */ 144 #define ATAPI_CMD2_48AD 0x0400 /* 48bit address supported */ 145 #define ATAPI_CMD2_AAM 0x0200 /* Automatic Acoustic Management supported */ 146 #define ATAPI_CMD2_SM 0x0100 /* Set Max security extension supported */ 147 #define ATAPI_CMD2_SF 0x0040 /* Set Features subcommand required */ 148 #define ATAPI_CMD2_PUIS 0x0020 /* Power up in standby supported */ 149 #define WDC_CMD2_RMSN 0x0010 150 #define ATA_CMD2_APM 0x0008 151 #define ATA_CMD2_CFA 0x0004 152 #define ATA_CMD2_RWQ 0x0002 153 #define WDC_CMD2_DM 0x0001 /* Download Microcode supported */ 154 u_int16_t atap_cmd_ext; /* 84: command/features supp. ext. */ 155 #define ATAPI_CMDE_MSER 0x0004 /* Media serial number supported */ 156 #define ATAPI_CMDE_TEST 0x0002 /* SMART self-test supported */ 157 #define ATAPI_CMDE_SLOG 0x0001 /* SMART error logging supported */ 158 u_int16_t atap_cmd1_en; /* 85: cmd/features enabled */ 159 /* bits are the same as atap_cmd_set1 */ 160 u_int16_t atap_cmd2_en; /* 86: cmd/features enabled */ 161 /* bits are the same as atap_cmd_set2 */ 162 u_int16_t atap_cmd_def; /* 87: cmd/features default */ 163 /* bits are NOT the same as atap_cmd_ext */ 164 #if BYTE_ORDER == LITTLE_ENDIAN 165 u_int8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */ 166 u_int8_t atap_udmamode_act; /* Ultra-DMA mode active */ 167 #else 168 u_int8_t atap_udmamode_act; /* Ultra-DMA mode active */ 169 u_int8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */ 170 #endif 171 /* 89-92 are ATA-only */ 172 u_int16_t atap_seu_time; /* 89: Sec. Erase Unit compl. time */ 173 u_int16_t atap_eseu_time; /* 90: Enhanced SEU compl. time */ 174 u_int16_t atap_apm_val; /* 91: current APM value */ 175 u_int16_t atap_mpasswd_rev; /* 92: Master Password revision */ 176 u_int16_t atap_hwreset_res; /* 93: Hardware reset value */ 177 #define ATA_HWRES_CBLID 0x2000 /* CBLID above Vih */ 178 #define ATA_HWRES_D1_PDIAG 0x0800 /* Device 1 PDIAG detect OK */ 179 #define ATA_HWRES_D1_CSEL 0x0400 /* Device 1 used CSEL for address */ 180 #define ATA_HWRES_D1_JUMP 0x0200 /* Device 1 jumpered to address */ 181 #define ATA_HWRES_D0_SEL 0x0040 /* Device 0 responds when Dev 1 selected */ 182 #define ATA_HWRES_D0_DASP 0x0020 /* Device 0 DASP detect OK */ 183 #define ATA_HWRES_D0_PDIAG 0x0010 /* Device 0 PDIAG detect OK */ 184 #define ATA_HWRES_D0_DIAG 0x0008 /* Device 0 diag OK */ 185 #define ATA_HWRES_D0_CSEL 0x0004 /* Device 0 used CSEL for address */ 186 #define ATA_HWRES_D0_JUMP 0x0002 /* Device 0 jumpered to address */ 187 #if BYTE_ORDER == LITTLE_ENDIAN 188 u_int8_t atap_acoustic_val; /* 94: Current acoustic level */ 189 u_int8_t atap_acoustic_def; /* recommended level */ 190 #else 191 u_int8_t atap_acoustic_def; /* recommended level */ 192 u_int8_t atap_acoustic_val; /* 94: Current acoustic level */ 193 #endif 194 u_int16_t __reserved6[5]; /* 95-99: reserved */ 195 u_int16_t atap_max_lba[4]; /* 100-103: Max. user LBA add */ 196 u_int16_t __reserved7[23]; /* 104-126: reserved */ 197 u_int16_t atap_rmsn_supp; /* 127: remov. media status notif. */ 198 #define WDC_RMSN_SUPP_MASK 0x0003 199 #define WDC_RMSN_SUPP 0x0001 200 u_int16_t atap_sec_st; /* 128: security status */ 201 #define WDC_SEC_LEV_MAX 0x0100 202 #define WDC_SEC_ESE_SUPP 0x0020 203 #define WDC_SEC_EXP 0x0010 204 #define WDC_SEC_FROZEN 0x0008 205 #define WDC_SEC_LOCKED 0x0004 206 #define WDC_SEC_EN 0x0002 207 #define WDC_SEC_SUPP 0x0001 208 u_int16_t __reserved8[31]; /* 129-159: vendor specific */ 209 u_int16_t atap_cfa_power; /* 160: CFA powermode */ 210 #define ATAPI_CFA_MAX_MASK 0x0FFF 211 #define ATAPI_CFA_MODE1_DIS 0x1000 /* CFA Mode 1 Disabled */ 212 #define ATAPI_CFA_MODE1_REQ 0x2000 /* CFA Mode 1 Required */ 213 #define ATAPI_CFA_WORD160 0x8000 /* Word 160 supported */ 214 u_int16_t __reserved9[15]; /* 161-175: reserved for CFA */ 215 u_int8_t atap_media_serial[60]; /* 176-205: media serial number */ 216 u_int16_t __reserved10[49]; /* 206-254: reserved */ 217 #if BYTE_ORDER == LITTLE_ENDIAN 218 u_int8_t atap_signature; /* 255: Signature */ 219 u_int8_t atap_checksum; /* Checksum */ 220 #else 221 u_int8_t atap_checksum; /* Checksum */ 222 u_int8_t atap_signature; /* 255: Signature */ 223 #endif 224 }; 225 226 #endif 227