1 /* $OpenBSD: if_rtw_cardbus.c,v 1.26 2015/11/24 17:11:39 mpi Exp $ */ 2 /* $NetBSD: if_rtw_cardbus.c,v 1.4 2004/12/20 21:05:34 dyoung Exp $ */ 3 4 /*- 5 * Copyright (c) 2004, 2005 David Young. All rights reserved. 6 * 7 * Adapted for the RTL8180 by David Young. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of David Young may not be used to endorse or promote 18 * products derived from this software without specific prior 19 * written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 23 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 24 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 25 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 26 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 27 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 * OF SUCH DAMAGE. 33 */ 34 /*- 35 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to The NetBSD Foundation 39 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 40 * NASA Ames Research Center. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 52 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 53 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 54 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 55 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 56 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 57 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 58 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 59 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 60 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 61 * POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Cardbus front-end for the Realtek RTL8180 802.11 MAC/BBP driver. 66 * 67 * TBD factor with atw, tlp Cardbus front-ends? 68 */ 69 70 #include "bpfilter.h" 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/mbuf.h> 75 #include <sys/malloc.h> 76 #include <sys/kernel.h> 77 #include <sys/socket.h> 78 #include <sys/ioctl.h> 79 #include <sys/errno.h> 80 #include <sys/device.h> 81 #include <sys/endian.h> 82 83 #include <net/if.h> 84 #include <net/if_media.h> 85 86 #include <netinet/in.h> 87 #include <netinet/if_ether.h> 88 89 #include <net80211/ieee80211_radiotap.h> 90 #include <net80211/ieee80211_var.h> 91 92 #if NBPFILTER > 0 93 #include <net/bpf.h> 94 #endif 95 96 #include <machine/bus.h> 97 98 #include <dev/ic/rtwreg.h> 99 #include <dev/ic/rtwvar.h> 100 101 #include <dev/pci/pcivar.h> 102 #include <dev/pci/pcireg.h> 103 #include <dev/pci/pcidevs.h> 104 105 #include <dev/cardbus/cardbusvar.h> 106 107 /* 108 * PCI configuration space registers used by the RTL8180. 109 */ 110 #define RTW_PCI_IOBA 0x10 /* i/o mapped base */ 111 #define RTW_PCI_MMBA 0x14 /* memory mapped base */ 112 113 struct rtw_cardbus_softc { 114 struct rtw_softc sc_rtw; /* real RTL8180 softc */ 115 116 /* CardBus-specific goo. */ 117 void *sc_ih; /* interrupt handle */ 118 cardbus_devfunc_t sc_ct; /* our CardBus devfuncs */ 119 pcitag_t sc_tag; /* our CardBus tag */ 120 pci_chipset_tag_t sc_pc; /* PCI chipset */ 121 int sc_csr; /* CSR bits */ 122 bus_size_t sc_mapsize; /* size of the mapped bus space 123 * region 124 */ 125 126 int sc_cben; /* CardBus enables */ 127 int sc_bar_reg; /* which BAR to use */ 128 pcireg_t sc_bar_val; /* value of the BAR */ 129 130 int sc_intrline; /* interrupt line */ 131 }; 132 133 int rtw_cardbus_match(struct device *, void *, void *); 134 void rtw_cardbus_attach(struct device *, struct device *, void *); 135 int rtw_cardbus_detach(struct device *, int); 136 void rtw_cardbus_intr_ack(struct rtw_regs *); 137 void rtw_cardbus_funcregen(struct rtw_regs *, int); 138 139 struct cfattach rtw_cardbus_ca = { 140 sizeof(struct rtw_cardbus_softc), rtw_cardbus_match, rtw_cardbus_attach, 141 rtw_cardbus_detach 142 }; 143 144 void rtw_cardbus_setup(struct rtw_cardbus_softc *); 145 146 int rtw_cardbus_enable(struct rtw_softc *); 147 void rtw_cardbus_disable(struct rtw_softc *); 148 void rtw_cardbus_power(struct rtw_softc *, int); 149 150 const struct pci_matchid rtw_cardbus_devices[] = { 151 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8180 }, 152 #ifdef RTW_DEBUG 153 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8185 }, 154 { PCI_VENDOR_BELKIN2, PCI_PRODUCT_BELKIN2_F5D7010 }, 155 #endif 156 { PCI_VENDOR_BELKIN2, PCI_PRODUCT_BELKIN2_F5D6020V3 }, 157 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DWL610 } 158 }; 159 160 int 161 rtw_cardbus_match(struct device *parent, void *match, void *aux) 162 { 163 return (cardbus_matchbyid((struct cardbus_attach_args *)aux, 164 rtw_cardbus_devices, nitems(rtw_cardbus_devices))); 165 } 166 167 void 168 rtw_cardbus_intr_ack(struct rtw_regs *regs) 169 { 170 RTW_WRITE(regs, RTW_FER, RTW_FER_INTR); 171 } 172 173 void 174 rtw_cardbus_funcregen(struct rtw_regs *regs, int enable) 175 { 176 u_int32_t reg; 177 rtw_config0123_enable(regs, 1); 178 reg = RTW_READ(regs, RTW_CONFIG3); 179 if (enable) { 180 RTW_WRITE(regs, RTW_CONFIG3, reg | RTW_CONFIG3_FUNCREGEN); 181 } else { 182 RTW_WRITE(regs, RTW_CONFIG3, reg & ~RTW_CONFIG3_FUNCREGEN); 183 } 184 rtw_config0123_enable(regs, 0); 185 } 186 187 void 188 rtw_cardbus_attach(struct device *parent, struct device *self, void *aux) 189 { 190 struct rtw_cardbus_softc *csc = (void *)self; 191 struct rtw_softc *sc = &csc->sc_rtw; 192 struct rtw_regs *regs = &sc->sc_regs; 193 struct cardbus_attach_args *ca = aux; 194 cardbus_devfunc_t ct = ca->ca_ct; 195 bus_addr_t adr; 196 int rev; 197 198 sc->sc_dmat = ca->ca_dmat; 199 csc->sc_ct = ct; 200 csc->sc_tag = ca->ca_tag; 201 csc->sc_pc = ca->ca_pc; 202 203 /* 204 * Power management hooks. 205 */ 206 sc->sc_enable = rtw_cardbus_enable; 207 sc->sc_disable = rtw_cardbus_disable; 208 sc->sc_power = rtw_cardbus_power; 209 210 sc->sc_intr_ack = rtw_cardbus_intr_ack; 211 212 /* Get revision info. */ 213 rev = PCI_REVISION(ca->ca_class); 214 215 RTW_DPRINTF(RTW_DEBUG_ATTACH, 216 ("%s: pass %d.%d signature %08x\n", sc->sc_dev.dv_xname, 217 (rev >> 4) & 0xf, rev & 0xf, 218 pci_conf_read(ca->ca_pc, csc->sc_tag, 0x80))); 219 220 /* 221 * Map the device. 222 */ 223 csc->sc_csr = PCI_COMMAND_MASTER_ENABLE; 224 if (Cardbus_mapreg_map(ct, RTW_PCI_MMBA, 225 PCI_MAPREG_TYPE_MEM, 0, ®s->r_bt, ®s->r_bh, &adr, 226 &csc->sc_mapsize) == 0) { 227 RTW_DPRINTF(RTW_DEBUG_ATTACH, 228 ("%s: %s mapped %lu bytes mem space\n", 229 sc->sc_dev.dv_xname, __func__, (long)csc->sc_mapsize)); 230 csc->sc_cben = CARDBUS_MEM_ENABLE; 231 csc->sc_csr |= PCI_COMMAND_MEM_ENABLE; 232 csc->sc_bar_reg = RTW_PCI_MMBA; 233 csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM; 234 } else if (Cardbus_mapreg_map(ct, RTW_PCI_IOBA, 235 PCI_MAPREG_TYPE_IO, 0, ®s->r_bt, ®s->r_bh, &adr, 236 &csc->sc_mapsize) == 0) { 237 RTW_DPRINTF(RTW_DEBUG_ATTACH, 238 ("%s: %s mapped %lu bytes I/O space\n", 239 sc->sc_dev.dv_xname, __func__, (long)csc->sc_mapsize)); 240 csc->sc_cben = CARDBUS_IO_ENABLE; 241 csc->sc_csr |= PCI_COMMAND_IO_ENABLE; 242 csc->sc_bar_reg = RTW_PCI_IOBA; 243 csc->sc_bar_val = adr | PCI_MAPREG_TYPE_IO; 244 } else { 245 printf("%s: unable to map device registers\n", 246 sc->sc_dev.dv_xname); 247 return; 248 } 249 250 /* 251 * Bring the chip out of powersave mode and initialize the 252 * configuration registers. 253 */ 254 rtw_cardbus_setup(csc); 255 256 /* Remember which interrupt line. */ 257 csc->sc_intrline = ca->ca_intrline; 258 259 printf(": irq %d\n", csc->sc_intrline); 260 261 /* 262 * Finish off the attach. 263 */ 264 rtw_attach(sc); 265 266 rtw_cardbus_funcregen(regs, 1); 267 268 RTW_WRITE(regs, RTW_FEMR, RTW_FEMR_INTR); 269 RTW_WRITE(regs, RTW_FER, RTW_FER_INTR); 270 271 /* 272 * Power down the socket. 273 */ 274 Cardbus_function_disable(csc->sc_ct); 275 } 276 277 int 278 rtw_cardbus_detach(struct device *self, int flags) 279 { 280 struct rtw_cardbus_softc *csc = (void *)self; 281 struct rtw_softc *sc = &csc->sc_rtw; 282 struct rtw_regs *regs = &sc->sc_regs; 283 struct cardbus_devfunc *ct = csc->sc_ct; 284 int rv; 285 286 #if defined(DIAGNOSTIC) 287 if (ct == NULL) 288 panic("%s: data structure lacks", sc->sc_dev.dv_xname); 289 #endif 290 291 rv = rtw_detach(sc); 292 if (rv) 293 return (rv); 294 295 rtw_cardbus_funcregen(regs, 0); 296 297 /* 298 * Unhook the interrupt handler. 299 */ 300 if (csc->sc_ih != NULL) 301 cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih); 302 303 /* 304 * Release bus space and close window. 305 */ 306 if (csc->sc_bar_reg != 0) 307 Cardbus_mapreg_unmap(ct, csc->sc_bar_reg, 308 regs->r_bt, regs->r_bh, csc->sc_mapsize); 309 310 return (0); 311 } 312 313 int 314 rtw_cardbus_enable(struct rtw_softc *sc) 315 { 316 struct rtw_cardbus_softc *csc = (void *) sc; 317 cardbus_devfunc_t ct = csc->sc_ct; 318 cardbus_chipset_tag_t cc = ct->ct_cc; 319 cardbus_function_tag_t cf = ct->ct_cf; 320 321 /* 322 * Power on the socket. 323 */ 324 Cardbus_function_enable(ct); 325 326 /* 327 * Set up the PCI configuration registers. 328 */ 329 rtw_cardbus_setup(csc); 330 331 /* 332 * Map and establish the interrupt. 333 */ 334 csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET, 335 rtw_intr, sc, sc->sc_dev.dv_xname); 336 if (csc->sc_ih == NULL) { 337 printf("%s: unable to establish interrupt at %d\n", 338 sc->sc_dev.dv_xname, csc->sc_intrline); 339 Cardbus_function_disable(csc->sc_ct); 340 return (1); 341 } 342 343 rtw_cardbus_funcregen(&sc->sc_regs, 1); 344 345 RTW_WRITE(&sc->sc_regs, RTW_FEMR, RTW_FEMR_INTR); 346 RTW_WRITE(&sc->sc_regs, RTW_FER, RTW_FER_INTR); 347 348 return (0); 349 } 350 351 void 352 rtw_cardbus_disable(struct rtw_softc *sc) 353 { 354 struct rtw_cardbus_softc *csc = (void *) sc; 355 cardbus_devfunc_t ct = csc->sc_ct; 356 cardbus_chipset_tag_t cc = ct->ct_cc; 357 cardbus_function_tag_t cf = ct->ct_cf; 358 359 RTW_WRITE(&sc->sc_regs, RTW_FEMR, 360 RTW_READ(&sc->sc_regs, RTW_FEMR) & ~RTW_FEMR_INTR); 361 362 rtw_cardbus_funcregen(&sc->sc_regs, 0); 363 364 /* Unhook the interrupt handler. */ 365 cardbus_intr_disestablish(cc, cf, csc->sc_ih); 366 csc->sc_ih = NULL; 367 368 /* Power down the socket. */ 369 Cardbus_function_disable(ct); 370 } 371 372 void 373 rtw_cardbus_power(struct rtw_softc *sc, int why) 374 { 375 RTW_DPRINTF(RTW_DEBUG_ATTACH, 376 ("%s: rtw_cardbus_power\n", sc->sc_dev.dv_xname)); 377 378 if (why == DVACT_RESUME) 379 rtw_enable(sc); 380 } 381 382 void 383 rtw_cardbus_setup(struct rtw_cardbus_softc *csc) 384 { 385 struct rtw_softc *sc = &csc->sc_rtw; 386 cardbus_devfunc_t ct = csc->sc_ct; 387 cardbus_chipset_tag_t cc = ct->ct_cc; 388 pci_chipset_tag_t pc = csc->sc_pc; 389 pcireg_t reg; 390 int pmreg; 391 392 if (pci_get_capability(pc, csc->sc_tag, 393 PCI_CAP_PWRMGMT, &pmreg, 0)) { 394 reg = pci_conf_read(pc, csc->sc_tag, pmreg + 4) & 0x03; 395 #if 1 /* XXX Probably not right for CardBus. */ 396 if (reg == 3) { 397 /* 398 * The card has lost all configuration data in 399 * this state, so punt. 400 */ 401 printf("%s: unable to wake up from power state D3\n", 402 sc->sc_dev.dv_xname); 403 return; 404 } 405 #endif 406 if (reg != 0) { 407 printf("%s: waking up from power state D%d\n", 408 sc->sc_dev.dv_xname, reg); 409 pci_conf_write(pc, csc->sc_tag, 410 pmreg + 4, 0); 411 } 412 } 413 414 /* Program the BAR. */ 415 pci_conf_write(pc, csc->sc_tag, csc->sc_bar_reg, 416 csc->sc_bar_val); 417 418 /* Make sure the right access type is on the CardBus bridge. */ 419 (*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cben); 420 (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); 421 422 /* Enable the appropriate bits in the PCI CSR. */ 423 reg = pci_conf_read(pc, csc->sc_tag, 424 PCI_COMMAND_STATUS_REG); 425 reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE); 426 reg |= csc->sc_csr; 427 pci_conf_write(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG, 428 reg); 429 430 /* 431 * Make sure the latency timer is set to some reasonable 432 * value. 433 */ 434 reg = pci_conf_read(pc, csc->sc_tag, PCI_BHLC_REG); 435 if (PCI_LATTIMER(reg) < 0x20) { 436 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 437 reg |= (0x20 << PCI_LATTIMER_SHIFT); 438 pci_conf_write(pc, csc->sc_tag, PCI_BHLC_REG, reg); 439 } 440 } 441