1 /* $OpenBSD: dwmmc.c,v 1.25 2021/10/24 17:52:26 mpi Exp $ */ 2 /* 3 * Copyright (c) 2017 Mark Kettenis 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/param.h> 19 #include <sys/kernel.h> 20 #include <sys/malloc.h> 21 #include <sys/systm.h> 22 23 #include <machine/bus.h> 24 #include <machine/fdt.h> 25 #include <machine/intr.h> 26 27 #include <dev/ofw/openfirm.h> 28 #include <dev/ofw/ofw_clock.h> 29 #include <dev/ofw/ofw_gpio.h> 30 #include <dev/ofw/ofw_pinctrl.h> 31 #include <dev/ofw/fdt.h> 32 33 #include <dev/sdmmc/sdmmcvar.h> 34 #include <dev/sdmmc/sdmmc_ioreg.h> 35 36 #define SDMMC_CTRL 0x0000 37 #define SDMMC_CTRL_USE_INTERNAL_DMAC (1 << 25) 38 #define SDMMC_CTRL_DMA_ENABLE (1 << 5) 39 #define SDMMC_CTRL_INT_ENABLE (1 << 4) 40 #define SDMMC_CTRL_DMA_RESET (1 << 2) 41 #define SDMMC_CTRL_FIFO_RESET (1 << 1) 42 #define SDMMC_CTRL_CONTROLLER_RESET (1 << 0) 43 #define SDMMC_CTRL_ALL_RESET (SDMMC_CTRL_CONTROLLER_RESET | \ 44 SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET) 45 #define SDMMC_PWREN 0x0004 46 #define SDMMC_CLKDIV 0x0008 47 #define SDMMC_CLKSRC 0x000c 48 #define SDMMC_CLKENA 0x0010 49 #define SDMMC_CLKENA_CCLK_LOW_POWER (1 << 16) 50 #define SDMMC_CLKENA_CCLK_ENABLE (1 << 0) 51 #define SDMMC_TMOUT 0x0014 52 #define SDMMC_CTYPE 0x0018 53 #define SDMMC_CTYPE_8BIT (1 << 16) 54 #define SDMMC_CTYPE_4BIT (1 << 0) 55 #define SDMMC_BLKSIZ 0x001c 56 #define SDMMC_BYTCNT 0x0020 57 #define SDMMC_INTMASK 0x0024 58 #define SDMMC_CMDARG 0x0028 59 #define SDMMC_CMD 0x002c 60 #define SDMMC_CMD_START_CMD (1U << 31) 61 #define SDMMC_CMD_USE_HOLD_REG (1 << 29) 62 #define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY (1 << 21) 63 #define SDMMC_CMD_SEND_INITIALIZATION (1 << 15) 64 #define SDMMC_CMD_STOP_ABORT_CMD (1 << 14) 65 #define SDMMC_CMD_WAIT_PRVDATA_COMPLETE (1 << 13) 66 #define SDMMC_CMD_SEND_AUTO_STOP (1 << 12) 67 #define SDMMC_CMD_WR (1 << 10) 68 #define SDMMC_CMD_DATA_EXPECTED (1 << 9) 69 #define SDMMC_CMD_CHECK_REPONSE_CRC (1 << 8) 70 #define SDMMC_CMD_RESPONSE_LENGTH (1 << 7) 71 #define SDMMC_CMD_RESPONSE_EXPECT (1 << 6) 72 #define SDMMC_RESP0 0x0030 73 #define SDMMC_RESP1 0x0034 74 #define SDMMC_RESP2 0x0038 75 #define SDMMC_RESP3 0x003c 76 #define SDMMC_MINTSTS 0x0040 77 #define SDMMC_RINTSTS 0x0044 78 #define SDMMC_RINTSTS_SDIO (1 << 24) 79 #define SDMMC_RINTSTS_EBE (1 << 15) 80 #define SDMMC_RINTSTS_ACD (1 << 14) 81 #define SDMMC_RINTSTS_SBE (1 << 13) 82 #define SDMMC_RINTSTS_HLE (1 << 12) 83 #define SDMMC_RINTSTS_FRUN (1 << 11) 84 #define SDMMC_RINTSTS_HTO (1 << 10) 85 #define SDMMC_RINTSTS_DRTO (1 << 9) 86 #define SDMMC_RINTSTS_RTO (1 << 8) 87 #define SDMMC_RINTSTS_DCRC (1 << 7) 88 #define SDMMC_RINTSTS_RCRC (1 << 6) 89 #define SDMMC_RINTSTS_RXDR (1 << 5) 90 #define SDMMC_RINTSTS_TXDR (1 << 4) 91 #define SDMMC_RINTSTS_DTO (1 << 3) 92 #define SDMMC_RINTSTS_CD (1 << 2) 93 #define SDMMC_RINTSTS_RE (1 << 1) 94 #define SDMMC_RINTSTS_CDT (1 << 0) 95 #define SDMMC_RINTSTS_DATA_ERR (SDMMC_RINTSTS_EBE | SDMMC_RINTSTS_SBE | \ 96 SDMMC_RINTSTS_HLE | SDMMC_RINTSTS_FRUN | SDMMC_RINTSTS_DCRC) 97 #define SDMMC_RINTSTS_DATA_TO (SDMMC_RINTSTS_HTO | SDMMC_RINTSTS_DRTO) 98 #define SDMMC_STATUS 0x0048 99 #define SDMMC_STATUS_FIFO_COUNT(x) (((x) >> 17) & 0x1fff) 100 #define SDMMC_STATUS_DATA_BUSY (1 << 9) 101 #define SDMMC_FIFOTH 0x004c 102 #define SDMMC_FIFOTH_MSIZE_SHIFT 28 103 #define SDMMC_FIFOTH_RXWM_SHIFT 16 104 #define SDMMC_FIFOTH_RXWM(x) (((x) >> 16) & 0xfff) 105 #define SDMMC_FIFOTH_TXWM_SHIFT 0 106 #define SDMMC_CDETECT 0x0050 107 #define SDMMC_CDETECT_CARD_DETECT_0 (1 << 0) 108 #define SDMMC_WRTPRT 0x0054 109 #define SDMMC_TCBCNT 0x005c 110 #define SDMMC_TBBCNT 0x0060 111 #define SDMMC_DEBNCE 0x0064 112 #define SDMMC_USRID 0x0068 113 #define SDMMC_VERID 0x006c 114 #define SDMMC_HCON 0x0070 115 #define SDMMC_HCON_DATA_WIDTH(x) (((x) >> 7) & 0x7) 116 #define SDMMC_HCON_DMA64 (1 << 27) 117 #define SDMMC_UHS_REG 0x0074 118 #define SDMMC_RST_n 0x0078 119 #define SDMMC_BMOD 0x0080 120 #define SDMMC_BMOD_DE (1 << 7) 121 #define SDMMC_BMOD_FB (1 << 1) 122 #define SDMMC_BMOD_SWR (1 << 0) 123 #define SDMMC_PLDMND 0x0084 124 #define SDMMC_DBADDR 0x0088 125 #define SDMMC_IDSTS32 0x008c 126 #define SDMMC_IDSTS_NIS (1 << 8) 127 #define SDMMC_IDSTS_RI (1 << 1) 128 #define SDMMC_IDSTS_TI (1 << 0) 129 #define SDMMC_IDINTEN32 0x0090 130 #define SDMMC_IDINTEN_NI (1 << 8) 131 #define SDMMC_IDINTEN_RI (1 << 1) 132 #define SDMMC_IDINTEN_TI (1 << 0) 133 #define SDMMC_DSCADDR 0x0094 134 #define SDMMC_BUFADDR 0x0098 135 #define SDMMC_CLKSEL 0x009c 136 #define SDMMC_CARDTHRCTL 0x0100 137 #define SDMMC_CARDTHRCTL_RDTHR_SHIFT 16 138 #define SDMMC_CARDTHRCTL_RDTHREN (1 << 0) 139 #define SDMMC_BACK_END_POWER 0x0104 140 #define SDMMC_EMMC_DDR_REG 0x0108 141 #define SDMMC_FIFO_BASE 0x0200 142 143 #define SDMMC_DBADDRL 0x0088 144 #define SDMMC_DBADDRH 0x008c 145 #define SDMMC_IDSTS64 0x0090 146 #define SDMMC_IDINTEN64 0x0094 147 #define SDMMC_DSCADDRL 0x0098 148 #define SDMMC_DSCADDRH 0x009c 149 #define SDMMC_BUFADDRL 0x00a0 150 #define SDMMC_BUFADDRH 0x00a4 151 152 #define SDMMC_IDSTS(sc) \ 153 ((sc)->sc_dma64 ? SDMMC_IDSTS64 : SDMMC_IDSTS32) 154 155 #define HREAD4(sc, reg) \ 156 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 157 #define HWRITE4(sc, reg, val) \ 158 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 159 #define HSET4(sc, reg, bits) \ 160 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits)) 161 #define HCLR4(sc, reg, bits) \ 162 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits)) 163 164 struct dwmmc_desc32 { 165 uint32_t des[4]; 166 }; 167 168 struct dwmmc_desc64 { 169 uint32_t des[8]; 170 }; 171 172 #define DWMMC_NDESC (PAGE_SIZE / sizeof(struct dwmmc_desc64)) 173 #define DWMMC_MAXSEGSZ 0x1000 174 175 #define DES0_OWN (1U << 31) 176 #define DES0_CES (1 << 30) 177 #define DES0_ER (1 << 5) 178 #define DES0_CH (1 << 4) 179 #define DES0_FS (1 << 3) 180 #define DES0_LD (1 << 2) 181 #define DES0_DIC (1 << 1) 182 183 #define DES1_BS2(sz) (((sz) & 0x1fff) << 13) 184 #define DES1_BS1(sz) (((sz) & 0x1fff) << 0) 185 #define DES2_BS2(sz) DES1_BS2(sz) 186 #define DES2_BS1(sz) DES1_BS1(sz) 187 188 struct dwmmc_softc { 189 struct device sc_dev; 190 bus_space_tag_t sc_iot; 191 bus_space_handle_t sc_ioh; 192 bus_size_t sc_size; 193 bus_dma_tag_t sc_dmat; 194 bus_dmamap_t sc_dmap; 195 int sc_node; 196 197 void *sc_ih; 198 199 uint32_t sc_clkbase; 200 uint32_t sc_fifo_depth; 201 uint32_t sc_fifo_width; 202 void (*sc_read_data)(struct dwmmc_softc *, u_char *, int); 203 void (*sc_write_data)(struct dwmmc_softc *, u_char *, int); 204 int sc_blklen; 205 206 bus_dmamap_t sc_desc_map; 207 bus_dma_segment_t sc_desc_segs[1]; 208 caddr_t sc_desc; 209 int sc_dma64; 210 int sc_dmamode; 211 uint32_t sc_idsts; 212 213 uint32_t sc_gpio[4]; 214 int sc_sdio_irq; 215 uint32_t sc_pwrseq; 216 uint32_t sc_vdd; 217 218 struct device *sc_sdmmc; 219 }; 220 221 int dwmmc_match(struct device *, void *, void *); 222 void dwmmc_attach(struct device *, struct device *, void *); 223 224 const struct cfattach dwmmc_ca = { 225 sizeof(struct dwmmc_softc), dwmmc_match, dwmmc_attach 226 }; 227 228 struct cfdriver dwmmc_cd = { 229 NULL, "dwmmc", DV_DULL 230 }; 231 232 int dwmmc_intr(void *); 233 234 int dwmmc_host_reset(sdmmc_chipset_handle_t); 235 uint32_t dwmmc_host_ocr(sdmmc_chipset_handle_t); 236 int dwmmc_host_maxblklen(sdmmc_chipset_handle_t); 237 int dwmmc_card_detect(sdmmc_chipset_handle_t); 238 int dwmmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 239 int dwmmc_bus_clock(sdmmc_chipset_handle_t, int, int); 240 int dwmmc_bus_width(sdmmc_chipset_handle_t, int); 241 void dwmmc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 242 void dwmmc_card_intr_mask(sdmmc_chipset_handle_t, int); 243 void dwmmc_card_intr_ack(sdmmc_chipset_handle_t); 244 245 struct sdmmc_chip_functions dwmmc_chip_functions = { 246 .host_reset = dwmmc_host_reset, 247 .host_ocr = dwmmc_host_ocr, 248 .host_maxblklen = dwmmc_host_maxblklen, 249 .card_detect = dwmmc_card_detect, 250 .bus_power = dwmmc_bus_power, 251 .bus_clock = dwmmc_bus_clock, 252 .bus_width = dwmmc_bus_width, 253 .exec_command = dwmmc_exec_command, 254 .card_intr_mask = dwmmc_card_intr_mask, 255 .card_intr_ack = dwmmc_card_intr_ack, 256 }; 257 258 void dwmmc_pio_mode(struct dwmmc_softc *); 259 int dwmmc_alloc_descriptors(struct dwmmc_softc *); 260 void dwmmc_init_descriptors(struct dwmmc_softc *); 261 void dwmmc_transfer_data(struct dwmmc_softc *, struct sdmmc_command *); 262 void dwmmc_read_data32(struct dwmmc_softc *, u_char *, int); 263 void dwmmc_write_data32(struct dwmmc_softc *, u_char *, int); 264 void dwmmc_read_data64(struct dwmmc_softc *, u_char *, int); 265 void dwmmc_write_data64(struct dwmmc_softc *, u_char *, int); 266 void dwmmc_pwrseq_pre(uint32_t); 267 void dwmmc_pwrseq_post(uint32_t); 268 269 int 270 dwmmc_match(struct device *parent, void *match, void *aux) 271 { 272 struct fdt_attach_args *faa = aux; 273 274 return (OF_is_compatible(faa->fa_node, "hisilicon,hi3660-dw-mshc") || 275 OF_is_compatible(faa->fa_node, "hisilicon,hi3670-dw-mshc") || 276 OF_is_compatible(faa->fa_node, "rockchip,rk3288-dw-mshc") || 277 OF_is_compatible(faa->fa_node, "samsung,exynos5420-dw-mshc") || 278 OF_is_compatible(faa->fa_node, "snps,dw-mshc")); 279 } 280 281 void 282 dwmmc_attach(struct device *parent, struct device *self, void *aux) 283 { 284 struct dwmmc_softc *sc = (struct dwmmc_softc *)self; 285 struct fdt_attach_args *faa = aux; 286 struct sdmmcbus_attach_args saa; 287 uint32_t freq = 0, div = 0; 288 uint32_t hcon, width; 289 uint32_t fifoth; 290 int error, timeout; 291 292 if (faa->fa_nreg < 1) { 293 printf(": no registers\n"); 294 return; 295 } 296 297 sc->sc_node = faa->fa_node; 298 sc->sc_iot = faa->fa_iot; 299 sc->sc_size = faa->fa_reg[0].size; 300 301 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, 302 faa->fa_reg[0].size, 0, &sc->sc_ioh)) { 303 printf(": can't map registers\n"); 304 return; 305 } 306 307 pinctrl_byname(faa->fa_node, "default"); 308 309 clock_enable_all(faa->fa_node); 310 reset_deassert_all(faa->fa_node); 311 312 /* 313 * Determine FIFO width from hardware configuration register. 314 * We only support 32-bit and 64-bit FIFOs. 315 */ 316 hcon = HREAD4(sc, SDMMC_HCON); 317 switch (SDMMC_HCON_DATA_WIDTH(hcon)) { 318 case 1: 319 sc->sc_fifo_width = 4; 320 sc->sc_read_data = dwmmc_read_data32; 321 sc->sc_write_data = dwmmc_write_data32; 322 break; 323 case 2: 324 sc->sc_fifo_width = 8; 325 sc->sc_read_data = dwmmc_read_data64; 326 sc->sc_write_data = dwmmc_write_data64; 327 break; 328 default: 329 printf(": unsupported FIFO width\n"); 330 return; 331 } 332 333 sc->sc_fifo_depth = OF_getpropint(faa->fa_node, "fifo-depth", 0); 334 if (sc->sc_fifo_depth == 0) { 335 fifoth = HREAD4(sc, SDMMC_FIFOTH); 336 sc->sc_fifo_depth = SDMMC_FIFOTH_RXWM(fifoth) + 1; 337 } 338 339 if (hcon & SDMMC_HCON_DMA64) 340 sc->sc_dma64 = 1; 341 342 /* Some SoCs pre-divide the clock. */ 343 if (OF_is_compatible(faa->fa_node, "rockchip,rk3288-dw-mshc")) 344 div = 1; 345 if (OF_is_compatible(faa->fa_node, "hisilicon,hi3660-dw-mshc") || 346 OF_is_compatible(faa->fa_node, "hisilicon,hi3670-dw-mshc")) 347 div = 7; 348 349 /* Force the base clock to 50MHz on Rockchip SoCs. */ 350 if (OF_is_compatible(faa->fa_node, "rockchip,rk3288-dw-mshc")) 351 freq = 50000000; 352 353 freq = OF_getpropint(faa->fa_node, "clock-frequency", freq); 354 if (freq > 0) 355 clock_set_frequency(faa->fa_node, "ciu", (div + 1) * freq); 356 357 sc->sc_clkbase = clock_get_frequency(faa->fa_node, "ciu"); 358 /* if ciu clock is missing the rate is clock-frequency */ 359 if (sc->sc_clkbase == 0) 360 sc->sc_clkbase = freq; 361 div = OF_getpropint(faa->fa_node, "samsung,dw-mshc-ciu-div", div); 362 sc->sc_clkbase /= (div + 1); 363 364 sc->sc_ih = fdt_intr_establish(faa->fa_node, IPL_BIO, 365 dwmmc_intr, sc, sc->sc_dev.dv_xname); 366 if (sc->sc_ih == NULL) { 367 printf(": can't establish interrupt\n"); 368 goto unmap; 369 } 370 371 OF_getpropintarray(faa->fa_node, "cd-gpios", sc->sc_gpio, 372 sizeof(sc->sc_gpio)); 373 if (sc->sc_gpio[0]) 374 gpio_controller_config_pin(sc->sc_gpio, GPIO_CONFIG_INPUT); 375 376 sc->sc_sdio_irq = (OF_getproplen(sc->sc_node, "cap-sdio-irq") == 0); 377 sc->sc_pwrseq = OF_getpropint(sc->sc_node, "mmc-pwrseq", 0); 378 379 printf(": %d MHz base clock\n", sc->sc_clkbase / 1000000); 380 381 HSET4(sc, SDMMC_CTRL, SDMMC_CTRL_ALL_RESET); 382 for (timeout = 5000; timeout > 0; timeout--) { 383 if ((HREAD4(sc, SDMMC_CTRL) & SDMMC_CTRL_ALL_RESET) == 0) 384 break; 385 delay(100); 386 } 387 if (timeout == 0) 388 printf("%s: reset failed\n", sc->sc_dev.dv_xname); 389 390 /* Enable interrupts, but mask them all. */ 391 HWRITE4(sc, SDMMC_INTMASK, 0); 392 HWRITE4(sc, SDMMC_RINTSTS, 0xffffffff); 393 HSET4(sc, SDMMC_CTRL, SDMMC_CTRL_INT_ENABLE); 394 395 dwmmc_bus_width(sc, 1); 396 397 /* Start out in non-DMA mode. */ 398 dwmmc_pio_mode(sc); 399 400 sc->sc_dmat = faa->fa_dmat; 401 dwmmc_alloc_descriptors(sc); 402 dwmmc_init_descriptors(sc); 403 404 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, DWMMC_NDESC, 405 DWMMC_MAXSEGSZ, 0, BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &sc->sc_dmap); 406 if (error) { 407 printf(": can't create DMA map\n"); 408 goto unmap; 409 } 410 411 memset(&saa, 0, sizeof(saa)); 412 saa.saa_busname = "sdmmc"; 413 saa.sct = &dwmmc_chip_functions; 414 saa.sch = sc; 415 saa.dmat = sc->sc_dmat; 416 saa.dmap = sc->sc_dmap; 417 saa.caps |= SMC_CAPS_DMA; 418 419 if (OF_getproplen(sc->sc_node, "cap-mmc-highspeed") == 0) 420 saa.caps |= SMC_CAPS_MMC_HIGHSPEED; 421 if (OF_getproplen(sc->sc_node, "cap-sd-highspeed") == 0) 422 saa.caps |= SMC_CAPS_SD_HIGHSPEED; 423 424 width = OF_getpropint(faa->fa_node, "bus-width", 1); 425 if (width >= 8) 426 saa.caps |= SMC_CAPS_8BIT_MODE; 427 if (width >= 4) 428 saa.caps |= SMC_CAPS_4BIT_MODE; 429 430 sc->sc_sdmmc = config_found(self, &saa, NULL); 431 return; 432 433 unmap: 434 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size); 435 } 436 437 int 438 dwmmc_alloc_descriptors(struct dwmmc_softc *sc) 439 { 440 int error, rseg; 441 442 /* Allocate descriptor memory */ 443 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 444 PAGE_SIZE, sc->sc_desc_segs, 1, &rseg, 445 BUS_DMA_WAITOK | BUS_DMA_ZERO); 446 if (error) 447 return error; 448 error = bus_dmamem_map(sc->sc_dmat, sc->sc_desc_segs, rseg, 449 PAGE_SIZE, &sc->sc_desc, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 450 if (error) { 451 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, rseg); 452 return error; 453 } 454 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 455 0, BUS_DMA_WAITOK, &sc->sc_desc_map); 456 if (error) { 457 bus_dmamem_unmap(sc->sc_dmat, sc->sc_desc, PAGE_SIZE); 458 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, rseg); 459 return error; 460 } 461 error = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_map, 462 sc->sc_desc, PAGE_SIZE, NULL, BUS_DMA_WAITOK | BUS_DMA_WRITE); 463 if (error) { 464 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_map); 465 bus_dmamem_unmap(sc->sc_dmat, sc->sc_desc, PAGE_SIZE); 466 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, rseg); 467 return error; 468 } 469 470 return 0; 471 } 472 473 void 474 dwmmc_init_descriptors32(struct dwmmc_softc *sc) 475 { 476 struct dwmmc_desc32 *desc; 477 bus_addr_t addr; 478 int i; 479 480 desc = (void *)sc->sc_desc; 481 addr = sc->sc_desc_map->dm_segs[0].ds_addr; 482 for (i = 0; i < DWMMC_NDESC; i++) { 483 addr += sizeof(struct dwmmc_desc32); 484 desc[i].des[3] = addr; 485 } 486 desc[DWMMC_NDESC - 1].des[3] = sc->sc_desc_map->dm_segs[0].ds_addr; 487 desc[DWMMC_NDESC - 1].des[0] = DES0_ER; 488 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, 489 PAGE_SIZE, BUS_DMASYNC_PREWRITE); 490 491 HWRITE4(sc, SDMMC_IDSTS32, 0xffffffff); 492 HWRITE4(sc, SDMMC_IDINTEN32, 493 SDMMC_IDINTEN_NI | SDMMC_IDINTEN_RI | SDMMC_IDINTEN_TI); 494 HWRITE4(sc, SDMMC_DBADDR, sc->sc_desc_map->dm_segs[0].ds_addr); 495 } 496 497 void 498 dwmmc_init_descriptors64(struct dwmmc_softc *sc) 499 { 500 struct dwmmc_desc64 *desc; 501 bus_addr_t addr; 502 int i; 503 504 desc = (void *)sc->sc_desc; 505 addr = sc->sc_desc_map->dm_segs[0].ds_addr; 506 for (i = 0; i < DWMMC_NDESC; i++) { 507 addr += sizeof(struct dwmmc_desc64); 508 desc[i].des[6] = addr; 509 desc[i].des[7] = (uint64_t)addr >> 32; 510 } 511 desc[DWMMC_NDESC - 1].des[6] = sc->sc_desc_map->dm_segs[0].ds_addr; 512 desc[DWMMC_NDESC - 1].des[7] = 513 (uint64_t)sc->sc_desc_map->dm_segs[0].ds_addr >> 32; 514 desc[DWMMC_NDESC - 1].des[0] = DES0_ER; 515 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, 516 PAGE_SIZE, BUS_DMASYNC_PREWRITE); 517 518 HWRITE4(sc, SDMMC_IDSTS64, 0xffffffff); 519 HWRITE4(sc, SDMMC_IDINTEN64, 520 SDMMC_IDINTEN_NI | SDMMC_IDINTEN_RI | SDMMC_IDINTEN_TI); 521 HWRITE4(sc, SDMMC_DBADDRL, sc->sc_desc_map->dm_segs[0].ds_addr); 522 HWRITE4(sc, SDMMC_DBADDRH, 523 (uint64_t)sc->sc_desc_map->dm_segs[0].ds_addr >> 32); 524 } 525 526 void 527 dwmmc_init_descriptors(struct dwmmc_softc *sc) 528 { 529 if (sc->sc_dma64) 530 dwmmc_init_descriptors64(sc); 531 else 532 dwmmc_init_descriptors32(sc); 533 } 534 535 int 536 dwmmc_intr(void *arg) 537 { 538 struct dwmmc_softc *sc = arg; 539 uint32_t stat; 540 int handled = 0; 541 542 stat = HREAD4(sc, SDMMC_IDSTS(sc)); 543 if (stat) { 544 HWRITE4(sc, SDMMC_IDSTS(sc), stat); 545 sc->sc_idsts |= stat; 546 wakeup(&sc->sc_idsts); 547 handled = 1; 548 } 549 550 stat = HREAD4(sc, SDMMC_MINTSTS); 551 if (stat & SDMMC_RINTSTS_SDIO) { 552 HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_SDIO); 553 HCLR4(sc, SDMMC_INTMASK, SDMMC_RINTSTS_SDIO); 554 sdmmc_card_intr(sc->sc_sdmmc); 555 handled = 1; 556 } 557 558 return handled; 559 } 560 561 void 562 dwmmc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable) 563 { 564 struct dwmmc_softc *sc = sch; 565 566 if (enable) 567 HSET4(sc, SDMMC_INTMASK, SDMMC_RINTSTS_SDIO); 568 else 569 HCLR4(sc, SDMMC_INTMASK, SDMMC_RINTSTS_SDIO); 570 } 571 572 void 573 dwmmc_card_intr_ack(sdmmc_chipset_handle_t sch) 574 { 575 struct dwmmc_softc *sc = sch; 576 577 HSET4(sc, SDMMC_INTMASK, SDMMC_RINTSTS_SDIO); 578 } 579 580 int 581 dwmmc_host_reset(sdmmc_chipset_handle_t sch) 582 { 583 printf("%s\n", __func__); 584 return 0; 585 } 586 587 uint32_t 588 dwmmc_host_ocr(sdmmc_chipset_handle_t sch) 589 { 590 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V; 591 } 592 593 int 594 dwmmc_host_maxblklen(sdmmc_chipset_handle_t sch) 595 { 596 return 512; 597 } 598 599 int 600 dwmmc_card_detect(sdmmc_chipset_handle_t sch) 601 { 602 struct dwmmc_softc *sc = sch; 603 uint32_t cdetect; 604 605 if (OF_getproplen(sc->sc_node, "non-removable") == 0) 606 return 1; 607 608 if (sc->sc_gpio[0]) { 609 int inverted, val; 610 611 val = gpio_controller_get_pin(sc->sc_gpio); 612 613 inverted = (OF_getproplen(sc->sc_node, "cd-inverted") == 0); 614 return inverted ? !val : val; 615 } 616 617 cdetect = HREAD4(sc, SDMMC_CDETECT); 618 return !(cdetect & SDMMC_CDETECT_CARD_DETECT_0); 619 } 620 621 int 622 dwmmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 623 { 624 struct dwmmc_softc *sc = sch; 625 uint32_t vdd = 0; 626 627 if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) 628 vdd = 3300000; 629 630 if (sc->sc_vdd == 0 && vdd > 0) 631 dwmmc_pwrseq_pre(sc->sc_pwrseq); 632 633 if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) 634 HSET4(sc, SDMMC_PWREN, 1); 635 else 636 HCLR4(sc, SDMMC_PWREN, 0); 637 638 if (sc->sc_vdd == 0 && vdd > 0) 639 dwmmc_pwrseq_post(sc->sc_pwrseq); 640 641 sc->sc_vdd = vdd; 642 return 0; 643 } 644 645 int 646 dwmmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing) 647 { 648 struct dwmmc_softc *sc = sch; 649 int div = 0, timeout; 650 uint32_t clkena; 651 652 HWRITE4(sc, SDMMC_CLKENA, 0); 653 HWRITE4(sc, SDMMC_CLKSRC, 0); 654 655 if (freq == 0) 656 return 0; 657 658 if (sc->sc_clkbase / 1000 > freq) { 659 for (div = 1; div < 256; div++) 660 if (sc->sc_clkbase / (2 * 1000 * div) <= freq) 661 break; 662 } 663 HWRITE4(sc, SDMMC_CLKDIV, div); 664 665 /* Update clock. */ 666 HWRITE4(sc, SDMMC_CMD, SDMMC_CMD_START_CMD | 667 SDMMC_CMD_WAIT_PRVDATA_COMPLETE | 668 SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY); 669 for (timeout = 1000; timeout > 0; timeout--) { 670 if ((HREAD4(sc, SDMMC_CMD) & SDMMC_CMD_START_CMD) == 0) 671 break; 672 } 673 if (timeout == 0) { 674 printf("%s: timeout\n", __func__); 675 return ETIMEDOUT; 676 } 677 678 /* Enable clock; low power mode only for memory mode. */ 679 clkena = SDMMC_CLKENA_CCLK_ENABLE; 680 if (!sc->sc_sdio_irq) 681 clkena |= SDMMC_CLKENA_CCLK_LOW_POWER; 682 HWRITE4(sc, SDMMC_CLKENA, clkena); 683 684 /* Update clock again. */ 685 HWRITE4(sc, SDMMC_CMD, SDMMC_CMD_START_CMD | 686 SDMMC_CMD_WAIT_PRVDATA_COMPLETE | 687 SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY); 688 for (timeout = 1000; timeout > 0; timeout--) { 689 if ((HREAD4(sc, SDMMC_CMD) & SDMMC_CMD_START_CMD) == 0) 690 break; 691 } 692 if (timeout == 0) { 693 printf("%s: timeout\n", __func__); 694 return ETIMEDOUT; 695 } 696 697 delay(1000000); 698 699 return 0; 700 } 701 702 int 703 dwmmc_bus_width(sdmmc_chipset_handle_t sch, int width) 704 { 705 struct dwmmc_softc *sc = sch; 706 707 switch (width) { 708 case 1: 709 HCLR4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT|SDMMC_CTYPE_4BIT); 710 break; 711 case 4: 712 HSET4(sc, SDMMC_CTYPE, SDMMC_CTYPE_4BIT); 713 HCLR4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT); 714 break; 715 case 8: 716 HSET4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT); 717 break; 718 default: 719 return EINVAL; 720 } 721 722 return 0; 723 } 724 725 void 726 dwmmc_pio_mode(struct dwmmc_softc *sc) 727 { 728 /* Disable DMA. */ 729 HCLR4(sc, SDMMC_CTRL, SDMMC_CTRL_USE_INTERNAL_DMAC | 730 SDMMC_CTRL_DMA_ENABLE); 731 732 /* Set FIFO thresholds. */ 733 HWRITE4(sc, SDMMC_FIFOTH, 2 << SDMMC_FIFOTH_MSIZE_SHIFT | 734 (sc->sc_fifo_depth / 2 - 1) << SDMMC_FIFOTH_RXWM_SHIFT | 735 (sc->sc_fifo_depth / 2) << SDMMC_FIFOTH_TXWM_SHIFT); 736 737 sc->sc_dmamode = 0; 738 sc->sc_blklen = 0; 739 } 740 741 void 742 dwmmc_dma_mode(struct dwmmc_softc *sc) 743 { 744 int timeout; 745 746 /* Reset DMA. */ 747 HSET4(sc, SDMMC_BMOD, SDMMC_BMOD_SWR); 748 for (timeout = 1000; timeout > 0; timeout--) { 749 if ((HREAD4(sc, SDMMC_BMOD) & SDMMC_BMOD_SWR) == 0) 750 break; 751 delay(100); 752 } 753 if (timeout == 0) 754 printf("%s: DMA reset failed\n", sc->sc_dev.dv_xname); 755 756 /* Enable DMA. */ 757 HSET4(sc, SDMMC_CTRL, SDMMC_CTRL_USE_INTERNAL_DMAC | 758 SDMMC_CTRL_DMA_ENABLE); 759 HSET4(sc, SDMMC_BMOD, SDMMC_BMOD_FB | SDMMC_BMOD_DE); 760 761 sc->sc_dmamode = 1; 762 } 763 764 void 765 dwmmc_dma_setup32(struct dwmmc_softc *sc, struct sdmmc_command *cmd) 766 { 767 struct dwmmc_desc32 *desc = (void *)sc->sc_desc; 768 uint32_t flags; 769 int seg; 770 771 flags = DES0_OWN | DES0_FS | DES0_CH | DES0_DIC; 772 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 773 bus_addr_t addr = cmd->c_dmamap->dm_segs[seg].ds_addr; 774 bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len; 775 776 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 777 flags |= DES0_LD; 778 flags &= ~DES0_DIC; 779 } 780 781 KASSERT((desc[seg].des[0] & DES0_OWN) == 0); 782 desc[seg].des[0] = flags; 783 desc[seg].des[1] = DES1_BS1(len); 784 desc[seg].des[2] = addr; 785 flags &= ~DES0_FS; 786 } 787 } 788 789 void 790 dwmmc_dma_setup64(struct dwmmc_softc *sc, struct sdmmc_command *cmd) 791 { 792 struct dwmmc_desc64 *desc = (void *)sc->sc_desc; 793 uint32_t flags; 794 int seg; 795 796 flags = DES0_OWN | DES0_FS | DES0_CH | DES0_DIC; 797 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 798 bus_addr_t addr = cmd->c_dmamap->dm_segs[seg].ds_addr; 799 bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len; 800 801 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 802 flags |= DES0_LD; 803 flags &= ~DES0_DIC; 804 } 805 806 KASSERT((desc[seg].des[0] & DES0_OWN) == 0); 807 desc[seg].des[0] = flags; 808 desc[seg].des[2] = DES2_BS1(len); 809 desc[seg].des[4] = addr; 810 desc[seg].des[5] = (uint64_t)addr >> 32; 811 flags &= ~DES0_FS; 812 } 813 } 814 815 void 816 dwmmc_dma_setup(struct dwmmc_softc *sc, struct sdmmc_command *cmd) 817 { 818 if (sc->sc_dma64) 819 dwmmc_dma_setup64(sc, cmd); 820 else 821 dwmmc_dma_setup32(sc, cmd); 822 823 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, PAGE_SIZE, 824 BUS_DMASYNC_PREWRITE); 825 826 sc->sc_idsts = 0; 827 } 828 829 void 830 dwmmc_dma_reset(struct dwmmc_softc *sc, struct sdmmc_command *cmd) 831 { 832 int timeout; 833 834 /* Reset DMA unit. */ 835 HSET4(sc, SDMMC_BMOD, SDMMC_BMOD_SWR); 836 for (timeout = 1000; timeout > 0; timeout--) { 837 if ((HREAD4(sc, SDMMC_BMOD) & 838 SDMMC_BMOD_SWR) == 0) 839 break; 840 delay(100); 841 } 842 843 dwmmc_pio_mode(sc); 844 845 /* Clear descriptors that were in use, */ 846 memset(sc->sc_desc, 0, PAGE_SIZE); 847 dwmmc_init_descriptors(sc); 848 } 849 850 void 851 dwmmc_fifo_setup(struct dwmmc_softc *sc, int blklen) 852 { 853 int blkdepth = blklen / sc->sc_fifo_width; 854 int txwm = sc->sc_fifo_depth / 2; 855 int rxwm, msize = 0; 856 857 /* 858 * Bursting is only possible of the block size is a multiple of 859 * the FIFO width. 860 */ 861 if (blklen % sc->sc_fifo_width == 0) 862 msize = 7; 863 864 /* Magic to calculate the maximum burst size. */ 865 while (msize > 0) { 866 if (blkdepth % (2 << msize) == 0 && 867 (sc->sc_fifo_depth - txwm) % (2 << msize) == 0) 868 break; 869 msize--; 870 } 871 rxwm = (2 << msize) - 1; 872 873 HWRITE4(sc, SDMMC_FIFOTH, 874 msize << SDMMC_FIFOTH_MSIZE_SHIFT | 875 rxwm << SDMMC_FIFOTH_RXWM_SHIFT | 876 txwm << SDMMC_FIFOTH_TXWM_SHIFT); 877 878 sc->sc_blklen = blklen; 879 } 880 881 void 882 dwmmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 883 { 884 struct dwmmc_softc *sc = sch; 885 uint32_t cmdval = SDMMC_CMD_START_CMD | SDMMC_CMD_USE_HOLD_REG; 886 uint32_t status; 887 int error, timeout; 888 int s; 889 890 #if 0 891 printf("%s: cmd %d arg 0x%x flags 0x%x data %p datalen %d blklen %d\n", 892 sc->sc_dev.dv_xname, cmd->c_opcode, cmd->c_arg, cmd->c_flags, 893 cmd->c_data, cmd->c_datalen, cmd->c_blklen); 894 #endif 895 896 s = splbio(); 897 898 for (timeout = 10000; timeout > 0; timeout--) { 899 status = HREAD4(sc, SDMMC_STATUS); 900 if ((status & SDMMC_STATUS_DATA_BUSY) == 0) 901 break; 902 delay(100); 903 } 904 if (timeout == 0) { 905 printf("%s: timeout on data busy\n", sc->sc_dev.dv_xname); 906 goto done; 907 } 908 909 if (cmd->c_opcode == MMC_STOP_TRANSMISSION) 910 cmdval |= SDMMC_CMD_STOP_ABORT_CMD; 911 else if (cmd->c_opcode != MMC_SEND_STATUS) 912 cmdval |= SDMMC_CMD_WAIT_PRVDATA_COMPLETE; 913 914 if (cmd->c_opcode == 0) 915 cmdval |= SDMMC_CMD_SEND_INITIALIZATION; 916 if (cmd->c_flags & SCF_RSP_PRESENT) 917 cmdval |= SDMMC_CMD_RESPONSE_EXPECT; 918 if (cmd->c_flags & SCF_RSP_136) 919 cmdval |= SDMMC_CMD_RESPONSE_LENGTH; 920 if (cmd->c_flags & SCF_RSP_CRC) 921 cmdval |= SDMMC_CMD_CHECK_REPONSE_CRC; 922 923 if (cmd->c_datalen > 0) { 924 HWRITE4(sc, SDMMC_TMOUT, 0xffffffff); 925 HWRITE4(sc, SDMMC_BYTCNT, cmd->c_datalen); 926 HWRITE4(sc, SDMMC_BLKSIZ, cmd->c_blklen); 927 928 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 929 /* Set card read threshold to the size of a block. */ 930 HWRITE4(sc, SDMMC_CARDTHRCTL, 931 cmd->c_blklen << SDMMC_CARDTHRCTL_RDTHR_SHIFT | 932 SDMMC_CARDTHRCTL_RDTHREN); 933 } 934 935 cmdval |= SDMMC_CMD_DATA_EXPECTED; 936 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) 937 cmdval |= SDMMC_CMD_WR; 938 if (cmd->c_datalen > cmd->c_blklen && 939 cmd->c_opcode != SD_IO_RW_EXTENDED) 940 cmdval |= SDMMC_CMD_SEND_AUTO_STOP; 941 } 942 943 if (cmd->c_datalen > 0 && !cmd->c_dmamap) { 944 HSET4(sc, SDMMC_CTRL, SDMMC_CTRL_FIFO_RESET); 945 for (timeout = 1000; timeout > 0; timeout--) { 946 if ((HREAD4(sc, SDMMC_CTRL) & 947 SDMMC_CTRL_FIFO_RESET) == 0) 948 break; 949 delay(100); 950 } 951 if (timeout == 0) 952 printf("%s: FIFO reset failed\n", sc->sc_dev.dv_xname); 953 954 /* Disable DMA if we are switching back to PIO. */ 955 if (sc->sc_dmamode) 956 dwmmc_pio_mode(sc); 957 } 958 959 if (cmd->c_datalen > 0 && cmd->c_dmamap) { 960 dwmmc_dma_setup(sc, cmd); 961 HWRITE4(sc, SDMMC_PLDMND, 1); 962 963 /* Ennable DMA if we did PIO before. */ 964 if (!sc->sc_dmamode) 965 dwmmc_dma_mode(sc); 966 967 /* Reconfigure FIFO thresholds if block size changed. */ 968 if (cmd->c_blklen != sc->sc_blklen) 969 dwmmc_fifo_setup(sc, cmd->c_blklen); 970 } 971 972 HWRITE4(sc, SDMMC_RINTSTS, ~SDMMC_RINTSTS_SDIO); 973 974 HWRITE4(sc, SDMMC_CMDARG, cmd->c_arg); 975 HWRITE4(sc, SDMMC_CMD, cmdval | cmd->c_opcode); 976 977 for (timeout = 1000; timeout > 0; timeout--) { 978 status = HREAD4(sc, SDMMC_RINTSTS); 979 if (status & SDMMC_RINTSTS_CD) 980 break; 981 delay(100); 982 } 983 if (timeout == 0 || status & SDMMC_RINTSTS_RTO) { 984 cmd->c_error = ETIMEDOUT; 985 dwmmc_dma_reset(sc, cmd); 986 goto done; 987 } 988 989 if (cmd->c_flags & SCF_RSP_PRESENT) { 990 if (cmd->c_flags & SCF_RSP_136) { 991 cmd->c_resp[0] = HREAD4(sc, SDMMC_RESP0); 992 cmd->c_resp[1] = HREAD4(sc, SDMMC_RESP1); 993 cmd->c_resp[2] = HREAD4(sc, SDMMC_RESP2); 994 cmd->c_resp[3] = HREAD4(sc, SDMMC_RESP3); 995 if (cmd->c_flags & SCF_RSP_CRC) { 996 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 997 (cmd->c_resp[1] << 24); 998 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 999 (cmd->c_resp[2] << 24); 1000 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 1001 (cmd->c_resp[3] << 24); 1002 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 1003 } 1004 } else { 1005 cmd->c_resp[0] = HREAD4(sc, SDMMC_RESP0); 1006 } 1007 } 1008 1009 if (cmd->c_datalen > 0 && !cmd->c_dmamap) 1010 dwmmc_transfer_data(sc, cmd); 1011 1012 if (cmd->c_datalen > 0 && cmd->c_dmamap) { 1013 while (sc->sc_idsts == 0) { 1014 error = tsleep_nsec(&sc->sc_idsts, PWAIT, "idsts", 1015 SEC_TO_NSEC(1)); 1016 if (error) { 1017 cmd->c_error = error; 1018 dwmmc_dma_reset(sc, cmd); 1019 goto done; 1020 } 1021 } 1022 1023 for (timeout = 10000; timeout > 0; timeout--) { 1024 status = HREAD4(sc, SDMMC_RINTSTS); 1025 if (status & SDMMC_RINTSTS_DTO) 1026 break; 1027 delay(100); 1028 } 1029 if (timeout == 0) { 1030 cmd->c_error = ETIMEDOUT; 1031 dwmmc_dma_reset(sc, cmd); 1032 goto done; 1033 } 1034 } 1035 1036 if (cmdval & SDMMC_CMD_SEND_AUTO_STOP) { 1037 for (timeout = 10000; timeout > 0; timeout--) { 1038 status = HREAD4(sc, SDMMC_RINTSTS); 1039 if (status & SDMMC_RINTSTS_ACD) 1040 break; 1041 delay(10); 1042 } 1043 if (timeout == 0) { 1044 cmd->c_error = ETIMEDOUT; 1045 dwmmc_dma_reset(sc, cmd); 1046 goto done; 1047 } 1048 } 1049 1050 done: 1051 cmd->c_flags |= SCF_ITSDONE; 1052 #if 0 1053 printf("%s: err %d rintsts 0x%x\n", sc->sc_dev.dv_xname, cmd->c_error, 1054 HREAD4(sc, SDMMC_RINTSTS)); 1055 #endif 1056 splx(s); 1057 } 1058 1059 void 1060 dwmmc_transfer_data(struct dwmmc_softc *sc, struct sdmmc_command *cmd) 1061 { 1062 int datalen = cmd->c_datalen; 1063 u_char *datap = cmd->c_data; 1064 uint32_t status; 1065 int count, timeout; 1066 int fifodr = SDMMC_RINTSTS_DTO | SDMMC_RINTSTS_HTO; 1067 1068 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1069 fifodr |= SDMMC_RINTSTS_RXDR; 1070 else 1071 fifodr |= SDMMC_RINTSTS_TXDR; 1072 1073 while (datalen > 0) { 1074 status = HREAD4(sc, SDMMC_RINTSTS); 1075 if (status & SDMMC_RINTSTS_DATA_ERR) { 1076 cmd->c_error = EIO; 1077 return; 1078 } 1079 if (status & SDMMC_RINTSTS_DRTO) { 1080 cmd->c_error = ETIMEDOUT; 1081 return; 1082 } 1083 1084 for (timeout = 10000; timeout > 0; timeout--) { 1085 status = HREAD4(sc, SDMMC_RINTSTS); 1086 if (status & fifodr) 1087 break; 1088 delay(100); 1089 } 1090 if (timeout == 0) { 1091 cmd->c_error = ETIMEDOUT; 1092 return; 1093 } 1094 1095 count = SDMMC_STATUS_FIFO_COUNT(HREAD4(sc, SDMMC_STATUS)); 1096 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) 1097 count = sc->sc_fifo_depth - count; 1098 1099 count = MIN(datalen, count * sc->sc_fifo_width); 1100 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1101 sc->sc_read_data(sc, datap, count); 1102 else 1103 sc->sc_write_data(sc, datap, count); 1104 1105 datap += count; 1106 datalen -= count; 1107 } 1108 1109 for (timeout = 10000; timeout > 0; timeout--) { 1110 status = HREAD4(sc, SDMMC_RINTSTS); 1111 if (status & SDMMC_RINTSTS_DTO) 1112 break; 1113 delay(100); 1114 } 1115 if (timeout == 0) 1116 cmd->c_error = ETIMEDOUT; 1117 } 1118 1119 void 1120 dwmmc_read_data32(struct dwmmc_softc *sc, u_char *datap, int datalen) 1121 { 1122 while (datalen > 3) { 1123 *(uint32_t *)datap = HREAD4(sc, SDMMC_FIFO_BASE); 1124 datap += 4; 1125 datalen -= 4; 1126 } 1127 if (datalen > 0) { 1128 uint32_t rv = HREAD4(sc, SDMMC_FIFO_BASE); 1129 do { 1130 *datap++ = rv & 0xff; 1131 rv = rv >> 8; 1132 } while (--datalen > 0); 1133 } 1134 HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_RXDR); 1135 } 1136 1137 void 1138 dwmmc_write_data32(struct dwmmc_softc *sc, u_char *datap, int datalen) 1139 { 1140 while (datalen > 3) { 1141 HWRITE4(sc, SDMMC_FIFO_BASE, *((uint32_t *)datap)); 1142 datap += 4; 1143 datalen -= 4; 1144 } 1145 if (datalen > 0) { 1146 uint32_t rv = *datap++; 1147 if (datalen > 1) 1148 rv |= *datap++ << 8; 1149 if (datalen > 2) 1150 rv |= *datap++ << 16; 1151 HWRITE4(sc, SDMMC_FIFO_BASE, rv); 1152 } 1153 HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_TXDR); 1154 } 1155 1156 void 1157 dwmmc_read_data64(struct dwmmc_softc *sc, u_char *datap, int datalen) 1158 { 1159 while (datalen > 7) { 1160 *(uint32_t *)datap = HREAD4(sc, SDMMC_FIFO_BASE); 1161 datap += 4; 1162 datalen -= 4; 1163 *(uint32_t *)datap = HREAD4(sc, SDMMC_FIFO_BASE + 4); 1164 datap += 4; 1165 datalen -= 4; 1166 } 1167 if (datalen > 0) { 1168 uint64_t rv = HREAD4(sc, SDMMC_FIFO_BASE) | 1169 ((uint64_t)HREAD4(sc, SDMMC_FIFO_BASE + 4) << 32); 1170 do { 1171 *datap++ = rv & 0xff; 1172 rv = rv >> 8; 1173 } while (--datalen > 0); 1174 } 1175 HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_RXDR); 1176 } 1177 1178 void 1179 dwmmc_write_data64(struct dwmmc_softc *sc, u_char *datap, int datalen) 1180 { 1181 while (datalen > 7) { 1182 HWRITE4(sc, SDMMC_FIFO_BASE, *((uint32_t *)datap)); 1183 datap += 4; 1184 datalen -= 4; 1185 HWRITE4(sc, SDMMC_FIFO_BASE + 4, *((uint32_t *)datap)); 1186 datap += 4; 1187 datalen -= 4; 1188 } 1189 if (datalen > 0) { 1190 uint32_t rv = *datap++; 1191 if (datalen > 1) 1192 rv |= *datap++ << 8; 1193 if (datalen > 2) 1194 rv |= *datap++ << 16; 1195 if (datalen > 3) 1196 rv |= *datap++ << 24; 1197 HWRITE4(sc, SDMMC_FIFO_BASE, rv); 1198 if (datalen > 4) 1199 rv = *datap++; 1200 if (datalen > 5) 1201 rv |= *datap++ << 8; 1202 if (datalen > 6) 1203 rv |= *datap++ << 16; 1204 HWRITE4(sc, SDMMC_FIFO_BASE + 4, rv); 1205 } 1206 HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_TXDR); 1207 } 1208 1209 void 1210 dwmmc_pwrseq_pre(uint32_t phandle) 1211 { 1212 uint32_t *gpios, *gpio; 1213 int node; 1214 int len; 1215 1216 node = OF_getnodebyphandle(phandle); 1217 if (node == 0) 1218 return; 1219 1220 if (!OF_is_compatible(node, "mmc-pwrseq-simple")) 1221 return; 1222 1223 pinctrl_byname(node, "default"); 1224 1225 clock_enable(node, "ext_clock"); 1226 1227 len = OF_getproplen(node, "reset-gpios"); 1228 if (len <= 0) 1229 return; 1230 1231 gpios = malloc(len, M_TEMP, M_WAITOK); 1232 OF_getpropintarray(node, "reset-gpios", gpios, len); 1233 1234 gpio = gpios; 1235 while (gpio && gpio < gpios + (len / sizeof(uint32_t))) { 1236 gpio_controller_config_pin(gpio, GPIO_CONFIG_OUTPUT); 1237 gpio_controller_set_pin(gpio, 1); 1238 gpio = gpio_controller_next_pin(gpio); 1239 } 1240 1241 free(gpios, M_TEMP, len); 1242 } 1243 1244 void 1245 dwmmc_pwrseq_post(uint32_t phandle) 1246 { 1247 uint32_t *gpios, *gpio; 1248 int node; 1249 int len; 1250 1251 node = OF_getnodebyphandle(phandle); 1252 if (node == 0) 1253 return; 1254 1255 if (!OF_is_compatible(node, "mmc-pwrseq-simple")) 1256 return; 1257 1258 len = OF_getproplen(node, "reset-gpios"); 1259 if (len <= 0) 1260 return; 1261 1262 gpios = malloc(len, M_TEMP, M_WAITOK); 1263 OF_getpropintarray(node, "reset-gpios", gpios, len); 1264 1265 gpio = gpios; 1266 while (gpio && gpio < gpios + (len / sizeof(uint32_t))) { 1267 gpio_controller_set_pin(gpio, 0); 1268 gpio = gpio_controller_next_pin(gpio); 1269 } 1270 1271 free(gpios, M_TEMP, len); 1272 } 1273