1 /* Public Domain */ 2 3 /* 4 * RK3288 clocks. 5 */ 6 7 #define RK3288_PLL_APLL 1 8 #define RK3288_PLL_CPLL 3 9 #define RK3288_PLL_GPLL 4 10 #define RK3288_PLL_NPLL 5 11 #define RK3288_ARMCLK 6 12 13 #define RK3288_CLK_SDMMC 68 14 #define RK3288_CLK_TSADC 72 15 #define RK3288_CLK_UART0 77 16 #define RK3288_CLK_UART1 78 17 #define RK3288_CLK_UART2 79 18 #define RK3288_CLK_UART3 80 19 #define RK3288_CLK_UART4 81 20 #define RK3288_CLK_MAC_RX 102 21 #define RK3288_CLK_MAC_TX 103 22 #define RK3288_CLK_SDMMC_DRV 114 23 #define RK3288_CLK_SDMMC_SAMPLE 118 24 #define RK3288_CLK_MAC 151 25 26 #define RK3288_ACLK_GMAC 196 27 28 #define RK3288_PCLK_I2C0 332 29 #define RK3288_PCLK_I2C1 333 30 #define RK3288_PCLK_I2C2 334 31 #define RK3288_PCLK_I2C3 335 32 #define RK3288_PCLK_I2C4 336 33 #define RK3288_PCLK_I2C5 337 34 #define RK3288_PCLK_TSADC 346 35 #define RK3288_PCLK_GMAC 349 36 37 #define RK3288_HCLK_HOST0 450 38 #define RK3288_HCLK_SDMMC 456 39 40 #define RK3288_XIN24M 1023 41 42 /* 43 * RK3328 clocks. 44 */ 45 46 #define RK3328_PLL_APLL 1 47 #define RK3328_PLL_DPLL 2 48 #define RK3328_PLL_CPLL 3 49 #define RK3328_PLL_GPLL 4 50 #define RK3328_PLL_NPLL 5 51 #define RK3328_ARMCLK 6 52 53 #define RK3328_CLK_RTC32K 30 54 #define RK3328_CLK_SDMMC 33 55 #define RK3328_CLK_SDIO 34 56 #define RK3328_CLK_EMMC 35 57 #define RK3328_CLK_TSADC 36 58 #define RK3328_CLK_UART0 38 59 #define RK3328_CLK_UART1 39 60 #define RK3328_CLK_UART2 40 61 #define RK3328_CLK_WIFI 53 62 #define RK3328_CLK_I2C0 55 63 #define RK3328_CLK_I2C1 56 64 #define RK3328_CLK_I2C2 57 65 #define RK3328_CLK_I2C3 58 66 #define RK3328_CLK_CRYPTO 59 67 #define RK3328_CLK_PDM 61 68 #define RK3328_CLK_VDEC_CABAC 65 69 #define RK3328_CLK_VDEC_CORE 66 70 #define RK3328_CLK_VENC_DSP 67 71 #define RK3328_CLK_VENC_CORE 68 72 #define RK3328_CLK_TSP 92 73 #define RK3328_CLK_MAC2IO_SRC 99 74 #define RK3328_CLK_MAC2IO 100 75 #define RK3328_CLK_MAC2IO_EXT 102 76 77 #define RK3328_DCLK_LCDC 120 78 #define RK3328_HDMIPHY 122 79 #define RK3328_USB480M 123 80 #define RK3328_DCLK_LCDC_SRC 124 81 82 #define RK3328_ACLK_VOP_PRE 131 83 #define RK3328_ACLK_RGA_PRE 133 84 #define RK3328_ACLK_BUS_PRE 136 85 #define RK3328_ACLK_PERI_PRE 137 86 #define RK3328_ACLK_RKVDEC_PRE 138 87 #define RK3328_ACLK_RKVENC 140 88 #define RK3328_ACLK_VPU_PRE 141 89 #define RK3328_ACLK_VIO_PRE 142 90 91 #define RK3328_PCLK_BUS_PRE 216 92 #define RK3328_PCLK_PERI 230 93 94 #define RK3328_HCLK_PERI 308 95 #define RK3328_HCLK_BUS_PRE 328 96 #define RK3328_HCLK_CRYPTO_SLV 337 97 98 #define RK3328_XIN24M 1023 99 #define RK3328_CLK_24M 1022 100 #define RK3328_GMAC_CLKIN 1021 101 102 /* 103 * RK3399 clocks. 104 */ 105 106 #define RK3399_PLL_ALPLL 1 107 #define RK3399_PLL_ABPLL 2 108 #define RK3399_PLL_DPLL 3 109 #define RK3399_PLL_CPLL 4 110 #define RK3399_PLL_GPLL 5 111 #define RK3399_PLL_NPLL 6 112 #define RK3399_PLL_VPLL 7 113 #define RK3399_ARMCLKL 8 114 #define RK3399_ARMCLKB 9 115 116 #define RK3399_CLK_I2C1 65 117 #define RK3399_CLK_I2C2 66 118 #define RK3399_CLK_I2C3 67 119 #define RK3399_CLK_I2C5 68 120 #define RK3399_CLK_I2C6 69 121 #define RK3399_CLK_I2C7 70 122 #define RK3399_CLK_SDMMC 76 123 #define RK3399_CLK_SDIO 77 124 #define RK3399_CLK_EMMC 78 125 #define RK3399_CLK_TSADC 79 126 #define RK3399_CLK_UART0 81 127 #define RK3399_CLK_UART1 82 128 #define RK3399_CLK_UART2 83 129 #define RK3399_CLK_UART3 84 130 #define RK3399_CLK_SPDIF_8CH 85 131 #define RK3399_CLK_I2S0_8CH 86 132 #define RK3399_CLK_I2S1_8CH 87 133 #define RK3399_CLK_I2S2_8CH 88 134 #define RK3399_CLK_I2S_8CH_OUT 89 135 #define RK3399_CLK_MAC_RX 103 136 #define RK3399_CLK_MAC_TX 104 137 #define RK3399_CLK_MAC 105 138 #define RK3399_CLK_USB3OTG0_REF 129 139 #define RK3399_CLK_USB3OTG1_REF 130 140 #define RK3399_CLK_USB3OTG0_SUSPEND 131 141 #define RK3399_CLK_USB3OTG1_SUSPEND 132 142 #define RK3399_CLK_SDMMC_DRV 154 143 #define RK3399_CLK_SDMMC_SAMPLE 155 144 145 #define RK3399_DCLK_VOP0 180 146 #define RK3399_DCLK_VOP1 181 147 #define RK3399_DCLK_VOP0_DIV 182 148 #define RK3399_DCLK_VOP1_DIV 183 149 #define RK3399_DCLK_VOP0_FRAC 185 150 #define RK3399_DCLK_VOP1_FRAC 186 151 152 #define RK3399_ACLK_PERIPH 192 153 #define RK3399_ACLK_PERILP0 194 154 #define RK3399_ACLK_CCI 201 155 #define RK3399_ACLK_GMAC 213 156 #define RK3399_ACLK_VOP0_NOC 216 157 #define RK3399_ACLK_VOP0 217 158 #define RK3399_ACLK_VOP1_NOC 218 159 #define RK3399_ACLK_VOP1 219 160 #define RK3399_ACLK_HDCP 222 161 #define RK3399_ACLK_VIO 227 162 #define RK3399_ACLK_EMMC 240 163 #define RK3399_ACLK_USB3OTG0 246 164 #define RK3399_ACLK_USB3OTG1 247 165 #define RK3399_ACLK_USB3_GRF 249 166 #define RK3399_ACLK_GIC_PRE 262 167 168 #define RK3399_PCLK_PERIPH 320 169 #define RK3399_PCLK_PERILP0 322 170 #define RK3399_PCLK_PERILP1 323 171 #define RK3399_PCLK_I2C1 341 172 #define RK3399_PCLK_I2C2 342 173 #define RK3399_PCLK_I2C3 343 174 #define RK3399_PCLK_I2C5 344 175 #define RK3399_PCLK_I2C6 345 176 #define RK3399_PCLK_I2C7 346 177 #define RK3399_PCLK_TSADC 356 178 #define RK3399_PCLK_GMAC 358 179 #define RK3399_PCLK_DDR 376 180 181 #define RK3399_HCLK_PERIPH 448 182 #define RK3399_HCLK_PERILP0 449 183 #define RK3399_HCLK_PERILP1 450 184 #define RK3399_HCLK_HOST0 456 185 #define RK3399_HCLK_HOST0_ARB 457 186 #define RK3399_HCLK_HOST1 458 187 #define RK3399_HCLK_HOST1_ARB 459 188 #define RK3399_HCLK_SDMMC 462 189 #define RK3399_HCLK_VOP0_NOC 472 190 #define RK3399_HCLK_VOP0 473 191 #define RK3399_HCLK_VOP1_NOC 474 192 #define RK3399_HCLK_VOP1 475 193 194 /* PMUCRU */ 195 196 #define RK3399_PLL_PPLL 1 197 198 #define RK3399_CLK_I2C0 9 199 #define RK3399_CLK_I2C4 10 200 #define RK3399_CLK_I2C8 11 201 202 #define RK3399_PCLK_I2C0 27 203 #define RK3399_PCLK_I2C4 28 204 #define RK3399_PCLK_I2C8 29 205 #define RK3399_PCLK_RKPWM 30 206 207 #define RK3399_XIN24M 1023 208 #define RK3399_CLK_32K 1022 209 #define RK3399_XIN12M 1021 210 #define RK3399_CLK_I2S0_DIV 1020 211 #define RK3399_CLK_I2S1_DIV 1019 212 #define RK3399_CLK_I2S2_DIV 1018 213 #define RK3399_CLK_I2SOUT_SRC 1017 214