1 /* Public Domain */ 2 3 /* 4 * RK3288 clocks. 5 */ 6 7 #define RK3288_PLL_APLL 1 8 #define RK3288_PLL_CPLL 3 9 #define RK3288_PLL_GPLL 4 10 #define RK3288_PLL_NPLL 5 11 #define RK3288_ARMCLK 6 12 13 #define RK3288_CLK_SDMMC 68 14 #define RK3288_CLK_TSADC 72 15 #define RK3288_CLK_UART0 77 16 #define RK3288_CLK_UART1 78 17 #define RK3288_CLK_UART2 79 18 #define RK3288_CLK_UART3 80 19 #define RK3288_CLK_UART4 81 20 #define RK3288_CLK_MAC_RX 102 21 #define RK3288_CLK_MAC_TX 103 22 #define RK3288_CLK_SDMMC_DRV 114 23 #define RK3288_CLK_SDMMC_SAMPLE 118 24 #define RK3288_CLK_MAC 151 25 26 #define RK3288_ACLK_GMAC 196 27 28 #define RK3288_PCLK_I2C0 332 29 #define RK3288_PCLK_I2C1 333 30 #define RK3288_PCLK_I2C2 334 31 #define RK3288_PCLK_I2C3 335 32 #define RK3288_PCLK_I2C4 336 33 #define RK3288_PCLK_I2C5 337 34 #define RK3288_PCLK_TSADC 346 35 #define RK3288_PCLK_GMAC 349 36 37 #define RK3288_HCLK_HOST0 450 38 #define RK3288_HCLK_SDMMC 456 39 40 #define RK3288_XIN24M 1023 41 42 /* 43 * RK3308 clocks. 44 */ 45 46 #define RK3308_PLL_APLL 1 47 #define RK3308_PLL_DPLL 2 48 #define RK3308_PLL_VPLL0 3 49 #define RK3308_PLL_VPLL1 4 50 #define RK3308_ARMCLK 5 51 52 #define RK3308_USB480M 14 53 #define RK3308_CLK_RTC32K 15 54 #define RK3308_CLK_UART0 17 55 #define RK3308_CLK_UART1 18 56 #define RK3308_CLK_UART2 19 57 #define RK3308_CLK_UART3 20 58 #define RK3308_CLK_UART4 21 59 #define RK3308_CLK_PWM0 26 60 #define RK3308_CLK_TSADC 36 61 #define RK3308_CLK_SARADC 37 62 #define RK3308_CLK_CRYPTO 41 63 #define RK3308_CLK_CRYPTO_APK 42 64 #define RK3308_CLK_SDMMC 48 65 #define RK3308_CLK_SDMMC_DRV 49 66 #define RK3308_CLK_SDMMC_SAMPLE 50 67 #define RK3308_CLK_SDIO 53 68 #define RK3308_CLK_SDIO_DRV 54 69 #define RK3308_CLK_SDIO_SAMPLE 55 70 #define RK3308_CLK_EMMC 58 71 #define RK3308_CLK_MAC_SRC 63 72 #define RK3308_CLK_MAC 64 73 #define RK3308_CLK_MAC_RMII 67 74 75 #define RK3308_ACLK_BUS_SRC 130 76 #define RK3308_ACLK_BUS 131 77 #define RK3308_ACLK_PERI_SRC 132 78 #define RK3308_ACLK_PERI 133 79 #define RK3308_ACLK_MAC 134 80 #define RK3308_ACLK_CRYPTO 135 81 #define RK3308_ACLK_GIC 137 82 83 #define RK3308_HCLK_BUS 150 84 #define RK3308_HCLK_PERI 151 85 #define RK3308_HCLK_SDMMC 154 86 #define RK3308_HCLK_CRYPTO 171 87 88 #define RK3308_PCLK_BUS 190 89 #define RK3308_PCLK_PERI 192 90 #define RK3308_PCLK_MAC 195 91 92 #define RK3308_XIN24M 1023 93 94 /* 95 * RK3328 clocks. 96 */ 97 98 #define RK3328_PLL_APLL 1 99 #define RK3328_PLL_DPLL 2 100 #define RK3328_PLL_CPLL 3 101 #define RK3328_PLL_GPLL 4 102 #define RK3328_PLL_NPLL 5 103 #define RK3328_ARMCLK 6 104 105 #define RK3328_CLK_RTC32K 30 106 #define RK3328_CLK_SDMMC 33 107 #define RK3328_CLK_SDIO 34 108 #define RK3328_CLK_EMMC 35 109 #define RK3328_CLK_TSADC 36 110 #define RK3328_CLK_UART0 38 111 #define RK3328_CLK_UART1 39 112 #define RK3328_CLK_UART2 40 113 #define RK3328_CLK_WIFI 53 114 #define RK3328_CLK_I2C0 55 115 #define RK3328_CLK_I2C1 56 116 #define RK3328_CLK_I2C2 57 117 #define RK3328_CLK_I2C3 58 118 #define RK3328_CLK_CRYPTO 59 119 #define RK3328_CLK_PDM 61 120 #define RK3328_CLK_VDEC_CABAC 65 121 #define RK3328_CLK_VDEC_CORE 66 122 #define RK3328_CLK_VENC_DSP 67 123 #define RK3328_CLK_VENC_CORE 68 124 #define RK3328_CLK_TSP 92 125 #define RK3328_CLK_MAC2IO_SRC 99 126 #define RK3328_CLK_MAC2IO 100 127 #define RK3328_CLK_MAC2IO_EXT 102 128 129 #define RK3328_DCLK_LCDC 120 130 #define RK3328_HDMIPHY 122 131 #define RK3328_USB480M 123 132 #define RK3328_DCLK_LCDC_SRC 124 133 134 #define RK3328_ACLK_VOP_PRE 131 135 #define RK3328_ACLK_RGA_PRE 133 136 #define RK3328_ACLK_BUS_PRE 136 137 #define RK3328_ACLK_PERI_PRE 137 138 #define RK3328_ACLK_RKVDEC_PRE 138 139 #define RK3328_ACLK_RKVENC 140 140 #define RK3328_ACLK_VPU_PRE 141 141 #define RK3328_ACLK_VIO_PRE 142 142 143 #define RK3328_PCLK_BUS_PRE 216 144 #define RK3328_PCLK_PERI 230 145 146 #define RK3328_HCLK_PERI 308 147 #define RK3328_HCLK_BUS_PRE 328 148 #define RK3328_HCLK_CRYPTO_SLV 337 149 150 #define RK3328_XIN24M 1023 151 #define RK3328_CLK_24M 1022 152 #define RK3328_GMAC_CLKIN 1021 153 154 /* 155 * RK3399 clocks. 156 */ 157 158 #define RK3399_PLL_ALPLL 1 159 #define RK3399_PLL_ABPLL 2 160 #define RK3399_PLL_DPLL 3 161 #define RK3399_PLL_CPLL 4 162 #define RK3399_PLL_GPLL 5 163 #define RK3399_PLL_NPLL 6 164 #define RK3399_PLL_VPLL 7 165 #define RK3399_ARMCLKL 8 166 #define RK3399_ARMCLKB 9 167 168 #define RK3399_CLK_I2C1 65 169 #define RK3399_CLK_I2C2 66 170 #define RK3399_CLK_I2C3 67 171 #define RK3399_CLK_I2C5 68 172 #define RK3399_CLK_I2C6 69 173 #define RK3399_CLK_I2C7 70 174 #define RK3399_CLK_SDMMC 76 175 #define RK3399_CLK_SDIO 77 176 #define RK3399_CLK_EMMC 78 177 #define RK3399_CLK_TSADC 79 178 #define RK3399_CLK_UART0 81 179 #define RK3399_CLK_UART1 82 180 #define RK3399_CLK_UART2 83 181 #define RK3399_CLK_UART3 84 182 #define RK3399_CLK_SPDIF_8CH 85 183 #define RK3399_CLK_I2S0_8CH 86 184 #define RK3399_CLK_I2S1_8CH 87 185 #define RK3399_CLK_I2S2_8CH 88 186 #define RK3399_CLK_I2S_8CH_OUT 89 187 #define RK3399_CLK_MAC_RX 103 188 #define RK3399_CLK_MAC_TX 104 189 #define RK3399_CLK_MAC 105 190 #define RK3399_CLK_USB2PHY0_REF 123 191 #define RK3399_CLK_USB2PHY1_REF 124 192 #define RK3399_CLK_UPHY0_TCPDPHY_REF 125 193 #define RK3399_CLK_UPHY0_TCPDCORE 126 194 #define RK3399_CLK_UPHY1_TCPDPHY_REF 127 195 #define RK3399_CLK_UPHY1_TCPDCORE 128 196 #define RK3399_CLK_USB3OTG0_REF 129 197 #define RK3399_CLK_USB3OTG1_REF 130 198 #define RK3399_CLK_USB3OTG0_SUSPEND 131 199 #define RK3399_CLK_USB3OTG1_SUSPEND 132 200 #define RK3399_CLK_PCIEPHY_REF 138 201 #define RK3399_CLK_SDMMC_DRV 154 202 #define RK3399_CLK_SDMMC_SAMPLE 155 203 #define RK3399_CLK_PCIEPHY_REF100M 167 204 205 #define RK3399_DCLK_VOP0 180 206 #define RK3399_DCLK_VOP1 181 207 #define RK3399_DCLK_VOP0_DIV 182 208 #define RK3399_DCLK_VOP1_DIV 183 209 #define RK3399_DCLK_VOP0_FRAC 185 210 #define RK3399_DCLK_VOP1_FRAC 186 211 212 #define RK3399_ACLK_PERIPH 192 213 #define RK3399_ACLK_PERILP0 194 214 #define RK3399_ACLK_CCI 201 215 #define RK3399_ACLK_GMAC 213 216 #define RK3399_ACLK_VOP0_NOC 216 217 #define RK3399_ACLK_VOP0 217 218 #define RK3399_ACLK_VOP1_NOC 218 219 #define RK3399_ACLK_VOP1 219 220 #define RK3399_ACLK_HDCP 222 221 #define RK3399_ACLK_VIO 227 222 #define RK3399_ACLK_EMMC 240 223 #define RK3399_ACLK_USB3OTG0 246 224 #define RK3399_ACLK_USB3OTG1 247 225 #define RK3399_ACLK_USB3_GRF 249 226 #define RK3399_ACLK_GIC_PRE 262 227 228 #define RK3399_PCLK_PERIPH 320 229 #define RK3399_PCLK_PERILP0 322 230 #define RK3399_PCLK_PERILP1 323 231 #define RK3399_PCLK_I2C1 341 232 #define RK3399_PCLK_I2C2 342 233 #define RK3399_PCLK_I2C3 343 234 #define RK3399_PCLK_I2C5 344 235 #define RK3399_PCLK_I2C6 345 236 #define RK3399_PCLK_I2C7 346 237 #define RK3399_PCLK_TSADC 356 238 #define RK3399_PCLK_GMAC 358 239 #define RK3399_PCLK_DDR 376 240 #define RK3399_PCLK_WDT 380 241 242 #define RK3399_HCLK_PERIPH 448 243 #define RK3399_HCLK_PERILP0 449 244 #define RK3399_HCLK_PERILP1 450 245 #define RK3399_HCLK_HOST0 456 246 #define RK3399_HCLK_HOST0_ARB 457 247 #define RK3399_HCLK_HOST1 458 248 #define RK3399_HCLK_HOST1_ARB 459 249 #define RK3399_HCLK_SDMMC 462 250 #define RK3399_HCLK_VOP0_NOC 472 251 #define RK3399_HCLK_VOP0 473 252 #define RK3399_HCLK_VOP1_NOC 474 253 #define RK3399_HCLK_VOP1 475 254 255 /* PMUCRU */ 256 257 #define RK3399_PLL_PPLL 1 258 259 #define RK3399_CLK_I2C0 9 260 #define RK3399_CLK_I2C4 10 261 #define RK3399_CLK_I2C8 11 262 263 #define RK3399_PCLK_I2C0 27 264 #define RK3399_PCLK_I2C4 28 265 #define RK3399_PCLK_I2C8 29 266 #define RK3399_PCLK_RKPWM 30 267 268 #define RK3399_XIN24M 1023 269 #define RK3399_CLK_32K 1022 270 #define RK3399_XIN12M 1021 271 #define RK3399_CLK_I2S0_DIV 1020 272 #define RK3399_CLK_I2S0_FRAC 1019 273 #define RK3399_CLK_I2S1_DIV 1018 274 #define RK3399_CLK_I2S1_FRAC 1017 275 #define RK3399_CLK_I2S2_DIV 1016 276 #define RK3399_CLK_I2S2_FRAC 1015 277 #define RK3399_CLK_I2SOUT_SRC 1014 278 279 /* 280 * RK3568 clocks. 281 */ 282 283 #define RK3568_PLL_APLL 1 284 #define RK3568_PLL_DPLL 2 285 #define RK3568_PLL_CPLL 3 286 #define RK3568_PLL_GPLL 4 287 #define RK3568_PLL_VPLL 5 288 #define RK3568_PLL_NPLL 6 289 290 #define RK3568_ACLK_EMMC 121 291 #define RK3568_HCLK_EMMC 122 292 #define RK3568_BCLK_EMMC 123 293 #define RK3568_CCLK_EMMC 124 294 #define RK3568_TCLK_EMMC 125 295 #define RK3568_ACLK_PHP 173 296 #define RK3568_PCLK_PHP 175 297 #define RK3568_CLK_SDMMC0 177 298 #define RK3568_CLK_SDMMC1 179 299 #define RK3568_ACLK_GMAC0 180 300 #define RK3568_PCLK_GMAC0 181 301 #define RK3568_CLK_MAC0_2TOP 182 302 #define RK3568_CLK_MAC0_REFOUT 184 303 #define RK3568_CLK_GMAC0_PTP_REF 185 304 #define RK3568_ACLK_USB 186 305 #define RK3568_PCLK_USB 188 306 #define RK3568_CLK_SDMMC2 194 307 #define RK3568_ACLK_GMAC1 195 308 #define RK3568_PCLK_GMAC1 196 309 #define RK3568_CLK_MAC1_2TOP 197 310 #define RK3568_CLK_MAC1_REFOUT 199 311 #define RK3568_CLK_GMAC1_PTP_REF 200 312 #define RK3568_CLK_TSADC_TSEN 272 313 #define RK3568_CLK_TSADC 273 314 #define RK3568_SCLK_UART1 287 315 #define RK3568_SCLK_UART2 291 316 #define RK3568_SCLK_UART3 295 317 #define RK3568_SCLK_UART4 299 318 #define RK3568_SCLK_UART5 303 319 #define RK3568_SCLK_UART6 307 320 #define RK3568_SCLK_UART7 311 321 #define RK3568_SCLK_UART8 315 322 #define RK3568_SCLK_UART9 319 323 #define RK3568_CLK_I2C 326 324 #define RK3568_CLK_I2C1 328 325 #define RK3568_CLK_I2C2 330 326 #define RK3568_CLK_I2C3 332 327 #define RK3568_CLK_I2C4 334 328 #define RK3568_CLK_I2C5 336 329 #define RK3568_SCLK_GMAC0 386 330 #define RK3568_SCLK_GMAC0_RGMII_SPEED 387 331 #define RK3568_SCLK_GMAC0_RMII_SPEED 388 332 #define RK3568_SCLK_GMAC0_RX_TX 389 333 #define RK3568_SCLK_GMAC1 390 334 #define RK3568_SCLK_GMAC1_RGMII_SPEED 391 335 #define RK3568_SCLK_GMAC1_RMII_SPEED 392 336 #define RK3568_SCLK_GMAC1_RX_TX 393 337 338 #define RK3568_CPLL_125M 413 339 #define RK3568_CPLL_62P5M 414 340 #define RK3568_CPLL_50M 415 341 #define RK3568_CPLL_25M 416 342 #define RK3568_CPLL_100M 417 343 344 #define RK3568_SCLK_GMAC0_DIV_50 1005 345 #define RK3568_SCLK_GMAC0_DIV_5 1006 346 #define RK3568_SCLK_GMAC0_DIV_20 1007 347 #define RK3568_SCLK_GMAC0_DIV_2 1008 348 #define RK3568_SCLK_GMAC1_DIV_50 1009 349 #define RK3568_SCLK_GMAC1_DIV_5 1010 350 #define RK3568_SCLK_GMAC1_DIV_20 1011 351 #define RK3568_SCLK_GMAC1_DIV_2 1012 352 #define RK3568_GPLL_400M 1013 353 #define RK3568_GPLL_300M 1014 354 #define RK3568_GPLL_200M 1015 355 #define RK3568_GPLL_150M 1016 356 #define RK3568_GPLL_100M 1017 357 #define RK3568_CLK_OSC0_DIV_375K 1018 358 #define RK3568_CLK_OSC0_DIV_750K 1019 359 #define RK3568_GMAC0_CLKIN 1020 360 #define RK3568_GMAC1_CLKIN 1021 361 #define RK3568_XIN32K 1022 362 #define RK3568_XIN24M 1023 363 364 /* PMUCRU */ 365 366 #define RK3568_PLL_PPLL 1 367 #define RK3568_PLL_HPLL 2 368 369 #define RK3568_CLK_RTC_32K 5 370 #define RK3568_CLK_I2C0 7 371 #define RK3568_CLK_RTC32K_FRAC 8 372 #define RK3568_SCLK_UART0 11 373 #define RK3568_CLK_USBPHY0_REF 19 374 #define RK3568_CLK_USBPHY1_REF 21 375 #define RK3568_CLK_PCIEPHY0_DIV 29 376 #define RK3568_CLK_PCIEPHY0_OSC0 30 377 #define RK3568_CLK_PCIEPHY0_REF 31 378 #define RK3568_CLK_PCIEPHY1_DIV 32 379 #define RK3568_CLK_PCIEPHY1_OSC0 33 380 #define RK3568_CLK_PCIEPHY1_REF 34 381 #define RK3568_CLK_PCIEPHY2_DIV 35 382 #define RK3568_CLK_PCIEPHY2_OSC0 36 383 #define RK3568_CLK_PCIEPHY2_REF 37 384 #define RK3568_CLK_PCIE30PHY_REF_M 38 385 #define RK3568_CLK_PCIE30PHY_REF_N 39 386 #define RK3568_PCLK_I2C0 45 387 #define RK3568_CLK_PDPMU 49 388 389 #define RK3568_PPLL_PH0 1021 390 391 /* 392 * RK3588 clocks. 393 */ 394 #define RK3588_PLL_AUPLL 4 395 #define RK3588_PLL_CPLL 5 396 #define RK3588_PLL_GPLL 6 397 #define RK3588_PLL_NPLL 7 398 #define RK3588_PLL_PPLL 8 399 400 #define RK3588_ACLK_BUS_ROOT 113 401 #define RK3588_CLK_I2C1 131 402 #define RK3588_CLK_I2C2 132 403 #define RK3588_CLK_I2C3 133 404 #define RK3588_CLK_I2C4 134 405 #define RK3588_CLK_I2C5 135 406 #define RK3588_CLK_I2C6 136 407 #define RK3588_CLK_I2C7 137 408 #define RK3588_CLK_I2C8 138 409 #define RK3588_CLK_UART1_SRC 168 410 #define RK3588_CLK_UART1_FRAC 169 411 #define RK3588_CLK_UART1 170 412 #define RK3588_SCLK_UART1 171 413 #define RK3588_CLK_UART2_SRC 172 414 #define RK3588_CLK_UART2_FRAC 173 415 #define RK3588_CLK_UART2 174 416 #define RK3588_SCLK_UART2 175 417 #define RK3588_CLK_UART3_SRC 176 418 #define RK3588_CLK_UART3_FRAC 177 419 #define RK3588_CLK_UART3 178 420 #define RK3588_SCLK_UART3 179 421 #define RK3588_CLK_UART4_SRC 180 422 #define RK3588_CLK_UART4_FRAC 181 423 #define RK3588_CLK_UART4 182 424 #define RK3588_SCLK_UART4 183 425 #define RK3588_CLK_UART5_SRC 184 426 #define RK3588_CLK_UART5_FRAC 185 427 #define RK3588_CLK_UART5 186 428 #define RK3588_SCLK_UART5 187 429 #define RK3588_CLK_UART6_SRC 188 430 #define RK3588_CLK_UART6_FRAC 189 431 #define RK3588_CLK_UART6 190 432 #define RK3588_SCLK_UART6 191 433 #define RK3588_CLK_UART7_SRC 192 434 #define RK3588_CLK_UART7_FRAC 193 435 #define RK3588_CLK_UART7 194 436 #define RK3588_SCLK_UART7 195 437 #define RK3588_CLK_UART8_SRC 196 438 #define RK3588_CLK_UART8_FRAC 197 439 #define RK3588_CLK_UART8 198 440 #define RK3588_SCLK_UART8 199 441 #define RK3588_CLK_UART9_SRC 200 442 #define RK3588_CLK_UART9_FRAC 201 443 #define RK3588_CLK_UART9 202 444 #define RK3588_SCLK_UART9 203 445 #define RK3588_ACLK_CENTER_ROOT 204 446 #define RK3588_ACLK_CENTER_LOW_ROOT 205 447 #define RK3588_HCLK_CENTER_ROOT 206 448 #define RK3588_CLK_50M_SRC 222 449 #define RK3588_CLK_100M_SRC 223 450 #define RK3588_CLK_150M_SRC 224 451 #define RK3588_CLK_200M_SRC 225 452 #define RK3588_CLK_250M_SRC 226 453 #define RK3588_CLK_400M_SRC 229 454 #define RK3588_CLK_500M_SRC 231 455 #define RK3588_CLK_700M_SRC 234 456 #define RK3588_ACLK_TOP_ROOT 256 457 #define RK3588_PCLK_TOP_ROOT 257 458 #define RK3588_ACLK_LOW_TOP_ROOT 258 459 #define RK3588_CLK_GPU_SRC 261 460 #define RK3588_CLK_GPU 262 461 #define RK3588_CCLK_SRC_SDIO 395 462 #define RK3588_ACLK_VOP_ROOT 600 463 #define RK3588_ACLK_VOP 605 464 #define RK3588_ACLK_VOP_SUB_SRC 619 465 #define RK3588_CLK_I2C0 628 466 #define RK3588_CLK_PMU1_50M_SRC 639 467 #define RK3588_CLK_PMU1_100M_SRC 640 468 #define RK3588_CLK_PMU1_200M_SRC 641 469 #define RK3588_CLK_PMU1_400M_SRC 643 470 #define RK3588_PCLK_PMU1_ROOT 645 471 #define RK3588_PCLK_PMU0_ROOT 646 472 #define RK3588_HCLK_PMU_CM0_ROOT 647 473 #define RK3588_CLK_PMU1PWM 658 474 #define RK3588_CLK_UART0_SRC 664 475 #define RK3588_CLK_UART0_FRAC 665 476 #define RK3588_CLK_UART0 666 477 #define RK3588_SCLK_UART0 667 478 #define RK3588_CLK_REF_PIPE_PHY0_OSC_SRC 674 479 #define RK3588_CLK_REF_PIPE_PHY1_OSC_SRC 675 480 #define RK3588_CLK_REF_PIPE_PHY2_OSC_SRC 676 481 #define RK3588_CLK_REF_PIPE_PHY0_PLL_SRC 677 482 #define RK3588_CLK_REF_PIPE_PHY1_PLL_SRC 678 483 #define RK3588_CLK_REF_PIPE_PHY2_PLL_SRC 679 484 #define RK3588_CLK_REF_PIPE_PHY0 680 485 #define RK3588_CLK_REF_PIPE_PHY1 681 486 #define RK3588_CLK_REF_PIPE_PHY2 682 487 488 #define RK3588_PLL_SPLL 1022 489 #define RK3588_XIN24M 1023 490 491 #define RK3588_SRST_PCIE0_POWER_UP 294 492 #define RK3588_SRST_PCIE1_POWER_UP 295 493 #define RK3588_SRST_PCIE2_POWER_UP 296 494 #define RK3588_SRST_PCIE3_POWER_UP 297 495 #define RK3588_SRST_PCIE4_POWER_UP 298 496 #define RK3588_SRST_P_PCIE0 299 497 #define RK3588_SRST_P_PCIE1 300 498 #define RK3588_SRST_P_PCIE2 301 499 #define RK3588_SRST_P_PCIE3 302 500 #define RK3588_SRST_P_PCIE4 303 501 #define RK3588_SRST_A_USB3OTG2 308 502 #define RK3588_SRST_A_USB3OTG0 338 503 #define RK3588_SRST_A_USB3OTG1 339 504 #define RK3588_SRST_REF_PIPE_PHY0 572 505 #define RK3588_SRST_REF_PIPE_PHY1 573 506 #define RK3588_SRST_REF_PIPE_PHY2 574 507 #define RK3588_SRST_P_PCIE2_PHY0 579 508 #define RK3588_SRST_P_PCIE2_PHY1 580 509 #define RK3588_SRST_P_PCIE2_PHY2 581 510 #define RK3588_SRST_PCIE30_PHY 584 511