1 /* Public Domain */ 2 3 4 /* 5 * Clocks Signals 6 */ 7 8 /* A10/A20 */ 9 10 #define A10_CLK_HOSC 1 11 #define A10_CLK_PLL_CORE 2 12 #define A10_CLK_PLL_PERIPH_BASE 14 13 #define A10_CLK_PLL_PERIPH 15 14 15 #define A10_CLK_CPU 20 16 #define A10_CLK_AXI 21 17 #define A10_CLK_AHB 23 18 #define A10_CLK_APB1 25 19 20 #define A10_CLK_AHB_EHCI0 27 21 #define A10_CLK_AHB_OHCI0 28 22 #define A10_CLK_AHB_EHCI1 29 23 #define A10_CLK_AHB_OHCI1 30 24 #define A10_CLK_AHB_MMC0 34 25 #define A10_CLK_AHB_MMC1 35 26 #define A10_CLK_AHB_MMC2 36 27 #define A10_CLK_AHB_MMC3 37 28 #define A10_CLK_AHB_EMAC 42 29 #define A10_CLK_AHB_SATA 49 30 #define A10_CLK_AHB_GMAC 66 31 #define A10_CLK_APB0_PIO 74 32 #define A10_CLK_APB1_I2C0 79 33 #define A10_CLK_APB1_I2C1 80 34 #define A10_CLK_APB1_I2C2 81 35 #define A10_CLK_APB1_I2C3 82 36 #define A10_CLK_APB1_I2C4 87 37 #define A10_CLK_APB1_UART0 88 38 #define A10_CLK_APB1_UART1 89 39 #define A10_CLK_APB1_UART2 90 40 #define A10_CLK_APB1_UART3 91 41 #define A10_CLK_APB1_UART4 92 42 #define A10_CLK_APB1_UART5 93 43 #define A10_CLK_APB1_UART6 94 44 #define A10_CLK_APB1_UART7 95 45 46 #define A10_CLK_MMC0 98 47 #define A10_CLK_MMC1 101 48 #define A10_CLK_MMC2 104 49 #define A10_CLK_MMC3 107 50 #define A10_CLK_SATA 122 51 #define A10_CLK_USB_OHCI0 123 52 #define A10_CLK_USB_OHCI1 124 53 #define A10_CLK_USB_PHY 125 54 55 #define A10_CLK_LOSC 254 56 57 const struct sxiccmu_ccu_bit sun4i_a10_gates[] = { 58 [A10_CLK_AHB_EHCI0] = { 0x0060, 1 }, 59 [A10_CLK_AHB_OHCI0] = { 0x0060, 2 }, 60 [A10_CLK_AHB_EHCI1] = { 0x0060, 3 }, 61 [A10_CLK_AHB_OHCI1] = { 0x0060, 4 }, 62 [A10_CLK_AHB_MMC0] = { 0x0060, 8 }, 63 [A10_CLK_AHB_MMC1] = { 0x0060, 9 }, 64 [A10_CLK_AHB_MMC2] = { 0x0060, 10 }, 65 [A10_CLK_AHB_MMC3] = { 0x0060, 11 }, 66 [A10_CLK_AHB_EMAC] = { 0x0060, 17 }, 67 [A10_CLK_AHB_SATA] = { 0x0060, 25 }, 68 [A10_CLK_AHB_GMAC] = { 0x0064, 17, A10_CLK_AHB }, 69 [A10_CLK_APB0_PIO] = { 0x0068, 5 }, 70 [A10_CLK_APB1_I2C0] = { 0x006c, 0, A10_CLK_APB1 }, 71 [A10_CLK_APB1_I2C1] = { 0x006c, 1, A10_CLK_APB1 }, 72 [A10_CLK_APB1_I2C2] = { 0x006c, 2, A10_CLK_APB1 }, 73 [A10_CLK_APB1_I2C3] = { 0x006c, 3, A10_CLK_APB1 }, 74 [A10_CLK_APB1_I2C4] = { 0x006c, 15, A10_CLK_APB1 }, 75 [A10_CLK_APB1_UART0] = { 0x006c, 16, A10_CLK_APB1 }, 76 [A10_CLK_APB1_UART1] = { 0x006c, 17, A10_CLK_APB1 }, 77 [A10_CLK_APB1_UART2] = { 0x006c, 18, A10_CLK_APB1 }, 78 [A10_CLK_APB1_UART3] = { 0x006c, 19, A10_CLK_APB1 }, 79 [A10_CLK_APB1_UART4] = { 0x006c, 20, A10_CLK_APB1 }, 80 [A10_CLK_APB1_UART5] = { 0x006c, 21, A10_CLK_APB1 }, 81 [A10_CLK_APB1_UART6] = { 0x006c, 22, A10_CLK_APB1 }, 82 [A10_CLK_APB1_UART7] = { 0x006c, 23, A10_CLK_APB1 }, 83 [A10_CLK_MMC0] = { 0x0088, 31 }, 84 [A10_CLK_MMC1] = { 0x008c, 31 }, 85 [A10_CLK_MMC2] = { 0x0090, 31 }, 86 [A10_CLK_MMC3] = { 0x0094, 31 }, 87 [A10_CLK_SATA] = { 0x00c8, 31 }, 88 [A10_CLK_USB_OHCI0] = { 0x00cc, 6 }, 89 [A10_CLK_USB_OHCI1] = { 0x00cc, 7 }, 90 [A10_CLK_USB_PHY] = { 0x00cc, 8 }, 91 }; 92 93 /* A23/A33 */ 94 95 #define A23_CLK_PLL_PERIPH 10 96 97 #define A23_CLK_AXI 19 98 #define A23_CLK_AHB1 20 99 #define A23_CLK_APB1 21 100 #define A23_CLK_APB2 22 101 102 #define A23_CLK_BUS_MMC0 26 103 #define A23_CLK_BUS_MMC1 27 104 #define A23_CLK_BUS_MMC2 28 105 #define A23_CLK_BUS_EHCI 35 106 #define A23_CLK_BUS_OHCI 36 107 #define A23_CLK_BUS_PIO 48 108 #define A23_CLK_BUS_I2C0 51 109 #define A23_CLK_BUS_I2C1 52 110 #define A23_CLK_BUS_I2C2 53 111 #define A23_CLK_BUS_UART0 54 112 #define A23_CLK_BUS_UART1 55 113 #define A23_CLK_BUS_UART2 56 114 #define A23_CLK_BUS_UART3 57 115 #define A23_CLK_BUS_UART4 58 116 117 #define A23_CLK_MMC0 60 118 #define A23_CLK_MMC1 63 119 #define A23_CLK_MMC2 66 120 #define A23_CLK_USB_OHCI 78 121 122 const struct sxiccmu_ccu_bit sun8i_a23_gates[] = { 123 [A23_CLK_BUS_MMC0] = { 0x0060, 8 }, 124 [A23_CLK_BUS_MMC1] = { 0x0060, 9 }, 125 [A23_CLK_BUS_MMC2] = { 0x0060, 10 }, 126 [A23_CLK_BUS_EHCI] = { 0x0060, 26 }, 127 [A23_CLK_BUS_OHCI] = { 0x0060, 29 }, 128 [A23_CLK_BUS_PIO] = { 0x0068, 5 }, 129 [A23_CLK_BUS_I2C0] = { 0x006c, 0, A23_CLK_APB2 }, 130 [A23_CLK_BUS_I2C1] = { 0x006c, 1, A23_CLK_APB2 }, 131 [A23_CLK_BUS_I2C2] = { 0x006c, 2, A23_CLK_APB2 }, 132 [A23_CLK_BUS_UART0] = { 0x006c, 16, A23_CLK_APB2 }, 133 [A23_CLK_BUS_UART1] = { 0x006c, 17, A23_CLK_APB2 }, 134 [A23_CLK_BUS_UART2] = { 0x006c, 18, A23_CLK_APB2 }, 135 [A23_CLK_BUS_UART3] = { 0x006c, 19, A23_CLK_APB2 }, 136 [A23_CLK_BUS_UART4] = { 0x006c, 20, A23_CLK_APB2 }, 137 [A23_CLK_MMC0] = { 0x0088, 31 }, 138 [A23_CLK_MMC1] = { 0x008c, 31 }, 139 [A23_CLK_MMC2] = { 0x0090, 31 }, 140 [A23_CLK_USB_OHCI] = { 0x00cc, 16 }, 141 }; 142 143 /* A64 */ 144 145 #define A64_CLK_PLL_CPUX 1 146 147 #define A64_CLK_PLL_PERIPH0 11 148 #define A64_CLK_PLL_PERIPH0_2X 12 149 150 #define A64_CLK_CPUX 21 151 #define A64_CLK_AXI 22 152 #define A64_CLK_APB 23 153 #define A64_CLK_AHB1 24 154 #define A64_CLK_APB1 25 155 #define A64_CLK_APB2 26 156 #define A64_CLK_AHB2 27 157 158 #define A64_CLK_BUS_MMC0 31 159 #define A64_CLK_BUS_MMC1 32 160 #define A64_CLK_BUS_MMC2 33 161 #define A64_CLK_BUS_EMAC 36 162 #define A64_CLK_BUS_EHCI0 42 163 #define A64_CLK_BUS_EHCI1 43 164 #define A64_CLK_BUS_OHCI0 44 165 #define A64_CLK_BUS_OHCI1 45 166 #define A64_CLK_BUS_PIO 58 167 #define A64_CLK_BUS_THS 59 168 #define A64_CLK_BUS_I2C0 63 169 #define A64_CLK_BUS_I2C1 64 170 #define A64_CLK_BUS_I2C2 65 171 #define A64_CLK_BUS_UART0 67 172 #define A64_CLK_BUS_UART1 68 173 #define A64_CLK_BUS_UART2 69 174 #define A64_CLK_BUS_UART3 70 175 #define A64_CLK_BUS_UART4 71 176 177 #define A64_CLK_THS 73 178 #define A64_CLK_MMC0 75 179 #define A64_CLK_MMC1 76 180 #define A64_CLK_MMC2 77 181 #define A64_CLK_USB_OHCI0 91 182 #define A64_CLK_USB_OHCI1 93 183 #define A64_CLK_USB_PHY0 86 184 #define A64_CLK_USB_PHY1 87 185 186 #define A64_CLK_LOSC 254 187 #define A64_CLK_HOSC 253 188 189 const struct sxiccmu_ccu_bit sun50i_a64_gates[] = { 190 [A64_CLK_PLL_PERIPH0] = { 0x0028, 31 }, 191 [A64_CLK_BUS_MMC0] = { 0x0060, 8 }, 192 [A64_CLK_BUS_MMC1] = { 0x0060, 9 }, 193 [A64_CLK_BUS_MMC2] = { 0x0060, 10 }, 194 [A64_CLK_BUS_EMAC] = { 0x0060, 17, A64_CLK_AHB2 }, 195 [A64_CLK_BUS_EHCI0] = { 0x0060, 24 }, 196 [A64_CLK_BUS_EHCI1] = { 0x0060, 25 }, 197 [A64_CLK_BUS_OHCI0] = { 0x0060, 28 }, 198 [A64_CLK_BUS_OHCI1] = { 0x0060, 29 }, 199 [A64_CLK_BUS_PIO] = { 0x0068, 5 }, 200 [A64_CLK_BUS_THS] = { 0x0068, 8 }, 201 [A64_CLK_BUS_I2C0] = { 0x006c, 0, A64_CLK_APB2 }, 202 [A64_CLK_BUS_I2C1] = { 0x006c, 1, A64_CLK_APB2 }, 203 [A64_CLK_BUS_I2C2] = { 0x006c, 2, A64_CLK_APB2 }, 204 [A64_CLK_BUS_UART0] = { 0x006c, 16, A64_CLK_APB2 }, 205 [A64_CLK_BUS_UART1] = { 0x006c, 17, A64_CLK_APB2 }, 206 [A64_CLK_BUS_UART2] = { 0x006c, 18, A64_CLK_APB2 }, 207 [A64_CLK_BUS_UART3] = { 0x006c, 19, A64_CLK_APB2 }, 208 [A64_CLK_BUS_UART4] = { 0x006c, 20, A64_CLK_APB2 }, 209 [A64_CLK_THS] = { 0x0074, 31 }, 210 [A64_CLK_MMC0] = { 0x0088, 31 }, 211 [A64_CLK_MMC1] = { 0x008c, 31 }, 212 [A64_CLK_MMC2] = { 0x0090, 31 }, 213 [A64_CLK_USB_OHCI0] = { 0x00cc, 16 }, 214 [A64_CLK_USB_OHCI1] = { 0x00cc, 17 }, 215 [A64_CLK_USB_PHY0] = { 0x00cc, 8 }, 216 [A64_CLK_USB_PHY1] = { 0x00cc, 9 }, 217 }; 218 219 /* A80 */ 220 221 #define A80_CLK_PLL_PERIPH0 3 222 #define A80_CLK_PLL_PERIPH1 11 223 224 #define A80_CLK_GTBUS 18 225 #define A80_CLK_AHB1 20 226 #define A80_CLK_APB1 23 227 228 #define A80_CLK_MMC0 33 229 #define A80_CLK_MMC1 36 230 #define A80_CLK_MMC2 39 231 #define A80_CLK_MMC3 42 232 233 #define A80_CLK_BUS_MMC 84 234 #define A80_CLK_BUS_USB 96 235 #define A80_CLK_BUS_GMAC 97 236 #define A80_CLK_BUS_PIO 111 237 #define A80_CLK_BUS_I2C0 119 238 #define A80_CLK_BUS_I2C1 120 239 #define A80_CLK_BUS_I2C2 121 240 #define A80_CLK_BUS_I2C3 122 241 #define A80_CLK_BUS_I2C4 123 242 #define A80_CLK_BUS_UART0 124 243 #define A80_CLK_BUS_UART1 125 244 #define A80_CLK_BUS_UART2 126 245 #define A80_CLK_BUS_UART3 127 246 #define A80_CLK_BUS_UART4 128 247 #define A80_CLK_BUS_UART5 129 248 249 const struct sxiccmu_ccu_bit sun9i_a80_gates[] = { 250 [A80_CLK_MMC0] = { 0x0410, 31 }, 251 [A80_CLK_MMC1] = { 0x0414, 31 }, 252 [A80_CLK_MMC2] = { 0x0418, 31 }, 253 [A80_CLK_MMC3] = { 0x041c, 31 }, /* Undocumented */ 254 [A80_CLK_BUS_MMC] = { 0x0580, 8 }, 255 [A80_CLK_BUS_GMAC] = { 0x0584, 17, A80_CLK_AHB1 }, 256 [A80_CLK_BUS_USB] = { 0x0584, 1 }, 257 [A80_CLK_BUS_PIO] = { 0x0590, 5 }, 258 [A80_CLK_BUS_I2C0] = { 0x0594, 0, A80_CLK_APB1 }, 259 [A80_CLK_BUS_I2C1] = { 0x0594, 1, A80_CLK_APB1 }, 260 [A80_CLK_BUS_I2C2] = { 0x0594, 2, A80_CLK_APB1 }, 261 [A80_CLK_BUS_I2C3] = { 0x0594, 3, A80_CLK_APB1 }, 262 [A80_CLK_BUS_I2C4] = { 0x0594, 4, A80_CLK_APB1 }, 263 [A80_CLK_BUS_UART0] = { 0x0594, 16, A80_CLK_APB1 }, 264 [A80_CLK_BUS_UART1] = { 0x0594, 17, A80_CLK_APB1 }, 265 [A80_CLK_BUS_UART2] = { 0x0594, 18, A80_CLK_APB1 }, 266 [A80_CLK_BUS_UART3] = { 0x0594, 19, A80_CLK_APB1 }, 267 [A80_CLK_BUS_UART4] = { 0x0594, 20, A80_CLK_APB1 }, 268 [A80_CLK_BUS_UART5] = { 0x0594, 21, A80_CLK_APB1 }, 269 }; 270 271 #define A80_USB_CLK_HCI0 0 272 #define A80_USB_CLK_OHCI0 1 273 #define A80_USB_CLK_HCI1 2 274 #define A80_USB_CLK_HCI2 3 275 #define A80_USB_CLK_OHCI2 4 276 277 #define A80_USB_CLK_HCI0_PHY 5 278 #define A80_USB_CLK_HCI1_HSIC 6 279 #define A80_USB_CLK_HCI1_PHY 7 280 #define A80_USB_CLK_HCI2_HSIC 8 281 #define A80_USB_CLK_HCI2_UTMIPHY 9 282 #define A80_USB_CLK_HCI1_HSIC_12M 10 283 284 const struct sxiccmu_ccu_bit sun9i_a80_usb_gates[] = { 285 [A80_USB_CLK_HCI0] = { 0x0000, 1 }, 286 [A80_USB_CLK_OHCI0] = { 0x0000, 2 }, 287 [A80_USB_CLK_HCI1] = { 0x0000, 3 }, 288 [A80_USB_CLK_HCI2] = { 0x0000, 5 }, 289 [A80_USB_CLK_OHCI2] = { 0x0000, 6 }, 290 [A80_USB_CLK_HCI0_PHY] = { 0x0004, 1 }, 291 [A80_USB_CLK_HCI1_HSIC] = { 0x0004, 2 }, 292 [A80_USB_CLK_HCI1_PHY] = { 0x0004, 3 }, /* Undocumented */ 293 [A80_USB_CLK_HCI2_HSIC] = { 0x0004, 4 }, 294 [A80_USB_CLK_HCI2_UTMIPHY] = { 0x0004, 5 }, 295 [A80_USB_CLK_HCI1_HSIC_12M] = { 0x0004, 10 }, 296 }; 297 298 const struct sxiccmu_ccu_bit sun9i_a80_mmc_gates[] = { 299 { 0x0000, 16 }, 300 { 0x0004, 16 }, 301 { 0x0008, 16 }, 302 { 0x000c, 16 }, 303 }; 304 305 /* D1 */ 306 307 #define D1_CLK_PLL_CPU 0 308 #define D1_CLK_PLL_PERIPH0 5 309 #define D1_CLK_APB1 25 310 #define D1_CLK_MMC0 56 311 #define D1_CLK_MMC1 57 312 #define D1_CLK_MMC2 58 313 #define D1_CLK_BUS_MMC0 59 314 #define D1_CLK_BUS_MMC1 60 315 #define D1_CLK_BUS_MMC2 61 316 #define D1_CLK_BUS_UART0 62 317 #define D1_CLK_BUS_UART1 63 318 #define D1_CLK_BUS_UART2 64 319 #define D1_CLK_BUS_UART3 65 320 #define D1_CLK_BUS_UART4 66 321 #define D1_CLK_BUS_UART5 67 322 #define D1_CLK_USB_OHCI0 97 323 #define D1_CLK_USB_OHCI1 98 324 #define D1_CLK_BUS_OHCI0 99 325 #define D1_CLK_BUS_OHCI1 100 326 #define D1_CLK_BUS_EHCI0 101 327 #define D1_CLK_BUS_EHCI1 102 328 #define D1_CLK_RISCV 132 329 330 #define D1_CLK_HOSC 255 331 332 const struct sxiccmu_ccu_bit sun20i_d1_gates[] = { 333 [D1_CLK_MMC0] = { 0x0830, 31 }, 334 [D1_CLK_MMC1] = { 0x0834, 31 }, 335 [D1_CLK_MMC2] = { 0x0838, 31 }, 336 [D1_CLK_BUS_MMC0] = { 0x084c, 0 }, 337 [D1_CLK_BUS_MMC1] = { 0x084c, 1 }, 338 [D1_CLK_BUS_MMC2] = { 0x084c, 2 }, 339 [D1_CLK_BUS_UART0] = { 0x090c, 0, D1_CLK_APB1 }, 340 [D1_CLK_BUS_UART1] = { 0x090c, 1, D1_CLK_APB1 }, 341 [D1_CLK_BUS_UART2] = { 0x090c, 2, D1_CLK_APB1 }, 342 [D1_CLK_BUS_UART3] = { 0x090c, 3, D1_CLK_APB1 }, 343 [D1_CLK_BUS_UART4] = { 0x090c, 4, D1_CLK_APB1 }, 344 [D1_CLK_BUS_UART5] = { 0x090c, 5, D1_CLK_APB1 }, 345 [D1_CLK_USB_OHCI0] = { 0x0a70, 31 }, 346 [D1_CLK_USB_OHCI1] = { 0x0a74, 31 }, 347 [D1_CLK_BUS_OHCI0] = { 0x0a8c, 0 }, 348 [D1_CLK_BUS_OHCI1] = { 0x0a8c, 1 }, 349 [D1_CLK_BUS_EHCI0] = { 0x0a8c, 4 }, 350 [D1_CLK_BUS_EHCI1] = { 0x0a8c, 5 }, 351 }; 352 353 /* H3/H5 */ 354 355 #define H3_CLK_PLL_CPUX 0 356 #define H3_CLK_PLL_PERIPH0 9 357 358 #define H3_CLK_CPUX 14 359 #define H3_CLK_AXI 15 360 #define H3_CLK_AHB1 16 361 #define H3_CLK_APB1 17 362 #define H3_CLK_APB2 18 363 #define H3_CLK_AHB2 19 364 365 #define H3_CLK_BUS_MMC0 22 366 #define H3_CLK_BUS_MMC1 23 367 #define H3_CLK_BUS_MMC2 24 368 #define H3_CLK_BUS_EMAC 27 369 #define H3_CLK_BUS_EHCI0 33 370 #define H3_CLK_BUS_EHCI1 34 371 #define H3_CLK_BUS_EHCI2 35 372 #define H3_CLK_BUS_EHCI3 36 373 #define H3_CLK_BUS_OHCI0 37 374 #define H3_CLK_BUS_OHCI1 38 375 #define H3_CLK_BUS_OHCI2 39 376 #define H3_CLK_BUS_OHCI3 40 377 #define H3_CLK_BUS_PIO 54 378 #define H3_CLK_BUS_THS 55 379 #define H3_CLK_BUS_I2C0 59 380 #define H3_CLK_BUS_I2C1 60 381 #define H3_CLK_BUS_I2C2 61 382 #define H3_CLK_BUS_UART0 62 383 #define H3_CLK_BUS_UART1 63 384 #define H3_CLK_BUS_UART2 64 385 #define H3_CLK_BUS_UART3 65 386 #define H3_CLK_BUS_EPHY 67 387 388 #define H3_CLK_THS 69 389 #define H3_CLK_MMC0 71 390 #define H3_CLK_MMC1 74 391 #define H3_CLK_MMC2 77 392 #define H3_CLK_USB_PHY0 88 393 #define H3_CLK_USB_PHY1 89 394 #define H3_CLK_USB_PHY2 90 395 #define H3_CLK_USB_PHY3 91 396 #define H3_CLK_USB_OHCI0 92 397 #define H3_CLK_USB_OHCI1 93 398 #define H3_CLK_USB_OHCI2 94 399 #define H3_CLK_USB_OHCI3 95 400 401 #define H3_CLK_LOSC 254 402 #define H3_CLK_HOSC 253 403 404 const struct sxiccmu_ccu_bit sun8i_h3_gates[] = { 405 [H3_CLK_PLL_PERIPH0] = { 0x0028, 31 }, 406 [H3_CLK_BUS_MMC0] = { 0x0060, 8 }, 407 [H3_CLK_BUS_MMC1] = { 0x0060, 9 }, 408 [H3_CLK_BUS_MMC2] = { 0x0060, 10 }, 409 [H3_CLK_BUS_EMAC] = { 0x0060, 17, H3_CLK_AHB2 }, 410 [H3_CLK_BUS_EHCI0] = { 0x0060, 24 }, 411 [H3_CLK_BUS_EHCI1] = { 0x0060, 25 }, 412 [H3_CLK_BUS_EHCI2] = { 0x0060, 26 }, 413 [H3_CLK_BUS_EHCI3] = { 0x0060, 27 }, 414 [H3_CLK_BUS_OHCI0] = { 0x0060, 28 }, 415 [H3_CLK_BUS_OHCI1] = { 0x0060, 29 }, 416 [H3_CLK_BUS_OHCI2] = { 0x0060, 30 }, 417 [H3_CLK_BUS_OHCI3] = { 0x0060, 31 }, 418 [H3_CLK_BUS_PIO] = { 0x0068, 5 }, 419 [H3_CLK_BUS_THS] = { 0x0068, 8 }, 420 [H3_CLK_BUS_I2C0] = { 0x006c, 0, H3_CLK_APB2 }, 421 [H3_CLK_BUS_I2C1] = { 0x006c, 1, H3_CLK_APB2 }, 422 [H3_CLK_BUS_I2C2] = { 0x006c, 2, H3_CLK_APB2 }, 423 [H3_CLK_BUS_UART0] = { 0x006c, 16, H3_CLK_APB2 }, 424 [H3_CLK_BUS_UART1] = { 0x006c, 17, H3_CLK_APB2 }, 425 [H3_CLK_BUS_UART2] = { 0x006c, 18, H3_CLK_APB2 }, 426 [H3_CLK_BUS_UART3] = { 0x006c, 19, H3_CLK_APB2 }, 427 [H3_CLK_BUS_EPHY] = { 0x0070, 0 }, 428 [H3_CLK_THS] = { 0x0074, 31 }, 429 [H3_CLK_MMC0] = { 0x0088, 31 }, 430 [H3_CLK_MMC1] = { 0x008c, 31 }, 431 [H3_CLK_MMC2] = { 0x0090, 31 }, 432 [H3_CLK_USB_PHY0] = { 0x00cc, 8 }, 433 [H3_CLK_USB_PHY1] = { 0x00cc, 9 }, 434 [H3_CLK_USB_PHY2] = { 0x00cc, 10 }, 435 [H3_CLK_USB_PHY3] = { 0x00cc, 11 }, 436 [H3_CLK_USB_OHCI0] = { 0x00cc, 16 }, 437 [H3_CLK_USB_OHCI1] = { 0x00cc, 17 }, 438 [H3_CLK_USB_OHCI2] = { 0x00cc, 18 }, 439 [H3_CLK_USB_OHCI3] = { 0x00cc, 19 }, 440 }; 441 442 #define H3_R_CLK_AHB0 1 443 #define H3_R_CLK_APB0 2 444 445 #define H3_R_CLK_APB0_PIO 3 446 #define H3_R_CLK_APB0_RSB 6 447 #define H3_R_CLK_APB0_I2C 9 448 449 const struct sxiccmu_ccu_bit sun8i_h3_r_gates[] = { 450 [H3_R_CLK_APB0_PIO] = { 0x0028, 0 }, 451 [H3_R_CLK_APB0_RSB] = { 0x0028, 3, H3_R_CLK_APB0 }, 452 [H3_R_CLK_APB0_I2C] = { 0x0028, 6, H3_R_CLK_APB0 }, 453 }; 454 455 /* H6 */ 456 457 #define H6_CLK_PLL_PERIPH0 3 458 #define H6_CLK_PLL_PERIPH0_2X 4 459 #define H6_CLK_AHB3 25 460 #define H6_CLK_APB1 26 461 #define H6_CLK_APB2 27 462 #define H6_CLK_MMC0 64 463 #define H6_CLK_MMC1 65 464 #define H6_CLK_MMC2 66 465 #define H6_CLK_BUS_MMC0 67 466 #define H6_CLK_BUS_MMC1 68 467 #define H6_CLK_BUS_MMC2 69 468 #define H6_CLK_BUS_UART0 70 469 #define H6_CLK_BUS_UART1 71 470 #define H6_CLK_BUS_UART2 72 471 #define H6_CLK_BUS_UART3 73 472 #define H6_CLK_BUS_EMAC 84 473 #define H6_CLK_USB_OHCI0 104 474 #define H6_CLK_USB_PHY0 105 475 #define H6_CLK_USB_PHY1 106 476 #define H6_CLK_USB_OHCI3 107 477 #define H6_CLK_USB_PHY3 108 478 #define H6_CLK_BUS_OHCI0 111 479 #define H6_CLK_BUS_OHCI3 112 480 #define H6_CLK_BUS_EHCI0 113 481 #define H6_CLK_BUS_EHCI3 115 482 483 const struct sxiccmu_ccu_bit sun50i_h6_gates[] = { 484 [H6_CLK_PLL_PERIPH0] = { 0x0020, 31 }, 485 [H6_CLK_APB1] = { 0xffff, 0xff }, 486 [H6_CLK_MMC0] = { 0x0830, 31 }, 487 [H6_CLK_MMC1] = { 0x0834, 31 }, 488 [H6_CLK_MMC2] = { 0x0838, 31 }, 489 [H6_CLK_BUS_MMC0] = { 0x084c, 0 }, 490 [H6_CLK_BUS_MMC1] = { 0x084c, 1 }, 491 [H6_CLK_BUS_MMC2] = { 0x084c, 2 }, 492 [H6_CLK_BUS_UART0] = { 0x090c, 0, H6_CLK_APB2 }, 493 [H6_CLK_BUS_UART1] = { 0x090c, 1, H6_CLK_APB2 }, 494 [H6_CLK_BUS_UART2] = { 0x090c, 2, H6_CLK_APB2 }, 495 [H6_CLK_BUS_UART3] = { 0x090c, 3, H6_CLK_APB2 }, 496 [H6_CLK_BUS_EMAC] = { 0x097c, 0, H6_CLK_AHB3 }, 497 [H6_CLK_USB_OHCI0] = { 0x0a70, 31 }, 498 [H6_CLK_USB_PHY0] = { 0x0a70, 29 }, 499 [H6_CLK_USB_PHY1] = { 0x0a74, 29 }, 500 [H6_CLK_USB_OHCI3] = { 0x0a7c, 31 }, 501 [H6_CLK_USB_PHY3] = { 0x0a7c, 29 }, 502 [H6_CLK_BUS_OHCI0] = { 0x0a8c, 0 }, 503 [H6_CLK_BUS_OHCI3] = { 0x0a8c, 3 }, 504 [H6_CLK_BUS_EHCI0] = { 0x0a8c, 4 }, 505 [H6_CLK_BUS_EHCI3] = { 0x0a8c, 7 }, 506 }; 507 508 #define H6_R_CLK_APB1 2 509 #define H6_R_CLK_APB2 3 510 #define H6_R_CLK_APB2_I2C 8 511 #define H6_R_CLK_APB2_RSB 13 512 513 const struct sxiccmu_ccu_bit sun50i_h6_r_gates[] = { 514 [H6_R_CLK_APB1] = { 0xffff, 0xff }, 515 [H6_R_CLK_APB2_I2C] = { 0x019c, 0, H6_R_CLK_APB2 }, 516 [H6_R_CLK_APB2_RSB] = { 0x01bc, 0, H6_R_CLK_APB2 }, 517 }; 518 519 /* R40 */ 520 521 #define R40_CLK_PLL_PERIPH0 11 522 #define R40_CLK_PLL_PERIPH0_2X 13 523 524 #define R40_CLK_AXI 25 525 #define R40_CLK_AHB1 26 526 #define R40_CLK_APB2 28 527 528 #define R40_CLK_BUS_MMC0 32 529 #define R40_CLK_BUS_MMC1 33 530 #define R40_CLK_BUS_MMC2 34 531 #define R40_CLK_BUS_MMC3 35 532 #define R40_CLK_BUS_SATA 45 533 #define R40_CLK_BUS_EHCI0 47 534 #define R40_CLK_BUS_EHCI1 48 535 #define R40_CLK_BUS_EHCI2 49 536 #define R40_CLK_BUS_OHCI0 50 537 #define R40_CLK_BUS_OHCI1 51 538 #define R40_CLK_BUS_OHCI2 52 539 #define R40_CLK_BUS_GMAC 64 540 #define R40_CLK_BUS_PIO 79 541 #define R40_CLK_BUS_THS 82 542 #define R40_CLK_BUS_I2C0 87 543 #define R40_CLK_BUS_I2C1 88 544 #define R40_CLK_BUS_I2C2 89 545 #define R40_CLK_BUS_I2C3 90 546 #define R40_CLK_BUS_I2C4 95 547 #define R40_CLK_BUS_UART0 96 548 #define R40_CLK_BUS_UART1 97 549 #define R40_CLK_BUS_UART2 98 550 #define R40_CLK_BUS_UART3 99 551 #define R40_CLK_BUS_UART4 100 552 #define R40_CLK_BUS_UART5 101 553 #define R40_CLK_BUS_UART6 102 554 #define R40_CLK_BUS_UART7 103 555 556 #define R40_CLK_THS 105 557 #define R40_CLK_MMC0 107 558 #define R40_CLK_MMC1 108 559 #define R40_CLK_MMC2 109 560 #define R40_CLK_MMC3 110 561 #define R40_CLK_SATA 123 562 #define R40_CLK_USB_PHY0 124 563 #define R40_CLK_USB_PHY1 125 564 #define R40_CLK_USB_PHY2 126 565 #define R40_CLK_USB_OHCI0 127 566 #define R40_CLK_USB_OHCI1 128 567 #define R40_CLK_USB_OHCI2 129 568 569 #define R40_CLK_HOSC 253 570 #define R40_CLK_LOSC 254 571 572 const struct sxiccmu_ccu_bit sun8i_r40_gates[] = { 573 [R40_CLK_BUS_MMC0] = { 0x0060, 8 }, 574 [R40_CLK_BUS_MMC1] = { 0x0060, 9 }, 575 [R40_CLK_BUS_MMC2] = { 0x0060, 10 }, 576 [R40_CLK_BUS_MMC3] = { 0x0060, 11 }, 577 [R40_CLK_BUS_SATA] = { 0x0060, 24 }, 578 [R40_CLK_BUS_EHCI0] = { 0x0060, 26 }, 579 [R40_CLK_BUS_EHCI1] = { 0x0060, 27 }, 580 [R40_CLK_BUS_EHCI2] = { 0x0060, 28 }, 581 [R40_CLK_BUS_OHCI0] = { 0x0060, 29 }, 582 [R40_CLK_BUS_OHCI1] = { 0x0060, 30 }, 583 [R40_CLK_BUS_OHCI2] = { 0x0060, 31 }, 584 [R40_CLK_BUS_GMAC] = { 0x0064, 17, R40_CLK_AHB1 }, 585 [R40_CLK_BUS_PIO] = { 0x0068, 5 }, 586 [R40_CLK_BUS_THS] = { 0x0068, 8 }, 587 [R40_CLK_BUS_I2C0] = { 0x006c, 0, R40_CLK_APB2 }, 588 [R40_CLK_BUS_I2C1] = { 0x006c, 1, R40_CLK_APB2 }, 589 [R40_CLK_BUS_I2C2] = { 0x006c, 2, R40_CLK_APB2 }, 590 [R40_CLK_BUS_I2C3] = { 0x006c, 3, R40_CLK_APB2 }, 591 [R40_CLK_BUS_I2C4] = { 0x006c, 15, R40_CLK_APB2 }, 592 [R40_CLK_BUS_UART0] = { 0x006c, 16, R40_CLK_APB2 }, 593 [R40_CLK_BUS_UART1] = { 0x006c, 17, R40_CLK_APB2 }, 594 [R40_CLK_BUS_UART2] = { 0x006c, 18, R40_CLK_APB2 }, 595 [R40_CLK_BUS_UART3] = { 0x006c, 19, R40_CLK_APB2 }, 596 [R40_CLK_BUS_UART4] = { 0x006c, 20, R40_CLK_APB2 }, 597 [R40_CLK_BUS_UART5] = { 0x006c, 21, R40_CLK_APB2 }, 598 [R40_CLK_BUS_UART6] = { 0x006c, 22, R40_CLK_APB2 }, 599 [R40_CLK_BUS_UART7] = { 0x006c, 23, R40_CLK_APB2 }, 600 [R40_CLK_THS] = { 0x0074, 31 }, 601 [R40_CLK_MMC0] = { 0x0088, 31 }, 602 [R40_CLK_MMC1] = { 0x008c, 31 }, 603 [R40_CLK_MMC2] = { 0x0090, 31 }, 604 [R40_CLK_MMC3] = { 0x0094, 31 }, 605 [R40_CLK_SATA] = { 0x00c8, 31 }, 606 [R40_CLK_USB_PHY0] = { 0x00cc, 8 }, 607 [R40_CLK_USB_PHY1] = { 0x00cc, 9 }, 608 [R40_CLK_USB_PHY2] = { 0x00cc, 10 }, 609 [R40_CLK_USB_OHCI0] = { 0x00cc, 16 }, 610 [R40_CLK_USB_OHCI1] = { 0x00cc, 17 }, 611 [R40_CLK_USB_OHCI2] = { 0x00cc, 18 }, 612 }; 613 614 /* V3s */ 615 616 #define V3S_CLK_PLL_PERIPH0 9 617 #define V3S_CLK_AXI 15 618 #define V3S_CLK_AHB1 16 619 #define V3S_CLK_APB2 18 620 #define V3S_CLK_AHB2 19 621 622 #define V3S_CLK_BUS_MMC0 22 623 #define V3S_CLK_BUS_MMC1 23 624 #define V3S_CLK_BUS_MMC2 24 625 #define V3S_CLK_BUS_EMAC 26 626 #define V3S_CLK_BUS_EHCI0 30 627 #define V3S_CLK_BUS_OHCI0 31 628 #define V3S_CLK_BUS_PIO 37 629 #define V3S_CLK_BUS_I2C0 38 630 #define V3S_CLK_BUS_I2C1 39 631 #define V3S_CLK_BUS_UART0 40 632 #define V3S_CLK_BUS_UART1 41 633 #define V3S_CLK_BUS_UART2 42 634 #define V3S_CLK_BUS_EPHY 43 635 636 #define V3S_CLK_MMC0 45 637 #define V3S_CLK_MMC1 48 638 #define V3S_CLK_MMC2 51 639 #define V3S_CLK_USB_PHY0 56 640 #define V3S_CLK_USB_OHCI0 57 641 642 #define V3S_CLK_LOSC 254 643 #define V3S_CLK_HOSC 253 644 645 const struct sxiccmu_ccu_bit sun8i_v3s_gates[] = { 646 [V3S_CLK_BUS_OHCI0] = { 0x0060, 29 }, 647 [V3S_CLK_BUS_EHCI0] = { 0x0060, 26 }, 648 [V3S_CLK_BUS_EMAC] = { 0x0060, 17, V3S_CLK_AHB2 }, 649 [V3S_CLK_BUS_MMC2] = { 0x0060, 10 }, 650 [V3S_CLK_BUS_MMC1] = { 0x0060, 9 }, 651 [V3S_CLK_BUS_MMC0] = { 0x0060, 8 }, 652 [V3S_CLK_BUS_PIO] = { 0x0068, 5 }, 653 [V3S_CLK_BUS_UART2] = { 0x006c, 18, V3S_CLK_APB2 }, 654 [V3S_CLK_BUS_UART1] = { 0x006c, 17, V3S_CLK_APB2 }, 655 [V3S_CLK_BUS_UART0] = { 0x006c, 16, V3S_CLK_APB2 }, 656 [V3S_CLK_BUS_I2C1] = { 0x006c, 1, V3S_CLK_APB2 }, 657 [V3S_CLK_BUS_I2C0] = { 0x006c, 0, V3S_CLK_APB2 }, 658 [V3S_CLK_BUS_EPHY] = { 0x0070, 0 }, 659 [V3S_CLK_MMC0] = { 0x0088, 31 }, 660 [V3S_CLK_MMC1] = { 0x008c, 31 }, 661 [V3S_CLK_MMC2] = { 0x0090, 31 }, 662 [V3S_CLK_USB_OHCI0] = { 0x00cc, 16 }, 663 [V3S_CLK_USB_PHY0] = { 0x00cc, 8 }, 664 }; 665 666 /* 667 * Reset Signals 668 */ 669 670 /* A10 */ 671 672 #define A10_RST_USB_PHY0 1 673 #define A10_RST_USB_PHY1 2 674 #define A10_RST_USB_PHY2 3 675 676 const struct sxiccmu_ccu_bit sun4i_a10_resets[] = { 677 [A10_RST_USB_PHY0] = { 0x00cc, 0 }, 678 [A10_RST_USB_PHY1] = { 0x00cc, 1 }, 679 [A10_RST_USB_PHY2] = { 0x00cc, 2 }, 680 }; 681 682 /* A23/A33 */ 683 684 #define A23_RST_USB_PHY0 0 685 #define A23_RST_USB_PHY1 1 686 687 #define A23_RST_BUS_MMC0 7 688 #define A23_RST_BUS_MMC1 8 689 #define A23_RST_BUS_MMC2 9 690 691 #define A23_RST_BUS_EHCI 16 692 #define A23_RST_BUS_OHCI 17 693 694 #define A23_RST_BUS_I2C0 32 695 #define A23_RST_BUS_I2C1 33 696 #define A23_RST_BUS_I2C2 34 697 698 #define A23_CLK_HOSC 253 699 #define A23_CLK_LOSC 254 700 701 const struct sxiccmu_ccu_bit sun8i_a23_resets[] = { 702 [A23_RST_USB_PHY0] = { 0x00cc, 0 }, 703 [A23_RST_USB_PHY1] = { 0x00cc, 1 }, 704 [A23_RST_BUS_MMC0] = { 0x02c0, 8 }, 705 [A23_RST_BUS_MMC1] = { 0x02c0, 9 }, 706 [A23_RST_BUS_MMC2] = { 0x02c0, 10 }, 707 [A23_RST_BUS_EHCI] = { 0x02c0, 26 }, 708 [A23_RST_BUS_OHCI] = { 0x02c0, 29 }, 709 [A23_RST_BUS_I2C0] = { 0x02d8, 0 }, 710 [A23_RST_BUS_I2C1] = { 0x02d8, 1 }, 711 [A23_RST_BUS_I2C2] = { 0x02d8, 2 }, 712 }; 713 714 /* A64 */ 715 716 #define A64_RST_USB_PHY0 0 717 #define A64_RST_USB_PHY1 1 718 719 #define A64_RST_BUS_MMC0 8 720 #define A64_RST_BUS_MMC1 9 721 #define A64_RST_BUS_MMC2 10 722 #define A64_RST_BUS_EMAC 13 723 #define A64_RST_BUS_EHCI0 19 724 #define A64_RST_BUS_EHCI1 20 725 #define A64_RST_BUS_OHCI0 21 726 #define A64_RST_BUS_OHCI1 22 727 #define A64_RST_BUS_THS 38 728 #define A64_RST_BUS_I2C0 42 729 #define A64_RST_BUS_I2C1 43 730 #define A64_RST_BUS_I2C2 44 731 #define A64_RST_BUS_UART0 46 732 #define A64_RST_BUS_UART1 47 733 #define A64_RST_BUS_UART2 48 734 #define A64_RST_BUS_UART3 49 735 #define A64_RST_BUS_UART4 50 736 737 const struct sxiccmu_ccu_bit sun50i_a64_resets[] = { 738 [A64_RST_USB_PHY0] = { 0x00cc, 0 }, 739 [A64_RST_USB_PHY1] = { 0x00cc, 1 }, 740 [A64_RST_BUS_MMC0] = { 0x02c0, 8 }, 741 [A64_RST_BUS_MMC1] = { 0x02c0, 9 }, 742 [A64_RST_BUS_MMC2] = { 0x02c0, 10 }, 743 [A64_RST_BUS_EMAC] = { 0x02c0, 17 }, 744 [A64_RST_BUS_EHCI0] = { 0x02c0, 24 }, 745 [A64_RST_BUS_EHCI1] = { 0x02c0, 25 }, 746 [A64_RST_BUS_OHCI0] = { 0x02c0, 28 }, 747 [A64_RST_BUS_OHCI1] = { 0x02c0, 29 }, 748 [A64_RST_BUS_THS] = { 0x02d0, 8 }, 749 [A64_RST_BUS_I2C0] = { 0x02d8, 0 }, 750 [A64_RST_BUS_I2C1] = { 0x02d8, 1 }, 751 [A64_RST_BUS_I2C2] = { 0x02d8, 2 }, 752 [A64_RST_BUS_UART0] = { 0x02d8, 16 }, 753 [A64_RST_BUS_UART1] = { 0x02d8, 17 }, 754 [A64_RST_BUS_UART2] = { 0x02d8, 18 }, 755 [A64_RST_BUS_UART3] = { 0x02d8, 19 }, 756 [A64_RST_BUS_UART4] = { 0x02d8, 20 }, 757 }; 758 759 /* A80 */ 760 761 #define A80_RST_BUS_MMC 4 762 #define A80_RST_BUS_GMAC 17 763 #define A80_RST_BUS_I2C0 40 764 #define A80_RST_BUS_I2C1 41 765 #define A80_RST_BUS_I2C2 42 766 #define A80_RST_BUS_I2C3 43 767 #define A80_RST_BUS_I2C4 44 768 #define A80_RST_BUS_UART0 45 769 #define A80_RST_BUS_UART1 46 770 #define A80_RST_BUS_UART2 47 771 #define A80_RST_BUS_UART3 48 772 #define A80_RST_BUS_UART4 49 773 #define A80_RST_BUS_UART5 50 774 775 const struct sxiccmu_ccu_bit sun9i_a80_resets[] = { 776 [A80_RST_BUS_MMC] = { 0x05a0, 8 }, 777 [A80_RST_BUS_GMAC] = { 0x05a4, 17 }, 778 [A80_RST_BUS_I2C0] = { 0x05b4, 0 }, 779 [A80_RST_BUS_I2C1] = { 0x05b4, 1 }, 780 [A80_RST_BUS_I2C2] = { 0x05b4, 2 }, 781 [A80_RST_BUS_I2C3] = { 0x05b4, 3 }, 782 [A80_RST_BUS_I2C4] = { 0x05b4, 4 }, 783 [A80_RST_BUS_UART0] = { 0x05b4, 16 }, 784 [A80_RST_BUS_UART1] = { 0x05b4, 17 }, 785 [A80_RST_BUS_UART2] = { 0x05b4, 18 }, 786 [A80_RST_BUS_UART3] = { 0x05b4, 19 }, 787 [A80_RST_BUS_UART4] = { 0x05b4, 20 }, 788 [A80_RST_BUS_UART5] = { 0x05b4, 21 }, 789 }; 790 791 #define A80_USB_RST_HCI0 0 792 #define A80_USB_RST_HCI1 1 793 #define A80_USB_RST_HCI2 2 794 795 #define A80_USB_RST_HCI0_PHY 3 796 #define A80_USB_RST_HCI1_HSIC 4 797 #define A80_USB_RST_HCI1_PHY 5 798 #define A80_USB_RST_HCI2_HSIC 6 799 #define A80_USB_RST_HCI2_UTMIPHY 7 800 801 const struct sxiccmu_ccu_bit sun9i_a80_usb_resets[] = { 802 [A80_USB_RST_HCI0] = { 0x0000, 17 }, 803 [A80_USB_RST_HCI1] = { 0x0000, 18 }, 804 [A80_USB_RST_HCI2] = { 0x0000, 19 }, 805 [A80_USB_RST_HCI0_PHY] = { 0x0004, 17 }, 806 [A80_USB_RST_HCI1_HSIC]= { 0x0004, 18 }, 807 [A80_USB_RST_HCI1_PHY]= { 0x0004, 19 }, /* Undocumented */ 808 [A80_USB_RST_HCI2_HSIC]= { 0x0004, 20 }, /* Undocumented */ 809 [A80_USB_RST_HCI2_UTMIPHY] = { 0x0004, 21 }, 810 }; 811 812 const struct sxiccmu_ccu_bit sun9i_a80_mmc_resets[] = { 813 { 0x0000, 18 }, 814 { 0x0004, 18 }, 815 { 0x0008, 18 }, 816 { 0x000c, 18 }, 817 }; 818 819 /* D1 */ 820 821 #define D1_RST_BUS_MMC0 15 822 #define D1_RST_BUS_MMC1 16 823 #define D1_RST_BUS_MMC2 17 824 #define D1_RST_BUS_UART0 18 825 #define D1_RST_BUS_UART1 19 826 #define D1_RST_BUS_UART2 20 827 #define D1_RST_BUS_UART3 21 828 #define D1_RST_BUS_UART4 22 829 #define D1_RST_BUS_UART5 23 830 #define D1_RST_USB_PHY0 40 831 #define D1_RST_USB_PHY1 41 832 #define D1_RST_BUS_OHCI0 42 833 #define D1_RST_BUS_OHCI1 43 834 #define D1_RST_BUS_EHCI0 44 835 #define D1_RST_BUS_EHCI1 45 836 837 const struct sxiccmu_ccu_bit sun20i_d1_resets[] = { 838 [D1_RST_BUS_MMC0] = { 0x084c, 16 }, 839 [D1_RST_BUS_MMC1] = { 0x084c, 17 }, 840 [D1_RST_BUS_MMC2] = { 0x084c, 18 }, 841 [D1_RST_BUS_UART0] = { 0x090c, 16 }, 842 [D1_RST_BUS_UART1] = { 0x090c, 17 }, 843 [D1_RST_BUS_UART2] = { 0x090c, 18 }, 844 [D1_RST_BUS_UART3] = { 0x090c, 19 }, 845 [D1_RST_BUS_UART4] = { 0x090c, 20 }, 846 [D1_RST_BUS_UART5] = { 0x090c, 21 }, 847 [D1_RST_USB_PHY0] = { 0x0a70, 30 }, 848 [D1_RST_USB_PHY1] = { 0x0a74, 30 }, 849 [D1_RST_BUS_OHCI0] = { 0x0a8c, 16 }, 850 [D1_RST_BUS_OHCI1] = { 0x0a8c, 17 }, 851 [D1_RST_BUS_EHCI0] = { 0x0a8c, 20 }, 852 [D1_RST_BUS_EHCI1] = { 0x0a8c, 21 }, 853 }; 854 855 /* H3/H5 */ 856 857 #define H3_RST_USB_PHY0 0 858 #define H3_RST_USB_PHY1 1 859 #define H3_RST_USB_PHY2 2 860 #define H3_RST_USB_PHY3 3 861 862 #define H3_RST_BUS_MMC0 7 863 #define H3_RST_BUS_MMC1 8 864 #define H3_RST_BUS_MMC2 9 865 866 #define H3_RST_BUS_EMAC 12 867 868 #define H3_RST_BUS_EHCI0 18 869 #define H3_RST_BUS_EHCI1 19 870 #define H3_RST_BUS_EHCI2 20 871 #define H3_RST_BUS_EHCI3 21 872 #define H3_RST_BUS_OHCI0 22 873 #define H3_RST_BUS_OHCI1 23 874 #define H3_RST_BUS_OHCI2 24 875 #define H3_RST_BUS_OHCI3 25 876 #define H3_RST_BUS_EPHY 39 877 #define H3_RST_BUS_THS 42 878 #define H3_RST_BUS_I2C0 46 879 #define H3_RST_BUS_I2C1 47 880 #define H3_RST_BUS_I2C2 48 881 #define H3_RST_BUS_UART0 49 882 #define H3_RST_BUS_UART1 50 883 #define H3_RST_BUS_UART2 51 884 #define H3_RST_BUS_UART3 52 885 886 const struct sxiccmu_ccu_bit sun8i_h3_resets[] = { 887 [H3_RST_USB_PHY0] = { 0x00cc, 0 }, 888 [H3_RST_USB_PHY1] = { 0x00cc, 1 }, 889 [H3_RST_USB_PHY2] = { 0x00cc, 2 }, 890 [H3_RST_USB_PHY3] = { 0x00cc, 3 }, 891 [H3_RST_BUS_MMC0] = { 0x02c0, 8 }, 892 [H3_RST_BUS_MMC1] = { 0x02c0, 9 }, 893 [H3_RST_BUS_MMC2] = { 0x02c0, 10 }, 894 [H3_RST_BUS_EMAC] = { 0x02c0, 17 }, 895 [H3_RST_BUS_EHCI0] = { 0x02c0, 24 }, 896 [H3_RST_BUS_EHCI1] = { 0x02c0, 25 }, 897 [H3_RST_BUS_EHCI2] = { 0x02c0, 26 }, 898 [H3_RST_BUS_EHCI3] = { 0x02c0, 27 }, 899 [H3_RST_BUS_OHCI0] = { 0x02c0, 28 }, 900 [H3_RST_BUS_OHCI1] = { 0x02c0, 29 }, 901 [H3_RST_BUS_OHCI2] = { 0x02c0, 30 }, 902 [H3_RST_BUS_OHCI3] = { 0x02c0, 31 }, 903 [H3_RST_BUS_EPHY] = { 0x02c8, 2 }, 904 [H3_RST_BUS_THS] = { 0x02d0, 8 }, 905 [H3_RST_BUS_I2C0] = { 0x02d8, 0 }, 906 [H3_RST_BUS_I2C1] = { 0x02d8, 1 }, 907 [H3_RST_BUS_I2C2] = { 0x02d8, 2 }, 908 [H3_RST_BUS_UART0] = { 0x02d8, 16 }, 909 [H3_RST_BUS_UART1] = { 0x02d8, 17 }, 910 [H3_RST_BUS_UART2] = { 0x02d8, 18 }, 911 [H3_RST_BUS_UART3] = { 0x02d8, 19 }, 912 }; 913 914 #define H3_R_RST_APB0_RSB 2 915 #define H3_R_RST_APB0_I2C 5 916 917 const struct sxiccmu_ccu_bit sun8i_h3_r_resets[] = { 918 [H3_R_RST_APB0_RSB] = { 0x00b0, 3 }, 919 [H3_R_RST_APB0_I2C] = { 0x00b0, 6 }, 920 }; 921 922 /* H6 */ 923 924 #define H6_RST_BUS_MMC0 18 925 #define H6_RST_BUS_MMC1 19 926 #define H6_RST_BUS_MMC2 20 927 #define H6_RST_BUS_UART0 21 928 #define H6_RST_BUS_UART1 22 929 #define H6_RST_BUS_UART2 23 930 #define H6_RST_BUS_UART3 24 931 #define H6_RST_BUS_EMAC 33 932 #define H6_RST_USB_PHY0 44 933 #define H6_RST_USB_PHY1 45 934 #define H6_RST_USB_PHY3 46 935 #define H6_RST_BUS_OHCI0 48 936 #define H6_RST_BUS_OHCI3 49 937 #define H6_RST_BUS_EHCI0 50 938 #define H6_RST_BUS_EHCI3 52 939 940 const struct sxiccmu_ccu_bit sun50i_h6_resets[] = { 941 [H6_RST_BUS_MMC0] = { 0x084c, 16 }, 942 [H6_RST_BUS_MMC1] = { 0x084c, 17 }, 943 [H6_RST_BUS_MMC2] = { 0x084c, 18 }, 944 [H6_RST_BUS_UART0] = { 0x090c, 16 }, 945 [H6_RST_BUS_UART1] = { 0x090c, 17 }, 946 [H6_RST_BUS_UART2] = { 0x090c, 18 }, 947 [H6_RST_BUS_UART3] = { 0x090c, 19 }, 948 [H6_RST_BUS_EMAC] = { 0x097c, 16 }, 949 [H6_RST_USB_PHY0] = { 0x0a70, 30 }, 950 [H6_RST_USB_PHY1] = { 0x0a74, 30 }, 951 [H6_RST_USB_PHY3] = { 0x0a7c, 30 }, 952 [H6_RST_BUS_OHCI0] = { 0x0a8c, 16 }, 953 [H6_RST_BUS_OHCI3] = { 0x0a8c, 19 }, 954 [H6_RST_BUS_EHCI0] = { 0x0a8c, 20 }, 955 [H6_RST_BUS_EHCI3] = { 0x0a8c, 23 }, 956 }; 957 958 #define H6_R_RST_APB2_I2C 4 959 #define H6_R_RST_APB2_RSB 7 960 961 const struct sxiccmu_ccu_bit sun50i_h6_r_resets[] = { 962 [H6_R_RST_APB2_I2C] = { 0x019c, 16 }, 963 [H6_R_RST_APB2_RSB] = { 0x01bc, 16 }, 964 }; 965 966 /* R40 */ 967 968 #define R40_RST_USB_PHY0 0 969 #define R40_RST_USB_PHY1 1 970 #define R40_RST_USB_PHY2 2 971 972 #define R40_RST_BUS_MMC0 8 973 #define R40_RST_BUS_MMC1 9 974 #define R40_RST_BUS_MMC2 10 975 #define R40_RST_BUS_MMC3 11 976 #define R40_RST_BUS_SATA 21 977 #define R40_RST_BUS_EHCI0 23 978 #define R40_RST_BUS_EHCI1 24 979 #define R40_RST_BUS_EHCI2 25 980 #define R40_RST_BUS_OHCI0 26 981 #define R40_RST_BUS_OHCI1 27 982 #define R40_RST_BUS_OHCI2 28 983 #define R40_RST_BUS_GMAC 40 984 #define R40_RST_BUS_THS 59 985 #define R40_RST_BUS_I2C0 64 986 #define R40_RST_BUS_I2C1 65 987 #define R40_RST_BUS_I2C2 66 988 #define R40_RST_BUS_I2C3 67 989 #define R40_RST_BUS_I2C4 72 990 #define R40_RST_BUS_UART0 73 991 #define R40_RST_BUS_UART1 74 992 #define R40_RST_BUS_UART2 75 993 #define R40_RST_BUS_UART3 76 994 #define R40_RST_BUS_UART4 77 995 #define R40_RST_BUS_UART5 78 996 #define R40_RST_BUS_UART6 79 997 #define R40_RST_BUS_UART7 80 998 999 const struct sxiccmu_ccu_bit sun8i_r40_resets[] = { 1000 [R40_RST_USB_PHY0] = { 0x00cc, 0 }, 1001 [R40_RST_USB_PHY1] = { 0x00cc, 1 }, 1002 [R40_RST_USB_PHY2] = { 0x00cc, 2 }, 1003 [R40_RST_BUS_MMC0] = { 0x02c0, 8 }, 1004 [R40_RST_BUS_MMC1] = { 0x02c0, 9 }, 1005 [R40_RST_BUS_MMC2] = { 0x02c0, 10 }, 1006 [R40_RST_BUS_MMC3] = { 0x02c0, 11 }, 1007 [R40_RST_BUS_SATA] = { 0x02c0, 24 }, 1008 [R40_RST_BUS_EHCI0] = { 0x02c0, 26 }, 1009 [R40_RST_BUS_EHCI1] = { 0x02c0, 27 }, 1010 [R40_RST_BUS_EHCI2] = { 0x02c0, 28 }, 1011 [R40_RST_BUS_OHCI0] = { 0x02c0, 29 }, 1012 [R40_RST_BUS_OHCI1] = { 0x02c0, 30 }, 1013 [R40_RST_BUS_OHCI2] = { 0x02c0, 31 }, 1014 [R40_RST_BUS_GMAC] = { 0x02c4, 17 }, 1015 [R40_RST_BUS_THS] = { 0x02d0, 8 }, 1016 [R40_RST_BUS_I2C0] = { 0x02d8, 0 }, 1017 [R40_RST_BUS_I2C1] = { 0x02d8, 1 }, 1018 [R40_RST_BUS_I2C2] = { 0x02d8, 2 }, 1019 [R40_RST_BUS_I2C3] = { 0x02d8, 3 }, 1020 [R40_RST_BUS_I2C4] = { 0x02d8, 15 }, 1021 [R40_RST_BUS_UART0] = { 0x02d8, 16 }, 1022 [R40_RST_BUS_UART1] = { 0x02d8, 17 }, 1023 [R40_RST_BUS_UART2] = { 0x02d8, 18 }, 1024 [R40_RST_BUS_UART3] = { 0x02d8, 19 }, 1025 [R40_RST_BUS_UART4] = { 0x02d8, 20 }, 1026 [R40_RST_BUS_UART5] = { 0x02d8, 21 }, 1027 [R40_RST_BUS_UART6] = { 0x02d8, 22 }, 1028 [R40_RST_BUS_UART7] = { 0x02d8, 23 }, 1029 }; 1030 1031 /* V3s */ 1032 1033 #define V3S_RST_USB_PHY0 0 1034 1035 #define V3S_RST_BUS_MMC0 7 1036 #define V3S_RST_BUS_MMC1 8 1037 #define V3S_RST_BUS_MMC2 9 1038 #define V3S_RST_BUS_EMAC 12 1039 #define V3S_RST_BUS_EHCI0 18 1040 #define V3S_RST_BUS_OHCI0 22 1041 #define V3S_RST_BUS_EPHY 39 1042 #define V3S_RST_BUS_I2C0 46 1043 #define V3S_RST_BUS_I2C1 47 1044 #define V3S_RST_BUS_UART0 49 1045 #define V3S_RST_BUS_UART1 50 1046 #define V3S_RST_BUS_UART2 51 1047 1048 const struct sxiccmu_ccu_bit sun8i_v3s_resets[] = { 1049 [V3S_RST_USB_PHY0] = { 0x00cc, 0 }, 1050 [V3S_RST_BUS_OHCI0] = { 0x02c0, 29 }, 1051 [V3S_RST_BUS_EHCI0] = { 0x02c0, 26 }, 1052 [V3S_RST_BUS_EMAC] = { 0x02c0, 17 }, 1053 [V3S_RST_BUS_MMC2] = { 0x02c0, 10 }, 1054 [V3S_RST_BUS_MMC1] = { 0x02c0, 9 }, 1055 [V3S_RST_BUS_MMC0] = { 0x02c0, 8 }, 1056 [V3S_RST_BUS_EPHY] = { 0x02c8, 2 }, 1057 [V3S_RST_BUS_UART2] = { 0x02d8, 18 }, 1058 [V3S_RST_BUS_UART1] = { 0x02d8, 17 }, 1059 [V3S_RST_BUS_UART0] = { 0x02d8, 16 }, 1060 [V3S_RST_BUS_I2C1] = { 0x02d8, 1 }, 1061 [V3S_RST_BUS_I2C0] = { 0x02d8, 0 }, 1062 }; 1063