1 /* Public Domain */ 2 3 4 /* 5 * Clocks Signals 6 */ 7 8 /* A10/A20 */ 9 10 #define A10_CLK_HOSC 1 11 #define A10_CLK_PLL_CORE 2 12 #define A10_CLK_PLL_PERIPH_BASE 14 13 #define A10_CLK_PLL_PERIPH 15 14 15 #define A10_CLK_CPU 20 16 #define A10_CLK_AXI 21 17 #define A10_CLK_AHB 23 18 #define A10_CLK_APB1 25 19 20 #define A10_CLK_AHB_EHCI0 27 21 #define A10_CLK_AHB_OHCI0 28 22 #define A10_CLK_AHB_EHCI1 29 23 #define A10_CLK_AHB_OHCI1 30 24 #define A10_CLK_AHB_MMC0 34 25 #define A10_CLK_AHB_MMC1 35 26 #define A10_CLK_AHB_MMC2 36 27 #define A10_CLK_AHB_MMC3 37 28 #define A10_CLK_AHB_EMAC 42 29 #define A10_CLK_AHB_SATA 49 30 #define A10_CLK_AHB_GMAC 66 31 #define A10_CLK_APB0_PIO 74 32 #define A10_CLK_APB1_I2C0 79 33 #define A10_CLK_APB1_I2C1 80 34 #define A10_CLK_APB1_I2C2 81 35 #define A10_CLK_APB1_I2C3 82 36 #define A10_CLK_APB1_I2C4 87 37 #define A10_CLK_APB1_UART0 88 38 #define A10_CLK_APB1_UART1 89 39 #define A10_CLK_APB1_UART2 90 40 #define A10_CLK_APB1_UART3 91 41 #define A10_CLK_APB1_UART4 92 42 #define A10_CLK_APB1_UART5 93 43 #define A10_CLK_APB1_UART6 94 44 #define A10_CLK_APB1_UART7 95 45 46 #define A10_CLK_MMC0 98 47 #define A10_CLK_MMC1 101 48 #define A10_CLK_MMC2 104 49 #define A10_CLK_MMC3 107 50 #define A10_CLK_SATA 122 51 #define A10_CLK_USB_OHCI0 123 52 #define A10_CLK_USB_OHCI1 124 53 #define A10_CLK_USB_PHY 125 54 55 #define A10_CLK_LOSC 254 56 57 struct sxiccmu_ccu_bit sun4i_a10_gates[] = { 58 [A10_CLK_AHB_EHCI0] = { 0x0060, 1 }, 59 [A10_CLK_AHB_OHCI0] = { 0x0060, 2 }, 60 [A10_CLK_AHB_EHCI1] = { 0x0060, 3 }, 61 [A10_CLK_AHB_OHCI1] = { 0x0060, 4 }, 62 [A10_CLK_AHB_MMC0] = { 0x0060, 8 }, 63 [A10_CLK_AHB_MMC1] = { 0x0060, 9 }, 64 [A10_CLK_AHB_MMC2] = { 0x0060, 10 }, 65 [A10_CLK_AHB_MMC3] = { 0x0060, 11 }, 66 [A10_CLK_AHB_EMAC] = { 0x0060, 17 }, 67 [A10_CLK_AHB_SATA] = { 0x0060, 25 }, 68 [A10_CLK_AHB_GMAC] = { 0x0064, 17, A10_CLK_AHB }, 69 [A10_CLK_APB0_PIO] = { 0x0068, 5 }, 70 [A10_CLK_APB1_I2C0] = { 0x006c, 0, A10_CLK_APB1 }, 71 [A10_CLK_APB1_I2C1] = { 0x006c, 1, A10_CLK_APB1 }, 72 [A10_CLK_APB1_I2C2] = { 0x006c, 2, A10_CLK_APB1 }, 73 [A10_CLK_APB1_I2C3] = { 0x006c, 3, A10_CLK_APB1 }, 74 [A10_CLK_APB1_I2C4] = { 0x006c, 15, A10_CLK_APB1 }, 75 [A10_CLK_APB1_UART0] = { 0x006c, 16, A10_CLK_APB1 }, 76 [A10_CLK_APB1_UART1] = { 0x006c, 17, A10_CLK_APB1 }, 77 [A10_CLK_APB1_UART2] = { 0x006c, 18, A10_CLK_APB1 }, 78 [A10_CLK_APB1_UART3] = { 0x006c, 19, A10_CLK_APB1 }, 79 [A10_CLK_APB1_UART4] = { 0x006c, 20, A10_CLK_APB1 }, 80 [A10_CLK_APB1_UART5] = { 0x006c, 21, A10_CLK_APB1 }, 81 [A10_CLK_APB1_UART6] = { 0x006c, 22, A10_CLK_APB1 }, 82 [A10_CLK_APB1_UART7] = { 0x006c, 23, A10_CLK_APB1 }, 83 [A10_CLK_MMC0] = { 0x0088, 31 }, 84 [A10_CLK_MMC1] = { 0x008c, 31 }, 85 [A10_CLK_MMC2] = { 0x0090, 31 }, 86 [A10_CLK_MMC3] = { 0x0094, 31 }, 87 [A10_CLK_SATA] = { 0x00c8, 31 }, 88 [A10_CLK_USB_OHCI0] = { 0x00cc, 6 }, 89 [A10_CLK_USB_OHCI1] = { 0x00cc, 7 }, 90 [A10_CLK_USB_PHY] = { 0x00cc, 8 }, 91 }; 92 93 /* A23/A33 */ 94 95 #define A23_CLK_PLL_PERIPH 10 96 97 #define A23_CLK_AXI 19 98 #define A23_CLK_AHB1 20 99 #define A23_CLK_APB1 21 100 #define A23_CLK_APB2 22 101 102 #define A23_CLK_BUS_MMC0 26 103 #define A23_CLK_BUS_MMC1 27 104 #define A23_CLK_BUS_MMC2 28 105 #define A23_CLK_BUS_EHCI 35 106 #define A23_CLK_BUS_OHCI 36 107 #define A23_CLK_BUS_PIO 48 108 #define A23_CLK_BUS_I2C0 51 109 #define A23_CLK_BUS_I2C1 52 110 #define A23_CLK_BUS_I2C2 53 111 #define A23_CLK_BUS_UART0 54 112 #define A23_CLK_BUS_UART1 55 113 #define A23_CLK_BUS_UART2 56 114 #define A23_CLK_BUS_UART3 57 115 #define A23_CLK_BUS_UART4 58 116 117 #define A23_CLK_MMC0 60 118 #define A23_CLK_MMC1 63 119 #define A23_CLK_MMC2 66 120 #define A23_CLK_USB_OHCI 78 121 122 struct sxiccmu_ccu_bit sun8i_a23_gates[] = { 123 [A23_CLK_BUS_MMC0] = { 0x0060, 8 }, 124 [A23_CLK_BUS_MMC1] = { 0x0060, 9 }, 125 [A23_CLK_BUS_MMC2] = { 0x0060, 10 }, 126 [A23_CLK_BUS_EHCI] = { 0x0060, 26 }, 127 [A23_CLK_BUS_OHCI] = { 0x0060, 29 }, 128 [A23_CLK_BUS_PIO] = { 0x0068, 5 }, 129 [A23_CLK_BUS_I2C0] = { 0x006c, 0, A23_CLK_APB2 }, 130 [A23_CLK_BUS_I2C1] = { 0x006c, 1, A23_CLK_APB2 }, 131 [A23_CLK_BUS_I2C2] = { 0x006c, 2, A23_CLK_APB2 }, 132 [A23_CLK_BUS_UART0] = { 0x006c, 16, A23_CLK_APB2 }, 133 [A23_CLK_BUS_UART1] = { 0x006c, 17, A23_CLK_APB2 }, 134 [A23_CLK_BUS_UART2] = { 0x006c, 18, A23_CLK_APB2 }, 135 [A23_CLK_BUS_UART3] = { 0x006c, 19, A23_CLK_APB2 }, 136 [A23_CLK_BUS_UART4] = { 0x006c, 20, A23_CLK_APB2 }, 137 [A23_CLK_MMC0] = { 0x0088, 31 }, 138 [A23_CLK_MMC1] = { 0x008c, 31 }, 139 [A23_CLK_MMC2] = { 0x0090, 31 }, 140 [A23_CLK_USB_OHCI] = { 0x00cc, 16 }, 141 }; 142 143 /* A64 */ 144 145 #define A64_CLK_PLL_CPUX 1 146 147 #define A64_CLK_PLL_PERIPH0 11 148 #define A64_CLK_PLL_PERIPH0_2X 12 149 150 #define A64_CLK_CPUX 21 151 #define A64_CLK_AXI 22 152 #define A64_CLK_APB 23 153 #define A64_CLK_AHB1 24 154 #define A64_CLK_APB1 25 155 #define A64_CLK_APB2 26 156 #define A64_CLK_AHB2 27 157 158 #define A64_CLK_BUS_MMC0 31 159 #define A64_CLK_BUS_MMC1 32 160 #define A64_CLK_BUS_MMC2 33 161 #define A64_CLK_BUS_EMAC 36 162 #define A64_CLK_BUS_EHCI0 42 163 #define A64_CLK_BUS_EHCI1 43 164 #define A64_CLK_BUS_OHCI0 44 165 #define A64_CLK_BUS_OHCI1 45 166 #define A64_CLK_BUS_PIO 58 167 #define A64_CLK_BUS_THS 59 168 #define A64_CLK_BUS_I2C0 63 169 #define A64_CLK_BUS_I2C1 64 170 #define A64_CLK_BUS_I2C2 65 171 #define A64_CLK_BUS_UART0 67 172 #define A64_CLK_BUS_UART1 68 173 #define A64_CLK_BUS_UART2 69 174 #define A64_CLK_BUS_UART3 70 175 #define A64_CLK_BUS_UART4 71 176 177 #define A64_CLK_THS 73 178 #define A64_CLK_MMC0 75 179 #define A64_CLK_MMC1 76 180 #define A64_CLK_MMC2 77 181 #define A64_CLK_USB_OHCI0 91 182 #define A64_CLK_USB_OHCI1 93 183 #define A64_CLK_USB_PHY0 86 184 #define A64_CLK_USB_PHY1 87 185 186 #define A64_CLK_LOSC 254 187 #define A64_CLK_HOSC 253 188 189 struct sxiccmu_ccu_bit sun50i_a64_gates[] = { 190 [A64_CLK_PLL_PERIPH0] = { 0x0028, 31 }, 191 [A64_CLK_BUS_MMC0] = { 0x0060, 8 }, 192 [A64_CLK_BUS_MMC1] = { 0x0060, 9 }, 193 [A64_CLK_BUS_MMC2] = { 0x0060, 10 }, 194 [A64_CLK_BUS_EMAC] = { 0x0060, 17, A64_CLK_AHB2 }, 195 [A64_CLK_BUS_EHCI0] = { 0x0060, 24 }, 196 [A64_CLK_BUS_EHCI1] = { 0x0060, 25 }, 197 [A64_CLK_BUS_OHCI0] = { 0x0060, 28 }, 198 [A64_CLK_BUS_OHCI1] = { 0x0060, 29 }, 199 [A64_CLK_BUS_PIO] = { 0x0068, 5 }, 200 [A64_CLK_BUS_THS] = { 0x0068, 8 }, 201 [A64_CLK_BUS_I2C0] = { 0x006c, 0, A64_CLK_APB2 }, 202 [A64_CLK_BUS_I2C1] = { 0x006c, 1, A64_CLK_APB2 }, 203 [A64_CLK_BUS_I2C2] = { 0x006c, 2, A64_CLK_APB2 }, 204 [A64_CLK_BUS_UART0] = { 0x006c, 16, A64_CLK_APB2 }, 205 [A64_CLK_BUS_UART1] = { 0x006c, 17, A64_CLK_APB2 }, 206 [A64_CLK_BUS_UART2] = { 0x006c, 18, A64_CLK_APB2 }, 207 [A64_CLK_BUS_UART3] = { 0x006c, 19, A64_CLK_APB2 }, 208 [A64_CLK_BUS_UART4] = { 0x006c, 20, A64_CLK_APB2 }, 209 [A64_CLK_THS] = { 0x0074, 31 }, 210 [A64_CLK_MMC0] = { 0x0088, 31 }, 211 [A64_CLK_MMC1] = { 0x008c, 31 }, 212 [A64_CLK_MMC2] = { 0x0090, 31 }, 213 [A64_CLK_USB_OHCI0] = { 0x00cc, 16 }, 214 [A64_CLK_USB_OHCI1] = { 0x00cc, 17 }, 215 [A64_CLK_USB_PHY0] = { 0x00cc, 8 }, 216 [A64_CLK_USB_PHY1] = { 0x00cc, 9 }, 217 }; 218 219 /* A80 */ 220 221 #define A80_CLK_PLL_PERIPH0 3 222 #define A80_CLK_PLL_PERIPH1 11 223 224 #define A80_CLK_GTBUS 18 225 #define A80_CLK_AHB1 20 226 #define A80_CLK_APB1 23 227 228 #define A80_CLK_MMC0 33 229 #define A80_CLK_MMC1 36 230 #define A80_CLK_MMC2 39 231 #define A80_CLK_MMC3 42 232 233 #define A80_CLK_BUS_MMC 84 234 #define A80_CLK_BUS_USB 96 235 #define A80_CLK_BUS_GMAC 97 236 #define A80_CLK_BUS_PIO 111 237 #define A80_CLK_BUS_I2C0 119 238 #define A80_CLK_BUS_I2C1 120 239 #define A80_CLK_BUS_I2C2 121 240 #define A80_CLK_BUS_I2C3 122 241 #define A80_CLK_BUS_I2C4 123 242 #define A80_CLK_BUS_UART0 124 243 #define A80_CLK_BUS_UART1 125 244 #define A80_CLK_BUS_UART2 126 245 #define A80_CLK_BUS_UART3 127 246 #define A80_CLK_BUS_UART4 128 247 #define A80_CLK_BUS_UART5 129 248 249 struct sxiccmu_ccu_bit sun9i_a80_gates[] = { 250 [A80_CLK_MMC0] = { 0x0410, 31 }, 251 [A80_CLK_MMC1] = { 0x0414, 31 }, 252 [A80_CLK_MMC2] = { 0x0418, 31 }, 253 [A80_CLK_MMC3] = { 0x041c, 31 }, /* Undocumented */ 254 [A80_CLK_BUS_MMC] = { 0x0580, 8 }, 255 [A80_CLK_BUS_GMAC] = { 0x0584, 17, A80_CLK_AHB1 }, 256 [A80_CLK_BUS_USB] = { 0x0584, 1 }, 257 [A80_CLK_BUS_PIO] = { 0x0590, 5 }, 258 [A80_CLK_BUS_I2C0] = { 0x0594, 0, A80_CLK_APB1 }, 259 [A80_CLK_BUS_I2C1] = { 0x0594, 1, A80_CLK_APB1 }, 260 [A80_CLK_BUS_I2C2] = { 0x0594, 2, A80_CLK_APB1 }, 261 [A80_CLK_BUS_I2C3] = { 0x0594, 3, A80_CLK_APB1 }, 262 [A80_CLK_BUS_I2C4] = { 0x0594, 4, A80_CLK_APB1 }, 263 [A80_CLK_BUS_UART0] = { 0x0594, 16, A80_CLK_APB1 }, 264 [A80_CLK_BUS_UART1] = { 0x0594, 17, A80_CLK_APB1 }, 265 [A80_CLK_BUS_UART2] = { 0x0594, 18, A80_CLK_APB1 }, 266 [A80_CLK_BUS_UART3] = { 0x0594, 19, A80_CLK_APB1 }, 267 [A80_CLK_BUS_UART4] = { 0x0594, 20, A80_CLK_APB1 }, 268 [A80_CLK_BUS_UART5] = { 0x0594, 21, A80_CLK_APB1 }, 269 }; 270 271 #define A80_USB_CLK_HCI0 0 272 #define A80_USB_CLK_OHCI0 1 273 #define A80_USB_CLK_HCI1 2 274 #define A80_USB_CLK_HCI2 3 275 #define A80_USB_CLK_OHCI2 4 276 277 #define A80_USB_CLK_HCI0_PHY 5 278 #define A80_USB_CLK_HCI1_HSIC 6 279 #define A80_USB_CLK_HCI1_PHY 7 280 #define A80_USB_CLK_HCI2_HSIC 8 281 #define A80_USB_CLK_HCI2_UTMIPHY 9 282 #define A80_USB_CLK_HCI1_HSIC_12M 10 283 284 struct sxiccmu_ccu_bit sun9i_a80_usb_gates[] = { 285 [A80_USB_CLK_HCI0] = { 0x0000, 1 }, 286 [A80_USB_CLK_OHCI0] = { 0x0000, 2 }, 287 [A80_USB_CLK_HCI1] = { 0x0000, 3 }, 288 [A80_USB_CLK_HCI2] = { 0x0000, 5 }, 289 [A80_USB_CLK_OHCI2] = { 0x0000, 6 }, 290 [A80_USB_CLK_HCI0_PHY] = { 0x0004, 1 }, 291 [A80_USB_CLK_HCI1_HSIC] = { 0x0004, 2 }, 292 [A80_USB_CLK_HCI1_PHY] = { 0x0004, 3 }, /* Undocumented */ 293 [A80_USB_CLK_HCI2_HSIC] = { 0x0004, 4 }, 294 [A80_USB_CLK_HCI2_UTMIPHY] = { 0x0004, 5 }, 295 [A80_USB_CLK_HCI1_HSIC_12M] = { 0x0004, 10 }, 296 }; 297 298 struct sxiccmu_ccu_bit sun9i_a80_mmc_gates[] = { 299 { 0x0000, 16 }, 300 { 0x0004, 16 }, 301 { 0x0008, 16 }, 302 { 0x000c, 16 }, 303 }; 304 305 /* H3/H5 */ 306 307 #define H3_CLK_PLL_CPUX 0 308 #define H3_CLK_PLL_PERIPH0 9 309 310 #define H3_CLK_CPUX 14 311 #define H3_CLK_AXI 15 312 #define H3_CLK_AHB1 16 313 #define H3_CLK_APB1 17 314 #define H3_CLK_APB2 18 315 #define H3_CLK_AHB2 19 316 317 #define H3_CLK_BUS_MMC0 22 318 #define H3_CLK_BUS_MMC1 23 319 #define H3_CLK_BUS_MMC2 24 320 #define H3_CLK_BUS_EMAC 27 321 #define H3_CLK_BUS_EHCI0 33 322 #define H3_CLK_BUS_EHCI1 34 323 #define H3_CLK_BUS_EHCI2 35 324 #define H3_CLK_BUS_EHCI3 36 325 #define H3_CLK_BUS_OHCI0 37 326 #define H3_CLK_BUS_OHCI1 38 327 #define H3_CLK_BUS_OHCI2 39 328 #define H3_CLK_BUS_OHCI3 40 329 #define H3_CLK_BUS_PIO 54 330 #define H3_CLK_BUS_THS 55 331 #define H3_CLK_BUS_I2C0 59 332 #define H3_CLK_BUS_I2C1 60 333 #define H3_CLK_BUS_I2C2 61 334 #define H3_CLK_BUS_UART0 62 335 #define H3_CLK_BUS_UART1 63 336 #define H3_CLK_BUS_UART2 64 337 #define H3_CLK_BUS_UART3 65 338 #define H3_CLK_BUS_EPHY 67 339 340 #define H3_CLK_THS 69 341 #define H3_CLK_MMC0 71 342 #define H3_CLK_MMC1 74 343 #define H3_CLK_MMC2 77 344 #define H3_CLK_USB_PHY0 88 345 #define H3_CLK_USB_PHY1 89 346 #define H3_CLK_USB_PHY2 90 347 #define H3_CLK_USB_PHY3 91 348 #define H3_CLK_USB_OHCI0 92 349 #define H3_CLK_USB_OHCI1 93 350 #define H3_CLK_USB_OHCI2 94 351 #define H3_CLK_USB_OHCI3 95 352 353 #define H3_CLK_LOSC 254 354 #define H3_CLK_HOSC 253 355 356 struct sxiccmu_ccu_bit sun8i_h3_gates[] = { 357 [H3_CLK_PLL_PERIPH0] = { 0x0028, 31 }, 358 [H3_CLK_BUS_MMC0] = { 0x0060, 8 }, 359 [H3_CLK_BUS_MMC1] = { 0x0060, 9 }, 360 [H3_CLK_BUS_MMC2] = { 0x0060, 10 }, 361 [H3_CLK_BUS_EMAC] = { 0x0060, 17, H3_CLK_AHB2 }, 362 [H3_CLK_BUS_EHCI0] = { 0x0060, 24 }, 363 [H3_CLK_BUS_EHCI1] = { 0x0060, 25 }, 364 [H3_CLK_BUS_EHCI2] = { 0x0060, 26 }, 365 [H3_CLK_BUS_EHCI3] = { 0x0060, 27 }, 366 [H3_CLK_BUS_OHCI0] = { 0x0060, 28 }, 367 [H3_CLK_BUS_OHCI1] = { 0x0060, 29 }, 368 [H3_CLK_BUS_OHCI2] = { 0x0060, 30 }, 369 [H3_CLK_BUS_OHCI3] = { 0x0060, 31 }, 370 [H3_CLK_BUS_PIO] = { 0x0068, 5 }, 371 [H3_CLK_BUS_THS] = { 0x0068, 8 }, 372 [H3_CLK_BUS_I2C0] = { 0x006c, 0, H3_CLK_APB2 }, 373 [H3_CLK_BUS_I2C1] = { 0x006c, 1, H3_CLK_APB2 }, 374 [H3_CLK_BUS_I2C2] = { 0x006c, 2, H3_CLK_APB2 }, 375 [H3_CLK_BUS_UART0] = { 0x006c, 16, H3_CLK_APB2 }, 376 [H3_CLK_BUS_UART1] = { 0x006c, 17, H3_CLK_APB2 }, 377 [H3_CLK_BUS_UART2] = { 0x006c, 18, H3_CLK_APB2 }, 378 [H3_CLK_BUS_UART3] = { 0x006c, 19, H3_CLK_APB2 }, 379 [H3_CLK_BUS_EPHY] = { 0x0070, 0 }, 380 [H3_CLK_THS] = { 0x0074, 31 }, 381 [H3_CLK_MMC0] = { 0x0088, 31 }, 382 [H3_CLK_MMC1] = { 0x008c, 31 }, 383 [H3_CLK_MMC2] = { 0x0090, 31 }, 384 [H3_CLK_USB_PHY0] = { 0x00cc, 8 }, 385 [H3_CLK_USB_PHY1] = { 0x00cc, 9 }, 386 [H3_CLK_USB_PHY2] = { 0x00cc, 10 }, 387 [H3_CLK_USB_PHY3] = { 0x00cc, 11 }, 388 [H3_CLK_USB_OHCI0] = { 0x00cc, 16 }, 389 [H3_CLK_USB_OHCI1] = { 0x00cc, 17 }, 390 [H3_CLK_USB_OHCI2] = { 0x00cc, 18 }, 391 [H3_CLK_USB_OHCI3] = { 0x00cc, 19 }, 392 }; 393 394 #define H3_R_CLK_AHB0 1 395 #define H3_R_CLK_APB0 2 396 397 #define H3_R_CLK_APB0_PIO 3 398 #define H3_R_CLK_APB0_RSB 6 399 #define H3_R_CLK_APB0_I2C 9 400 401 struct sxiccmu_ccu_bit sun8i_h3_r_gates[] = { 402 [H3_R_CLK_APB0_PIO] = { 0x0028, 0 }, 403 [H3_R_CLK_APB0_RSB] = { 0x0028, 3, H3_R_CLK_APB0 }, 404 [H3_R_CLK_APB0_I2C] = { 0x0028, 6, H3_R_CLK_APB0 }, 405 }; 406 407 /* H6 */ 408 409 #define H6_CLK_PLL_PERIPH0 3 410 #define H6_CLK_PLL_PERIPH0_2X 4 411 #define H6_CLK_APB1 26 412 #define H6_CLK_APB2 27 413 #define H6_CLK_MMC0 64 414 #define H6_CLK_MMC1 65 415 #define H6_CLK_MMC2 66 416 #define H6_CLK_BUS_MMC0 67 417 #define H6_CLK_BUS_MMC1 68 418 #define H6_CLK_BUS_MMC2 69 419 #define H6_CLK_BUS_UART0 70 420 #define H6_CLK_BUS_UART1 71 421 #define H6_CLK_BUS_UART2 72 422 #define H6_CLK_BUS_UART3 73 423 #define H6_CLK_USB_OHCI0 104 424 #define H6_CLK_USB_OHCI3 107 425 #define H6_CLK_BUS_OHCI0 111 426 #define H6_CLK_BUS_OHCI3 112 427 #define H6_CLK_BUS_EHCI0 113 428 #define H6_CLK_BUS_EHCI3 115 429 430 struct sxiccmu_ccu_bit sun50i_h6_gates[] = { 431 [H6_CLK_PLL_PERIPH0] = { 0x0020, 31 }, 432 [H6_CLK_APB1] = { 0xffff, 0xff }, 433 [H6_CLK_MMC0] = { 0x0830, 31 }, 434 [H6_CLK_MMC1] = { 0x0834, 31 }, 435 [H6_CLK_MMC2] = { 0x0838, 31 }, 436 [H6_CLK_BUS_MMC0] = { 0x084c, 0 }, 437 [H6_CLK_BUS_MMC1] = { 0x084c, 1 }, 438 [H6_CLK_BUS_MMC2] = { 0x084c, 2 }, 439 [H6_CLK_BUS_UART0] = { 0x090c, 0, H6_CLK_APB2 }, 440 [H6_CLK_BUS_UART1] = { 0x090c, 1, H6_CLK_APB2 }, 441 [H6_CLK_BUS_UART2] = { 0x090c, 2, H6_CLK_APB2 }, 442 [H6_CLK_BUS_UART3] = { 0x090c, 3, H6_CLK_APB2 }, 443 [H6_CLK_USB_OHCI0] = { 0x0a70, 31 }, 444 [H6_CLK_USB_OHCI3] = { 0x0a7c, 31 }, 445 [H6_CLK_BUS_OHCI0] = { 0x0a8c, 0 }, 446 [H6_CLK_BUS_OHCI3] = { 0x0a8c, 3 }, 447 [H6_CLK_BUS_EHCI0] = { 0x0a8c, 4 }, 448 [H6_CLK_BUS_EHCI3] = { 0x0a8c, 7 }, 449 }; 450 451 #define H6_R_CLK_APB1 2 452 #define H6_R_CLK_APB2 3 453 #define H6_R_CLK_APB2_I2C 8 454 455 struct sxiccmu_ccu_bit sun50i_h6_r_gates[] = { 456 [H6_R_CLK_APB1] = { 0xffff, 0xff }, 457 [H6_R_CLK_APB2_I2C] = { 0x019c, 1, H6_R_CLK_APB2 }, 458 }; 459 460 /* R40 */ 461 462 #define R40_CLK_PLL_PERIPH0 11 463 #define R40_CLK_PLL_PERIPH0_2X 13 464 465 #define R40_CLK_AXI 25 466 #define R40_CLK_AHB1 26 467 #define R40_CLK_APB2 28 468 469 #define R40_CLK_BUS_MMC0 32 470 #define R40_CLK_BUS_MMC1 33 471 #define R40_CLK_BUS_MMC2 34 472 #define R40_CLK_BUS_MMC3 35 473 #define R40_CLK_BUS_SATA 45 474 #define R40_CLK_BUS_EHCI0 47 475 #define R40_CLK_BUS_EHCI1 48 476 #define R40_CLK_BUS_EHCI2 49 477 #define R40_CLK_BUS_OHCI0 50 478 #define R40_CLK_BUS_OHCI1 51 479 #define R40_CLK_BUS_OHCI2 52 480 #define R40_CLK_BUS_GMAC 64 481 #define R40_CLK_BUS_PIO 79 482 #define R40_CLK_BUS_THS 82 483 #define R40_CLK_BUS_I2C0 87 484 #define R40_CLK_BUS_I2C1 88 485 #define R40_CLK_BUS_I2C2 89 486 #define R40_CLK_BUS_I2C3 90 487 #define R40_CLK_BUS_I2C4 95 488 #define R40_CLK_BUS_UART0 96 489 #define R40_CLK_BUS_UART1 97 490 #define R40_CLK_BUS_UART2 98 491 #define R40_CLK_BUS_UART3 99 492 #define R40_CLK_BUS_UART4 100 493 #define R40_CLK_BUS_UART5 101 494 #define R40_CLK_BUS_UART6 102 495 #define R40_CLK_BUS_UART7 103 496 497 #define R40_CLK_THS 105 498 #define R40_CLK_MMC0 107 499 #define R40_CLK_MMC1 108 500 #define R40_CLK_MMC2 109 501 #define R40_CLK_MMC3 110 502 #define R40_CLK_SATA 123 503 #define R40_CLK_USB_PHY0 124 504 #define R40_CLK_USB_PHY1 125 505 #define R40_CLK_USB_PHY2 126 506 #define R40_CLK_USB_OHCI0 127 507 #define R40_CLK_USB_OHCI1 128 508 #define R40_CLK_USB_OHCI2 129 509 510 #define R40_CLK_HOSC 253 511 #define R40_CLK_LOSC 254 512 513 struct sxiccmu_ccu_bit sun8i_r40_gates[] = { 514 [R40_CLK_BUS_MMC0] = { 0x0060, 8 }, 515 [R40_CLK_BUS_MMC1] = { 0x0060, 9 }, 516 [R40_CLK_BUS_MMC2] = { 0x0060, 10 }, 517 [R40_CLK_BUS_MMC3] = { 0x0060, 11 }, 518 [R40_CLK_BUS_SATA] = { 0x0060, 24 }, 519 [R40_CLK_BUS_EHCI0] = { 0x0060, 26 }, 520 [R40_CLK_BUS_EHCI1] = { 0x0060, 27 }, 521 [R40_CLK_BUS_EHCI2] = { 0x0060, 28 }, 522 [R40_CLK_BUS_OHCI0] = { 0x0060, 29 }, 523 [R40_CLK_BUS_OHCI1] = { 0x0060, 30 }, 524 [R40_CLK_BUS_OHCI2] = { 0x0060, 31 }, 525 [R40_CLK_BUS_GMAC] = { 0x0064, 17, R40_CLK_AHB1 }, 526 [R40_CLK_BUS_PIO] = { 0x0068, 5 }, 527 [R40_CLK_BUS_THS] = { 0x0068, 8 }, 528 [R40_CLK_BUS_I2C0] = { 0x006c, 0, R40_CLK_APB2 }, 529 [R40_CLK_BUS_I2C1] = { 0x006c, 1, R40_CLK_APB2 }, 530 [R40_CLK_BUS_I2C2] = { 0x006c, 2, R40_CLK_APB2 }, 531 [R40_CLK_BUS_I2C3] = { 0x006c, 3, R40_CLK_APB2 }, 532 [R40_CLK_BUS_I2C4] = { 0x006c, 15, R40_CLK_APB2 }, 533 [R40_CLK_BUS_UART0] = { 0x006c, 16, R40_CLK_APB2 }, 534 [R40_CLK_BUS_UART1] = { 0x006c, 17, R40_CLK_APB2 }, 535 [R40_CLK_BUS_UART2] = { 0x006c, 18, R40_CLK_APB2 }, 536 [R40_CLK_BUS_UART3] = { 0x006c, 19, R40_CLK_APB2 }, 537 [R40_CLK_BUS_UART4] = { 0x006c, 20, R40_CLK_APB2 }, 538 [R40_CLK_BUS_UART5] = { 0x006c, 21, R40_CLK_APB2 }, 539 [R40_CLK_BUS_UART6] = { 0x006c, 22, R40_CLK_APB2 }, 540 [R40_CLK_BUS_UART7] = { 0x006c, 23, R40_CLK_APB2 }, 541 [R40_CLK_THS] = { 0x0074, 31 }, 542 [R40_CLK_MMC0] = { 0x0088, 31 }, 543 [R40_CLK_MMC1] = { 0x008c, 31 }, 544 [R40_CLK_MMC2] = { 0x0090, 31 }, 545 [R40_CLK_MMC3] = { 0x0094, 31 }, 546 [R40_CLK_SATA] = { 0x00c8, 31 }, 547 [R40_CLK_USB_PHY0] = { 0x00cc, 8 }, 548 [R40_CLK_USB_PHY1] = { 0x00cc, 9 }, 549 [R40_CLK_USB_PHY2] = { 0x00cc, 10 }, 550 [R40_CLK_USB_OHCI0] = { 0x00cc, 16 }, 551 [R40_CLK_USB_OHCI1] = { 0x00cc, 17 }, 552 [R40_CLK_USB_OHCI2] = { 0x00cc, 18 }, 553 }; 554 555 /* V3s */ 556 557 #define V3S_CLK_PLL_PERIPH0 9 558 #define V3S_CLK_AXI 15 559 #define V3S_CLK_AHB1 16 560 #define V3S_CLK_APB2 18 561 #define V3S_CLK_AHB2 19 562 563 #define V3S_CLK_BUS_MMC0 22 564 #define V3S_CLK_BUS_MMC1 23 565 #define V3S_CLK_BUS_MMC2 24 566 #define V3S_CLK_BUS_EMAC 26 567 #define V3S_CLK_BUS_EHCI0 30 568 #define V3S_CLK_BUS_OHCI0 31 569 #define V3S_CLK_BUS_PIO 37 570 #define V3S_CLK_BUS_I2C0 38 571 #define V3S_CLK_BUS_I2C1 39 572 #define V3S_CLK_BUS_UART0 40 573 #define V3S_CLK_BUS_UART1 41 574 #define V3S_CLK_BUS_UART2 42 575 #define V3S_CLK_BUS_EPHY 43 576 577 #define V3S_CLK_MMC0 45 578 #define V3S_CLK_MMC1 48 579 #define V3S_CLK_MMC2 51 580 #define V3S_CLK_USB_PHY0 56 581 #define V3S_CLK_USB_OHCI0 57 582 583 #define V3S_CLK_LOSC 254 584 #define V3S_CLK_HOSC 253 585 586 struct sxiccmu_ccu_bit sun8i_v3s_gates[] = { 587 [V3S_CLK_BUS_OHCI0] = { 0x0060, 29 }, 588 [V3S_CLK_BUS_EHCI0] = { 0x0060, 26 }, 589 [V3S_CLK_BUS_EMAC] = { 0x0060, 17, V3S_CLK_AHB2 }, 590 [V3S_CLK_BUS_MMC2] = { 0x0060, 10 }, 591 [V3S_CLK_BUS_MMC1] = { 0x0060, 9 }, 592 [V3S_CLK_BUS_MMC0] = { 0x0060, 8 }, 593 [V3S_CLK_BUS_PIO] = { 0x0068, 5 }, 594 [V3S_CLK_BUS_UART2] = { 0x006c, 18, V3S_CLK_APB2 }, 595 [V3S_CLK_BUS_UART1] = { 0x006c, 17, V3S_CLK_APB2 }, 596 [V3S_CLK_BUS_UART0] = { 0x006c, 16, V3S_CLK_APB2 }, 597 [V3S_CLK_BUS_I2C1] = { 0x006c, 1, V3S_CLK_APB2 }, 598 [V3S_CLK_BUS_I2C0] = { 0x006c, 0, V3S_CLK_APB2 }, 599 [V3S_CLK_BUS_EPHY] = { 0x0070, 0 }, 600 [V3S_CLK_MMC0] = { 0x0088, 31 }, 601 [V3S_CLK_MMC1] = { 0x008c, 31 }, 602 [V3S_CLK_MMC2] = { 0x0090, 31 }, 603 [V3S_CLK_USB_OHCI0] = { 0x00cc, 16 }, 604 [V3S_CLK_USB_PHY0] = { 0x00cc, 8 }, 605 }; 606 607 /* 608 * Reset Signals 609 */ 610 611 /* A10 */ 612 613 #define A10_RST_USB_PHY0 1 614 #define A10_RST_USB_PHY1 2 615 #define A10_RST_USB_PHY2 3 616 617 struct sxiccmu_ccu_bit sun4i_a10_resets[] = { 618 [A10_RST_USB_PHY0] = { 0x00cc, 0 }, 619 [A10_RST_USB_PHY1] = { 0x00cc, 1 }, 620 [A10_RST_USB_PHY2] = { 0x00cc, 2 }, 621 }; 622 623 /* A23/A33 */ 624 625 #define A23_RST_USB_PHY0 0 626 #define A23_RST_USB_PHY1 1 627 628 #define A23_RST_BUS_MMC0 7 629 #define A23_RST_BUS_MMC1 8 630 #define A23_RST_BUS_MMC2 9 631 632 #define A23_RST_BUS_EHCI 16 633 #define A23_RST_BUS_OHCI 17 634 635 #define A23_RST_BUS_I2C0 32 636 #define A23_RST_BUS_I2C1 33 637 #define A23_RST_BUS_I2C2 34 638 639 #define A23_CLK_HOSC 253 640 #define A23_CLK_LOSC 254 641 642 struct sxiccmu_ccu_bit sun8i_a23_resets[] = { 643 [A23_RST_USB_PHY0] = { 0x00cc, 0 }, 644 [A23_RST_USB_PHY1] = { 0x00cc, 1 }, 645 [A23_RST_BUS_MMC0] = { 0x02c0, 8 }, 646 [A23_RST_BUS_MMC1] = { 0x02c0, 9 }, 647 [A23_RST_BUS_MMC2] = { 0x02c0, 10 }, 648 [A23_RST_BUS_EHCI] = { 0x02c0, 26 }, 649 [A23_RST_BUS_OHCI] = { 0x02c0, 29 }, 650 [A23_RST_BUS_I2C0] = { 0x02d8, 0 }, 651 [A23_RST_BUS_I2C1] = { 0x02d8, 1 }, 652 [A23_RST_BUS_I2C2] = { 0x02d8, 2 }, 653 }; 654 655 /* A64 */ 656 657 #define A64_RST_USB_PHY0 0 658 #define A64_RST_USB_PHY1 1 659 660 #define A64_RST_BUS_MMC0 8 661 #define A64_RST_BUS_MMC1 9 662 #define A64_RST_BUS_MMC2 10 663 #define A64_RST_BUS_EMAC 13 664 #define A64_RST_BUS_EHCI0 19 665 #define A64_RST_BUS_EHCI1 20 666 #define A64_RST_BUS_OHCI0 21 667 #define A64_RST_BUS_OHCI1 22 668 #define A64_RST_BUS_THS 38 669 #define A64_RST_BUS_I2C0 42 670 #define A64_RST_BUS_I2C1 43 671 #define A64_RST_BUS_I2C2 44 672 673 struct sxiccmu_ccu_bit sun50i_a64_resets[] = { 674 [A64_RST_USB_PHY0] = { 0x00cc, 0 }, 675 [A64_RST_USB_PHY1] = { 0x00cc, 1 }, 676 [A64_RST_BUS_MMC0] = { 0x02c0, 8 }, 677 [A64_RST_BUS_MMC1] = { 0x02c0, 9 }, 678 [A64_RST_BUS_MMC2] = { 0x02c0, 10 }, 679 [A64_RST_BUS_EMAC] = { 0x02c0, 17 }, 680 [A64_RST_BUS_EHCI0] = { 0x02c0, 24 }, 681 [A64_RST_BUS_EHCI1] = { 0x02c0, 25 }, 682 [A64_RST_BUS_OHCI0] = { 0x02c0, 28 }, 683 [A64_RST_BUS_OHCI1] = { 0x02c0, 29 }, 684 [A64_RST_BUS_THS] = { 0x02d0, 8 }, 685 [A64_RST_BUS_I2C0] = { 0x02d8, 0 }, 686 [A64_RST_BUS_I2C1] = { 0x02d8, 1 }, 687 [A64_RST_BUS_I2C2] = { 0x02d8, 2 }, 688 }; 689 690 /* A80 */ 691 692 #define A80_RST_BUS_MMC 4 693 #define A80_RST_BUS_GMAC 17 694 #define A80_RST_BUS_I2C0 40 695 #define A80_RST_BUS_I2C1 41 696 #define A80_RST_BUS_I2C2 42 697 #define A80_RST_BUS_I2C3 43 698 #define A80_RST_BUS_I2C4 44 699 #define A80_RST_BUS_UART0 45 700 #define A80_RST_BUS_UART1 46 701 #define A80_RST_BUS_UART2 47 702 #define A80_RST_BUS_UART3 48 703 #define A80_RST_BUS_UART4 49 704 #define A80_RST_BUS_UART5 50 705 706 struct sxiccmu_ccu_bit sun9i_a80_resets[] = { 707 [A80_RST_BUS_MMC] = { 0x05a0, 8 }, 708 [A80_RST_BUS_GMAC] = { 0x05a4, 17 }, 709 [A80_RST_BUS_I2C0] = { 0x05b4, 0 }, 710 [A80_RST_BUS_I2C1] = { 0x05b4, 1 }, 711 [A80_RST_BUS_I2C2] = { 0x05b4, 2 }, 712 [A80_RST_BUS_I2C3] = { 0x05b4, 3 }, 713 [A80_RST_BUS_I2C4] = { 0x05b4, 4 }, 714 [A80_RST_BUS_UART0] = { 0x05b4, 16 }, 715 [A80_RST_BUS_UART1] = { 0x05b4, 17 }, 716 [A80_RST_BUS_UART2] = { 0x05b4, 18 }, 717 [A80_RST_BUS_UART3] = { 0x05b4, 19 }, 718 [A80_RST_BUS_UART4] = { 0x05b4, 20 }, 719 [A80_RST_BUS_UART5] = { 0x05b4, 21 }, 720 }; 721 722 #define A80_USB_RST_HCI0 0 723 #define A80_USB_RST_HCI1 1 724 #define A80_USB_RST_HCI2 2 725 726 #define A80_USB_RST_HCI0_PHY 3 727 #define A80_USB_RST_HCI1_HSIC 4 728 #define A80_USB_RST_HCI1_PHY 5 729 #define A80_USB_RST_HCI2_HSIC 6 730 #define A80_USB_RST_HCI2_UTMIPHY 7 731 732 struct sxiccmu_ccu_bit sun9i_a80_usb_resets[] = { 733 [A80_USB_RST_HCI0] = { 0x0000, 17 }, 734 [A80_USB_RST_HCI1] = { 0x0000, 18 }, 735 [A80_USB_RST_HCI2] = { 0x0000, 19 }, 736 [A80_USB_RST_HCI0_PHY] = { 0x0004, 17 }, 737 [A80_USB_RST_HCI1_HSIC]= { 0x0004, 18 }, 738 [A80_USB_RST_HCI1_PHY]= { 0x0004, 19 }, /* Undocumented */ 739 [A80_USB_RST_HCI2_HSIC]= { 0x0004, 20 }, /* Undocumented */ 740 [A80_USB_RST_HCI2_UTMIPHY] = { 0x0004, 21 }, 741 }; 742 743 struct sxiccmu_ccu_bit sun9i_a80_mmc_resets[] = { 744 { 0x0000, 18 }, 745 { 0x0004, 18 }, 746 { 0x0008, 18 }, 747 { 0x000c, 18 }, 748 }; 749 750 /* H3/H5 */ 751 752 #define H3_RST_USB_PHY0 0 753 #define H3_RST_USB_PHY1 1 754 #define H3_RST_USB_PHY2 2 755 #define H3_RST_USB_PHY3 3 756 757 #define H3_RST_BUS_MMC0 7 758 #define H3_RST_BUS_MMC1 8 759 #define H3_RST_BUS_MMC2 9 760 761 #define H3_RST_BUS_EMAC 12 762 763 #define H3_RST_BUS_EHCI0 18 764 #define H3_RST_BUS_EHCI1 19 765 #define H3_RST_BUS_EHCI2 20 766 #define H3_RST_BUS_EHCI3 21 767 #define H3_RST_BUS_OHCI0 22 768 #define H3_RST_BUS_OHCI1 23 769 #define H3_RST_BUS_OHCI2 24 770 #define H3_RST_BUS_OHCI3 25 771 #define H3_RST_BUS_EPHY 39 772 #define H3_RST_BUS_THS 42 773 #define H3_RST_BUS_I2C0 46 774 #define H3_RST_BUS_I2C1 47 775 #define H3_RST_BUS_I2C2 48 776 #define H3_RST_BUS_UART0 49 777 #define H3_RST_BUS_UART1 50 778 #define H3_RST_BUS_UART2 51 779 #define H3_RST_BUS_UART3 52 780 781 struct sxiccmu_ccu_bit sun8i_h3_resets[] = { 782 [H3_RST_USB_PHY0] = { 0x00cc, 0 }, 783 [H3_RST_USB_PHY1] = { 0x00cc, 1 }, 784 [H3_RST_USB_PHY2] = { 0x00cc, 2 }, 785 [H3_RST_USB_PHY3] = { 0x00cc, 3 }, 786 [H3_RST_BUS_MMC0] = { 0x02c0, 8 }, 787 [H3_RST_BUS_MMC1] = { 0x02c0, 9 }, 788 [H3_RST_BUS_MMC2] = { 0x02c0, 10 }, 789 [H3_RST_BUS_EMAC] = { 0x02c0, 17 }, 790 [H3_RST_BUS_EHCI0] = { 0x02c0, 24 }, 791 [H3_RST_BUS_EHCI1] = { 0x02c0, 25 }, 792 [H3_RST_BUS_EHCI2] = { 0x02c0, 26 }, 793 [H3_RST_BUS_EHCI3] = { 0x02c0, 27 }, 794 [H3_RST_BUS_OHCI0] = { 0x02c0, 28 }, 795 [H3_RST_BUS_OHCI1] = { 0x02c0, 29 }, 796 [H3_RST_BUS_OHCI2] = { 0x02c0, 30 }, 797 [H3_RST_BUS_OHCI3] = { 0x02c0, 31 }, 798 [H3_RST_BUS_EPHY] = { 0x02c8, 2 }, 799 [H3_RST_BUS_THS] = { 0x02d0, 8 }, 800 [H3_RST_BUS_I2C0] = { 0x02d8, 0 }, 801 [H3_RST_BUS_I2C1] = { 0x02d8, 1 }, 802 [H3_RST_BUS_I2C2] = { 0x02d8, 2 }, 803 [H3_RST_BUS_UART0] = { 0x02d8, 16 }, 804 [H3_RST_BUS_UART1] = { 0x02d8, 17 }, 805 [H3_RST_BUS_UART2] = { 0x02d8, 18 }, 806 [H3_RST_BUS_UART3] = { 0x02d8, 19 }, 807 }; 808 809 #define H3_R_RST_APB0_RSB 2 810 #define H3_R_RST_APB0_I2C 5 811 812 struct sxiccmu_ccu_bit sun8i_h3_r_resets[] = { 813 [H3_R_RST_APB0_RSB] = { 0x00b0, 3 }, 814 [H3_R_RST_APB0_I2C] = { 0x00b0, 6 }, 815 }; 816 817 /* H6 */ 818 819 #define H6_RST_BUS_MMC0 18 820 #define H6_RST_BUS_MMC1 19 821 #define H6_RST_BUS_MMC2 20 822 #define H6_RST_BUS_UART0 21 823 #define H6_RST_BUS_UART1 22 824 #define H6_RST_BUS_UART2 23 825 #define H6_RST_BUS_UART3 24 826 #define H6_RST_BUS_OHCI0 48 827 #define H6_RST_BUS_OHCI3 49 828 #define H6_RST_BUS_EHCI0 50 829 #define H6_RST_BUS_EHCI3 52 830 831 struct sxiccmu_ccu_bit sun50i_h6_resets[] = { 832 [H6_RST_BUS_MMC0] = { 0x084c, 16 }, 833 [H6_RST_BUS_MMC1] = { 0x084c, 17 }, 834 [H6_RST_BUS_MMC2] = { 0x084c, 18 }, 835 [H6_RST_BUS_UART0] = { 0x090c, 16 }, 836 [H6_RST_BUS_UART1] = { 0x090c, 17 }, 837 [H6_RST_BUS_UART2] = { 0x090c, 18 }, 838 [H6_RST_BUS_UART3] = { 0x090c, 19 }, 839 [H6_RST_BUS_OHCI0] = { 0x0a8c, 16 }, 840 [H6_RST_BUS_OHCI3] = { 0x0a8c, 19 }, 841 [H6_RST_BUS_EHCI0] = { 0x0a8c, 20 }, 842 [H6_RST_BUS_EHCI3] = { 0x0a8c, 23 }, 843 }; 844 845 #define H6_R_RST_APB2_I2C 4 846 847 struct sxiccmu_ccu_bit sun50i_h6_r_resets[] = { 848 [H6_R_RST_APB2_I2C] = { 0x019c, 16 }, 849 }; 850 851 /* R40 */ 852 853 #define R40_RST_USB_PHY0 0 854 #define R40_RST_USB_PHY1 1 855 #define R40_RST_USB_PHY2 2 856 857 #define R40_RST_BUS_MMC0 8 858 #define R40_RST_BUS_MMC1 9 859 #define R40_RST_BUS_MMC2 10 860 #define R40_RST_BUS_MMC3 11 861 #define R40_RST_BUS_SATA 21 862 #define R40_RST_BUS_EHCI0 23 863 #define R40_RST_BUS_EHCI1 24 864 #define R40_RST_BUS_EHCI2 25 865 #define R40_RST_BUS_OHCI0 26 866 #define R40_RST_BUS_OHCI1 27 867 #define R40_RST_BUS_OHCI2 28 868 #define R40_RST_BUS_GMAC 40 869 #define R40_RST_BUS_THS 59 870 #define R40_RST_BUS_I2C0 64 871 #define R40_RST_BUS_I2C1 65 872 #define R40_RST_BUS_I2C2 66 873 #define R40_RST_BUS_I2C3 67 874 #define R40_RST_BUS_I2C4 72 875 #define R40_RST_BUS_UART0 73 876 #define R40_RST_BUS_UART1 74 877 #define R40_RST_BUS_UART2 75 878 #define R40_RST_BUS_UART3 76 879 #define R40_RST_BUS_UART4 77 880 #define R40_RST_BUS_UART5 78 881 #define R40_RST_BUS_UART6 79 882 #define R40_RST_BUS_UART7 80 883 884 struct sxiccmu_ccu_bit sun8i_r40_resets[] = { 885 [R40_RST_USB_PHY0] = { 0x00cc, 0 }, 886 [R40_RST_USB_PHY1] = { 0x00cc, 1 }, 887 [R40_RST_USB_PHY2] = { 0x00cc, 2 }, 888 [R40_RST_BUS_MMC0] = { 0x02c0, 8 }, 889 [R40_RST_BUS_MMC1] = { 0x02c0, 9 }, 890 [R40_RST_BUS_MMC2] = { 0x02c0, 10 }, 891 [R40_RST_BUS_MMC3] = { 0x02c0, 11 }, 892 [R40_RST_BUS_SATA] = { 0x02c0, 24 }, 893 [R40_RST_BUS_EHCI0] = { 0x02c0, 26 }, 894 [R40_RST_BUS_EHCI1] = { 0x02c0, 27 }, 895 [R40_RST_BUS_EHCI2] = { 0x02c0, 28 }, 896 [R40_RST_BUS_OHCI0] = { 0x02c0, 29 }, 897 [R40_RST_BUS_OHCI1] = { 0x02c0, 30 }, 898 [R40_RST_BUS_OHCI2] = { 0x02c0, 31 }, 899 [R40_RST_BUS_GMAC] = { 0x02c4, 17 }, 900 [R40_RST_BUS_THS] = { 0x02d0, 8 }, 901 [R40_RST_BUS_I2C0] = { 0x02d8, 0 }, 902 [R40_RST_BUS_I2C1] = { 0x02d8, 1 }, 903 [R40_RST_BUS_I2C2] = { 0x02d8, 2 }, 904 [R40_RST_BUS_I2C3] = { 0x02d8, 3 }, 905 [R40_RST_BUS_I2C4] = { 0x02d8, 15 }, 906 [R40_RST_BUS_UART0] = { 0x02d8, 16 }, 907 [R40_RST_BUS_UART1] = { 0x02d8, 17 }, 908 [R40_RST_BUS_UART2] = { 0x02d8, 18 }, 909 [R40_RST_BUS_UART3] = { 0x02d8, 19 }, 910 [R40_RST_BUS_UART4] = { 0x02d8, 20 }, 911 [R40_RST_BUS_UART5] = { 0x02d8, 21 }, 912 [R40_RST_BUS_UART6] = { 0x02d8, 22 }, 913 [R40_RST_BUS_UART7] = { 0x02d8, 23 }, 914 }; 915 916 /* V3s */ 917 918 #define V3S_RST_USB_PHY0 0 919 920 #define V3S_RST_BUS_MMC0 7 921 #define V3S_RST_BUS_MMC1 8 922 #define V3S_RST_BUS_MMC2 9 923 #define V3S_RST_BUS_EMAC 12 924 #define V3S_RST_BUS_EHCI0 18 925 #define V3S_RST_BUS_OHCI0 22 926 #define V3S_RST_BUS_EPHY 39 927 #define V3S_RST_BUS_I2C0 46 928 #define V3S_RST_BUS_I2C1 47 929 #define V3S_RST_BUS_UART0 49 930 #define V3S_RST_BUS_UART1 50 931 #define V3S_RST_BUS_UART2 51 932 933 struct sxiccmu_ccu_bit sun8i_v3s_resets[] = { 934 [V3S_RST_USB_PHY0] = { 0x00cc, 0 }, 935 [V3S_RST_BUS_OHCI0] = { 0x02c0, 29 }, 936 [V3S_RST_BUS_EHCI0] = { 0x02c0, 26 }, 937 [V3S_RST_BUS_EMAC] = { 0x02c0, 17 }, 938 [V3S_RST_BUS_MMC2] = { 0x02c0, 10 }, 939 [V3S_RST_BUS_MMC1] = { 0x02c0, 9 }, 940 [V3S_RST_BUS_MMC0] = { 0x02c0, 8 }, 941 [V3S_RST_BUS_EPHY] = { 0x02c8, 2 }, 942 [V3S_RST_BUS_UART2] = { 0x02d8, 18 }, 943 [V3S_RST_BUS_UART1] = { 0x02d8, 17 }, 944 [V3S_RST_BUS_UART0] = { 0x02d8, 16 }, 945 [V3S_RST_BUS_I2C1] = { 0x02d8, 1 }, 946 [V3S_RST_BUS_I2C0] = { 0x02d8, 0 }, 947 }; 948