1 /* $OpenBSD: aic6360.c,v 1.3 2000/12/13 16:15:57 mickey Exp $ */ 2 /* $NetBSD: aic6360.c,v 1.52 1996/12/10 21:27:51 thorpej Exp $ */ 3 4 #ifdef DDB 5 #define integrate 6 #else 7 #define integrate static inline 8 #endif 9 10 /* 11 * Copyright (c) 1994, 1995, 1996 Charles Hannum. All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by Charles M. Hannum. 24 * 4. The name of the author may not be used to endorse or promote products 25 * derived from this software without specific prior written permission. 26 * 27 * Copyright (c) 1994 Jarle Greipsland 28 * All rights reserved. 29 * 30 * Redistribution and use in source and binary forms, with or without 31 * modification, are permitted provided that the following conditions 32 * are met: 33 * 1. Redistributions of source code must retain the above copyright 34 * notice, this list of conditions and the following disclaimer. 35 * 2. Redistributions in binary form must reproduce the above copyright 36 * notice, this list of conditions and the following disclaimer in the 37 * documentation and/or other materials provided with the distribution. 38 * 3. The name of the author may not be used to endorse or promote products 39 * derived from this software without specific prior written permission. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 43 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 44 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 45 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 49 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 50 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 51 * POSSIBILITY OF SUCH DAMAGE. 52 */ 53 54 /* 55 * Acknowledgements: Many of the algorithms used in this driver are 56 * inspired by the work of Julian Elischer (julian@tfs.com) and 57 * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million! 58 */ 59 60 /* TODO list: 61 * 1) Get the DMA stuff working. 62 * 2) Get the iov/uio stuff working. Is this a good thing ??? 63 * 3) Get the synch stuff working. 64 * 4) Rewrite it to use malloc for the acb structs instead of static alloc.? 65 */ 66 67 /* 68 * A few customizable items: 69 */ 70 71 /* Use doubleword transfers to/from SCSI chip. Note: This requires 72 * motherboard support. Basicly, some motherboard chipsets are able to 73 * split a 32 bit I/O operation into two 16 bit I/O operations, 74 * transparently to the processor. This speeds up some things, notably long 75 * data transfers. 76 */ 77 #define AIC_USE_DWORDS 0 78 79 /* Synchronous data transfers? */ 80 #define AIC_USE_SYNCHRONOUS 0 81 #define AIC_SYNC_REQ_ACK_OFS 8 82 83 /* Wide data transfers? */ 84 #define AIC_USE_WIDE 0 85 #define AIC_MAX_WIDTH 0 86 87 /* Max attempts made to transmit a message */ 88 #define AIC_MSG_MAX_ATTEMPT 3 /* Not used now XXX */ 89 90 /* Use DMA (else we do programmed I/O using string instructions) (not yet!)*/ 91 #define AIC_USE_EISA_DMA 0 92 #define AIC_USE_ISA_DMA 0 93 94 /* How to behave on the (E)ISA bus when/if DMAing (on<<4) + off in us */ 95 #define EISA_BRST_TIM ((15<<4) + 1) /* 15us on, 1us off */ 96 97 /* Some spin loop parameters (essentially how long to wait some places) 98 * The problem(?) is that sometimes we expect either to be able to transmit a 99 * byte or to get a new one from the SCSI bus pretty soon. In order to avoid 100 * returning from the interrupt just to get yanked back for the next byte we 101 * may spin in the interrupt routine waiting for this byte to come. How long? 102 * This is really (SCSI) device and processor dependent. Tuneable, I guess. 103 */ 104 #define AIC_MSGIN_SPIN 1 /* Spin upto ?ms for a new msg byte */ 105 #define AIC_MSGOUT_SPIN 1 106 107 /* Include debug functions? At the end of this file there are a bunch of 108 * functions that will print out various information regarding queued SCSI 109 * commands, driver state and chip contents. You can call them from the 110 * kernel debugger. If you set AIC_DEBUG to 0 they are not included (the 111 * kernel uses less memory) but you lose the debugging facilities. 112 */ 113 #define AIC_DEBUG 1 114 115 #define AIC_ABORT_TIMEOUT 2000 /* time to wait for abort */ 116 117 /* End of customizable parameters */ 118 119 #if AIC_USE_EISA_DMA || AIC_USE_ISA_DMA 120 #error "I said not yet! Start paying attention... grumble" 121 #endif 122 123 #include <sys/types.h> 124 #include <sys/param.h> 125 #include <sys/systm.h> 126 #include <sys/kernel.h> 127 #include <sys/errno.h> 128 #include <sys/ioctl.h> 129 #include <sys/device.h> 130 #include <sys/buf.h> 131 #include <sys/proc.h> 132 #include <sys/user.h> 133 #include <sys/queue.h> 134 135 #include <machine/bus.h> 136 #include <machine/intr.h> 137 138 #include <scsi/scsi_all.h> 139 #include <scsi/scsi_message.h> 140 #include <scsi/scsiconf.h> 141 142 #include <dev/isa/isavar.h> 143 144 #include <dev/ic/aic6360reg.h> 145 #include <dev/ic/aic6360var.h> 146 147 #ifndef DDB 148 #define Debugger() panic("should call debugger here (aic6360.c)") 149 #endif /* ! DDB */ 150 151 #if AIC_DEBUG 152 int aic_debug = 0x00; /* AIC_SHOWSTART|AIC_SHOWMISC|AIC_SHOWTRACE; */ 153 #endif 154 155 void aic_minphys __P((struct buf *)); 156 void aic_init __P((struct aic_softc *)); 157 void aic_done __P((struct aic_softc *, struct aic_acb *)); 158 void aic_dequeue __P((struct aic_softc *, struct aic_acb *)); 159 int aic_scsi_cmd __P((struct scsi_xfer *)); 160 int aic_poll __P((struct aic_softc *, struct scsi_xfer *, int)); 161 integrate void aic_sched_msgout __P((struct aic_softc *, u_char)); 162 integrate void aic_setsync __P((struct aic_softc *, struct aic_tinfo *)); 163 void aic_select __P((struct aic_softc *, struct aic_acb *)); 164 void aic_timeout __P((void *)); 165 void aic_sched __P((struct aic_softc *)); 166 void aic_scsi_reset __P((struct aic_softc *)); 167 void aic_reset __P((struct aic_softc *)); 168 void aic_free_acb __P((struct aic_softc *, struct aic_acb *, int)); 169 struct aic_acb* aic_get_acb __P((struct aic_softc *, int)); 170 int aic_reselect __P((struct aic_softc *, int)); 171 void aic_sense __P((struct aic_softc *, struct aic_acb *)); 172 void aic_msgin __P((struct aic_softc *)); 173 void aic_abort __P((struct aic_softc *, struct aic_acb *)); 174 void aic_msgout __P((struct aic_softc *)); 175 int aic_dataout_pio __P((struct aic_softc *, u_char *, int)); 176 int aic_datain_pio __P((struct aic_softc *, u_char *, int)); 177 #if AIC_DEBUG 178 void aic_print_acb __P((struct aic_acb *)); 179 void aic_dump_driver __P((struct aic_softc *)); 180 void aic_dump6360 __P((struct aic_softc *)); 181 void aic_show_scsi_cmd __P((struct aic_acb *)); 182 void aic_print_active_acb __P((void)); 183 #endif 184 185 struct cfdriver aic_cd = { 186 NULL, "aic", DV_DULL 187 }; 188 189 struct scsi_adapter aic_switch = { 190 aic_scsi_cmd, 191 aic_minphys, 192 0, 193 0, 194 }; 195 196 struct scsi_device aic_dev = { 197 NULL, /* Use default error handler */ 198 NULL, /* have a queue, served by this */ 199 NULL, /* have no async handler */ 200 NULL, /* Use default 'done' routine */ 201 }; 202 203 204 /* 205 * Do the real search-for-device. 206 */ 207 int 208 aic_find(iot, ioh) 209 bus_space_tag_t iot; 210 bus_space_handle_t ioh; 211 { 212 char chip_id[sizeof(IDSTRING)]; /* For chips that support it */ 213 int i; 214 215 /* Remove aic6360 from possible powerdown mode */ 216 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 217 218 /* Thanks to mark@aggregate.com for the new method for detecting 219 * whether the chip is present or not. Bonus: may also work for 220 * the AIC-6260! 221 */ 222 AIC_TRACE(("aic: probing for aic-chip\n")); 223 /* 224 * Linux also init's the stack to 1-16 and then clears it, 225 * 6260's don't appear to have an ID reg - mpg 226 */ 227 /* Push the sequence 0,1,..,15 on the stack */ 228 #define STSIZE 16 229 bus_space_write_1(iot, ioh, DMACNTRL1, 0); /* Reset stack pointer */ 230 for (i = 0; i < STSIZE; i++) 231 bus_space_write_1(iot, ioh, STACK, i); 232 233 /* See if we can pull out the same sequence */ 234 bus_space_write_1(iot, ioh, DMACNTRL1, 0); 235 for (i = 0; i < STSIZE && bus_space_read_1(iot, ioh, STACK) == i; i++) 236 ; 237 if (i != STSIZE) { 238 AIC_START(("STACK futzed at %d.\n", i)); 239 return (0); 240 } 241 242 /* See if we can pull the id string out of the ID register, 243 * now only used for informational purposes. 244 */ 245 bzero(chip_id, sizeof(chip_id)); 246 bus_space_read_multi_1(iot, ioh, ID, chip_id, sizeof(IDSTRING) - 1); 247 AIC_START(("AIC ID: %s ", chip_id)); 248 AIC_START(("chip revision %d\n", 249 (int)bus_space_read_1(iot, ioh, REV))); 250 251 return (1); 252 } 253 254 /* 255 * Attach the AIC6360, fill out some high and low level data structures 256 */ 257 void 258 aicattach(sc) 259 struct aic_softc *sc; 260 { 261 AIC_TRACE(("aicattach ")); 262 sc->sc_state = AIC_INIT; 263 264 sc->sc_initiator = 7; 265 sc->sc_freq = 20; /* XXXX assume 20 MHz. */ 266 267 /* 268 * These are the bounds of the sync period, based on the frequency of 269 * the chip's clock input and the size and offset of the sync period 270 * register. 271 * 272 * For a 20Mhz clock, this gives us 25, or 100nS, or 10MB/s, as a 273 * maximum transfer rate, and 112.5, or 450nS, or 2.22MB/s, as a 274 * minimum transfer rate. 275 */ 276 sc->sc_minsync = (2 * 250) / sc->sc_freq; 277 sc->sc_maxsync = (9 * 250) / sc->sc_freq; 278 279 aic_init(sc); /* init chip and driver */ 280 281 /* 282 * Fill in the prototype scsi_link 283 */ 284 sc->sc_link.adapter_softc = sc; 285 sc->sc_link.adapter_target = sc->sc_initiator; 286 sc->sc_link.adapter = &aic_switch; 287 sc->sc_link.device = &aic_dev; 288 sc->sc_link.openings = 2; 289 290 config_found(&sc->sc_dev, &sc->sc_link, scsiprint); 291 } 292 293 /* Initialize AIC6360 chip itself 294 * The following conditions should hold: 295 * aicprobe should have succeeded, i.e. the ioh handle in aic_softc must 296 * be valid. 297 */ 298 void 299 aic_reset(sc) 300 struct aic_softc *sc; 301 { 302 bus_space_tag_t iot = sc->sc_iot; 303 bus_space_handle_t ioh = sc->sc_ioh; 304 305 /* 306 * Doc. recommends to clear these two registers before operations 307 * commence 308 */ 309 bus_space_write_1(iot, ioh, SCSITEST, 0); 310 bus_space_write_1(iot, ioh, TEST, 0); 311 312 /* Reset SCSI-FIFO and abort any transfers */ 313 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | CLRCH | CLRSTCNT); 314 315 /* Reset DMA-FIFO */ 316 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO); 317 bus_space_write_1(iot, ioh, DMACNTRL1, 0); 318 319 /* Disable all selection features */ 320 bus_space_write_1(iot, ioh, SCSISEQ, 0); 321 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 322 323 /* Disable some interrupts */ 324 bus_space_write_1(iot, ioh, SIMODE0, 0x00); 325 /* Clear a slew of interrupts */ 326 bus_space_write_1(iot, ioh, CLRSINT0, 0x7f); 327 328 /* Disable some more interrupts */ 329 bus_space_write_1(iot, ioh, SIMODE1, 0x00); 330 /* Clear another slew of interrupts */ 331 bus_space_write_1(iot, ioh, CLRSINT1, 0xef); 332 333 /* Disable synchronous transfers */ 334 bus_space_write_1(iot, ioh, SCSIRATE, 0); 335 336 /* Haven't seen ant errors (yet) */ 337 bus_space_write_1(iot, ioh, CLRSERR, 0x07); 338 339 /* Set our SCSI-ID */ 340 bus_space_write_1(iot, ioh, SCSIID, sc->sc_initiator << OID_S); 341 bus_space_write_1(iot, ioh, BRSTCNTRL, EISA_BRST_TIM); 342 } 343 344 /* Pull the SCSI RST line for 500 us */ 345 void 346 aic_scsi_reset(sc) 347 struct aic_softc *sc; 348 { 349 bus_space_tag_t iot = sc->sc_iot; 350 bus_space_handle_t ioh = sc->sc_ioh; 351 352 bus_space_write_1(iot, ioh, SCSISEQ, SCSIRSTO); 353 delay(500); 354 bus_space_write_1(iot, ioh, SCSISEQ, 0); 355 delay(50); 356 } 357 358 /* 359 * Initialize aic SCSI driver. 360 */ 361 void 362 aic_init(sc) 363 struct aic_softc *sc; 364 { 365 bus_space_tag_t iot = sc->sc_iot; 366 bus_space_handle_t ioh = sc->sc_ioh; 367 struct aic_acb *acb; 368 int r; 369 370 aic_reset(sc); 371 aic_scsi_reset(sc); 372 aic_reset(sc); 373 374 if (sc->sc_state == AIC_INIT) { 375 /* First time through; initialize. */ 376 TAILQ_INIT(&sc->ready_list); 377 TAILQ_INIT(&sc->nexus_list); 378 TAILQ_INIT(&sc->free_list); 379 sc->sc_nexus = NULL; 380 acb = sc->sc_acb; 381 bzero(acb, sizeof(sc->sc_acb)); 382 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) { 383 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain); 384 acb++; 385 } 386 bzero(&sc->sc_tinfo, sizeof(sc->sc_tinfo)); 387 } else { 388 /* Cancel any active commands. */ 389 sc->sc_state = AIC_CLEANING; 390 if ((acb = sc->sc_nexus) != NULL) { 391 acb->xs->error = XS_DRIVER_STUFFUP; 392 timeout_del(&acb->xs->stimeout); 393 aic_done(sc, acb); 394 } 395 while ((acb = sc->nexus_list.tqh_first) != NULL) { 396 acb->xs->error = XS_DRIVER_STUFFUP; 397 timeout_del(&acb->xs->stimeout); 398 aic_done(sc, acb); 399 } 400 } 401 402 sc->sc_prevphase = PH_INVALID; 403 for (r = 0; r < 8; r++) { 404 struct aic_tinfo *ti = &sc->sc_tinfo[r]; 405 406 ti->flags = 0; 407 #if AIC_USE_SYNCHRONOUS 408 ti->flags |= DO_SYNC; 409 ti->period = sc->sc_minsync; 410 ti->offset = AIC_SYNC_REQ_ACK_OFS; 411 #else 412 ti->period = ti->offset = 0; 413 #endif 414 #if AIC_USE_WIDE 415 ti->flags |= DO_WIDE; 416 ti->width = AIC_MAX_WIDTH; 417 #else 418 ti->width = 0; 419 #endif 420 } 421 422 sc->sc_state = AIC_IDLE; 423 bus_space_write_1(iot, ioh, DMACNTRL0, INTEN); 424 } 425 426 void 427 aic_free_acb(sc, acb, flags) 428 struct aic_softc *sc; 429 struct aic_acb *acb; 430 int flags; 431 { 432 int s; 433 434 s = splbio(); 435 436 acb->flags = 0; 437 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 438 439 /* 440 * If there were none, wake anybody waiting for one to come free, 441 * starting with queued entries. 442 */ 443 if (acb->chain.tqe_next == 0) 444 wakeup(&sc->free_list); 445 446 splx(s); 447 } 448 449 struct aic_acb * 450 aic_get_acb(sc, flags) 451 struct aic_softc *sc; 452 int flags; 453 { 454 struct aic_acb *acb; 455 int s; 456 457 s = splbio(); 458 459 while ((acb = sc->free_list.tqh_first) == NULL && 460 (flags & SCSI_NOSLEEP) == 0) 461 tsleep(&sc->free_list, PRIBIO, "aicacb", 0); 462 if (acb) { 463 TAILQ_REMOVE(&sc->free_list, acb, chain); 464 acb->flags |= ACB_ALLOC; 465 } 466 467 splx(s); 468 return acb; 469 } 470 471 /* 472 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 473 */ 474 475 /* 476 * Expected sequence: 477 * 1) Command inserted into ready list 478 * 2) Command selected for execution 479 * 3) Command won arbitration and has selected target device 480 * 4) Send message out (identify message, eventually also sync.negotiations) 481 * 5) Send command 482 * 5a) Receive disconnect message, disconnect. 483 * 5b) Reselected by target 484 * 5c) Receive identify message from target. 485 * 6) Send or receive data 486 * 7) Receive status 487 * 8) Receive message (command complete etc.) 488 * 9) If status == SCSI_CHECK construct a synthetic request sense SCSI cmd. 489 * Repeat 2-8 (no disconnects please...) 490 */ 491 492 /* 493 * Start a SCSI-command 494 * This function is called by the higher level SCSI-driver to queue/run 495 * SCSI-commands. 496 */ 497 int 498 aic_scsi_cmd(xs) 499 struct scsi_xfer *xs; 500 { 501 struct scsi_link *sc_link = xs->sc_link; 502 struct aic_softc *sc = sc_link->adapter_softc; 503 struct aic_acb *acb; 504 int s, flags; 505 506 AIC_TRACE(("aic_scsi_cmd ")); 507 AIC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 508 sc_link->target)); 509 510 flags = xs->flags; 511 if ((acb = aic_get_acb(sc, flags)) == NULL) { 512 xs->error = XS_DRIVER_STUFFUP; 513 return TRY_AGAIN_LATER; 514 } 515 516 /* Initialize acb */ 517 acb->xs = xs; 518 acb->timeout = xs->timeout; 519 timeout_set(&xs->stimeout, aic_timeout, acb); 520 521 if (xs->flags & SCSI_RESET) { 522 acb->flags |= ACB_RESET; 523 acb->scsi_cmd_length = 0; 524 acb->data_length = 0; 525 } else { 526 bcopy(xs->cmd, &acb->scsi_cmd, xs->cmdlen); 527 acb->scsi_cmd_length = xs->cmdlen; 528 acb->data_addr = xs->data; 529 acb->data_length = xs->datalen; 530 } 531 acb->target_stat = 0; 532 533 s = splbio(); 534 535 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 536 if (sc->sc_state == AIC_IDLE) 537 aic_sched(sc); 538 539 splx(s); 540 541 if ((flags & SCSI_POLL) == 0) 542 return SUCCESSFULLY_QUEUED; 543 544 /* Not allowed to use interrupts, use polling instead */ 545 if (aic_poll(sc, xs, acb->timeout)) { 546 aic_timeout(acb); 547 if (aic_poll(sc, xs, acb->timeout)) 548 aic_timeout(acb); 549 } 550 return COMPLETE; 551 } 552 553 /* 554 * Adjust transfer size in buffer structure 555 */ 556 void 557 aic_minphys(bp) 558 struct buf *bp; 559 { 560 561 AIC_TRACE(("aic_minphys ")); 562 if (bp->b_bcount > (AIC_NSEG << PGSHIFT)) 563 bp->b_bcount = (AIC_NSEG << PGSHIFT); 564 minphys(bp); 565 } 566 567 /* 568 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 569 */ 570 int 571 aic_poll(sc, xs, count) 572 struct aic_softc *sc; 573 struct scsi_xfer *xs; 574 int count; 575 { 576 bus_space_tag_t iot = sc->sc_iot; 577 bus_space_handle_t ioh = sc->sc_ioh; 578 579 AIC_TRACE(("aic_poll ")); 580 while (count) { 581 /* 582 * If we had interrupts enabled, would we 583 * have got an interrupt? 584 */ 585 if ((bus_space_read_1(iot, ioh, DMASTAT) & INTSTAT) != 0) 586 aicintr(sc); 587 if ((xs->flags & ITSDONE) != 0) 588 return 0; 589 delay(1000); 590 count--; 591 } 592 return 1; 593 } 594 595 /* 596 * LOW LEVEL SCSI UTILITIES 597 */ 598 599 integrate void 600 aic_sched_msgout(sc, m) 601 struct aic_softc *sc; 602 u_char m; 603 { 604 bus_space_tag_t iot = sc->sc_iot; 605 bus_space_handle_t ioh = sc->sc_ioh; 606 607 if (sc->sc_msgpriq == 0) 608 bus_space_write_1(iot, ioh, SCSISIG, sc->sc_phase | ATNO); 609 sc->sc_msgpriq |= m; 610 } 611 612 /* 613 * Set synchronous transfer offset and period. 614 */ 615 integrate void 616 aic_setsync(sc, ti) 617 struct aic_softc *sc; 618 struct aic_tinfo *ti; 619 { 620 #if AIC_USE_SYNCHRONOUS 621 bus_space_tag_t iot = sc->sc_iot; 622 bus_space_handle_t ioh = sc->sc_ioh; 623 624 if (ti->offset != 0) 625 bus_space_write_1(iot, ioh, SCSIRATE, 626 ((ti->period * sc->sc_freq) / 250 - 2) << 4 | ti->offset); 627 else 628 bus_space_write_1(iot, ioh, SCSIRATE, 0); 629 #endif 630 } 631 632 /* 633 * Start a selection. This is used by aic_sched() to select an idle target, 634 * and by aic_done() to immediately reselect a target to get sense information. 635 */ 636 void 637 aic_select(sc, acb) 638 struct aic_softc *sc; 639 struct aic_acb *acb; 640 { 641 bus_space_tag_t iot = sc->sc_iot; 642 bus_space_handle_t ioh = sc->sc_ioh; 643 struct scsi_link *sc_link = acb->xs->sc_link; 644 int target = sc_link->target; 645 struct aic_tinfo *ti = &sc->sc_tinfo[target]; 646 647 bus_space_write_1(iot, ioh, SCSIID, 648 sc->sc_initiator << OID_S | target); 649 aic_setsync(sc, ti); 650 bus_space_write_1(iot, ioh, SXFRCTL1, STIMO_256ms | ENSTIMER); 651 652 /* Always enable reselections. */ 653 bus_space_write_1(iot, ioh, SIMODE0, ENSELDI | ENSELDO); 654 bus_space_write_1(iot, ioh, SIMODE1, ENSCSIRST | ENSELTIMO); 655 bus_space_write_1(iot, ioh, SCSISEQ, ENRESELI | ENSELO | ENAUTOATNO); 656 657 sc->sc_state = AIC_SELECTING; 658 } 659 660 int 661 aic_reselect(sc, message) 662 struct aic_softc *sc; 663 int message; 664 { 665 u_char selid, target, lun; 666 struct aic_acb *acb; 667 struct scsi_link *sc_link; 668 struct aic_tinfo *ti; 669 670 /* 671 * The SCSI chip made a snapshot of the data bus while the reselection 672 * was being negotiated. This enables us to determine which target did 673 * the reselect. 674 */ 675 selid = sc->sc_selid & ~(1 << sc->sc_initiator); 676 if (selid & (selid - 1)) { 677 printf("%s: reselect with invalid selid %02x; ", 678 sc->sc_dev.dv_xname, selid); 679 printf("sending DEVICE RESET\n"); 680 AIC_BREAK(); 681 goto reset; 682 } 683 684 /* Search wait queue for disconnected cmd 685 * The list should be short, so I haven't bothered with 686 * any more sophisticated structures than a simple 687 * singly linked list. 688 */ 689 target = ffs(selid) - 1; 690 lun = message & 0x07; 691 for (acb = sc->nexus_list.tqh_first; acb != NULL; 692 acb = acb->chain.tqe_next) { 693 sc_link = acb->xs->sc_link; 694 if (sc_link->target == target && sc_link->lun == lun) 695 break; 696 } 697 if (acb == NULL) { 698 printf("%s: reselect from target %d lun %d with no nexus; ", 699 sc->sc_dev.dv_xname, target, lun); 700 printf("sending ABORT\n"); 701 AIC_BREAK(); 702 goto abort; 703 } 704 705 /* Make this nexus active again. */ 706 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 707 sc->sc_state = AIC_CONNECTED; 708 sc->sc_nexus = acb; 709 ti = &sc->sc_tinfo[target]; 710 ti->lubusy |= (1 << lun); 711 aic_setsync(sc, ti); 712 713 if (acb->flags & ACB_RESET) 714 aic_sched_msgout(sc, SEND_DEV_RESET); 715 else if (acb->flags & ACB_ABORT) 716 aic_sched_msgout(sc, SEND_ABORT); 717 718 /* Do an implicit RESTORE POINTERS. */ 719 sc->sc_dp = acb->data_addr; 720 sc->sc_dleft = acb->data_length; 721 sc->sc_cp = (u_char *)&acb->scsi_cmd; 722 sc->sc_cleft = acb->scsi_cmd_length; 723 724 return (0); 725 726 reset: 727 aic_sched_msgout(sc, SEND_DEV_RESET); 728 return (1); 729 730 abort: 731 aic_sched_msgout(sc, SEND_ABORT); 732 return (1); 733 } 734 735 /* 736 * Schedule a SCSI operation. This has now been pulled out of the interrupt 737 * handler so that we may call it from aic_scsi_cmd and aic_done. This may 738 * save us an unecessary interrupt just to get things going. Should only be 739 * called when state == AIC_IDLE and at bio pl. 740 */ 741 void 742 aic_sched(sc) 743 register struct aic_softc *sc; 744 { 745 bus_space_tag_t iot = sc->sc_iot; 746 bus_space_handle_t ioh = sc->sc_ioh; 747 struct aic_acb *acb; 748 struct scsi_link *sc_link; 749 struct aic_tinfo *ti; 750 751 /* 752 * Find first acb in ready queue that is for a target/lunit pair that 753 * is not busy. 754 */ 755 bus_space_write_1(iot, ioh, CLRSINT1, 756 CLRSELTIMO | CLRBUSFREE | CLRSCSIPERR); 757 for (acb = sc->ready_list.tqh_first; acb != NULL; 758 acb = acb->chain.tqe_next) { 759 sc_link = acb->xs->sc_link; 760 ti = &sc->sc_tinfo[sc_link->target]; 761 if ((ti->lubusy & (1 << sc_link->lun)) == 0) { 762 AIC_MISC(("selecting %d:%d ", 763 sc_link->target, sc_link->lun)); 764 TAILQ_REMOVE(&sc->ready_list, acb, chain); 765 sc->sc_nexus = acb; 766 aic_select(sc, acb); 767 return; 768 } else 769 AIC_MISC(("%d:%d busy\n", 770 sc_link->target, sc_link->lun)); 771 } 772 AIC_MISC(("idle ")); 773 /* Nothing to start; just enable reselections and wait. */ 774 bus_space_write_1(iot, ioh, SIMODE0, ENSELDI); 775 bus_space_write_1(iot, ioh, SIMODE1, ENSCSIRST); 776 bus_space_write_1(iot, ioh, SCSISEQ, ENRESELI); 777 } 778 779 void 780 aic_sense(sc, acb) 781 struct aic_softc *sc; 782 struct aic_acb *acb; 783 { 784 struct scsi_xfer *xs = acb->xs; 785 struct scsi_link *sc_link = xs->sc_link; 786 struct aic_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 787 struct scsi_sense *ss = (void *)&acb->scsi_cmd; 788 789 AIC_MISC(("requesting sense ")); 790 /* Next, setup a request sense command block */ 791 bzero(ss, sizeof(*ss)); 792 ss->opcode = REQUEST_SENSE; 793 ss->byte2 = sc_link->lun << 5; 794 ss->length = sizeof(struct scsi_sense_data); 795 acb->scsi_cmd_length = sizeof(*ss); 796 acb->data_addr = (char *)&xs->sense; 797 acb->data_length = sizeof(struct scsi_sense_data); 798 acb->flags |= ACB_SENSE; 799 ti->senses++; 800 if (acb->flags & ACB_NEXUS) 801 ti->lubusy &= ~(1 << sc_link->lun); 802 if (acb == sc->sc_nexus) { 803 aic_select(sc, acb); 804 } else { 805 aic_dequeue(sc, acb); 806 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 807 if (sc->sc_state == AIC_IDLE) 808 aic_sched(sc); 809 } 810 } 811 812 /* 813 * POST PROCESSING OF SCSI_CMD (usually current) 814 */ 815 void 816 aic_done(sc, acb) 817 struct aic_softc *sc; 818 struct aic_acb *acb; 819 { 820 struct scsi_xfer *xs = acb->xs; 821 struct scsi_link *sc_link = xs->sc_link; 822 struct aic_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 823 824 AIC_TRACE(("aic_done ")); 825 826 /* 827 * Now, if we've come here with no error code, i.e. we've kept the 828 * initial XS_NOERROR, and the status code signals that we should 829 * check sense, we'll need to set up a request sense cmd block and 830 * push the command back into the ready queue *before* any other 831 * commands for this target/lunit, else we lose the sense info. 832 * We don't support chk sense conditions for the request sense cmd. 833 */ 834 if (xs->error == XS_NOERROR) { 835 if (acb->flags & ACB_ABORT) { 836 xs->error = XS_DRIVER_STUFFUP; 837 } else if (acb->flags & ACB_SENSE) { 838 xs->error = XS_SENSE; 839 } else if (acb->target_stat == SCSI_CHECK) { 840 /* First, save the return values */ 841 xs->resid = acb->data_length; 842 xs->status = acb->target_stat; 843 aic_sense(sc, acb); 844 return; 845 } else { 846 xs->resid = acb->data_length; 847 } 848 } 849 850 xs->flags |= ITSDONE; 851 852 #if AIC_DEBUG 853 if ((aic_debug & AIC_SHOWMISC) != 0) { 854 if (xs->resid != 0) 855 printf("resid=%d ", xs->resid); 856 if (xs->error == XS_SENSE) 857 printf("sense=0x%02x\n", xs->sense.error_code); 858 else 859 printf("error=%d\n", xs->error); 860 } 861 #endif 862 863 /* 864 * Remove the ACB from whatever queue it happens to be on. 865 */ 866 if (acb->flags & ACB_NEXUS) 867 ti->lubusy &= ~(1 << sc_link->lun); 868 if (acb == sc->sc_nexus) { 869 sc->sc_nexus = NULL; 870 sc->sc_state = AIC_IDLE; 871 aic_sched(sc); 872 } else 873 aic_dequeue(sc, acb); 874 875 aic_free_acb(sc, acb, xs->flags); 876 ti->cmds++; 877 scsi_done(xs); 878 } 879 880 void 881 aic_dequeue(sc, acb) 882 struct aic_softc *sc; 883 struct aic_acb *acb; 884 { 885 886 if (acb->flags & ACB_NEXUS) { 887 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 888 } else { 889 TAILQ_REMOVE(&sc->ready_list, acb, chain); 890 } 891 } 892 893 /* 894 * INTERRUPT/PROTOCOL ENGINE 895 */ 896 897 #define IS1BYTEMSG(m) (((m) != 0x01 && (m) < 0x20) || (m) >= 0x80) 898 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 899 #define ISEXTMSG(m) ((m) == 0x01) 900 901 /* 902 * Precondition: 903 * The SCSI bus is already in the MSGI phase and there is a message byte 904 * on the bus, along with an asserted REQ signal. 905 */ 906 void 907 aic_msgin(sc) 908 register struct aic_softc *sc; 909 { 910 bus_space_tag_t iot = sc->sc_iot; 911 bus_space_handle_t ioh = sc->sc_ioh; 912 u_char sstat1; 913 int n; 914 915 AIC_TRACE(("aic_msgin ")); 916 917 if (sc->sc_prevphase == PH_MSGIN) { 918 /* This is a continuation of the previous message. */ 919 n = sc->sc_imp - sc->sc_imess; 920 goto nextbyte; 921 } 922 923 /* This is a new MESSAGE IN phase. Clean up our state. */ 924 sc->sc_flags &= ~AIC_DROP_MSGIN; 925 926 nextmsg: 927 n = 0; 928 sc->sc_imp = &sc->sc_imess[n]; 929 930 nextbyte: 931 /* 932 * Read a whole message, but don't ack the last byte. If we reject the 933 * message, we have to assert ATN during the message transfer phase 934 * itself. 935 */ 936 for (;;) { 937 for (;;) { 938 sstat1 = bus_space_read_1(iot, ioh, SSTAT1); 939 if ((sstat1 & (REQINIT | PHASECHG | BUSFREE)) != 0) 940 break; 941 /* Wait for REQINIT. XXX Need timeout. */ 942 } 943 if ((sstat1 & (PHASECHG | BUSFREE)) != 0) { 944 /* 945 * Target left MESSAGE IN, probably because it 946 * a) noticed our ATN signal, or 947 * b) ran out of messages. 948 */ 949 goto out; 950 } 951 952 /* If parity error, just dump everything on the floor. */ 953 if ((sstat1 & SCSIPERR) != 0) { 954 sc->sc_flags |= AIC_DROP_MSGIN; 955 aic_sched_msgout(sc, SEND_PARITY_ERROR); 956 } 957 958 /* Gather incoming message bytes if needed. */ 959 if ((sc->sc_flags & AIC_DROP_MSGIN) == 0) { 960 if (n >= AIC_MAX_MSG_LEN) { 961 (void) bus_space_read_1(iot, ioh, SCSIDAT); 962 sc->sc_flags |= AIC_DROP_MSGIN; 963 aic_sched_msgout(sc, SEND_REJECT); 964 } else { 965 *sc->sc_imp++ = bus_space_read_1(iot, ioh, 966 SCSIDAT); 967 n++; 968 /* 969 * This testing is suboptimal, but most 970 * messages will be of the one byte variety, so 971 * it should not affect performance 972 * significantly. 973 */ 974 if (n == 1 && IS1BYTEMSG(sc->sc_imess[0])) 975 break; 976 if (n == 2 && IS2BYTEMSG(sc->sc_imess[0])) 977 break; 978 if (n >= 3 && ISEXTMSG(sc->sc_imess[0]) && 979 n == sc->sc_imess[1] + 2) 980 break; 981 } 982 } else 983 (void) bus_space_read_1(iot, ioh, SCSIDAT); 984 985 /* 986 * If we reach this spot we're either: 987 * a) in the middle of a multi-byte message, or 988 * b) dropping bytes. 989 */ 990 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 991 /* Ack the last byte read. */ 992 (void) bus_space_read_1(iot, ioh, SCSIDAT); 993 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 994 while ((bus_space_read_1(iot, ioh, SCSISIG) & ACKI) != 0) 995 ; 996 } 997 998 AIC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 999 1000 /* We now have a complete message. Parse it. */ 1001 switch (sc->sc_state) { 1002 struct aic_acb *acb; 1003 struct scsi_link *sc_link; 1004 struct aic_tinfo *ti; 1005 1006 case AIC_CONNECTED: 1007 AIC_ASSERT(sc->sc_nexus != NULL); 1008 acb = sc->sc_nexus; 1009 ti = &sc->sc_tinfo[acb->xs->sc_link->target]; 1010 1011 switch (sc->sc_imess[0]) { 1012 case MSG_CMDCOMPLETE: 1013 if (sc->sc_dleft < 0) { 1014 sc_link = acb->xs->sc_link; 1015 printf("%s: %d extra bytes from %d:%d\n", 1016 sc->sc_dev.dv_xname, -sc->sc_dleft, 1017 sc_link->target, sc_link->lun); 1018 acb->data_length = 0; 1019 } 1020 acb->xs->resid = acb->data_length = sc->sc_dleft; 1021 sc->sc_state = AIC_CMDCOMPLETE; 1022 break; 1023 1024 case MSG_PARITY_ERROR: 1025 /* Resend the last message. */ 1026 aic_sched_msgout(sc, sc->sc_lastmsg); 1027 break; 1028 1029 case MSG_MESSAGE_REJECT: 1030 AIC_MISC(("message rejected %02x ", sc->sc_lastmsg)); 1031 switch (sc->sc_lastmsg) { 1032 #if AIC_USE_SYNCHRONOUS + AIC_USE_WIDE 1033 case SEND_IDENTIFY: 1034 ti->flags &= ~(DO_SYNC | DO_WIDE); 1035 ti->period = ti->offset = 0; 1036 aic_setsync(sc, ti); 1037 ti->width = 0; 1038 break; 1039 #endif 1040 #if AIC_USE_SYNCHRONOUS 1041 case SEND_SDTR: 1042 ti->flags &= ~DO_SYNC; 1043 ti->period = ti->offset = 0; 1044 aic_setsync(sc, ti); 1045 break; 1046 #endif 1047 #if AIC_USE_WIDE 1048 case SEND_WDTR: 1049 ti->flags &= ~DO_WIDE; 1050 ti->width = 0; 1051 break; 1052 #endif 1053 case SEND_INIT_DET_ERR: 1054 aic_sched_msgout(sc, SEND_ABORT); 1055 break; 1056 } 1057 break; 1058 1059 case MSG_NOOP: 1060 break; 1061 1062 case MSG_DISCONNECT: 1063 ti->dconns++; 1064 sc->sc_state = AIC_DISCONNECT; 1065 break; 1066 1067 case MSG_SAVEDATAPOINTER: 1068 acb->data_addr = sc->sc_dp; 1069 acb->data_length = sc->sc_dleft; 1070 break; 1071 1072 case MSG_RESTOREPOINTERS: 1073 sc->sc_dp = acb->data_addr; 1074 sc->sc_dleft = acb->data_length; 1075 sc->sc_cp = (u_char *)&acb->scsi_cmd; 1076 sc->sc_cleft = acb->scsi_cmd_length; 1077 break; 1078 1079 case MSG_EXTENDED: 1080 switch (sc->sc_imess[2]) { 1081 #if AIC_USE_SYNCHRONOUS 1082 case MSG_EXT_SDTR: 1083 if (sc->sc_imess[1] != 3) 1084 goto reject; 1085 ti->period = sc->sc_imess[3]; 1086 ti->offset = sc->sc_imess[4]; 1087 ti->flags &= ~DO_SYNC; 1088 if (ti->offset == 0) { 1089 } else if (ti->period < sc->sc_minsync || 1090 ti->period > sc->sc_maxsync || 1091 ti->offset > 8) { 1092 ti->period = ti->offset = 0; 1093 aic_sched_msgout(sc, SEND_SDTR); 1094 } else { 1095 sc_print_addr(acb->xs->sc_link); 1096 printf("sync, offset %d, ", 1097 ti->offset); 1098 printf("period %dnsec\n", 1099 ti->period * 4); 1100 } 1101 aic_setsync(sc, ti); 1102 break; 1103 #endif 1104 1105 #if AIC_USE_WIDE 1106 case MSG_EXT_WDTR: 1107 if (sc->sc_imess[1] != 2) 1108 goto reject; 1109 ti->width = sc->sc_imess[3]; 1110 ti->flags &= ~DO_WIDE; 1111 if (ti->width == 0) { 1112 } else if (ti->width > AIC_MAX_WIDTH) { 1113 ti->width = 0; 1114 aic_sched_msgout(sc, SEND_WDTR); 1115 } else { 1116 sc_print_addr(acb->xs->sc_link); 1117 printf("wide, width %d\n", 1118 1 << (3 + ti->width)); 1119 } 1120 break; 1121 #endif 1122 1123 default: 1124 printf("%s: unrecognized MESSAGE EXTENDED; ", 1125 sc->sc_dev.dv_xname); 1126 printf("sending REJECT\n"); 1127 AIC_BREAK(); 1128 goto reject; 1129 } 1130 break; 1131 1132 default: 1133 printf("%s: unrecognized MESSAGE; sending REJECT\n", 1134 sc->sc_dev.dv_xname); 1135 AIC_BREAK(); 1136 reject: 1137 aic_sched_msgout(sc, SEND_REJECT); 1138 break; 1139 } 1140 break; 1141 1142 case AIC_RESELECTED: 1143 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1144 printf("%s: reselect without IDENTIFY; ", 1145 sc->sc_dev.dv_xname); 1146 printf("sending DEVICE RESET\n"); 1147 AIC_BREAK(); 1148 goto reset; 1149 } 1150 1151 (void) aic_reselect(sc, sc->sc_imess[0]); 1152 break; 1153 1154 default: 1155 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1156 sc->sc_dev.dv_xname); 1157 AIC_BREAK(); 1158 reset: 1159 aic_sched_msgout(sc, SEND_DEV_RESET); 1160 break; 1161 1162 #ifdef notdef 1163 abort: 1164 aic_sched_msgout(sc, SEND_ABORT); 1165 break; 1166 #endif 1167 } 1168 1169 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 1170 /* Ack the last message byte. */ 1171 (void) bus_space_read_1(iot, ioh, SCSIDAT); 1172 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1173 while ((bus_space_read_1(iot, ioh, SCSISIG) & ACKI) != 0) 1174 ; 1175 1176 /* Go get the next message, if any. */ 1177 goto nextmsg; 1178 1179 out: 1180 AIC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 1181 } 1182 1183 /* 1184 * Send the highest priority, scheduled message. 1185 */ 1186 void 1187 aic_msgout(sc) 1188 register struct aic_softc *sc; 1189 { 1190 bus_space_tag_t iot = sc->sc_iot; 1191 bus_space_handle_t ioh = sc->sc_ioh; 1192 #if AIC_USE_SYNCHRONOUS 1193 struct aic_tinfo *ti; 1194 #endif 1195 u_char sstat1; 1196 int n; 1197 1198 AIC_TRACE(("aic_msgout ")); 1199 1200 /* Reset the FIFO. */ 1201 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO); 1202 /* Enable REQ/ACK protocol. */ 1203 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 1204 1205 if (sc->sc_prevphase == PH_MSGOUT) { 1206 if (sc->sc_omp == sc->sc_omess) { 1207 /* 1208 * This is a retransmission. 1209 * 1210 * We get here if the target stayed in MESSAGE OUT 1211 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates 1212 * that all of the previously transmitted messages must 1213 * be sent again, in the same order. Therefore, we 1214 * requeue all the previously transmitted messages, and 1215 * start again from the top. Our simple priority 1216 * scheme keeps the messages in the right order. 1217 */ 1218 AIC_MISC(("retransmitting ")); 1219 sc->sc_msgpriq |= sc->sc_msgoutq; 1220 /* 1221 * Set ATN. If we're just sending a trivial 1-byte 1222 * message, we'll clear ATN later on anyway. 1223 */ 1224 bus_space_write_1(iot, ioh, SCSISIG, PH_MSGOUT | ATNO); 1225 } else { 1226 /* This is a continuation of the previous message. */ 1227 n = sc->sc_omp - sc->sc_omess; 1228 goto nextbyte; 1229 } 1230 } 1231 1232 /* No messages transmitted so far. */ 1233 sc->sc_msgoutq = 0; 1234 sc->sc_lastmsg = 0; 1235 1236 nextmsg: 1237 /* Pick up highest priority message. */ 1238 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq; 1239 sc->sc_msgpriq &= ~sc->sc_currmsg; 1240 sc->sc_msgoutq |= sc->sc_currmsg; 1241 1242 /* Build the outgoing message data. */ 1243 switch (sc->sc_currmsg) { 1244 case SEND_IDENTIFY: 1245 AIC_ASSERT(sc->sc_nexus != NULL); 1246 sc->sc_omess[0] = 1247 MSG_IDENTIFY(sc->sc_nexus->xs->sc_link->lun, 1); 1248 n = 1; 1249 break; 1250 1251 #if AIC_USE_SYNCHRONOUS 1252 case SEND_SDTR: 1253 AIC_ASSERT(sc->sc_nexus != NULL); 1254 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->target]; 1255 sc->sc_omess[4] = MSG_EXTENDED; 1256 sc->sc_omess[3] = 3; 1257 sc->sc_omess[2] = MSG_EXT_SDTR; 1258 sc->sc_omess[1] = ti->period >> 2; 1259 sc->sc_omess[0] = ti->offset; 1260 n = 5; 1261 break; 1262 #endif 1263 1264 #if AIC_USE_WIDE 1265 case SEND_WDTR: 1266 AIC_ASSERT(sc->sc_nexus != NULL); 1267 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->target]; 1268 sc->sc_omess[3] = MSG_EXTENDED; 1269 sc->sc_omess[2] = 2; 1270 sc->sc_omess[1] = MSG_EXT_WDTR; 1271 sc->sc_omess[0] = ti->width; 1272 n = 4; 1273 break; 1274 #endif 1275 1276 case SEND_DEV_RESET: 1277 sc->sc_flags |= AIC_ABORTING; 1278 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1279 n = 1; 1280 break; 1281 1282 case SEND_REJECT: 1283 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1284 n = 1; 1285 break; 1286 1287 case SEND_PARITY_ERROR: 1288 sc->sc_omess[0] = MSG_PARITY_ERROR; 1289 n = 1; 1290 break; 1291 1292 case SEND_INIT_DET_ERR: 1293 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1294 n = 1; 1295 break; 1296 1297 case SEND_ABORT: 1298 sc->sc_flags |= AIC_ABORTING; 1299 sc->sc_omess[0] = MSG_ABORT; 1300 n = 1; 1301 break; 1302 1303 default: 1304 printf("%s: unexpected MESSAGE OUT; sending NOOP\n", 1305 sc->sc_dev.dv_xname); 1306 AIC_BREAK(); 1307 sc->sc_omess[0] = MSG_NOOP; 1308 n = 1; 1309 break; 1310 } 1311 sc->sc_omp = &sc->sc_omess[n]; 1312 1313 nextbyte: 1314 /* Send message bytes. */ 1315 for (;;) { 1316 for (;;) { 1317 sstat1 = bus_space_read_1(iot, ioh, SSTAT1); 1318 if ((sstat1 & (REQINIT | PHASECHG | BUSFREE)) != 0) 1319 break; 1320 /* Wait for REQINIT. XXX Need timeout. */ 1321 } 1322 if ((sstat1 & (PHASECHG | BUSFREE)) != 0) { 1323 /* 1324 * Target left MESSAGE OUT, possibly to reject 1325 * our message. 1326 * 1327 * If this is the last message being sent, then we 1328 * deassert ATN, since either the target is going to 1329 * ignore this message, or it's going to ask for a 1330 * retransmission via MESSAGE PARITY ERROR (in which 1331 * case we reassert ATN anyway). 1332 */ 1333 if (sc->sc_msgpriq == 0) 1334 bus_space_write_1(iot, ioh, CLRSINT1, CLRATNO); 1335 goto out; 1336 } 1337 1338 /* Clear ATN before last byte if this is the last message. */ 1339 if (n == 1 && sc->sc_msgpriq == 0) 1340 bus_space_write_1(iot, ioh, CLRSINT1, CLRATNO); 1341 /* Send message byte. */ 1342 bus_space_write_1(iot, ioh, SCSIDAT, *--sc->sc_omp); 1343 --n; 1344 /* Keep track of the last message we've sent any bytes of. */ 1345 sc->sc_lastmsg = sc->sc_currmsg; 1346 /* Wait for ACK to be negated. XXX Need timeout. */ 1347 while ((bus_space_read_1(iot, ioh, SCSISIG) & ACKI) != 0) 1348 ; 1349 1350 if (n == 0) 1351 break; 1352 } 1353 1354 /* We get here only if the entire message has been transmitted. */ 1355 if (sc->sc_msgpriq != 0) { 1356 /* There are more outgoing messages. */ 1357 goto nextmsg; 1358 } 1359 1360 /* 1361 * The last message has been transmitted. We need to remember the last 1362 * message transmitted (in case the target switches to MESSAGE IN phase 1363 * and sends a MESSAGE REJECT), and the list of messages transmitted 1364 * this time around (in case the target stays in MESSAGE OUT phase to 1365 * request a retransmit). 1366 */ 1367 1368 out: 1369 /* Disable REQ/ACK protocol. */ 1370 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1371 } 1372 1373 /* aic_dataout_pio: perform a data transfer using the FIFO datapath in the aic6360 1374 * Precondition: The SCSI bus should be in the DOUT phase, with REQ asserted 1375 * and ACK deasserted (i.e. waiting for a data byte) 1376 * This new revision has been optimized (I tried) to make the common case fast, 1377 * and the rarer cases (as a result) somewhat more comlex 1378 */ 1379 int 1380 aic_dataout_pio(sc, p, n) 1381 register struct aic_softc *sc; 1382 u_char *p; 1383 int n; 1384 { 1385 bus_space_tag_t iot = sc->sc_iot; 1386 bus_space_handle_t ioh = sc->sc_ioh; 1387 register u_char dmastat = 0; 1388 int out = 0; 1389 #define DOUTAMOUNT 128 /* Full FIFO */ 1390 1391 AIC_MISC(("%02x%02x ", bus_space_read_1(iot, ioh, FIFOSTAT), 1392 bus_space_read_1(iot, ioh, SSTAT2))); 1393 1394 /* Clear host FIFO and counter. */ 1395 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO | WRITE); 1396 /* Enable FIFOs. */ 1397 bus_space_write_1(iot, ioh, DMACNTRL0, ENDMA | DWORDPIO | WRITE); 1398 bus_space_write_1(iot, ioh, SXFRCTL0, SCSIEN | DMAEN | CHEN); 1399 1400 /* Turn off ENREQINIT for now. */ 1401 bus_space_write_1(iot, ioh, SIMODE1, 1402 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENPHASECHG); 1403 1404 /* I have tried to make the main loop as tight as possible. This 1405 * means that some of the code following the loop is a bit more 1406 * complex than otherwise. 1407 */ 1408 while (n > 0) { 1409 for (;;) { 1410 dmastat = bus_space_read_1(iot, ioh, DMASTAT); 1411 if ((dmastat & (DFIFOEMP | INTSTAT)) != 0) 1412 break; 1413 } 1414 1415 if ((dmastat & INTSTAT) != 0) 1416 goto phasechange; 1417 1418 if (n >= DOUTAMOUNT) { 1419 n -= DOUTAMOUNT; 1420 out += DOUTAMOUNT; 1421 1422 #if AIC_USE_DWORDS 1423 bus_space_write_multi_4(iot, ioh, DMADATALONG, 1424 (u_int32_t *)p, DOUTAMOUNT >> 2); 1425 #else 1426 bus_space_write_multi_2(iot, ioh, DMADATA, 1427 (u_int16_t *)p, DOUTAMOUNT >> 1); 1428 #endif 1429 1430 p += DOUTAMOUNT; 1431 } else { 1432 register int xfer; 1433 1434 xfer = n; 1435 AIC_MISC(("%d> ", xfer)); 1436 1437 n -= xfer; 1438 out += xfer; 1439 1440 #if AIC_USE_DWORDS 1441 if (xfer >= 12) { 1442 bus_space_write_multi_4(iot, ioh, DMADATALONG, 1443 (u_int32_t *)p, xfer >> 2); 1444 p += xfer & ~3; 1445 xfer &= 3; 1446 } 1447 #else 1448 if (xfer >= 8) { 1449 bus_space_write_multi_2(iot, ioh, DMADATA, 1450 (u_int16_t *)p, xfer >> 1); 1451 p += xfer & ~1; 1452 xfer &= 1; 1453 } 1454 #endif 1455 1456 if (xfer > 0) { 1457 bus_space_write_1(iot, ioh, DMACNTRL0, 1458 ENDMA | B8MODE | WRITE); 1459 bus_space_write_multi_1(iot, ioh, DMADATA, p, 1460 xfer); 1461 p += xfer; 1462 bus_space_write_1(iot, ioh, DMACNTRL0, 1463 ENDMA | DWORDPIO | WRITE); 1464 } 1465 } 1466 } 1467 1468 if (out == 0) { 1469 bus_space_write_1(iot, ioh, SXFRCTL1, BITBUCKET); 1470 for (;;) { 1471 if ((bus_space_read_1(iot, ioh, DMASTAT) & INTSTAT) != 1472 0) 1473 break; 1474 } 1475 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1476 AIC_MISC(("extra data ")); 1477 } else { 1478 /* See the bytes off chip */ 1479 for (;;) { 1480 dmastat = bus_space_read_1(iot, ioh, DMASTAT); 1481 if ((dmastat & INTSTAT) != 0) 1482 goto phasechange; 1483 if ((dmastat & DFIFOEMP) != 0 && 1484 (bus_space_read_1(iot, ioh, SSTAT2) & SEMPTY) != 0) 1485 break; 1486 } 1487 } 1488 1489 phasechange: 1490 if ((dmastat & INTSTAT) != 0) { 1491 /* Some sort of phase change. */ 1492 int amount; 1493 1494 /* Stop transfers, do some accounting */ 1495 amount = bus_space_read_1(iot, ioh, FIFOSTAT) + 1496 (bus_space_read_1(iot, ioh, SSTAT2) & 15); 1497 if (amount > 0) { 1498 out -= amount; 1499 bus_space_write_1(iot, ioh, DMACNTRL0, 1500 RSTFIFO | WRITE); 1501 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | CLRCH); 1502 AIC_MISC(("+%d ", amount)); 1503 } 1504 } 1505 1506 /* Turn on ENREQINIT again. */ 1507 bus_space_write_1(iot, ioh, SIMODE1, 1508 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENREQINIT | ENPHASECHG); 1509 1510 /* Stop the FIFO data path. */ 1511 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1512 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 1513 1514 return out; 1515 } 1516 1517 /* aic_datain_pio: perform data transfers using the FIFO datapath in the aic6360 1518 * Precondition: The SCSI bus should be in the DIN phase, with REQ asserted 1519 * and ACK deasserted (i.e. at least one byte is ready). 1520 * For now, uses a pretty dumb algorithm, hangs around until all data has been 1521 * transferred. This, is OK for fast targets, but not so smart for slow 1522 * targets which don't disconnect or for huge transfers. 1523 */ 1524 int 1525 aic_datain_pio(sc, p, n) 1526 register struct aic_softc *sc; 1527 u_char *p; 1528 int n; 1529 { 1530 bus_space_tag_t iot = sc->sc_iot; 1531 bus_space_handle_t ioh = sc->sc_ioh; 1532 register u_char dmastat; 1533 int in = 0; 1534 #define DINAMOUNT 128 /* Full FIFO */ 1535 1536 AIC_MISC(("%02x%02x ", bus_space_read_1(iot, ioh, FIFOSTAT), 1537 bus_space_read_1(iot, ioh, SSTAT2))); 1538 1539 /* Clear host FIFO and counter. */ 1540 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO); 1541 /* Enable FIFOs. */ 1542 bus_space_write_1(iot, ioh, DMACNTRL0, ENDMA | DWORDPIO); 1543 bus_space_write_1(iot, ioh, SXFRCTL0, SCSIEN | DMAEN | CHEN); 1544 1545 /* Turn off ENREQINIT for now. */ 1546 bus_space_write_1(iot, ioh, SIMODE1, 1547 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENPHASECHG); 1548 1549 /* We leave this loop if one or more of the following is true: 1550 * a) phase != PH_DATAIN && FIFOs are empty 1551 * b) SCSIRSTI is set (a reset has occurred) or busfree is detected. 1552 */ 1553 while (n > 0) { 1554 /* Wait for fifo half full or phase mismatch */ 1555 for (;;) { 1556 dmastat = bus_space_read_1(iot, ioh, DMASTAT); 1557 if ((dmastat & (DFIFOFULL | INTSTAT)) != 0) 1558 break; 1559 } 1560 1561 if ((dmastat & DFIFOFULL) != 0) { 1562 n -= DINAMOUNT; 1563 in += DINAMOUNT; 1564 1565 #if AIC_USE_DWORDS 1566 bus_space_read_multi_4(iot, ioh, DMADATALONG, 1567 (u_int32_t *)p, DINAMOUNT >> 2); 1568 #else 1569 bus_space_read_multi_2(iot, ioh, DMADATA, 1570 (u_int16_t *)p, DINAMOUNT >> 1); 1571 #endif 1572 1573 p += DINAMOUNT; 1574 } else { 1575 register int xfer; 1576 1577 xfer = min(bus_space_read_1(iot, ioh, FIFOSTAT), n); 1578 AIC_MISC((">%d ", xfer)); 1579 1580 n -= xfer; 1581 in += xfer; 1582 1583 #if AIC_USE_DWORDS 1584 if (xfer >= 12) { 1585 bus_space_read_multi_4(iot, ioh, DMADATALONG, 1586 (u_int32_t *)p, xfer >> 2); 1587 p += xfer & ~3; 1588 xfer &= 3; 1589 } 1590 #else 1591 if (xfer >= 8) { 1592 bus_space_read_multi_2(iot, ioh, DMADATA, 1593 (u_int16_t *)p, xfer >> 1); 1594 p += xfer & ~1; 1595 xfer &= 1; 1596 } 1597 #endif 1598 1599 if (xfer > 0) { 1600 bus_space_write_1(iot, ioh, DMACNTRL0, 1601 ENDMA | B8MODE); 1602 bus_space_read_multi_1(iot, ioh, DMADATA, p, 1603 xfer); 1604 p += xfer; 1605 bus_space_write_1(iot, ioh, DMACNTRL0, 1606 ENDMA | DWORDPIO); 1607 } 1608 } 1609 1610 if ((dmastat & INTSTAT) != 0) 1611 goto phasechange; 1612 } 1613 1614 /* Some SCSI-devices are rude enough to transfer more data than what 1615 * was requested, e.g. 2048 bytes from a CD-ROM instead of the 1616 * requested 512. Test for progress, i.e. real transfers. If no real 1617 * transfers have been performed (n is probably already zero) and the 1618 * FIFO is not empty, waste some bytes.... 1619 */ 1620 if (in == 0) { 1621 bus_space_write_1(iot, ioh, SXFRCTL1, BITBUCKET); 1622 for (;;) { 1623 if ((bus_space_read_1(iot, ioh, DMASTAT) & INTSTAT) != 1624 0) 1625 break; 1626 } 1627 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1628 AIC_MISC(("extra data ")); 1629 } 1630 1631 phasechange: 1632 /* Turn on ENREQINIT again. */ 1633 bus_space_write_1(iot, ioh, SIMODE1, 1634 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENREQINIT | ENPHASECHG); 1635 1636 /* Stop the FIFO data path. */ 1637 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1638 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 1639 1640 return in; 1641 } 1642 1643 /* 1644 * This is the workhorse routine of the driver. 1645 * Deficiencies (for now): 1646 * 1) always uses programmed I/O 1647 */ 1648 int 1649 aicintr(arg) 1650 void *arg; 1651 { 1652 register struct aic_softc *sc = arg; 1653 bus_space_tag_t iot = sc->sc_iot; 1654 bus_space_handle_t ioh = sc->sc_ioh; 1655 u_char sstat0, sstat1; 1656 register struct aic_acb *acb; 1657 register struct scsi_link *sc_link; 1658 struct aic_tinfo *ti; 1659 int n; 1660 1661 /* 1662 * Clear INTEN. We enable it again before returning. This makes the 1663 * interrupt esssentially level-triggered. 1664 */ 1665 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 1666 1667 AIC_TRACE(("aicintr ")); 1668 1669 loop: 1670 /* 1671 * First check for abnormal conditions, such as reset. 1672 */ 1673 sstat1 = bus_space_read_1(iot, ioh, SSTAT1); 1674 AIC_MISC(("sstat1:0x%02x ", sstat1)); 1675 1676 if ((sstat1 & SCSIRSTI) != 0) { 1677 printf("%s: SCSI bus reset\n", sc->sc_dev.dv_xname); 1678 goto reset; 1679 } 1680 1681 /* 1682 * Check for less serious errors. 1683 */ 1684 if ((sstat1 & SCSIPERR) != 0) { 1685 printf("%s: SCSI bus parity error\n", sc->sc_dev.dv_xname); 1686 bus_space_write_1(iot, ioh, CLRSINT1, CLRSCSIPERR); 1687 if (sc->sc_prevphase == PH_MSGIN) { 1688 sc->sc_flags |= AIC_DROP_MSGIN; 1689 aic_sched_msgout(sc, SEND_PARITY_ERROR); 1690 } else 1691 aic_sched_msgout(sc, SEND_INIT_DET_ERR); 1692 } 1693 1694 /* 1695 * If we're not already busy doing something test for the following 1696 * conditions: 1697 * 1) We have been reselected by something 1698 * 2) We have selected something successfully 1699 * 3) Our selection process has timed out 1700 * 4) This is really a bus free interrupt just to get a new command 1701 * going? 1702 * 5) Spurious interrupt? 1703 */ 1704 switch (sc->sc_state) { 1705 case AIC_IDLE: 1706 case AIC_SELECTING: 1707 sstat0 = bus_space_read_1(iot, ioh, SSTAT0); 1708 AIC_MISC(("sstat0:0x%02x ", sstat0)); 1709 1710 if ((sstat0 & TARGET) != 0) { 1711 /* 1712 * We don't currently support target mode. 1713 */ 1714 printf("%s: target mode selected; going to BUS FREE\n", 1715 sc->sc_dev.dv_xname); 1716 bus_space_write_1(iot, ioh, SCSISIG, 0); 1717 1718 goto sched; 1719 } else if ((sstat0 & SELDI) != 0) { 1720 AIC_MISC(("reselected ")); 1721 1722 /* 1723 * If we're trying to select a target ourselves, 1724 * push our command back into the ready list. 1725 */ 1726 if (sc->sc_state == AIC_SELECTING) { 1727 AIC_MISC(("backoff selector ")); 1728 AIC_ASSERT(sc->sc_nexus != NULL); 1729 acb = sc->sc_nexus; 1730 sc->sc_nexus = NULL; 1731 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 1732 } 1733 1734 /* Save reselection ID. */ 1735 sc->sc_selid = bus_space_read_1(iot, ioh, SELID); 1736 1737 sc->sc_state = AIC_RESELECTED; 1738 } else if ((sstat0 & SELDO) != 0) { 1739 AIC_MISC(("selected ")); 1740 1741 /* We have selected a target. Things to do: 1742 * a) Determine what message(s) to send. 1743 * b) Verify that we're still selecting the target. 1744 * c) Mark device as busy. 1745 */ 1746 if (sc->sc_state != AIC_SELECTING) { 1747 printf("%s: selection out while idle; ", 1748 sc->sc_dev.dv_xname); 1749 printf("resetting\n"); 1750 AIC_BREAK(); 1751 goto reset; 1752 } 1753 AIC_ASSERT(sc->sc_nexus != NULL); 1754 acb = sc->sc_nexus; 1755 sc_link = acb->xs->sc_link; 1756 ti = &sc->sc_tinfo[sc_link->target]; 1757 1758 sc->sc_msgpriq = SEND_IDENTIFY; 1759 if (acb->flags & ACB_RESET) 1760 sc->sc_msgpriq |= SEND_DEV_RESET; 1761 else if (acb->flags & ACB_ABORT) 1762 sc->sc_msgpriq |= SEND_ABORT; 1763 else { 1764 #if AIC_USE_SYNCHRONOUS 1765 if ((ti->flags & DO_SYNC) != 0) 1766 sc->sc_msgpriq |= SEND_SDTR; 1767 #endif 1768 #if AIC_USE_WIDE 1769 if ((ti->flags & DO_WIDE) != 0) 1770 sc->sc_msgpriq |= SEND_WDTR; 1771 #endif 1772 } 1773 1774 acb->flags |= ACB_NEXUS; 1775 ti->lubusy |= (1 << sc_link->lun); 1776 1777 /* Do an implicit RESTORE POINTERS. */ 1778 sc->sc_dp = acb->data_addr; 1779 sc->sc_dleft = acb->data_length; 1780 sc->sc_cp = (u_char *)&acb->scsi_cmd; 1781 sc->sc_cleft = acb->scsi_cmd_length; 1782 1783 /* On our first connection, schedule a timeout. */ 1784 if ((acb->xs->flags & SCSI_POLL) == 0) 1785 timeout_add(&acb->xs->stimeout, 1786 (acb->timeout * hz) / 1000); 1787 1788 sc->sc_state = AIC_CONNECTED; 1789 } else if ((sstat1 & SELTO) != 0) { 1790 AIC_MISC(("selection timeout ")); 1791 1792 if (sc->sc_state != AIC_SELECTING) { 1793 printf("%s: selection timeout while idle; ", 1794 sc->sc_dev.dv_xname); 1795 printf("resetting\n"); 1796 AIC_BREAK(); 1797 goto reset; 1798 } 1799 AIC_ASSERT(sc->sc_nexus != NULL); 1800 acb = sc->sc_nexus; 1801 1802 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1803 bus_space_write_1(iot, ioh, SCSISEQ, ENRESELI); 1804 bus_space_write_1(iot, ioh, CLRSINT1, CLRSELTIMO); 1805 delay(250); 1806 1807 acb->xs->error = XS_SELTIMEOUT; 1808 goto finish; 1809 } else { 1810 if (sc->sc_state != AIC_IDLE) { 1811 printf("%s: BUS FREE while not idle; ", 1812 sc->sc_dev.dv_xname); 1813 printf("state=%d\n", sc->sc_state); 1814 AIC_BREAK(); 1815 goto out; 1816 } 1817 1818 goto sched; 1819 } 1820 1821 /* 1822 * Turn off selection stuff, and prepare to catch bus free 1823 * interrupts, parity errors, and phase changes. 1824 */ 1825 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | CLRSTCNT | CLRCH); 1826 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1827 bus_space_write_1(iot, ioh, SCSISEQ, ENAUTOATNP); 1828 bus_space_write_1(iot, ioh, CLRSINT0, CLRSELDI | CLRSELDO); 1829 bus_space_write_1(iot, ioh, CLRSINT1, 1830 CLRBUSFREE | CLRPHASECHG); 1831 bus_space_write_1(iot, ioh, SIMODE0, 0); 1832 bus_space_write_1(iot, ioh, SIMODE1, 1833 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENREQINIT | 1834 ENPHASECHG); 1835 1836 sc->sc_flags = 0; 1837 sc->sc_prevphase = PH_INVALID; 1838 goto dophase; 1839 } 1840 1841 if ((sstat1 & BUSFREE) != 0) { 1842 /* We've gone to BUS FREE phase. */ 1843 bus_space_write_1(iot, ioh, CLRSINT1, 1844 CLRBUSFREE | CLRPHASECHG); 1845 1846 switch (sc->sc_state) { 1847 case AIC_RESELECTED: 1848 goto sched; 1849 1850 case AIC_CONNECTED: 1851 AIC_ASSERT(sc->sc_nexus != NULL); 1852 acb = sc->sc_nexus; 1853 1854 #if AIC_USE_SYNCHRONOUS + AIC_USE_WIDE 1855 if (sc->sc_prevphase == PH_MSGOUT) { 1856 /* 1857 * If the target went to BUS FREE phase during 1858 * or immediately after sending a SDTR or WDTR 1859 * message, disable negotiation. 1860 */ 1861 sc_link = acb->xs->sc_link; 1862 ti = &sc->sc_tinfo[sc_link->target]; 1863 switch (sc->sc_lastmsg) { 1864 #if AIC_USE_SYNCHRONOUS 1865 case SEND_SDTR: 1866 ti->flags &= ~DO_SYNC; 1867 ti->period = ti->offset = 0; 1868 break; 1869 #endif 1870 #if AIC_USE_WIDE 1871 case SEND_WDTR: 1872 ti->flags &= ~DO_WIDE; 1873 ti->width = 0; 1874 break; 1875 #endif 1876 } 1877 } 1878 #endif 1879 1880 if ((sc->sc_flags & AIC_ABORTING) == 0) { 1881 /* 1882 * Section 5.1.1 of the SCSI 2 spec suggests 1883 * issuing a REQUEST SENSE following an 1884 * unexpected disconnect. Some devices go into 1885 * a contingent allegiance condition when 1886 * disconnecting, and this is necessary to 1887 * clean up their state. 1888 */ 1889 printf("%s: unexpected disconnect; ", 1890 sc->sc_dev.dv_xname); 1891 printf("sending REQUEST SENSE\n"); 1892 AIC_BREAK(); 1893 aic_sense(sc, acb); 1894 goto out; 1895 } 1896 1897 acb->xs->error = XS_DRIVER_STUFFUP; 1898 goto finish; 1899 1900 case AIC_DISCONNECT: 1901 AIC_ASSERT(sc->sc_nexus != NULL); 1902 acb = sc->sc_nexus; 1903 #if 1 /* XXXX */ 1904 acb->data_addr = sc->sc_dp; 1905 acb->data_length = sc->sc_dleft; 1906 #endif 1907 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); 1908 sc->sc_nexus = NULL; 1909 goto sched; 1910 1911 case AIC_CMDCOMPLETE: 1912 AIC_ASSERT(sc->sc_nexus != NULL); 1913 acb = sc->sc_nexus; 1914 goto finish; 1915 } 1916 } 1917 1918 bus_space_write_1(iot, ioh, CLRSINT1, CLRPHASECHG); 1919 1920 dophase: 1921 if ((sstat1 & REQINIT) == 0) { 1922 /* Wait for REQINIT. */ 1923 goto out; 1924 } 1925 1926 sc->sc_phase = bus_space_read_1(iot, ioh, SCSISIG) & PH_MASK; 1927 bus_space_write_1(iot, ioh, SCSISIG, sc->sc_phase); 1928 1929 switch (sc->sc_phase) { 1930 case PH_MSGOUT: 1931 if (sc->sc_state != AIC_CONNECTED && 1932 sc->sc_state != AIC_RESELECTED) 1933 break; 1934 aic_msgout(sc); 1935 sc->sc_prevphase = PH_MSGOUT; 1936 goto loop; 1937 1938 case PH_MSGIN: 1939 if (sc->sc_state != AIC_CONNECTED && 1940 sc->sc_state != AIC_RESELECTED) 1941 break; 1942 aic_msgin(sc); 1943 sc->sc_prevphase = PH_MSGIN; 1944 goto loop; 1945 1946 case PH_CMD: 1947 if (sc->sc_state != AIC_CONNECTED) 1948 break; 1949 #if AIC_DEBUG 1950 if ((aic_debug & AIC_SHOWMISC) != 0) { 1951 AIC_ASSERT(sc->sc_nexus != NULL); 1952 acb = sc->sc_nexus; 1953 printf("cmd=0x%02x+%d ", 1954 acb->scsi_cmd.opcode, acb->scsi_cmd_length-1); 1955 } 1956 #endif 1957 n = aic_dataout_pio(sc, sc->sc_cp, sc->sc_cleft); 1958 sc->sc_cp += n; 1959 sc->sc_cleft -= n; 1960 sc->sc_prevphase = PH_CMD; 1961 goto loop; 1962 1963 case PH_DATAOUT: 1964 if (sc->sc_state != AIC_CONNECTED) 1965 break; 1966 AIC_MISC(("dataout dleft=%d ", sc->sc_dleft)); 1967 n = aic_dataout_pio(sc, sc->sc_dp, sc->sc_dleft); 1968 sc->sc_dp += n; 1969 sc->sc_dleft -= n; 1970 sc->sc_prevphase = PH_DATAOUT; 1971 goto loop; 1972 1973 case PH_DATAIN: 1974 if (sc->sc_state != AIC_CONNECTED) 1975 break; 1976 AIC_MISC(("datain %d ", sc->sc_dleft)); 1977 n = aic_datain_pio(sc, sc->sc_dp, sc->sc_dleft); 1978 sc->sc_dp += n; 1979 sc->sc_dleft -= n; 1980 sc->sc_prevphase = PH_DATAIN; 1981 goto loop; 1982 1983 case PH_STAT: 1984 if (sc->sc_state != AIC_CONNECTED) 1985 break; 1986 AIC_ASSERT(sc->sc_nexus != NULL); 1987 acb = sc->sc_nexus; 1988 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 1989 acb->target_stat = bus_space_read_1(iot, ioh, SCSIDAT); 1990 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1991 AIC_MISC(("target_stat=0x%02x ", acb->target_stat)); 1992 sc->sc_prevphase = PH_STAT; 1993 goto loop; 1994 } 1995 1996 printf("%s: unexpected bus phase; resetting\n", sc->sc_dev.dv_xname); 1997 AIC_BREAK(); 1998 reset: 1999 aic_init(sc); 2000 return 1; 2001 2002 finish: 2003 timeout_del(&acb->xs->stimeout); 2004 aic_done(sc, acb); 2005 goto out; 2006 2007 sched: 2008 sc->sc_state = AIC_IDLE; 2009 aic_sched(sc); 2010 goto out; 2011 2012 out: 2013 bus_space_write_1(iot, ioh, DMACNTRL0, INTEN); 2014 return 1; 2015 } 2016 2017 void 2018 aic_abort(sc, acb) 2019 struct aic_softc *sc; 2020 struct aic_acb *acb; 2021 { 2022 2023 /* 2 secs for the abort */ 2024 acb->timeout = AIC_ABORT_TIMEOUT; 2025 acb->flags |= ACB_ABORT; 2026 2027 if (acb == sc->sc_nexus) { 2028 /* 2029 * If we're still selecting, the message will be scheduled 2030 * after selection is complete. 2031 */ 2032 if (sc->sc_state == AIC_CONNECTED) 2033 aic_sched_msgout(sc, SEND_ABORT); 2034 } else { 2035 aic_dequeue(sc, acb); 2036 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 2037 if (sc->sc_state == AIC_IDLE) 2038 aic_sched(sc); 2039 } 2040 } 2041 2042 void 2043 aic_timeout(arg) 2044 void *arg; 2045 { 2046 struct aic_acb *acb = arg; 2047 struct scsi_xfer *xs = acb->xs; 2048 struct scsi_link *sc_link = xs->sc_link; 2049 struct aic_softc *sc = sc_link->adapter_softc; 2050 int s; 2051 2052 sc_print_addr(sc_link); 2053 printf("timed out"); 2054 2055 s = splbio(); 2056 2057 if (acb->flags & ACB_ABORT) { 2058 /* abort timed out */ 2059 printf(" AGAIN\n"); 2060 /* XXX Must reset! */ 2061 } else { 2062 /* abort the operation that has timed out */ 2063 printf("\n"); 2064 acb->xs->error = XS_TIMEOUT; 2065 aic_abort(sc, acb); 2066 } 2067 2068 splx(s); 2069 } 2070 2071 #if AIC_DEBUG 2072 /* 2073 * The following functions are mostly used for debugging purposes, either 2074 * directly called from the driver or from the kernel debugger. 2075 */ 2076 2077 void 2078 aic_show_scsi_cmd(acb) 2079 struct aic_acb *acb; 2080 { 2081 u_char *b = (u_char *)&acb->scsi_cmd; 2082 struct scsi_link *sc_link = acb->xs->sc_link; 2083 int i; 2084 2085 sc_print_addr(sc_link); 2086 if ((acb->xs->flags & SCSI_RESET) == 0) { 2087 for (i = 0; i < acb->scsi_cmd_length; i++) { 2088 if (i) 2089 printf(","); 2090 printf("%x", b[i]); 2091 } 2092 printf("\n"); 2093 } else 2094 printf("RESET\n"); 2095 } 2096 2097 void 2098 aic_print_acb(acb) 2099 struct aic_acb *acb; 2100 { 2101 2102 printf("acb@%p xs=%p flags=%x", acb, acb->xs, acb->flags); 2103 printf(" dp=%p dleft=%d target_stat=%x\n", 2104 acb->data_addr, acb->data_length, acb->target_stat); 2105 aic_show_scsi_cmd(acb); 2106 } 2107 2108 void 2109 aic_print_active_acb() 2110 { 2111 struct aic_acb *acb; 2112 struct aic_softc *sc = aic_cd.cd_devs[0]; 2113 2114 printf("ready list:\n"); 2115 for (acb = sc->ready_list.tqh_first; acb != NULL; 2116 acb = acb->chain.tqe_next) 2117 aic_print_acb(acb); 2118 printf("nexus:\n"); 2119 if (sc->sc_nexus != NULL) 2120 aic_print_acb(sc->sc_nexus); 2121 printf("nexus list:\n"); 2122 for (acb = sc->nexus_list.tqh_first; acb != NULL; 2123 acb = acb->chain.tqe_next) 2124 aic_print_acb(acb); 2125 } 2126 2127 void 2128 aic_dump6360(sc) 2129 struct aic_softc *sc; 2130 { 2131 bus_space_tag_t iot = sc->sc_iot; 2132 bus_space_handle_t ioh = sc->sc_ioh; 2133 2134 printf("aic6360: SCSISEQ=%x SXFRCTL0=%x SXFRCTL1=%x SCSISIG=%x\n", 2135 bus_space_read_1(iot, ioh, SCSISEQ), 2136 bus_space_read_1(iot, ioh, SXFRCTL0), 2137 bus_space_read_1(iot, ioh, SXFRCTL1), 2138 bus_space_read_1(iot, ioh, SCSISIG)); 2139 printf(" SSTAT0=%x SSTAT1=%x SSTAT2=%x SSTAT3=%x SSTAT4=%x\n", 2140 bus_space_read_1(iot, ioh, SSTAT0), 2141 bus_space_read_1(iot, ioh, SSTAT1), 2142 bus_space_read_1(iot, ioh, SSTAT2), 2143 bus_space_read_1(iot, ioh, SSTAT3), 2144 bus_space_read_1(iot, ioh, SSTAT4)); 2145 printf(" SIMODE0=%x SIMODE1=%x ", 2146 bus_space_read_1(iot, ioh, SIMODE0), 2147 bus_space_read_1(iot, ioh, SIMODE1)); 2148 printf("DMACNTRL0=%x DMACNTRL1=%x DMASTAT=%x\n", 2149 bus_space_read_1(iot, ioh, DMACNTRL0), 2150 bus_space_read_1(iot, ioh, DMACNTRL1), 2151 bus_space_read_1(iot, ioh, DMASTAT)); 2152 printf(" FIFOSTAT=%d SCSIBUS=0x%x\n", 2153 bus_space_read_1(iot, ioh, FIFOSTAT), 2154 bus_space_read_1(iot, ioh, SCSIBUS)); 2155 } 2156 2157 void 2158 aic_dump_driver(sc) 2159 struct aic_softc *sc; 2160 { 2161 struct aic_tinfo *ti; 2162 int i; 2163 2164 printf("nexus=%p prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase); 2165 printf("state=%x msgin=%x ", sc->sc_state, sc->sc_imess[0]); 2166 printf("msgpriq=%x msgoutq=%x lastmsg=%x currmsg=%x\n", sc->sc_msgpriq, 2167 sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg); 2168 for (i = 0; i < 7; i++) { 2169 ti = &sc->sc_tinfo[i]; 2170 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2171 i, ti->cmds, ti->dconns, ti->touts); 2172 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2173 } 2174 } 2175 #endif 2176