1 /* $OpenBSD: athvar.h,v 1.35 2020/10/11 07:05:28 mpi Exp $ */ 2 /* $NetBSD: athvar.h,v 1.10 2004/08/10 01:03:53 dyoung Exp $ */ 3 4 /*- 5 * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 16 * redistribution must be conditioned upon including a substantially 17 * similar Disclaimer requirement for further binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * NO WARRANTY 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 26 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 27 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 28 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 31 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGES. 34 * 35 * $FreeBSD: src/sys/dev/ath/if_athvar.h,v 1.14 2004/04/03 03:33:02 sam Exp $ 36 */ 37 38 /* 39 * Definitions for the Atheros Wireless LAN controller driver. 40 */ 41 #ifndef _DEV_ATH_ATHVAR_H 42 #define _DEV_ATH_ATHVAR_H 43 44 #ifdef _KERNEL 45 46 #include <net80211/ieee80211_radiotap.h> 47 #include <dev/ic/ar5xxx.h> 48 49 #include "bpfilter.h" 50 51 #ifdef notyet 52 #include "gpio.h" 53 #endif 54 55 #define ATH_TIMEOUT 1000 56 57 #define ATH_RXBUF 40 /* number of RX buffers */ 58 #define ATH_TXBUF 60 /* number of TX buffers */ 59 #define ATH_TXDESC 8 /* number of descriptors per buffer */ 60 #define ATH_MAXGPIO 10 /* maximal number of gpio pins */ 61 62 struct ath_recv_hist { 63 int arh_ticks; /* sample time by system clock */ 64 u_int8_t arh_rssi; /* rssi */ 65 u_int8_t arh_antenna; /* antenna */ 66 }; 67 #define ATH_RHIST_SIZE 16 /* number of samples */ 68 #define ATH_RHIST_NOTIME (~0) 69 70 /* 71 * Ioctl-related definitions for the Atheros Wireless LAN controller driver. 72 */ 73 struct ath_stats { 74 u_int32_t ast_watchdog; /* device reset by watchdog */ 75 u_int32_t ast_hardware; /* fatal hardware error interrupts */ 76 u_int32_t ast_bmiss; /* beacon miss interrupts */ 77 u_int32_t ast_mib; /* MIB counter interrupts */ 78 u_int32_t ast_rxorn; /* rx overrun interrupts */ 79 u_int32_t ast_rxeol; /* rx eol interrupts */ 80 u_int32_t ast_txurn; /* tx underrun interrupts */ 81 u_int32_t ast_intrcoal; /* interrupts coalesced */ 82 u_int32_t ast_tx_mgmt; /* management frames transmitted */ 83 u_int32_t ast_tx_discard; /* frames discarded prior to assoc */ 84 u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */ 85 u_int32_t ast_tx_encap; /* tx encapsulation failed */ 86 u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */ 87 u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */ 88 u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */ 89 u_int32_t ast_tx_linear; /* tx linearized to cluster */ 90 u_int32_t ast_tx_nodata; /* tx discarded empty frame */ 91 u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */ 92 u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */ 93 u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ 94 u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */ 95 u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */ 96 u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */ 97 u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */ 98 u_int32_t ast_tx_noack; /* tx frames with no ack marked */ 99 u_int32_t ast_tx_rts; /* tx frames with rts enabled */ 100 u_int32_t ast_tx_cts; /* tx frames with cts enabled */ 101 u_int32_t ast_tx_shortpre;/* tx frames with short preamble */ 102 u_int32_t ast_tx_altrate; /* tx frames with alternate rate */ 103 u_int32_t ast_tx_protect; /* tx frames with protection */ 104 u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */ 105 u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */ 106 u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */ 107 u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ 108 u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ 109 u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */ 110 u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */ 111 u_int32_t ast_rx_phy[32]; /* rx PHY error per-code counts */ 112 u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */ 113 u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */ 114 u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */ 115 u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */ 116 u_int32_t ast_per_cal; /* periodic calibration calls */ 117 u_int32_t ast_per_calfail;/* periodic calibration failed */ 118 u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */ 119 u_int32_t ast_rate_calls; /* rate control checks */ 120 u_int32_t ast_rate_raise; /* rate control raised xmit rate */ 121 u_int32_t ast_rate_drop; /* rate control dropped xmit rate */ 122 }; 123 124 /* 125 * Radio capture format. 126 */ 127 #define ATH_RX_RADIOTAP_PRESENT ( \ 128 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 129 (1 << IEEE80211_RADIOTAP_RATE) | \ 130 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 131 (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 132 (1 << IEEE80211_RADIOTAP_RSSI) | \ 133 0) 134 135 struct ath_rx_radiotap_header { 136 struct ieee80211_radiotap_header wr_ihdr; 137 u_int8_t wr_flags; 138 u_int8_t wr_rate; 139 u_int16_t wr_chan_freq; 140 u_int16_t wr_chan_flags; 141 u_int8_t wr_antenna; 142 u_int8_t wr_rssi; 143 u_int8_t wr_max_rssi; 144 } __packed; 145 146 #define ATH_TX_RADIOTAP_PRESENT ( \ 147 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 148 (1 << IEEE80211_RADIOTAP_RATE) | \ 149 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 150 (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \ 151 (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 152 0) 153 154 struct ath_tx_radiotap_header { 155 struct ieee80211_radiotap_header wt_ihdr; 156 u_int8_t wt_flags; 157 u_int8_t wt_rate; 158 u_int16_t wt_chan_freq; 159 u_int16_t wt_chan_flags; 160 u_int8_t wt_txpower; 161 u_int8_t wt_antenna; 162 } __packed; 163 164 /* 165 * driver-specific node 166 */ 167 struct ath_node { 168 struct ieee80211_node an_node; /* base class */ 169 struct ieee80211_rssadapt an_rssadapt; /* rate adaption */ 170 u_int an_tx_antenna; /* antenna for last good frame */ 171 u_int an_rx_antenna; /* antenna for last rcvd frame */ 172 struct ath_recv_hist an_rx_hist[ATH_RHIST_SIZE]; 173 u_int an_rx_hist_next;/* index of next ``free entry'' */ 174 }; 175 #define ATH_NODE(_n) ((struct ath_node *)(_n)) 176 177 struct ath_buf { 178 TAILQ_ENTRY(ath_buf) bf_list; 179 bus_dmamap_t bf_dmamap; /* DMA map of the buffer */ 180 #define bf_nseg bf_dmamap->dm_nsegs 181 #define bf_mapsize bf_dmamap->dm_mapsize 182 #define bf_segs bf_dmamap->dm_segs 183 struct ath_desc *bf_desc; /* virtual addr of desc */ 184 bus_addr_t bf_daddr; /* physical addr of desc */ 185 struct mbuf *bf_m; /* mbuf for buf */ 186 struct ieee80211_node *bf_node; /* pointer to the node */ 187 struct ieee80211_rssdesc bf_id; 188 #define ATH_MAX_SCATTER 64 189 }; 190 191 typedef struct ath_task { 192 void (*t_func)(void*, int); 193 void *t_context; 194 } ath_task_t; 195 196 struct ath_softc { 197 #ifndef __FreeBSD__ 198 struct device sc_dev; 199 #endif 200 struct ieee80211com sc_ic; /* IEEE 802.11 common */ 201 #ifndef __FreeBSD__ 202 int (*sc_enable)(struct ath_softc *); 203 void (*sc_disable)(struct ath_softc *); 204 void (*sc_power)(struct ath_softc *, int); 205 #endif 206 int (*sc_newstate)(struct ieee80211com *, 207 enum ieee80211_state, int); 208 void (*sc_node_free)(struct ieee80211com *, 209 struct ieee80211_node *); 210 void (*sc_node_copy)(struct ieee80211com *, 211 struct ieee80211_node *, 212 const struct ieee80211_node *); 213 void (*sc_recv_mgmt)(struct ieee80211com *, 214 struct mbuf *, struct ieee80211_node *, 215 struct ieee80211_rxinfo *, int); 216 #ifdef __FreeBSD__ 217 device_t sc_dev; 218 #endif 219 bus_space_tag_t sc_st; /* bus space tag */ 220 bus_space_handle_t sc_sh; /* bus space handle */ 221 bus_size_t sc_ss; /* bus space size */ 222 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 223 #ifdef __FreeBSD__ 224 struct mtx sc_mtx; /* master lock (recursive) */ 225 #endif 226 struct ath_hal *sc_ah; /* Atheros HAL */ 227 unsigned int sc_invalid : 1, /* disable hardware accesses */ 228 sc_doani : 1, /* dynamic noise immunity */ 229 sc_veol : 1, /* tx VEOL support */ 230 sc_softled : 1, /* GPIO software LED */ 231 sc_probing : 1, /* probing AP on beacon miss */ 232 sc_pcie : 1; /* indicates PCI Express */ 233 u_int sc_nchan; /* number of valid channels */ 234 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 235 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 236 enum ieee80211_phymode sc_curmode; /* current phy mode */ 237 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 238 u_int8_t sc_hwmap[32]; /* h/w rate ix to IEEE table */ 239 HAL_INT sc_imask; /* interrupt mask copy */ 240 241 #if NBPFILTER > 0 242 caddr_t sc_drvbpf; 243 244 union { 245 struct ath_rx_radiotap_header th; 246 uint8_t pad[IEEE80211_RADIOTAP_HDRLEN]; 247 } sc_rxtapu; 248 #define sc_rxtap sc_rxtapu.th 249 int sc_rxtap_len; 250 251 union { 252 struct ath_tx_radiotap_header th; 253 uint8_t pad[IEEE80211_RADIOTAP_HDRLEN]; 254 } sc_txtapu; 255 #define sc_txtap sc_txtapu.th 256 int sc_txtap_len; 257 #endif 258 259 struct ath_desc *sc_desc; /* TX/RX descriptors */ 260 bus_dma_segment_t sc_dseg; 261 int sc_dnseg; /* number of segments */ 262 bus_dmamap_t sc_ddmamap; /* DMA map for descriptors */ 263 bus_addr_t sc_desc_paddr; /* physical addr of sc_desc */ 264 bus_addr_t sc_desc_len; /* size of sc_desc */ 265 266 ath_task_t sc_fataltask; /* fatal int processing */ 267 ath_task_t sc_rxorntask; /* rxorn int processing */ 268 269 TAILQ_HEAD(, ath_buf) sc_rxbuf; /* receive buffer */ 270 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 271 ath_task_t sc_rxtask; /* rx int processing */ 272 273 u_int sc_txhalq[HAL_NUM_TX_QUEUES]; /* HAL q for outgoing frames */ 274 u_int32_t *sc_txlink; /* link ptr in last TX desc */ 275 int sc_tx_timer; /* transmit timeout */ 276 TAILQ_HEAD(, ath_buf) sc_txbuf; /* transmit buffer */ 277 #ifdef __FreeBSD__ 278 struct mtx sc_txbuflock; /* txbuf lock */ 279 #endif 280 TAILQ_HEAD(, ath_buf) sc_txq; /* transmitting queue */ 281 #ifdef __FreeBSD__ 282 struct mtx sc_txqlock; /* lock on txq and txlink */ 283 #endif 284 ath_task_t sc_txtask; /* tx int processing */ 285 286 u_int sc_bhalq; /* HAL q for outgoing beacons */ 287 struct ath_buf *sc_bcbuf; /* beacon buffer */ 288 struct ath_buf *sc_bufptr; /* allocated buffer ptr */ 289 ath_task_t sc_swbatask; /* swba int processing */ 290 ath_task_t sc_bmisstask; /* bmiss int processing */ 291 292 #ifdef __OpenBSD__ 293 struct timeval sc_last_ch; 294 struct timeout sc_cal_to; 295 struct timeval sc_last_beacon; 296 struct timeout sc_scan_to; 297 struct timeout sc_rssadapt_to; 298 #else 299 struct callout sc_cal_ch; /* callout handle for cals */ 300 struct callout sc_scan_ch; /* callout handle for scan */ 301 #endif 302 struct ath_stats sc_stats; /* interface statistics */ 303 HAL_MIB_STATS sc_mib_stats; /* MIB counter statistics */ 304 305 #ifndef __FreeBSD__ 306 u_int sc_flags; /* misc flags */ 307 #endif 308 309 u_int8_t sc_broadcast_addr[IEEE80211_ADDR_LEN]; 310 311 struct gpio_chipset_tag sc_gpio_gc; /* gpio(4) framework */ 312 gpio_pin_t sc_gpio_pins[ATH_MAXGPIO]; 313 }; 314 315 /* unaligned little endian access */ 316 #define LE_READ_2(p) \ 317 ((u_int16_t) \ 318 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 319 #define LE_READ_4(p) \ 320 ((u_int32_t) \ 321 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 322 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 323 324 #ifdef AR_DEBUG 325 enum { 326 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 327 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 328 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 329 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 330 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 331 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 332 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 333 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 334 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 335 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 336 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 337 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 338 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 339 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 340 ATH_DEBUG_ANY = 0xffffffff 341 }; 342 #define IFF_DUMPPKTS(_ifp, _m) \ 343 ((ath_debug & _m) || \ 344 ((_ifp)->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 345 #define DPRINTF(_m,X) if (ath_debug & (_m)) printf X 346 #else 347 #define IFF_DUMPPKTS(_ifp, _m) \ 348 (((_ifp)->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 349 #define DPRINTF(_m, X) 350 #endif 351 352 /* 353 * Wrapper code 354 */ 355 #ifndef __FreeBSD__ 356 #undef KASSERT 357 #define KASSERT(cond, complaint) if (!(cond)) panic complaint 358 359 #define ATH_ATTACHED 0x0001 /* attach has succeeded */ 360 #define ATH_ENABLED 0x0002 /* chip is enabled */ 361 #define ATH_GPIO 0x0004 /* gpio device attached */ 362 363 #define ATH_IS_ENABLED(sc) ((sc)->sc_flags & ATH_ENABLED) 364 #endif 365 366 #define ATH_LOCK_INIT(_sc) \ 367 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 368 MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE) 369 #define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 370 #define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 371 #define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 372 #define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 373 374 #define ATH_TXBUF_LOCK_INIT(_sc) \ 375 mtx_init(&(_sc)->sc_txbuflock, \ 376 device_get_nameunit((_sc)->sc_dev), "xmit buf q", MTX_DEF) 377 #define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 378 #define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 379 #define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 380 #define ATH_TXBUF_LOCK_ASSERT(_sc) \ 381 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 382 383 #define ATH_TXQ_LOCK_INIT(_sc) \ 384 mtx_init(&(_sc)->sc_txqlock, \ 385 device_get_nameunit((_sc)->sc_dev), "xmit q", MTX_DEF) 386 #define ATH_TXQ_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txqlock) 387 #define ATH_TXQ_LOCK(_sc) mtx_lock(&(_sc)->sc_txqlock) 388 #define ATH_TXQ_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txqlock) 389 #define ATH_TXQ_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_txqlock, MA_OWNED) 390 391 #define ATH_TICKS() (ticks) 392 #define ATH_CALLOUT_INIT(chp) callout_init((chp)) 393 #define ATH_TASK_INIT(task, func, context) \ 394 do { \ 395 (task)->t_func = (func); \ 396 (task)->t_context = (context); \ 397 } while (0) 398 #define ATH_TASK_RUN_OR_ENQUEUE(task) ((*(task)->t_func)((task)->t_context, 1)) 399 400 typedef unsigned long u_intptr_t; 401 402 int ath_attach(u_int16_t, struct ath_softc *); 403 int ath_detach(struct ath_softc *, int); 404 int ath_enable(struct ath_softc *); 405 int ath_activate(struct device *, int); 406 int ath_intr(void *); 407 int ath_enable(struct ath_softc *); 408 409 /* 410 * HAL definitions to comply with local coding convention. 411 */ 412 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 413 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 414 #define ath_hal_get_rate_table(_ah, _mode) \ 415 ((*(_ah)->ah_get_rate_table)((_ah), (_mode))) 416 #define ath_hal_get_lladdr(_ah, _mac) \ 417 ((*(_ah)->ah_get_lladdr)((_ah), (_mac))) 418 #define ath_hal_set_lladdr(_ah, _mac) \ 419 ((*(_ah)->ah_set_lladdr)((_ah), (_mac))) 420 #define ath_hal_set_intr(_ah, _mask) \ 421 ((*(_ah)->ah_set_intr)((_ah), (_mask))) 422 #define ath_hal_get_intr(_ah) \ 423 ((*(_ah)->ah_get_intr)((_ah))) 424 #define ath_hal_is_intr_pending(_ah) \ 425 ((*(_ah)->ah_is_intr_pending)((_ah))) 426 #define ath_hal_get_isr(_ah, _pmask) \ 427 ((*(_ah)->ah_get_isr)((_ah), (_pmask))) 428 #define ath_hal_update_tx_triglevel(_ah, _inc) \ 429 ((*(_ah)->ah_update_tx_triglevel)((_ah), (_inc))) 430 #define ath_hal_set_power(_ah, _mode, _sleepduration) \ 431 ((*(_ah)->ah_set_power)((_ah), (_mode), AH_TRUE, (_sleepduration))) 432 #define ath_hal_reset_key(_ah, _ix) \ 433 ((*(_ah)->ah_reset_key)((_ah), (_ix))) 434 #define ath_hal_set_key(_ah, _ix, _pk) \ 435 ((*(_ah)->ah_set_key)((_ah), (_ix), (_pk), NULL, AH_FALSE)) 436 #define ath_hal_is_key_valid(_ah, _ix) \ 437 (((*(_ah)->ah_is_key_valid)((_ah), (_ix)))) 438 #define ath_hal_set_key_lladdr(_ah, _ix, _mac) \ 439 ((*(_ah)->ah_set_key_lladdr)((_ah), (_ix), (_mac))) 440 #define ath_hal_softcrypto(_ah, _val ) \ 441 ((*(_ah)->ah_softcrypto)((_ah), (_val))) 442 #define ath_hal_get_rx_filter(_ah) \ 443 ((*(_ah)->ah_get_rx_filter)((_ah))) 444 #define ath_hal_set_rx_filter(_ah, _filter) \ 445 ((*(_ah)->ah_set_rx_filter)((_ah), (_filter))) 446 #define ath_hal_set_mcast_filter(_ah, _mfilt0, _mfilt1) \ 447 ((*(_ah)->ah_set_mcast_filter)((_ah), (_mfilt0), (_mfilt1))) 448 #define ath_hal_wait_for_beacon(_ah, _bf) \ 449 ((*(_ah)->ah_wait_for_beacon)((_ah), (_bf)->bf_daddr)) 450 #define ath_hal_put_rx_buf(_ah, _bufaddr) \ 451 ((*(_ah)->ah_put_rx_buf)((_ah), (_bufaddr))) 452 #define ath_hal_get_tsf32(_ah) \ 453 ((*(_ah)->ah_get_tsf32)((_ah))) 454 #define ath_hal_get_tsf64(_ah) \ 455 ((*(_ah)->ah_get_tsf64)((_ah))) 456 #define ath_hal_reset_tsf(_ah) \ 457 ((*(_ah)->ah_reset_tsf)((_ah))) 458 #define ath_hal_start_rx(_ah) \ 459 ((*(_ah)->ah_start_rx)((_ah))) 460 #define ath_hal_put_tx_buf(_ah, _q, _bufaddr) \ 461 ((*(_ah)->ah_put_tx_buf)((_ah), (_q), (_bufaddr))) 462 #define ath_hal_get_tx_buf(_ah, _q) \ 463 ((*(_ah)->ah_get_tx_buf)((_ah), (_q))) 464 #define ath_hal_get_rx_buf(_ah) \ 465 ((*(_ah)->ah_get_rx_buf)((_ah))) 466 #define ath_hal_tx_start(_ah, _q) \ 467 ((*(_ah)->ah_tx_start)((_ah), (_q))) 468 #define ath_hal_setchannel(_ah, _chan) \ 469 ((*(_ah)->ah_setchannel)((_ah), (_chan))) 470 #define ath_hal_calibrate(_ah, _chan) \ 471 ((*(_ah)->ah_calibrate)((_ah), (_chan))) 472 #define ath_hal_set_ledstate(_ah, _state) \ 473 ((*(_ah)->ah_set_ledstate)((_ah), (_state))) 474 #define ath_hal_init_beacon(_ah, _nextb, _bperiod) \ 475 ((*(_ah)->ah_init_beacon)((_ah), (_nextb), (_bperiod))) 476 #define ath_hal_reset_beacon(_ah) \ 477 ((*(_ah)->ah_reset_beacon)((_ah))) 478 #define ath_hal_set_beacon_timers(_ah, _bs, _tsf, _dc, _cc) \ 479 ((*(_ah)->ah_set_beacon_timers)((_ah), (_bs), (_tsf), \ 480 (_dc), (_cc))) 481 #define ath_hal_set_associd(_ah, _bss, _associd) \ 482 ((*(_ah)->ah_set_associd)((_ah), (_bss), (_associd), 0)) 483 #define ath_hal_get_regdomain(_ah, _prd) \ 484 (*(_prd) = (_ah)->ah_get_regdomain(_ah)) 485 #define ath_hal_detach(_ah) \ 486 ((*(_ah)->ah_detach)(_ah)) 487 #define ath_hal_set_slot_time(_ah, _t) \ 488 ((*(_ah)->ah_set_slot_time)(_ah, _t)) 489 #define ath_hal_set_gpio_output(_ah, _gpio) \ 490 ((*(_ah)->ah_set_gpio_output)((_ah), (_gpio))) 491 #define ath_hal_set_gpio_input(_ah, _gpio) \ 492 ((*(_ah)->ah_set_gpio_input)((_ah), (_gpio))) 493 #define ath_hal_get_gpio(_ah, _gpio) \ 494 ((*(_ah)->ah_get_gpio)((_ah), (_gpio))) 495 #define ath_hal_set_gpio(_ah, _gpio, _b) \ 496 ((*(_ah)->ah_set_gpio)((_ah), (_gpio), (_b))) 497 #define ath_hal_set_gpio_intr(_ah, _gpio, _b) \ 498 ((*(_ah)->ah_set_gpio_intr)((_ah), (_gpio), (_b))) 499 500 #define ath_hal_set_opmode(_ah) \ 501 ((*(_ah)->ah_set_opmode)((_ah))) 502 #define ath_hal_stop_tx_dma(_ah, _qnum) \ 503 ((*(_ah)->ah_stop_tx_dma)((_ah), (_qnum))) 504 #define ath_hal_stop_pcu_recv(_ah) \ 505 ((*(_ah)->ah_stop_pcu_recv)((_ah))) 506 #define ath_hal_start_rx_pcu(_ah) \ 507 ((*(_ah)->ah_start_rx_pcu)((_ah))) 508 #define ath_hal_stop_rx_dma(_ah) \ 509 ((*(_ah)->ah_stop_rx_dma)((_ah))) 510 #define ath_hal_get_diag_state(_ah, _id, _indata, _insize, _outdata, _outsize) \ 511 ((*(_ah)->ah_get_diag_state)((_ah), (_id), \ 512 (_indata), (_insize), (_outdata), (_outsize))) 513 514 #define ath_hal_setup_tx_queue(_ah, _type, _qinfo) \ 515 ((*(_ah)->ah_setup_tx_queue)((_ah), (_type), (_qinfo))) 516 #define ath_hal_reset_tx_queue(_ah, _q) \ 517 ((*(_ah)->ah_reset_tx_queue)((_ah), (_q))) 518 #define ath_hal_release_tx_queue(_ah, _q) \ 519 ((*(_ah)->ah_release_tx_queue)((_ah), (_q))) 520 #define ath_hal_has_veol(_ah) \ 521 ((*(_ah)->ah_has_veol)((_ah))) 522 #define ath_hal_update_mib_counters(_ah, _stats) \ 523 ((*(_ah)->ah_update_mib_counters)((_ah), (_stats))) 524 #define ath_hal_get_rf_gain(_ah) \ 525 ((*(_ah)->ah_get_rf_gain)((_ah))) 526 #define ath_hal_set_rx_signal(_ah) \ 527 ((*(_ah)->ah_set_rx_signal)((_ah))) 528 529 #define ath_hal_setup_rx_desc(_ah, _ds, _size, _intreq) \ 530 ((*(_ah)->ah_setup_rx_desc)((_ah), (_ds), (_size), (_intreq))) 531 #define ath_hal_proc_rx_desc(_ah, _ds, _dspa, _dsnext) \ 532 ((*(_ah)->ah_proc_rx_desc)((_ah), (_ds), (_dspa), (_dsnext))) 533 #define ath_hal_setup_tx_desc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 534 _txr0, _txtr0, _keyix, _ant, _flags, \ 535 _rtsrate, _rtsdura) \ 536 ((*(_ah)->ah_setup_tx_desc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 537 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 538 (_flags), (_rtsrate), (_rtsdura))) 539 #define ath_hal_setup_xtx_desc(_ah, _ds, \ 540 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 541 ((*(_ah)->ah_setup_xtx_desc)((_ah), (_ds), \ 542 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 543 #define ath_hal_fill_tx_desc(_ah, _ds, _l, _first, _last) \ 544 ((*(_ah)->ah_fill_tx_desc)((_ah), (_ds), (_l), (_first), (_last))) 545 #define ath_hal_proc_tx_desc(_ah, _ds) \ 546 ((*(_ah)->ah_proc_tx_desc)((_ah), (_ds))) 547 548 #endif /* _KERNEL */ 549 550 #define SIOCGATHSTATS _IOWR('i', 137, struct ifreq) 551 552 #endif /* _DEV_ATH_ATHVAR_H */ 553