1 /* $OpenBSD: atwreg.h,v 1.7 2009/08/16 18:03:48 jsg Exp $ */ 2 /* $NetBSD: atwreg.h,v 1.10 2004/07/23 05:01:29 dyoung Exp $ */ 3 4 /* 5 * Copyright (c) 2003 The NetBSD Foundation, Inc. All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL David Young 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* glossary */ 33 34 /* DTIM Delivery Traffic Indication Map, sent by AP 35 * ATIM Ad Hoc Traffic Indication Map 36 * TU 1024 microseconds 37 * TSF time synchronization function 38 * TBTT target beacon transmission time 39 * DIFS distributed inter-frame space 40 * SIFS short inter-frame space 41 * EIFS extended inter-frame space 42 */ 43 44 /* Macros for bit twiddling. */ 45 46 #ifndef _BIT_TWIDDLE 47 #define _BIT_TWIDDLE 48 49 /* find least significant bit that is set */ 50 #define LOWEST_SET_BIT(x) ((((x) - 1) & (x)) ^ (x)) 51 52 /* for x a power of two and p a non-negative integer, is x a greater power than 2**p? */ 53 #define GTEQ_POWER(x, p) (((u_long)(x) >> (p)) != 0) 54 55 #define MASK_TO_SHIFT2(m) (GTEQ_POWER(LOWEST_SET_BIT((m)), 1) ? 1 : 0) 56 57 #define MASK_TO_SHIFT4(m) \ 58 (GTEQ_POWER(LOWEST_SET_BIT((m)), 2) \ 59 ? 2 + MASK_TO_SHIFT2((m) >> 2) \ 60 : MASK_TO_SHIFT2((m))) 61 62 #define MASK_TO_SHIFT8(m) \ 63 (GTEQ_POWER(LOWEST_SET_BIT((m)), 4) \ 64 ? 4 + MASK_TO_SHIFT4((m) >> 4) \ 65 : MASK_TO_SHIFT4((m))) 66 67 #define MASK_TO_SHIFT16(m) \ 68 (GTEQ_POWER(LOWEST_SET_BIT((m)), 8) \ 69 ? 8 + MASK_TO_SHIFT8((m) >> 8) \ 70 : MASK_TO_SHIFT8((m))) 71 72 #define MASK_TO_SHIFT(m) \ 73 (GTEQ_POWER(LOWEST_SET_BIT((m)), 16) \ 74 ? 16 + MASK_TO_SHIFT16((m) >> 16) \ 75 : MASK_TO_SHIFT16((m))) 76 77 #define MASK_AND_RSHIFT(x, mask) (((x) & (mask)) >> MASK_TO_SHIFT(mask)) 78 #define LSHIFT(x, mask) ((x) << MASK_TO_SHIFT(mask)) 79 #define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask)) 80 #define PRESHIFT(m) MASK_AND_RSHIFT((m), (m)) 81 82 #endif /* _BIT_TWIDDLE */ 83 84 /* ADM8211 Host Control and Status Registers */ 85 86 #define ATW_PAR 0x00 /* PCI access */ 87 #define ATW_FRCTL 0x04 /* Frame control */ 88 #define ATW_TDR 0x08 /* Transmit demand */ 89 #define ATW_WTDP 0x0C /* Current transmit descriptor pointer */ 90 #define ATW_RDR 0x10 /* Receive demand */ 91 #define ATW_WRDP 0x14 /* Current receive descriptor pointer */ 92 #define ATW_RDB 0x18 /* Receive descriptor base address */ 93 #define ATW_CSR3A 0x1C /* Unused (on ADM8211A) */ 94 #define ATW_C_TDBH 0x1C /* Transmit descriptor base address, 95 * high-priority packet 96 */ 97 #define ATW_TDBD 0x20 /* Transmit descriptor base address, DCF */ 98 #define ATW_TDBP 0x24 /* Transmit descriptor base address, PCF */ 99 #define ATW_STSR 0x28 /* Status */ 100 #define ATW_CSR5A 0x2C /* Unused */ 101 #define ATW_C_TDBB 0x2C /* Transmit descriptor base address, buffered 102 * broadcast/multicast packet 103 */ 104 #define ATW_NAR 0x30 /* Network access */ 105 #define ATW_CSR6A 0x34 /* Unused */ 106 #define ATW_IER 0x38 /* Interrupt enable */ 107 #define ATW_CSR7A 0x3C 108 #define ATW_LPC 0x40 /* Lost packet counter */ 109 #define ATW_TEST1 0x44 /* Test register 1 */ 110 #define ATW_SPR 0x48 /* Serial port */ 111 #define ATW_TEST0 0x4C /* Test register 0 */ 112 #define ATW_WCSR 0x50 /* Wake-up control/status */ 113 #define ATW_WPDR 0x54 /* Wake-up pattern data */ 114 #define ATW_GPTMR 0x58 /* General purpose timer */ 115 #define ATW_GPIO 0x5C /* GPIO[5:0] configuration and control */ 116 #define ATW_BBPCTL 0x60 /* BBP control port */ 117 #define ATW_SYNCTL 0x64 /* synthesizer control port */ 118 #define ATW_PLCPHD 0x68 /* PLCP header setting */ 119 #define ATW_MMIWADDR 0x6C /* MMI write address */ 120 #define ATW_MMIRADDR1 0x70 /* MMI read address 1 */ 121 #define ATW_MMIRADDR2 0x74 /* MMI read address 2 */ 122 #define ATW_TXBR 0x78 /* Transmit burst counter */ 123 #define ATW_CSR15A 0x7C /* Unused */ 124 #define ATW_ALCSTAT 0x80 /* ALC statistics */ 125 #define ATW_TOFS2 0x84 /* Timing offset parameter 2, 16b */ 126 #define ATW_CMDR 0x88 /* Command */ 127 #define ATW_PCIC 0x8C /* PCI bus performance counter */ 128 #define ATW_PMCSR 0x90 /* Power management command and status */ 129 #define ATW_PAR0 0x94 /* Local MAC address register 0, 32b */ 130 #define ATW_PAR1 0x98 /* Local MAC address register 1, 16b */ 131 #define ATW_MAR0 0x9C /* Multicast address hash table register 0 */ 132 #define ATW_MAR1 0xA0 /* Multicast address hash table register 1 */ 133 #define ATW_ATIMDA0 0xA4 /* Ad Hoc Traffic Indication Map (ATIM) 134 * frame DA, byte[3:0] 135 */ 136 #define ATW_ABDA1 0xA8 /* BSSID address byte[5:4]; 137 * ATIM frame DA byte[5:4] 138 */ 139 #define ATW_BSSID0 0xAC /* BSSID address byte[3:0] */ 140 #define ATW_TXLMT 0xB0 /* WLAN retry limit, 8b; 141 * Max TX MSDU lifetime, 16b 142 */ 143 #define ATW_MIBCNT 0xB4 /* RTS/ACK/FCS MIB count, 32b */ 144 #define ATW_BCNT 0xB8 /* Beacon transmission time, 32b */ 145 #define ATW_TSFTH 0xBC /* TSFT[63:32], 32b */ 146 #define ATW_TSC 0xC0 /* TSFT[39:32] down count value */ 147 #define ATW_SYNRF 0xC4 /* SYN RF IF direct control */ 148 #define ATW_BPLI 0xC8 /* Beacon interval, 16b. 149 * STA listen interval, 16b. 150 */ 151 #define ATW_CAP0 0xCC /* Current channel, 4b. RCVDTIM, 1b. */ 152 #define ATW_CAP1 0xD0 /* Capability information, 16b. 153 * ATIM window, 1b. 154 */ 155 #define ATW_RMD 0xD4 /* RX max reception duration, 16b */ 156 #define ATW_CFPP 0xD8 /* CFP parameter, 32b */ 157 #define ATW_TOFS0 0xDC /* Timing offset parameter 0, 28b */ 158 #define ATW_TOFS1 0xE0 /* Timing offset parameter 1, 24b */ 159 #define ATW_IFST 0xE4 /* IFS timing parameter 1, 32b */ 160 #define ATW_RSPT 0xE8 /* Response time, 24b */ 161 #define ATW_TSFTL 0xEC /* TSFT[31:0], 32b */ 162 #define ATW_WEPCTL 0xF0 /* WEP control */ 163 #define ATW_WESK 0xF4 /* Write entry for shared/individual key */ 164 #define ATW_WEPCNT 0xF8 /* WEP count */ 165 #define ATW_MACTEST 0xFC 166 167 #define ATW_FER 0x100 /* Function event */ 168 #define ATW_FEMR 0x104 /* Function event mask */ 169 #define ATW_FPSR 0x108 /* Function present state */ 170 #define ATW_FFER 0x10C /* Function force event */ 171 172 173 #define ATW_PAR_MWIE (1<<24) /* memory write and invalidate 174 * enable 175 */ 176 #define ATW_PAR_MRLE (1<<23) /* memory read line enable */ 177 #define ATW_PAR_MRME (1<<21) /* memory read multiple 178 * enable 179 */ 180 #define ATW_PAR_RAP_MASK 0x60000 /* receive auto-polling in 181 * receive suspended state 182 */ 183 #define ATW_PAR_CAL_MASK 0xc000 /* cache alignment */ 184 #define ATW_PAR_CAL_PBL 0x0 185 /* min(8 DW, PBL) */ 186 #define ATW_PAR_CAL_8DW LSHIFT(0x1, ATW_PAR_CAL_MASK) 187 /* min(16 DW, PBL) */ 188 #define ATW_PAR_CAL_16DW LSHIFT(0x2, ATW_PAR_CAL_MASK) 189 /* min(32 DW, PBL) */ 190 #define ATW_PAR_CAL_32DW LSHIFT(0x3, ATW_PAR_CAL_MASK) 191 #define ATW_PAR_PBL_MASK 0x3f00 /* programmable burst length */ 192 #define ATW_PAR_PBL_UNLIMITED 0x0 193 #define ATW_PAR_PBL_1DW LSHIFT(0x1, ATW_PAR_PBL_MASK) 194 #define ATW_PAR_PBL_2DW LSHIFT(0x2, ATW_PAR_PBL_MASK) 195 #define ATW_PAR_PBL_4DW LSHIFT(0x4, ATW_PAR_PBL_MASK) 196 #define ATW_PAR_PBL_8DW LSHIFT(0x8, ATW_PAR_PBL_MASK) 197 #define ATW_PAR_PBL_16DW LSHIFT(0x16, ATW_PAR_PBL_MASK) 198 #define ATW_PAR_PBL_32DW LSHIFT(0x32, ATW_PAR_PBL_MASK) 199 #define ATW_PAR_BLE (1<<7) /* big/little endian selection */ 200 #define ATW_PAR_DSL_MASK 0x7c /* descriptor skip length */ 201 #define ATW_PAR_BAR (1<<1) /* bus arbitration */ 202 #define ATW_PAR_SWR (1<<0) /* software reset */ 203 204 #define ATW_FRCTL_PWRMGMT (1<<31) /* power management */ 205 #define ATW_FRCTL_VER_MASK 0x60000000 /* protocol version */ 206 #define ATW_FRCTL_ORDER (1<<28) /* order bit */ 207 #define ATW_FRCTL_MAXPSP (1<<27) /* maximum power saving */ 208 #define ATW_C_FRCTL_PRSP (1<<26) /* 1: driver sends probe 209 * response 210 * 0: ASIC sends prresp 211 */ 212 #define ATW_C_FRCTL_DRVBCON (1<<25) /* 1: driver sends beacons 213 * 0: ASIC sends beacons 214 */ 215 #define ATW_C_FRCTL_DRVLINKCTRL (1<<24) /* 1: driver controls link LED 216 * 0: ASIC controls link LED 217 */ 218 #define ATW_C_FRCTL_DRVLINKON (1<<23) /* 1: turn on link LED 219 * 0: turn off link LED 220 */ 221 #define ATW_C_FRCTL_CTX_DATA (1<<22) /* 0: set by CSR28 222 * 1: random 223 */ 224 #define ATW_C_FRCTL_RSVFRM (1<<21) /* 1: receive "reserved" 225 * frames, 0: ignore 226 * reserved frames 227 */ 228 #define ATW_C_FRCTL_CFEND (1<<19) /* write to send CF_END, 229 * ADM8211C/CR clears 230 */ 231 #define ATW_FRCTL_DOZEFRM (1<<18) /* select pre-sleep frame */ 232 #define ATW_FRCTL_PSAWAKE (1<<17) /* MAC is awake (?) */ 233 #define ATW_FRCTL_PSMODE (1<<16) /* MAC is power-saving (?) */ 234 #define ATW_FRCTL_AID_MASK 0xffff /* STA Association ID */ 235 236 #define ATW_INTR_PCF (1<<31) /* started/ended CFP */ 237 #define ATW_INTR_BCNTC (1<<30) /* transmitted IBSS beacon */ 238 #define ATW_INTR_GPINT (1<<29) /* GPIO interrupt */ 239 #define ATW_INTR_LINKOFF (1<<28) /* lost ATW_WCSR_BLN beacons */ 240 #define ATW_INTR_ATIMTC (1<<27) /* transmitted ATIM */ 241 #define ATW_INTR_TSFTF (1<<26) /* TSFT out of range */ 242 #define ATW_INTR_TSCZ (1<<25) /* TSC countdown expired */ 243 #define ATW_INTR_LINKON (1<<24) /* matched SSID, BSSID */ 244 #define ATW_INTR_SQL (1<<23) /* Marvel signal quality */ 245 #define ATW_INTR_WEPTD (1<<22) /* switched WEP table */ 246 #define ATW_INTR_ATIME (1<<21) /* ended ATIM window */ 247 #define ATW_INTR_TBTT (1<<20) /* (TBTT) Target Beacon TX Time 248 * passed 249 */ 250 #define ATW_INTR_NISS (1<<16) /* normal interrupt status 251 * summary: any of 31, 30, 27, 252 * 24, 14, 12, 6, 2, 0. 253 */ 254 #define ATW_INTR_AISS (1<<15) /* abnormal interrupt status 255 * summary: any of 29, 28, 26, 256 * 25, 23, 22, 13, 11, 8, 7, 5, 257 * 4, 3, 1. 258 */ 259 #define ATW_INTR_TEIS (1<<14) /* transmit early interrupt 260 * status: moved TX packet to 261 * FIFO 262 */ 263 #define ATW_INTR_FBE (1<<13) /* fatal bus error */ 264 #define ATW_INTR_REIS (1<<12) /* receive early interrupt 265 * status: RX packet filled 266 * its first descriptor 267 */ 268 #define ATW_INTR_GPTT (1<<11) /* general purpose timer expired */ 269 #define ATW_INTR_RPS (1<<8) /* stopped receive process */ 270 #define ATW_INTR_RDU (1<<7) /* receive descriptor 271 * unavailable 272 */ 273 #define ATW_INTR_RCI (1<<6) /* completed packet reception */ 274 #define ATW_INTR_TUF (1<<5) /* transmit underflow */ 275 #define ATW_INTR_TRT (1<<4) /* transmit retry count 276 * expired 277 */ 278 #define ATW_INTR_TLT (1<<3) /* transmit lifetime exceeded */ 279 #define ATW_INTR_TDU (1<<2) /* transmit descriptor 280 * unavailable 281 */ 282 #define ATW_INTR_TPS (1<<1) /* stopped transmit process */ 283 #define ATW_INTR_TCI (1<<0) /* completed transmit */ 284 #define ATW_NAR_TXCF (1<<31) /* stop process on TX failure */ 285 #define ATW_NAR_HF (1<<30) /* flush TX FIFO to host (?) */ 286 #define ATW_NAR_UTR (1<<29) /* select retry count source */ 287 #define ATW_NAR_PCF (1<<28) /* use one/both transmit 288 * descriptor base addresses 289 */ 290 #define ATW_NAR_CFP (1<<27) /* indicate more TX data to 291 * point coordinator 292 */ 293 #define ATW_C_NAR_APSTA (1<<26) /* 0: STA mode 294 * 1: AP mode 295 */ 296 #define ATW_C_NAR_TDBBE (1<<25) /* 0: disable TDBB 297 * 1: enable TDBB 298 */ 299 #define ATW_C_NAR_TDBHE (1<<24) /* 0: disable TDBH 300 * 1: enable TDBH 301 */ 302 #define ATW_C_NAR_TDBHT (1<<23) /* write 1 to make ASIC 303 * poll TDBH once; ASIC clears 304 */ 305 #define ATW_NAR_SF (1<<21) /* store and forward: ignore 306 * TX threshold 307 */ 308 #define ATW_NAR_TR_MASK 0xc000 /* TX threshold */ 309 #define ATW_NAR_TR_L64 LSHIFT(0x0, ATW_NAR_TR_MASK) 310 #define ATW_NAR_TR_L160 LSHIFT(0x2, ATW_NAR_TR_MASK) 311 #define ATW_NAR_TR_L192 LSHIFT(0x3, ATW_NAR_TR_MASK) 312 #define ATW_NAR_TR_H96 LSHIFT(0x0, ATW_NAR_TR_MASK) 313 #define ATW_NAR_TR_H288 LSHIFT(0x2, ATW_NAR_TR_MASK) 314 #define ATW_NAR_TR_H544 LSHIFT(0x3, ATW_NAR_TR_MASK) 315 #define ATW_NAR_ST (1<<13) /* start/stop transmit */ 316 #define ATW_NAR_OM_MASK 0xc00 /* operating mode */ 317 #define ATW_NAR_OM_NORMAL 0x0 318 #define ATW_NAR_OM_LOOPBACK LSHIFT(0x1, ATW_NAR_OM_MASK) 319 #define ATW_NAR_MM (1<<7) /* RX any multicast */ 320 #define ATW_NAR_PR (1<<6) /* promiscuous mode */ 321 #define ATW_NAR_EA (1<<5) /* match ad hoc packets (?) */ 322 #define ATW_NAR_DISPCF (1<<4) /* 1: PCF *not* supported 323 * 0: PCF supported 324 */ 325 #define ATW_NAR_PB (1<<3) /* pass bad packets */ 326 #define ATW_NAR_STPDMA (1<<2) /* stop DMA, abort packet */ 327 #define ATW_NAR_SR (1<<1) /* start/stop receive */ 328 #define ATW_NAR_CTX (1<<0) /* continuous TX mode */ 329 330 /* IER bits are identical to STSR bits. Use ATW_INTR_*. */ 331 #if 0 332 #define ATW_IER_NIE (1<<16) /* normal interrupt enable */ 333 #define ATW_IER_AIE (1<<15) /* abnormal interrupt enable */ 334 /* normal interrupts: combine with ATW_IER_NIE */ 335 #define ATW_IER_PCFIE (1<<31) /* STA entered CFP */ 336 #define ATW_IER_BCNTCIE (1<<30) /* STA TX'd beacon */ 337 #define ATW_IER_ATIMTCIE (1<<27) /* transmitted ATIM */ 338 #define ATW_IER_LINKONIE (1<<24) /* matched beacon */ 339 #define ATW_IER_ATIMIE (1<<21) /* ended ATIM window */ 340 #define ATW_IER_TBTTIE (1<<20) /* TBTT */ 341 #define ATW_IER_TEIE (1<<14) /* moved TX packet to FIFO */ 342 #define ATW_IER_REIE (1<<12) /* RX packet filled its first 343 * descriptor 344 */ 345 #define ATW_IER_RCIE (1<<6) /* completed RX */ 346 #define ATW_IER_TDUIE (1<<2) /* transmit descriptor 347 * unavailable 348 */ 349 #define ATW_IER_TCIE (1<<0) /* completed TX */ 350 /* abnormal interrupts: combine with ATW_IER_AIE */ 351 #define ATW_IER_GPIE (1<<29) /* GPIO interrupt */ 352 #define ATW_IER_LINKOFFIE (1<<28) /* lost beacon */ 353 #define ATW_IER_TSFTFIE (1<<26) /* TSFT out of range */ 354 #define ATW_IER_TSCIE (1<<25) /* TSC countdown expired */ 355 #define ATW_IER_SQLIE (1<<23) /* signal quality */ 356 #define ATW_IER_WEPIE (1<<22) /* finished WEP table switch */ 357 #define ATW_IER_FBEIE (1<<13) /* fatal bus error */ 358 #define ATW_IER_GPTIE (1<<11) /* general purpose timer expired */ 359 #define ATW_IER_RPSIE (1<<8) /* stopped receive process */ 360 #define ATW_IER_RUIE (1<<7) /* receive descriptor unavailable */ 361 #define ATW_IER_TUIE (1<<5) /* transmit underflow */ 362 #define ATW_IER_TRTIE (1<<4) /* exceeded transmit retry count */ 363 #define ATW_IER_TLTTIE (1<<3) /* transmit lifetime exceeded */ 364 #define ATW_IER_TPSIE (1<<1) /* stopped transmit process */ 365 #endif 366 367 #define ATW_LPC_LPCO (1<<16) /* lost packet counter overflow */ 368 #define ATW_LPC_LPC_MASK 0xffff /* lost packet counter */ 369 370 #define ATW_TEST1_CONTROL (1<<31) /* "0: read from dxfer_control, 371 * 1: read from dxfer_state" 372 */ 373 #define ATW_TEST1_DBGREAD_MASK 0x70000000 /* "control of read data, 374 * debug only" 375 */ 376 #define ATW_TEST1_TXWP_MASK 0xe000000 /* select ATW_WTDP content? */ 377 #define ATW_TEST1_TXWP_TDBD LSHIFT(0x0, ATW_TEST1_TXWP_MASK) 378 #define ATW_TEST1_TXWP_TDBH LSHIFT(0x1, ATW_TEST1_TXWP_MASK) 379 #define ATW_TEST1_TXWP_TDBB LSHIFT(0x2, ATW_TEST1_TXWP_MASK) 380 #define ATW_TEST1_TXWP_TDBP LSHIFT(0x3, ATW_TEST1_TXWP_MASK) 381 #define ATW_TEST1_RSVD0_MASK 0x1ffffc0 /* reserved */ 382 #define ATW_TEST1_TESTMODE_MASK 0x30 383 /* normal operation */ 384 #define ATW_TEST1_TESTMODE_NORMAL LSHIFT(0x0, ATW_TEST1_TESTMODE_MASK) 385 /* MAC-only mode */ 386 #define ATW_TEST1_TESTMODE_MACONLY LSHIFT(0x1, ATW_TEST1_TESTMODE_MASK) 387 /* normal operation */ 388 #define ATW_TEST1_TESTMODE_NORMAL2 LSHIFT(0x2, ATW_TEST1_TESTMODE_MASK) 389 /* monitor mode */ 390 #define ATW_TEST1_TESTMODE_MONITOR LSHIFT(0x3, ATW_TEST1_TESTMODE_MASK) 391 392 #define ATW_TEST1_DUMP_MASK 0xf /* select dump signal 393 * from dxfer (huh?) 394 */ 395 396 #define ATW_SPR_SRS (1<<11) /* activate SEEPROM access */ 397 #define ATW_SPR_SDO (1<<3) /* data out of SEEPROM */ 398 #define ATW_SPR_SDI (1<<2) /* data into SEEPROM */ 399 #define ATW_SPR_SCLK (1<<1) /* SEEPROM clock */ 400 #define ATW_SPR_SCS (1<<0) /* SEEPROM chip select */ 401 402 #define ATW_TEST0_BE_MASK 0xe0000000 /* Bus error state */ 403 #define ATW_TEST0_TS_MASK 0x1c000000 /* Transmit process state */ 404 405 /* Stopped */ 406 #define ATW_TEST0_TS_STOPPED LSHIFT(0, ATW_TEST0_TS_MASK) 407 /* Running - fetch transmit descriptor */ 408 #define ATW_TEST0_TS_FETCH LSHIFT(1, ATW_TEST0_TS_MASK) 409 /* Running - wait for end of transmission */ 410 #define ATW_TEST0_TS_WAIT LSHIFT(2, ATW_TEST0_TS_MASK) 411 /* Running - read buffer from memory and queue into FIFO */ 412 #define ATW_TEST0_TS_READING LSHIFT(3, ATW_TEST0_TS_MASK) 413 #define ATW_TEST0_TS_RESERVED1 LSHIFT(4, ATW_TEST0_TS_MASK) 414 #define ATW_TEST0_TS_RESERVED2 LSHIFT(5, ATW_TEST0_TS_MASK) 415 /* Suspended */ 416 #define ATW_TEST0_TS_SUSPENDED LSHIFT(6, ATW_TEST0_TS_MASK) 417 /* Running - close transmit descriptor */ 418 #define ATW_TEST0_TS_CLOSE LSHIFT(7, ATW_TEST0_TS_MASK) 419 420 /* ADM8211C/CR registers */ 421 /* Suspended */ 422 #define ATW_C_TEST0_TS_SUSPENDED LSHIFT(4, ATW_TEST0_TS_MASK) 423 /* Descriptor write */ 424 #define ATW_C_TEST0_TS_CLOSE LSHIFT(5, ATW_TEST0_TS_MASK) 425 /* Last descriptor write */ 426 #define ATW_C_TEST0_TS_CLOSELAST LSHIFT(6, ATW_TEST0_TS_MASK) 427 /* FIFO full */ 428 #define ATW_C_TEST0_TS_FIFOFULL LSHIFT(7, ATW_TEST0_TS_MASK) 429 430 #define ATW_TEST0_RS_MASK 0x3800000 /* Receive process state */ 431 432 /* Stopped */ 433 #define ATW_TEST0_RS_STOPPED LSHIFT(0, ATW_TEST0_RS_MASK) 434 /* Running - fetch receive descriptor */ 435 #define ATW_TEST0_RS_FETCH LSHIFT(1, ATW_TEST0_RS_MASK) 436 /* Running - check for end of receive */ 437 #define ATW_TEST0_RS_CHECK LSHIFT(2, ATW_TEST0_RS_MASK) 438 /* Running - wait for packet */ 439 #define ATW_TEST0_RS_WAIT LSHIFT(3, ATW_TEST0_RS_MASK) 440 /* Suspended */ 441 #define ATW_TEST0_RS_SUSPENDED LSHIFT(4, ATW_TEST0_RS_MASK) 442 /* Running - close receive descriptor */ 443 #define ATW_TEST0_RS_CLOSE LSHIFT(5, ATW_TEST0_RS_MASK) 444 /* Running - flush current frame from FIFO */ 445 #define ATW_TEST0_RS_FLUSH LSHIFT(6, ATW_TEST0_RS_MASK) 446 /* Running - queue current frame from FIFO into buffer */ 447 #define ATW_TEST0_RS_QUEUE LSHIFT(7, ATW_TEST0_RS_MASK) 448 449 #define ATW_TEST0_EPNE (1<<18) /* SEEPROM not detected */ 450 #define ATW_TEST0_EPSNM (1<<17) /* SEEPROM bad signature */ 451 #define ATW_TEST0_EPTYP_MASK (1<<16) /* SEEPROM type 452 * 1: 93c66, 453 * 0: 93c46 454 */ 455 #define ATW_TEST0_EPTYP_93c66 ATW_TEST0_EPTYP_MASK 456 #define ATW_TEST0_EPTYP_93c46 0 457 #define ATW_TEST0_EPRLD (1<<15) /* recall SEEPROM (write 1) */ 458 459 #define ATW_WCSR_CRCT (1<<30) /* CRC-16 type */ 460 #define ATW_WCSR_WP1E (1<<29) /* match wake-up pattern 1 */ 461 #define ATW_WCSR_WP2E (1<<28) /* match wake-up pattern 2 */ 462 #define ATW_WCSR_WP3E (1<<27) /* match wake-up pattern 3 */ 463 #define ATW_WCSR_WP4E (1<<26) /* match wake-up pattern 4 */ 464 #define ATW_WCSR_WP5E (1<<25) /* match wake-up pattern 5 */ 465 #define ATW_WCSR_BLN_MASK 0xe00000 /* lose link after BLN lost 466 * beacons 467 */ 468 #define ATW_WCSR_TSFTWE (1<<20) /* wake up on TSFT out of 469 * range 470 */ 471 #define ATW_WCSR_TIMWE (1<<19) /* wake up on TIM */ 472 #define ATW_WCSR_ATIMWE (1<<18) /* wake up on ATIM */ 473 #define ATW_WCSR_KEYWE (1<<17) /* wake up on key update */ 474 #define ATW_WCSR_WFRE (1<<10) /* wake up on wake-up frame */ 475 #define ATW_WCSR_MPRE (1<<9) /* wake up on magic packet */ 476 #define ATW_WCSR_LSOE (1<<8) /* wake up on link loss */ 477 /* wake-up reasons correspond to enable bits */ 478 #define ATW_WCSR_KEYUP (1<<6) /* */ 479 #define ATW_WCSR_TSFTW (1<<5) /* */ 480 #define ATW_WCSR_TIMW (1<<4) /* */ 481 #define ATW_WCSR_ATIMW (1<<3) /* */ 482 #define ATW_WCSR_WFR (1<<2) /* */ 483 #define ATW_WCSR_MPR (1<<1) /* */ 484 #define ATW_WCSR_LSO (1<<0) /* */ 485 486 #define ATW_GPTMR_COM_MASK (1<<16) /* continuous operation mode */ 487 #define ATW_GPTMR_GTV_MASK 0xffff /* set countdown in 204us ticks */ 488 489 #define ATW_GPIO_EC1_MASK 0x3000000 /* GPIO1 event configuration */ 490 #define ATW_GPIO_LAT_MASK 0x300000 /* input latch */ 491 #define ATW_GPIO_INTEN_MASK 0xc0000 /* interrupt enable */ 492 #define ATW_GPIO_EN_MASK 0x3f000 /* output enable */ 493 #define ATW_GPIO_O_MASK 0xfc0 /* output value */ 494 #define ATW_GPIO_I_MASK 0x3f /* pin static input */ 495 496 #define ATW_BBPCTL_TWI (1<<31) /* Intersil 3-wire interface */ 497 #define ATW_BBPCTL_RF3KADDR_MASK 0x7f000000 /* Address for RF3000 */ 498 #define ATW_BBPCTL_RF3KADDR_ADDR LSHIFT(0x20, ATW_BBPCTL_RF3KADDR_MASK) 499 #define ATW_BBPCTL_NEGEDGE_DO (1<<23) /* data-out on negative edge */ 500 #define ATW_BBPCTL_NEGEDGE_DI (1<<22) /* data-in on negative edge */ 501 #define ATW_BBPCTL_CCA_ACTLO (1<<21) /* CCA low when busy */ 502 #define ATW_BBPCTL_TYPE_MASK 0x1c0000 /* BBP type */ 503 #define ATW_BBPCTL_WR (1<<17) /* start write; reset on 504 * completion 505 */ 506 #define ATW_BBPCTL_RD (1<<16) /* start read; reset on 507 * completion 508 */ 509 #define ATW_BBPCTL_ADDR_MASK 0xff00 /* BBP address */ 510 #define ATW_BBPCTL_DATA_MASK 0xff /* BBP data */ 511 512 #define ATW_SYNCTL_WR (1<<31) /* start write; reset on 513 * completion 514 */ 515 #define ATW_SYNCTL_RD (1<<30) /* start read; reset on 516 * completion 517 */ 518 #define ATW_SYNCTL_CS0 (1<<29) /* chip select */ 519 #define ATW_SYNCTL_CS1 (1<<28) 520 #define ATW_SYNCTL_CAL (1<<27) /* generate RF CAL pulse after 521 * Rx 522 */ 523 #define ATW_SYNCTL_SELCAL (1<<26) /* RF CAL source, 0: CAL bit, 524 * 1: MAC; needed by Intersil 525 * BBP 526 */ 527 #define ATW_C_SYNCTL_MMICE (1<<25) /* ADM8211C/CR define this 528 * bit. 0: latch data on 529 * negative edge, 1: positive 530 * edge. 531 */ 532 #define ATW_SYNCTL_RFTYPE_MASK 0x1c00000 /* RF type */ 533 #define ATW_SYNCTL_DATA_MASK 0x3fffff /* synthesizer setting */ 534 535 #define ATW_PLCPHD_SIGNAL_MASK 0xff000000 /* signal field in PLCP header, 536 * only for beacon, ATIM, and 537 * RTS. 538 */ 539 #define ATW_PLCPHD_SERVICE_MASK 0xff0000 /* service field in PLCP 540 * header; with RFMD BBP, 541 * sets Tx power for beacon, 542 * RTS, ATIM. 543 */ 544 #define ATW_PLCPHD_PMBL (1<<15) /* 0: long preamble, 1: short */ 545 546 #define ATW_MMIWADDR_LENLO_MASK 0xff000000 /* tx: written 4th */ 547 #define ATW_MMIWADDR_LENHI_MASK 0xff0000 /* tx: written 3rd */ 548 #define ATW_MMIWADDR_GAIN_MASK 0xff00 /* tx: written 2nd */ 549 #define ATW_MMIWADDR_RATE_MASK 0xff /* tx: written 1st */ 550 551 /* was magic 0x100E0C0A */ 552 #define ATW_MMIWADDR_INTERSIL \ 553 (LSHIFT(0x0c, ATW_MMIWADDR_GAIN_MASK) | \ 554 LSHIFT(0x0a, ATW_MMIWADDR_RATE_MASK) | \ 555 LSHIFT(0x0e, ATW_MMIWADDR_LENHI_MASK) | \ 556 LSHIFT(0x10, ATW_MMIWADDR_LENLO_MASK)) 557 558 /* was magic 0x00009101 559 * 560 * ADMtek sets the AI bit on the ATW_MMIWADDR_GAIN_MASK address to 561 * put the RF3000 into auto-increment mode so that it can write Tx gain, 562 * Tx length (high) and Tx length (low) registers back-to-back. 563 */ 564 #define ATW_MMIWADDR_RFMD \ 565 (LSHIFT(RF3000_TWI_AI|RF3000_GAINCTL, ATW_MMIWADDR_GAIN_MASK) | \ 566 LSHIFT(RF3000_CTL, ATW_MMIWADDR_RATE_MASK)) 567 568 #define ATW_MMIRADDR1_RSVD_MASK 0xff000000 569 #define ATW_MMIRADDR1_PWRLVL_MASK 0xff0000 570 #define ATW_MMIRADDR1_RSSI_MASK 0xff00 571 #define ATW_MMIRADDR1_RXSTAT_MASK 0xff 572 573 /* was magic 0x00007c7e 574 * 575 * TBD document registers for Intersil 3861 baseband 576 */ 577 #define ATW_MMIRADDR1_INTERSIL \ 578 (LSHIFT(0x7c, ATW_MMIRADDR1_RSSI_MASK) | \ 579 LSHIFT(0x7e, ATW_MMIRADDR1_RXSTAT_MASK)) 580 581 /* was magic 0x00000301 */ 582 #define ATW_MMIRADDR1_RFMD \ 583 (LSHIFT(RF3000_RSSI, ATW_MMIRADDR1_RSSI_MASK) | \ 584 LSHIFT(RF3000_RXSTAT, ATW_MMIRADDR1_RXSTAT_MASK)) 585 586 /* was magic 0x00100000 */ 587 #define ATW_MMIRADDR2_INTERSIL \ 588 (LSHIFT(0x0, ATW_MMIRADDR2_ID_MASK) | \ 589 LSHIFT(0x10, ATW_MMIRADDR2_RXPECNT_MASK)) 590 591 /* was magic 0x7e100000 */ 592 #define ATW_MMIRADDR2_RFMD \ 593 (LSHIFT(0x7e, ATW_MMIRADDR2_ID_MASK) | \ 594 LSHIFT(0x10, ATW_MMIRADDR2_RXPECNT_MASK)) 595 596 #define ATW_MMIRADDR2_ID_MASK 0xff000000 /* 1st element ID in WEP table 597 * for Probe Response (huh?) 598 */ 599 /* RXPE is re-asserted after RXPECNT * 22MHz. */ 600 #define ATW_MMIRADDR2_RXPECNT_MASK 0xff0000 601 #define ATW_MMIRADDR2_PROREXT (1<<15) /* Probe Response 602 * 11Mb/s length 603 * extension. 604 */ 605 #define ATW_MMIRADDR2_PRORLEN_MASK 0x7fff /* Probe Response 606 * microsecond length 607 */ 608 609 #define ATW_TXBR_ALCUPDATE_MASK (1<<31) /* auto-update BBP with ALCSET */ 610 #define ATW_TXBR_TBCNT_MASK 0x1f0000 /* transmit burst count */ 611 #define ATW_TXBR_ALCSET_MASK 0xff00 /* TX power level set point */ 612 #define ATW_TXBR_ALCREF_MASK 0xff /* TX power level reference point */ 613 614 #define ATW_ALCSTAT_MCOV_MASK (1<<27) /* MPDU count overflow */ 615 #define ATW_ALCSTAT_ESOV_MASK (1<<26) /* error sum overflow */ 616 #define ATW_ALCSTAT_MCNT_MASK 0x3ff0000 /* MPDU count, unsigned integer */ 617 #define ATW_ALCSTAT_ERSUM_MASK 0xffff /* power error sum, 618 * 2's complement signed integer 619 */ 620 621 #define ATW_TOFS2_PWR1UP_MASK 0xf0000000 /* delay of Tx/Rx from PE1, 622 * Radio, PHYRST change after 623 * power-up, in 2ms units 624 */ 625 #define ATW_TOFS2_PWR0PAPE_MASK 0xf000000 /* delay of PAPE going low 626 * after internal data 627 * transmit end, in us 628 */ 629 #define ATW_TOFS2_PWR1PAPE_MASK 0xf00000 /* delay of PAPE going high 630 * after TXPE asserted, in us 631 */ 632 #define ATW_TOFS2_PWR0TRSW_MASK 0xf0000 /* delay of TRSW going low 633 * after internal data transmit 634 * end, in us 635 */ 636 #define ATW_TOFS2_PWR1TRSW_MASK 0xf000 /* delay of TRSW going high 637 * after TXPE asserted, in us 638 */ 639 #define ATW_TOFS2_PWR0PE2_MASK 0xf00 /* delay of PE2 going low 640 * after internal data transmit 641 * end, in us 642 */ 643 #define ATW_TOFS2_PWR1PE2_MASK 0xf0 /* delay of PE2 going high 644 * after TXPE asserted, in us 645 */ 646 #define ATW_TOFS2_PWR0TXPE_MASK 0xf /* delay of TXPE going low 647 * after internal data transmit 648 * end, in us 649 */ 650 651 #define ATW_CMDR_PM (1<<19) /* enables power mgmt 652 * capabilities. 653 */ 654 #define ATW_CMDR_APM (1<<18) /* APM mode, effective when 655 * PM = 1. 656 */ 657 #define ATW_CMDR_RTE (1<<4) /* enable Rx FIFO threshold */ 658 #define ATW_CMDR_DRT_MASK 0xc /* drain Rx FIFO threshold */ 659 /* 32 bytes */ 660 #define ATW_CMDR_DRT_8DW LSHIFT(0x0, ATW_CMDR_DRT_MASK) 661 /* 64 bytes */ 662 #define ATW_CMDR_DRT_16DW LSHIFT(0x1, ATW_CMDR_DRT_MASK) 663 /* Store & Forward */ 664 #define ATW_CMDR_DRT_SF LSHIFT(0x2, ATW_CMDR_DRT_MASK) 665 /* Reserved */ 666 #define ATW_CMDR_DRT_RSVD LSHIFT(0x3, ATW_CMDR_DRT_MASK) 667 #define ATW_CMDR_SINT_MASK (1<<1) /* software interrupt---huh? */ 668 669 /* TBD PCIC */ 670 671 /* TBD PMCSR */ 672 673 674 #define ATW_PAR0_PAB0_MASK 0xff /* MAC address byte 0 */ 675 #define ATW_PAR0_PAB1_MASK 0xff00 /* MAC address byte 1 */ 676 #define ATW_PAR0_PAB2_MASK 0xff0000 /* MAC address byte 2 */ 677 #define ATW_PAR0_PAB3_MASK 0xff000000 /* MAC address byte 3 */ 678 679 #define ATW_C_PAR1_CTD 0xffff0000 /* Continuous Tx pattern */ 680 #define ATW_PAR1_PAB5_MASK 0xff00 /* MAC address byte 5 */ 681 #define ATW_PAR1_PAB4_MASK 0xff /* MAC address byte 4 */ 682 683 #define ATW_MAR0_MAB3_MASK 0xff000000 /* multicast table bits 31:24 */ 684 #define ATW_MAR0_MAB2_MASK 0xff0000 /* multicast table bits 23:16 */ 685 #define ATW_MAR0_MAB1_MASK 0xff00 /* multicast table bits 15:8 */ 686 #define ATW_MAR0_MAB0_MASK 0xff /* multicast table bits 7:0 */ 687 688 #define ATW_MAR1_MAB7_MASK 0xff000000 /* multicast table bits 63:56 */ 689 #define ATW_MAR1_MAB6_MASK 0xff0000 /* multicast table bits 55:48 */ 690 #define ATW_MAR1_MAB5_MASK 0xff00 /* multicast table bits 47:40 */ 691 #define ATW_MAR1_MAB4_MASK 0xff /* multicast table bits 39:32 */ 692 693 /* ATIM destination address */ 694 #define ATW_ATIMDA0_ATIMB3_MASK 0xff000000 695 #define ATW_ATIMDA0_ATIMB2_MASK 0xff0000 696 #define ATW_ATIMDA0_ATIMB1_MASK 0xff00 697 #define ATW_ATIMDA0_ATIMB0_MASK 0xff 698 699 /* ATIM destination address, BSSID */ 700 #define ATW_ABDA1_BSSIDB5_MASK 0xff000000 701 #define ATW_ABDA1_BSSIDB4_MASK 0xff0000 702 #define ATW_ABDA1_ATIMB5_MASK 0xff00 703 #define ATW_ABDA1_ATIMB4_MASK 0xff 704 705 /* BSSID */ 706 #define ATW_BSSID0_BSSIDB3_MASK 0xff000000 707 #define ATW_BSSID0_BSSIDB2_MASK 0xff0000 708 #define ATW_BSSID0_BSSIDB1_MASK 0xff00 709 #define ATW_BSSID0_BSSIDB0_MASK 0xff 710 711 #define ATW_TXLMT_MTMLT_MASK 0xffff0000 /* max TX MSDU lifetime in TU */ 712 #define ATW_TXLMT_SRTYLIM_MASK 0xff /* short retry limit */ 713 714 #define ATW_MIBCNT_FFCNT_MASK 0xff000000 /* FCS failure count */ 715 #define ATW_MIBCNT_AFCNT_MASK 0xff0000 /* ACK failure count */ 716 #define ATW_MIBCNT_RSCNT_MASK 0xff00 /* RTS success count */ 717 #define ATW_MIBCNT_RFCNT_MASK 0xff /* RTS failure count */ 718 719 #define ATW_BCNT_PLCPH_MASK 0xff0000 /* 11M PLCP length (us) */ 720 #define ATW_BCNT_PLCPL_MASK 0xff00 /* 5.5M PLCP length (us) */ 721 #define ATW_BCNT_BCNT_MASK 0xff /* byte count of beacon frame */ 722 723 /* For ADM8211C/CR */ 724 /* ATW_C_TSC_TIMTABSEL = 1 */ 725 #define ATW_C_BCNT_EXTEN1 (1<<31) /* 11M beacon len. extension */ 726 #define ATW_C_BCNT_BEANLEN1 0x7fff0000 /* beacon length in us */ 727 /* ATW_C_TSC_TIMTABSEL = 0 */ 728 #define ATW_C_BCNT_EXTEN0 (1<<15) /* 11M beacon len. extension */ 729 #define ATW_C_BCNT_BEANLEN0 BIT(14,0) /* beacon length in us */ 730 731 #define ATW_C_TSC_TIMOFS 0xff000000 /* I think this is the 732 * SRAM offset for the TIM 733 */ 734 #define ATW_C_TSC_TIMLEN 0x3ff000 /* length of TIM */ 735 #define ATW_C_TSC_TIMTABSEL (1<<4) /* select TIM table 0 or 1 */ 736 #define ATW_TSC_TSC_MASK 0xf /* TSFT countdown value, 0 737 * disables 738 */ 739 740 #define ATW_SYNRF_SELSYN (1<<31) /* 0: MAC controls SYN IF pins, 741 * 1: ATW_SYNRF controls SYN IF pins. 742 */ 743 #define ATW_SYNRF_SELRF (1<<30) /* 0: MAC controls RF IF pins, 744 * 1: ATW_SYNRF controls RF IF pins. 745 */ 746 #define ATW_SYNRF_LERF (1<<29) /* if SELSYN = 1, direct control of 747 * LERF# pin 748 */ 749 #define ATW_SYNRF_LEIF (1<<28) /* if SELSYN = 1, direct control of 750 * LEIF# pin 751 */ 752 #define ATW_SYNRF_SYNCLK (1<<27) /* if SELSYN = 1, direct control of 753 * SYNCLK pin 754 */ 755 #define ATW_SYNRF_SYNDATA (1<<26) /* if SELSYN = 1, direct control of 756 * SYNDATA pin 757 */ 758 #define ATW_SYNRF_PE1 (1<<25) /* if SELRF = 1, direct control of 759 * PE1 pin 760 */ 761 #define ATW_SYNRF_PE2 (1<<24) /* if SELRF = 1, direct control of 762 * PE2 pin 763 */ 764 #define ATW_SYNRF_PAPE (1<<23) /* if SELRF = 1, direct control of 765 * PAPE pin 766 */ 767 #define ATW_C_SYNRF_TRSW (1<<22) /* if SELRF = 1, direct control of 768 * TRSW pin 769 */ 770 #define ATW_C_SYNRF_TRSWN (1<<21) /* if SELRF = 1, direct control of 771 * TRSWn pin 772 */ 773 #define ATW_SYNRF_INTERSIL_EN (1<<20) /* if SELRF = 1, enables 774 * some signal used by the 775 * Intersil RF front-end? 776 * Undocumented. 777 */ 778 #define ATW_SYNRF_PHYRST (1<<18) /* if SELRF = 1, direct control of 779 * PHYRST# pin 780 */ 781 /* 1: force TXPE = RXPE = 1 if ATW_CMDR[27] = 0. */ 782 #define ATW_C_SYNRF_RF2958PD ATW_SYNRF_PHYRST 783 784 #define ATW_BPLI_BP_MASK 0xffff0000 /* beacon interval in TU */ 785 #define ATW_BPLI_LI_MASK 0xffff /* STA listen interval in 786 * beacon intervals 787 */ 788 789 #define ATW_C_CAP0_TIMLEN1 0xff000000 /* TIM table 1 len in bytes 790 * including TIM ID (XXX huh?) 791 */ 792 #define ATW_C_CAP0_TIMLEN0 0xff0000 /* TIM table 0 len in bytes, 793 * including TIM ID (XXX huh?) 794 */ 795 #define ATW_C_CAP0_CWMAX 0xf00 /* 1 <= CWMAX <= 5 fixes CW? 796 * 5 < CWMAX <= 9 sets max? 797 * 10? 798 * default 0 799 */ 800 #define ATW_CAP0_RCVDTIM (1<<4) /* receive every DTIM */ 801 #define ATW_CAP0_CHN_MASK 0xf /* current DSSS channel */ 802 803 #define ATW_CAP1_CAPI_MASK 0xffff0000 /* capability information */ 804 #define ATW_CAP1_ATIMW_MASK 0xffff /* ATIM window in TU */ 805 806 #define ATW_RMD_ATIMST (1<<31) /* ATIM frame TX status */ 807 #define ATW_RMD_CFP (1<<30) /* CFP indicator */ 808 #define ATW_RMD_PCNT 0xfff0000 /* idle time between 809 * awake/ps mode, in seconds 810 */ 811 #define ATW_RMD_RMRD_MASK 0xffff /* max RX reception duration 812 * in us 813 */ 814 815 #define ATW_CFPP_CFPP 0xff000000 /* CFP unit DTIM */ 816 #define ATW_CFPP_CFPMD 0xffff00 /* CFP max duration in TU */ 817 #define ATW_CFPP_DTIMP 0xff /* DTIM period in beacon 818 * intervals 819 */ 820 #define ATW_TOFS0_USCNT_MASK 0x3f000000 /* number of system clocks 821 * in 1 microsecond. 822 * Depends PCI bus speed? 823 */ 824 #define ATW_C_TOFS0_TUCNT_MASK 0x7c00 /* PIFS (microseconds) */ 825 #define ATW_TOFS0_TUCNT_MASK 0x3ff /* TU counter in microseconds */ 826 827 /* TBD TOFS1 */ 828 #define ATW_TOFS1_TSFTOFSR_MASK 0xff000000 /* RX TSFT offset in 829 * microseconds: RF+BBP 830 * latency 831 */ 832 #define ATW_TOFS1_TBTTPRE_MASK 0xffff00 /* prediction time, (next 833 * Nth TBTT - TBTTOFS) in 834 * microseconds (huh?). To 835 * match TSFT[25:10] (huh?). 836 */ 837 #define ATW_TBTTPRE_MASK 0x3fffc00 838 #define ATW_TOFS1_TBTTOFS_MASK 0xff /* wake-up time offset before 839 * TBTT in TU 840 */ 841 #define ATW_IFST_SLOT_MASK 0xf800000 /* SLOT time in us */ 842 #define ATW_IFST_SIFS_MASK 0x7f8000 /* SIFS time in us */ 843 #define ATW_IFST_DIFS_MASK 0x7e00 /* DIFS time in us */ 844 #define ATW_IFST_EIFS_MASK 0x1ff /* EIFS time in us */ 845 846 #define ATW_RSPT_MART_MASK 0xffff0000 /* max response time in us */ 847 #define ATW_RSPT_MIRT_MASK 0xff00 /* min response time in us */ 848 #define ATW_RSPT_TSFTOFST_MASK 0xff /* TX TSFT offset in us */ 849 850 #define ATW_WEPCTL_WEPENABLE (1<<31) /* enable WEP engine */ 851 #define ATW_WEPCTL_AUTOSWITCH (1<<30) /* auto-switch enable (huh?) */ 852 #define ATW_WEPCTL_CURTBL (1<<29) /* current table in use */ 853 #define ATW_WEPCTL_WR (1<<28) /* */ 854 #define ATW_WEPCTL_RD (1<<27) /* */ 855 #define ATW_WEPCTL_WEPRXBYP (1<<25) /* bypass WEP on RX */ 856 #define ATW_WEPCTL_SHKEY (1<<24) /* 1: pass to host if tbl 857 * lookup fails, 0: use 858 * shared-key 859 */ 860 #define ATW_WEPCTL_UNKNOWN0 (1<<23) /* has something to do with 861 * revision 0x20. Possibly 862 * selects a different WEP 863 * table. 864 */ 865 #define ATW_WEPCTL_TBLADD_MASK 0x1ff /* add to table */ 866 867 /* set these bits in the second byte of a SRAM shared key record to affect 868 * the use and interpretation of the key in the record. 869 */ 870 #define ATW_WEP_ENABLED (1<<7) 871 #define ATW_WEP_104BIT (1<<6) 872 873 #define ATW_WESK_DATA_MASK 0xffff /* data */ 874 #define ATW_WEPCNT_WIEC_MASK 0xffff /* WEP ICV error count */ 875 876 #define ATW_MACTEST_FORCE_IV (1<<23) 877 #define ATW_MACTEST_FORCE_KEYID (1<<22) 878 #define ATW_MACTEST_KEYID_MASK 0x300000 879 #define ATW_MACTEST_MMI_USETXCLK (1<<11) 880 881 /* Function Event/Status registers */ 882 883 #define ATW_FER_INTR (1<<15) /* interrupt: set regardless of mask */ 884 #define ATW_FER_GWAKE (1<<4) /* general wake-up: set regardless of mask */ 885 886 #define ATW_FEMR_INTR_EN (1<<15) /* enable INTA# */ 887 #define ATW_FEMR_WAKEUP_EN (1<<14) /* enable wake-up */ 888 #define ATW_FEMR_GWAKE_EN (1<<4) /* enable general wake-up */ 889 890 #define ATW_FPSR_INTR_STATUS (1<<15) /* interrupt status */ 891 #define ATW_FPSR_WAKEUP_STATUS (1<<4) /* CSTSCHG state */ 892 #define ATW_FFER_INTA_FORCE (1<<15) /* activate INTA (if not masked) */ 893 #define ATW_FFER_GWAKE_FORCE (1<<4) /* activate CSTSCHG (if not masked) */ 894 895 /* Serial EEPROM offsets */ 896 #define ATW_SR_CLASS_CODE (0x00/2) 897 #define ATW_SR_FORMAT_VERSION (0x02/2) 898 #define ATW_SR_MAJOR_MASK 0xff 899 #define ATW_SR_MINOR_MASK 0xff00 900 #define ATW_SR_MAC00 (0x08/2) /* CSR21 */ 901 #define ATW_SR_MAC01 (0x0A/2) /* CSR21/22 */ 902 #define ATW_SR_MAC10 (0x0C/2) /* CSR22 */ 903 #define ATW_SR_CSR20 (0x16/2) 904 #define ATW_SR_ANT_MASK 0x1c00 905 #define ATW_SR_PWRSCALE_MASK 0x300 906 #define ATW_SR_CLKSAVE_MASK 0xc0 907 #define ATW_SR_RFTYPE_MASK 0x38 908 #define ATW_SR_BBPTYPE_MASK 0x7 909 #define ATW_SR_CR28_CR03 (0x18/2) 910 #define ATW_SR_CR28_MASK 0xff00 911 #define ATW_SR_CR03_MASK 0xff 912 #define ATW_SR_CTRY_CR29 (0x1A/2) 913 #define ATW_SR_CTRY_MASK 0xff00 /* country code */ 914 #define COUNTRY_FCC 0 915 #define COUNTRY_IC 1 916 #define COUNTRY_ETSI 2 917 #define COUNTRY_SPAIN 3 918 #define COUNTRY_FRANCE 4 919 #define COUNTRY_MMK 5 920 #define COUNTRY_MMK2 6 921 #define ATW_SR_CR29_MASK 0xff 922 #define ATW_SR_PCI_DEVICE (0x20/2) /* CR0 */ 923 #define ATW_SR_PCI_VENDOR (0x22/2) /* CR0 */ 924 #define ATW_SR_SUB_DEVICE (0x24/2) /* CR11 */ 925 #define ATW_SR_SUB_VENDOR (0x26/2) /* CR11 */ 926 #define ATW_SR_CR15 (0x28/2) 927 #define ATW_SR_LOCISPTR (0x2A/2) /* CR10 */ 928 #define ATW_SR_HICISPTR (0x2C/2) /* CR10 */ 929 #define ATW_SR_CSR18 (0x2E/2) 930 #define ATW_SR_D0_D1_PWR (0x40/2) /* CR49 */ 931 #define ATW_SR_D2_D3_PWR (0x42/2) /* CR49 */ 932 #define ATW_SR_CIS_WORDS (0x52/2) 933 /* CR17 of RFMD RF3000 BBP: returns TWO channels */ 934 #define ATW_SR_TXPOWER(chnl) (0x54/2 + ((chnl) - 1)/2) 935 /* CR20 of RFMD RF3000 BBP: returns TWO channels */ 936 #define ATW_SR_LPF_CUTOFF(chnl) (0x62/2 + ((chnl) - 1)/2) 937 /* CR21 of RFMD RF3000 BBP: returns TWO channels */ 938 #define ATW_SR_LNA_GS_THRESH(chnl) (0x70/2 + ((chnl) - 1)/2) 939 #define ATW_SR_CHECKSUM (0x7e/2) /* for data 0x00-0x7d */ 940 #define ATW_SR_CIS (0x80/2) /* Cardbus CIS */ 941 942 /* Tx descriptor */ 943 struct atw_txdesc { 944 u_int32_t at_ctl; 945 #define at_stat at_ctl 946 u_int32_t at_flags; 947 u_int32_t at_buf1; 948 u_int32_t at_buf2; 949 }; 950 951 #define ATW_TXCTL_OWN (1<<31) /* 1: ready to transmit */ 952 #define ATW_TXCTL_DONE (1<<30) /* 0: not processed */ 953 #define ATW_TXCTL_TXDR_MASK 0xff00000 /* TX data rate (?) */ 954 #define ATW_TXCTL_TL_MASK 0xfffff /* retry limit, 0 - 255 */ 955 956 #define ATW_TXSTAT_OWN ATW_TXCTL_OWN /* 0: not for transmission */ 957 #define ATW_TXSTAT_DONE ATW_TXCTL_DONE /* 1: been processed */ 958 #define ATW_TXSTAT_ES (1<<29) /* 0: TX successful */ 959 #define ATW_TXSTAT_TLT (1<<28) /* TX lifetime expired */ 960 #define ATW_TXSTAT_TRT (1<<27) /* TX retry limit expired */ 961 #define ATW_TXSTAT_TUF (1<<26) /* TX under-run error */ 962 #define ATW_TXSTAT_TRO (1<<25) /* TX over-run error */ 963 #define ATW_TXSTAT_SOFBR (1<<24) /* packet size != buffer size 964 * (?) 965 */ 966 #define ATW_TXSTAT_ARC_MASK 0xfff /* accumulated retry count */ 967 968 #define ATW_TXFLAG_IC (1<<31) /* interrupt on completion */ 969 #define ATW_TXFLAG_LS (1<<30) /* packet's last descriptor */ 970 #define ATW_TXFLAG_FS (1<<29) /* packet's first descriptor */ 971 #define ATW_TXFLAG_TER (1<<25) /* end of ring */ 972 #define ATW_TXFLAG_TCH (1<<24) /* at_buf2 is 2nd chain */ 973 #define ATW_TXFLAG_TBS2_MASK 0xfff000 /* at_buf2 byte count */ 974 #define ATW_TXFLAG_TBS1_MASK 0xfff /* at_buf1 byte count */ 975 976 /* Rx descriptor */ 977 struct atw_rxdesc { 978 u_int32_t ar_stat; 979 u_int32_t ar_ctl; 980 u_int32_t ar_buf1; 981 u_int32_t ar_buf2; 982 }; 983 984 #define ar_rssi ar_ctl 985 986 #define ATW_RXCTL_RER (1<<25) /* end of ring */ 987 #define ATW_RXCTL_RCH (1<<24) /* ar_buf2 is 2nd chain */ 988 #define ATW_RXCTL_RBS2_MASK 0xfff000 /* ar_buf2 byte count */ 989 #define ATW_RXCTL_RBS1_MASK 0xfff /* ar_buf1 byte count */ 990 991 #define ATW_RXSTAT_OWN (1<<31) /* 1: NIC may fill descriptor */ 992 #define ATW_RXSTAT_ES (1<<30) /* error summary, 0 on 993 * success 994 */ 995 #define ATW_RXSTAT_SQL (1<<29) /* has signal quality (?) */ 996 #define ATW_RXSTAT_DE (1<<28) /* descriptor error---packet is 997 * truncated. last descriptor 998 * only 999 */ 1000 #define ATW_RXSTAT_FS (1<<27) /* packet's first descriptor */ 1001 #define ATW_RXSTAT_LS (1<<26) /* packet's last descriptor */ 1002 #define ATW_RXSTAT_PCF (1<<25) /* received during CFP */ 1003 #define ATW_RXSTAT_SFDE (1<<24) /* PLCP SFD error */ 1004 #define ATW_RXSTAT_SIGE (1<<23) /* PLCP signal error */ 1005 #define ATW_RXSTAT_CRC16E (1<<22) /* PLCP CRC16 error */ 1006 #define ATW_RXSTAT_RXTOE (1<<21) /* RX time-out, last descriptor 1007 * only. 1008 */ 1009 #define ATW_RXSTAT_CRC32E (1<<20) /* CRC32 error */ 1010 #define ATW_RXSTAT_ICVE (1<<19) /* WEP ICV error */ 1011 #define ATW_RXSTAT_DA1 (1<<17) /* DA bit 1, admin'd address */ 1012 #define ATW_RXSTAT_DA0 (1<<16) /* DA bit 0, group address */ 1013 #define ATW_RXSTAT_RXDR_MASK 0xf000 /* RX data rate */ 1014 #define ATW_RXSTAT_FL_MASK 0xfff /* RX frame length, last 1015 * descriptor only 1016 */ 1017 1018 /* Static RAM (contains WEP keys, beacon content). Addresses and size 1019 * are in 16-bit words. 1020 */ 1021 #define ATW_SRAM_ADDR_INDIVL_KEY 0x0 1022 #define ATW_SRAM_ADDR_SHARED_KEY (0x160 * 2) 1023 #define ATW_SRAM_ADDR_SSID (0x180 * 2) 1024 #define ATW_SRAM_ADDR_SUPRATES (0x191 * 2) 1025 #define ATW_SRAM_MAXSIZE (0x200 * 2) 1026 #define ATW_SRAM_A_SIZE ATW_SRAM_MAXSIZE 1027 #define ATW_SRAM_B_SIZE (0x1c0 * 2) 1028 1029