1 /* $OpenBSD: dc21040reg.h,v 1.15 2005/11/07 00:03:09 brad Exp $ */ 2 /* $NetBSD: dc21040reg.h,v 1.11 1997/06/08 18:44:02 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1994, 1995, 1996 Matt Thomas <matt@3am-software.com> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * Id: dc21040reg.h,v 1.24 1997/05/16 19:47:09 thomas Exp 28 */ 29 30 #if !defined(_DC21040_H) 31 #define _DC21040_H 32 33 /* XXX The following only works with 21x4x chips which have 34 * the descriptor swap bit. 21040 chips need to have the 35 * descriptor in LE order regardles............. 36 */ 37 #if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN 38 #define TULIP_BITFIELD2(a, b) b, a 39 #define TULIP_BITFIELD3(a, b, c) c, b, a 40 #define TULIP_BITFIELD4(a, b, c, d) d, c, b, a 41 #else 42 #define TULIP_BITFIELD2(a, b) a, b 43 #define TULIP_BITFIELD3(a, b, c) a, b, c 44 #define TULIP_BITFIELD4(a, b, c, d) a, b, c, d 45 #endif 46 47 typedef struct { 48 u_int32_t d_status; 49 u_int32_t TULIP_BITFIELD3(d_length1 : 11, 50 d_length2 : 11, 51 d_flag : 10); 52 u_int32_t d_addr1; 53 u_int32_t d_addr2; 54 } tulip_desc_t; 55 56 #define TULIP_DSTS_OWNER 0x80000000 /* Owner (1 = 21040) */ 57 #define TULIP_DSTS_ERRSUM 0x00008000 /* Error Summary */ 58 /* 59 * Transmit Status 60 */ 61 #define TULIP_DSTS_TxBABBLE 0x00004000 /* Transmitter Babbled */ 62 #define TULIP_DSTS_TxCARRLOSS 0x00000800 /* Carrier Loss */ 63 #define TULIP_DSTS_TxNOCARR 0x00000400 /* No Carrier */ 64 #define TULIP_DSTS_TxLATECOLL 0x00000200 /* Late Collision */ 65 #define TULIP_DSTS_TxEXCCOLL 0x00000100 /* Excessive Collisions */ 66 #define TULIP_DSTS_TxNOHRTBT 0x00000080 /* No Heartbeat */ 67 #define TULIP_DSTS_TxCOLLMASK 0x00000078 /* Collision Count (mask) */ 68 #define TULIP_DSTS_V_TxCOLLCNT 0x00000003 /* Collision Count (bit) */ 69 #define TULIP_DSTS_TxLINKFAIL 0x00000004 /* Link Failure */ 70 #define TULIP_DSTS_TxUNDERFLOW 0x00000002 /* Underflow Error */ 71 #define TULIP_DSTS_TxDEFERRED 0x00000001 /* Initially Deferred */ 72 /* 73 * Receive Status 74 */ 75 #define TULIP_DSTS_RxBADLENGTH 0x00004000 /* Length Error */ 76 #define TULIP_DSTS_RxDATATYPE 0x00003000 /* Data Type */ 77 #define TULIP_DSTS_RxRUNT 0x00000800 /* Runt Frame */ 78 #define TULIP_DSTS_RxMULTICAST 0x00000400 /* Multicast Frame */ 79 #define TULIP_DSTS_RxFIRSTDESC 0x00000200 /* First Descriptor */ 80 #define TULIP_DSTS_RxLASTDESC 0x00000100 /* Last Descriptor */ 81 #define TULIP_DSTS_RxTOOLONG 0x00000080 /* Frame Too Long */ 82 #define TULIP_DSTS_RxCOLLSEEN 0x00000040 /* Collision Seen */ 83 #define TULIP_DSTS_RxFRAMETYPE 0x00000020 /* Frame Type */ 84 #define TULIP_DSTS_RxWATCHDOG 0x00000010 /* Receive Watchdog */ 85 #define TULIP_DSTS_RxDRBBLBIT 0x00000004 /* Dribble Bit */ 86 #define TULIP_DSTS_RxBADCRC 0x00000002 /* CRC Error */ 87 #define TULIP_DSTS_RxOVERFLOW 0x00000001 /* Overflow */ 88 89 90 #define TULIP_DFLAG_ENDRING 0x0008 /* End of Transmit Ring */ 91 #define TULIP_DFLAG_CHAIN 0x0004 /* Chain using d_addr2 */ 92 93 #define TULIP_DFLAG_TxWANTINTR 0x0200 /* Signal Interrupt on Completion */ 94 #define TULIP_DFLAG_TxLASTSEG 0x0100 /* Last Segment */ 95 #define TULIP_DFLAG_TxFIRSTSEG 0x0080 /* First Segment */ 96 #define TULIP_DFLAG_TxINVRSFILT 0x0040 /* Inverse Filtering */ 97 #define TULIP_DFLAG_TxSETUPPKT 0x0020 /* Setup Packet */ 98 #define TULIP_DFLAG_TxHASCRC 0x0010 /* Don't Append the CRC */ 99 #define TULIP_DFLAG_TxNOPADDING 0x0002 /* Don't AutoPad */ 100 #define TULIP_DFLAG_TxHASHFILT 0x0001 /* Hash/Perfect Filtering */ 101 102 /* 103 * The 21040 Registers (IO Space Addresses) 104 */ 105 #define TULIP_REG_BUSMODE 0x00 /* CSR0 -- Bus Mode */ 106 #define TULIP_REG_TXPOLL 0x08 /* CSR1 -- Transmit Poll Demand */ 107 #define TULIP_REG_RXPOLL 0x10 /* CSR2 -- Receive Poll Demand */ 108 #define TULIP_REG_RXLIST 0x18 /* CSR3 -- Receive List Base Addr */ 109 #define TULIP_REG_TXLIST 0x20 /* CSR4 -- Transmit List Base Addr */ 110 #define TULIP_REG_STATUS 0x28 /* CSR5 -- Status */ 111 #define TULIP_REG_CMD 0x30 /* CSR6 -- Command */ 112 #define TULIP_REG_INTR 0x38 /* CSR7 -- Interrupt Control */ 113 #define TULIP_REG_MISSES 0x40 /* CSR8 -- Missed Frame Counter */ 114 #define TULIP_REG_ADDRROM 0x48 /* CSR9 -- ENET ROM Register */ 115 #define TULIP_REG_RSRVD 0x50 /* CSR10 -- Reserved */ 116 #define TULIP_REG_FULL_DUPLEX 0x58 /* CSR11 -- Full Duplex */ 117 #define TULIP_REG_SIA_STATUS 0x60 /* CSR12 -- SIA Status */ 118 #define TULIP_REG_SIA_CONN 0x68 /* CSR13 -- SIA Connectivity */ 119 #define TULIP_REG_SIA_TXRX 0x70 /* CSR14 -- SIA Tx Rx */ 120 #define TULIP_REG_SIA_GEN 0x78 /* CSR15 -- SIA General */ 121 122 /* 123 * CSR5 -- Status Register 124 * CSR7 -- Interrupt Control 125 */ 126 #define TULIP_STS_ERRORMASK 0x03800000L /* ( R) Error Bits (Valid when SYSERROR is set) */ 127 #define TULIP_STS_ERR_PARITY 0x00000000L /* 000 - Parity Error (Perform Reset) */ 128 #define TULIP_STS_ERR_MASTER 0x00800000L /* 001 - Master Abort */ 129 #define TULIP_STS_ERR_TARGET 0x01000000L /* 010 - Target Abort */ 130 #define TULIP_STS_ERR_SHIFT 23 131 #define TULIP_STS_TXSTATEMASK 0x00700000L /* ( R) Transmission Process State */ 132 #define TULIP_STS_TXS_RESET 0x00000000L /* 000 - Rset or transmit jabber expired */ 133 #define TULIP_STS_TXS_FETCH 0x00100000L /* 001 - Fetching transmit descriptor */ 134 #define TULIP_STS_TXS_WAITEND 0x00200000L /* 010 - Wait for end of transmission */ 135 #define TULIP_STS_TXS_READING 0x00300000L /* 011 - Read buffer and enqueue data */ 136 #define TULIP_STS_TXS_RSRVD 0x00400000L /* 100 - Reserved */ 137 #define TULIP_STS_TXS_SETUP 0x00500000L /* 101 - Setup Packet */ 138 #define TULIP_STS_TXS_SUSPEND 0x00600000L /* 110 - Transmit FIFO underflow or an 139 unavailable transmit descriptor */ 140 #define TULIP_STS_TXS_CLOSE 0x00700000L /* 111 - Close transmit descriptor */ 141 #define TULIP_STS_RXSTATEMASK 0x000E0000L /* ( R) Receive Process State*/ 142 #define TULIP_STS_RXS_STOPPED 0x00000000L /* 000 - Stopped */ 143 #define TULIP_STS_RXS_FETCH 0x00020000L /* 001 - Running -- Fetch receive descriptor */ 144 #define TULIP_STS_RXS_ENDCHECK 0x00040000L /* 010 - Running -- Check for end of receive 145 packet before prefetch of next descriptor */ 146 #define TULIP_STS_RXS_WAIT 0x00060000L /* 011 - Running -- Wait for receive packet */ 147 #define TULIP_STS_RXS_SUSPEND 0x00080000L /* 100 - Suspended -- As a result of 148 unavailable receive buffers */ 149 #define TULIP_STS_RXS_CLOSE 0x000A0000L /* 101 - Running -- Close receive descriptor */ 150 #define TULIP_STS_RXS_FLUSH 0x000C0000L /* 110 - Running -- Flush the current frame 151 from the receive FIFO as a result of 152 an unavailable receive buffer */ 153 #define TULIP_STS_RXS_DEQUEUE 0x000E0000L /* 111 - Running -- Dequeue the receive frame 154 from the receive FIFO into the receive 155 buffer. */ 156 #define TULIP_STS_NORMALINTR 0x00010000L /* (RW) Normal Interrupt */ 157 #define TULIP_STS_ABNRMLINTR 0x00008000L /* (RW) Abnormal Interrupt */ 158 #define TULIP_STS_SYSERROR 0x00002000L /* (RW) System Error */ 159 #define TULIP_STS_LINKFAIL 0x00001000L /* (RW) Link Failure (21040) */ 160 #define TULIP_STS_FULDPLXSHRT 0x00000800L /* (RW) Full Duplex Short Fram Rcvd (21040) */ 161 #define TULIP_STS_GPTIMEOUT 0x00000800L /* (RW) General Purpose Timeout (21140) */ 162 #define TULIP_STS_AUI 0x00000400L /* (RW) AUI/TP Switch (21040) */ 163 #define TULIP_STS_RXTIMEOUT 0x00000200L /* (RW) Receive Watchdog Timeout */ 164 #define TULIP_STS_RXSTOPPED 0x00000100L /* (RW) Receive Process Stopped */ 165 #define TULIP_STS_RXNOBUF 0x00000080L /* (RW) Receive Buffer Unavailable */ 166 #define TULIP_STS_RXINTR 0x00000040L /* (RW) Receive Interrupt */ 167 #define TULIP_STS_TXUNDERFLOW 0x00000020L /* (RW) Transmit Underflow */ 168 #define TULIP_STS_LINKPASS 0x00000010L /* (RW) LinkPass (21041) */ 169 #define TULIP_STS_TXBABBLE 0x00000008L /* (RW) Transmit Jabber Timeout */ 170 #define TULIP_STS_TXNOBUF 0x00000004L /* (RW) Transmit Buffer Unavailable */ 171 #define TULIP_STS_TXSTOPPED 0x00000002L /* (RW) Transmit Process Stopped */ 172 #define TULIP_STS_TXINTR 0x00000001L /* (RW) Transmit Interrupt */ 173 174 /* 175 * CSR6 -- Command (Operation Mode) Register 176 */ 177 #define TULIP_CMD_MUSTBEONE 0x02000000L /* (RW) Must Be One (21140) */ 178 #define TULIP_CMD_SCRAMBLER 0x01000000L /* (RW) Scrambler Mode (21140) */ 179 #define TULIP_CMD_PCSFUNCTION 0x00800000L /* (RW) PCS Function (21140) */ 180 #define TULIP_CMD_TXTHRSHLDCTL 0x00400000L /* (RW) Transmit Threshold Mode (21140) */ 181 #define TULIP_CMD_STOREFWD 0x00200000L /* (RW) Store and Forward (21140) */ 182 #define TULIP_CMD_NOHEARTBEAT 0x00080000L /* (RW) No Heartbeat (21140) */ 183 #define TULIP_CMD_PORTSELECT 0x00040000L /* (RW) Post Select (100Mb) (21140) */ 184 #define TULIP_CMD_ENHCAPTEFFCT 0x00040000L /* (RW) Enhanced Capture Effect (21041) */ 185 #define TULIP_CMD_CAPTREFFCT 0x00020000L /* (RW) Capture Effect (!802.3) */ 186 #define TULIP_CMD_BACKPRESSURE 0x00010000L /* (RW) Back Pressure (!802.3) (21040) */ 187 #define TULIP_CMD_THRESHOLDCTL 0x0000C000L /* (RW) Threshold Control */ 188 #define TULIP_CMD_THRSHLD72 0x00000000L /* 00 - 72 Bytes */ 189 #define TULIP_CMD_THRSHLD96 0x00004000L /* 01 - 96 Bytes */ 190 #define TULIP_CMD_THRSHLD128 0x00008000L /* 10 - 128 bytes */ 191 #define TULIP_CMD_THRSHLD160 0x0000C000L /* 11 - 160 Bytes */ 192 #define TULIP_CMD_TXRUN 0x00002000L /* (RW) Start/Stop Transmitter */ 193 #define TULIP_CMD_FORCECOLL 0x00001000L /* (RW) Force Collisions */ 194 #define TULIP_CMD_OPERMODE 0x00000C00L /* (RW) Operating Mode */ 195 #define TULIP_CMD_FULLDUPLEX 0x00000200L /* (RW) Full Duplex Mode */ 196 #define TULIP_CMD_FLAKYOSCDIS 0x00000100L /* (RW) Flakey Oscillator Disable */ 197 #define TULIP_CMD_ALLMULTI 0x00000080L /* (RW) Pass All Multicasts */ 198 #define TULIP_CMD_PROMISCUOUS 0x00000040L /* (RW) Promiscuous Mode */ 199 #define TULIP_CMD_BACKOFFCTR 0x00000020L /* (RW) Start/Stop Backoff Counter (!802.3) */ 200 #define TULIP_CMD_INVFILTER 0x00000010L /* (R ) Inverse Filtering */ 201 #define TULIP_CMD_PASSBADPKT 0x00000008L /* (RW) Pass Bad Frames */ 202 #define TULIP_CMD_HASHONLYFLTR 0x00000004L /* (R ) Hash Only Filtering */ 203 #define TULIP_CMD_RXRUN 0x00000002L /* (RW) Start/Stop Receive Filtering */ 204 #define TULIP_CMD_HASHPRFCTFLTR 0x00000001L /* (R ) Hash/Perfect Receive Filtering */ 205 206 #define TULIP_SIASTS_OTHERRXACTIVITY 0x00000200L 207 #define TULIP_SIASTS_RXACTIVITY 0x00000100L 208 #define TULIP_SIASTS_LINKFAIL 0x00000004L 209 #define TULIP_SIASTS_LINK100FAIL 0x00000002L 210 #define TULIP_SIACONN_RESET 0x00000000L 211 212 /* 213 * 21040 SIA definitions 214 */ 215 #define TULIP_21040_PROBE_10BASET_TIMEOUT 2500 216 #define TULIP_21040_PROBE_AUIBNC_TIMEOUT 300 217 #define TULIP_21040_PROBE_EXTSIA_TIMEOUT 300 218 219 #define TULIP_21040_SIACONN_10BASET 0x0000EF01L 220 #define TULIP_21040_SIATXRX_10BASET 0x0000FFFFL 221 #define TULIP_21040_SIAGEN_10BASET 0x00000000L 222 223 #define TULIP_21040_SIACONN_10BASET_FD 0x0000EF01L 224 #define TULIP_21040_SIATXRX_10BASET_FD 0x0000FFFDL 225 #define TULIP_21040_SIAGEN_10BASET_FD 0x00000000L 226 227 #define TULIP_21040_SIACONN_AUIBNC 0x0000EF09L 228 #define TULIP_21040_SIATXRX_AUIBNC 0x00000705L 229 #define TULIP_21040_SIAGEN_AUIBNC 0x00000006L 230 231 #define TULIP_21040_SIACONN_EXTSIA 0x00003041L 232 #define TULIP_21040_SIATXRX_EXTSIA 0x00000000L 233 #define TULIP_21040_SIAGEN_EXTSIA 0x00000006L 234 235 /* 236 * 21041 SIA definitions 237 */ 238 239 #define TULIP_21041_PROBE_10BASET_TIMEOUT 2500 240 #define TULIP_21041_PROBE_AUIBNC_TIMEOUT 300 241 242 #define TULIP_21041_SIACONN_10BASET 0x0000EF01L 243 #define TULIP_21041_SIATXRX_10BASET 0x0000FF3FL 244 #define TULIP_21041_SIAGEN_10BASET 0x00000000L 245 246 #define TULIP_21041P2_SIACONN_10BASET 0x0000EF01L 247 #define TULIP_21041P2_SIATXRX_10BASET 0x0000FFFFL 248 #define TULIP_21041P2_SIAGEN_10BASET 0x00000000L 249 250 #define TULIP_21041_SIACONN_10BASET_FD 0x0000EF01L 251 #define TULIP_21041_SIATXRX_10BASET_FD 0x0000FF3DL 252 #define TULIP_21041_SIAGEN_10BASET_FD 0x00000000L 253 254 #define TULIP_21041P2_SIACONN_10BASET_FD 0x0000EF01L 255 #define TULIP_21041P2_SIATXRX_10BASET_FD 0x0000FFFFL 256 #define TULIP_21041P2_SIAGEN_10BASET_FD 0x00000000L 257 258 #define TULIP_21041_SIACONN_AUI 0x0000EF09L 259 #define TULIP_21041_SIATXRX_AUI 0x0000F73DL 260 #define TULIP_21041_SIAGEN_AUI 0x0000000EL 261 262 #define TULIP_21041P2_SIACONN_AUI 0x0000EF09L 263 #define TULIP_21041P2_SIATXRX_AUI 0x0000F7FDL 264 #define TULIP_21041P2_SIAGEN_AUI 0x0000000EL 265 266 #define TULIP_21041_SIACONN_BNC 0x0000EF09L 267 #define TULIP_21041_SIATXRX_BNC 0x0000F73DL 268 #define TULIP_21041_SIAGEN_BNC 0x00000006L 269 270 #define TULIP_21041P2_SIACONN_BNC 0x0000EF09L 271 #define TULIP_21041P2_SIATXRX_BNC 0x0000F7FDL 272 #define TULIP_21041P2_SIAGEN_BNC 0x00000006L 273 274 /* 275 * 21142 SIA definitions 276 */ 277 278 #define TULIP_21142_PROBE_10BASET_TIMEOUT 2500 279 #define TULIP_21142_PROBE_AUIBNC_TIMEOUT 300 280 281 #define TULIP_21142_SIACONN_10BASET 0x00000001L 282 #define TULIP_21142_SIATXRX_10BASET 0x00007F3FL 283 #define TULIP_21142_SIAGEN_10BASET 0x00000008L 284 285 #define TULIP_21142_SIACONN_10BASET_FD 0x00000001L 286 #define TULIP_21142_SIATXRX_10BASET_FD 0x00007F3DL 287 #define TULIP_21142_SIAGEN_10BASET_FD 0x00000008L 288 289 #define TULIP_21142_SIACONN_AUI 0x00000009L 290 #define TULIP_21142_SIATXRX_AUI 0x00000705L 291 #define TULIP_21142_SIAGEN_AUI 0x0000000EL 292 293 #define TULIP_21142_SIACONN_BNC 0x00000009L 294 #define TULIP_21142_SIATXRX_BNC 0x00000705L 295 #define TULIP_21142_SIAGEN_BNC 0x00000006L 296 297 298 299 300 #define TULIP_WATCHDOG_TXDISABLE 0x00000001L 301 #define TULIP_WATCHDOG_RXDISABLE 0x00000010L 302 303 #define TULIP_BUSMODE_SWRESET 0x00000001L 304 #define TULIP_BUSMODE_DESCSKIPLEN_MASK 0x0000007CL 305 #define TULIP_BUSMODE_BIGENDIAN 0x00000080L 306 #define TULIP_BUSMODE_BURSTLEN_MASK 0x00003F00L 307 #define TULIP_BUSMODE_BURSTLEN_DEFAULT 0x00000000L 308 #define TULIP_BUSMODE_BURSTLEN_1LW 0x00000100L 309 #define TULIP_BUSMODE_BURSTLEN_2LW 0x00000200L 310 #define TULIP_BUSMODE_BURSTLEN_4LW 0x00000400L 311 #define TULIP_BUSMODE_BURSTLEN_8LW 0x00000800L 312 #define TULIP_BUSMODE_BURSTLEN_16LW 0x00001000L 313 #define TULIP_BUSMODE_BURSTLEN_32LW 0x00002000L 314 #define TULIP_BUSMODE_CACHE_NOALIGN 0x00000000L 315 #define TULIP_BUSMODE_CACHE_ALIGN8 0x00004000L 316 #define TULIP_BUSMODE_CACHE_ALIGN16 0x00008000L 317 #define TULIP_BUSMODE_CACHE_ALIGN32 0x0000C000L 318 #define TULIP_BUSMODE_TXPOLL_NEVER 0x00000000L 319 #define TULIP_BUSMODE_TXPOLL_200000ns 0x00020000L 320 #define TULIP_BUSMODE_TXPOLL_800000ns 0x00040000L 321 #define TULIP_BUSMODE_TXPOLL_1600000ns 0x00060000L 322 #define TULIP_BUSMODE_TXPOLL_12800ns 0x00080000L /* 21041 only */ 323 #define TULIP_BUSMODE_TXPOLL_25600ns 0x000A0000L /* 21041 only */ 324 #define TULIP_BUSMODE_TXPOLL_51200ns 0x000C0000L /* 21041 only */ 325 #define TULIP_BUSMODE_TXPOLL_102400ns 0x000E0000L /* 21041 only */ 326 #define TULIP_BUSMODE_DESC_BIGENDIAN 0x00100000L /* 21041 only */ 327 #define TULIP_BUSMODE_READMULTIPLE 0x00200000L /* */ 328 329 #define TULIP_REG_CFDA 0x40 330 #define TULIP_CFDA_SLEEP 0x80000000L 331 #define TULIP_CFDA_SNOOZE 0x40000000L 332 333 #define TULIP_GP_PINSET 0x00000100L 334 /* 335 * These are the definitions used for the DEC 21140 336 * evaluation board. 337 */ 338 #define TULIP_GP_EB_PINS 0x0000001F /* General Purpose Pin directions */ 339 #define TULIP_GP_EB_OK10 0x00000080 /* 10 Mb/sec Signal Detect gep<7> */ 340 #define TULIP_GP_EB_OK100 0x00000040 /* 100 Mb/sec Signal Detect gep<6> */ 341 #define TULIP_GP_EB_INIT 0x0000000B /* No loopback --- point-to-point */ 342 343 /* 344 * These are the definitions used for the SMC9332 (21140) board. 345 */ 346 #define TULIP_GP_SMC_9332_PINS 0x0000003F /* General Purpose Pin directions */ 347 #define TULIP_GP_SMC_9332_OK10 0x00000080 /* 10 Mb/sec Signal Detect gep<7> */ 348 #define TULIP_GP_SMC_9332_OK100 0x00000040 /* 100 Mb/sec Signal Detect gep<6> */ 349 #define TULIP_GP_SMC_9332_INIT 0x00000009 /* No loopback --- point-to-point */ 350 351 #define TULIP_OUI_SMC_0 0x00 352 #define TULIP_OUI_SMC_1 0x00 353 #define TULIP_OUI_SMC_2 0xC0 354 355 /* 356 * There are the definitions used for the DEC DE500 357 * 10/100 family of boards 358 */ 359 #define TULIP_GP_DE500_PINS 0x0000001FL 360 #define TULIP_GP_DE500_LINK_PASS 0x00000080L 361 #define TULIP_GP_DE500_SYM_LINK 0x00000040L 362 #define TULIP_GP_DE500_SIGNAL_DETECT 0x00000020L 363 #define TULIP_GP_DE500_PHY_RESET 0x00000010L 364 #define TULIP_GP_DE500_HALFDUPLEX 0x00000008L 365 #define TULIP_GP_DE500_PHY_LOOPBACK 0x00000004L 366 #define TULIP_GP_DE500_FORCE_LED 0x00000002L 367 #define TULIP_GP_DE500_FORCE_100 0x00000001L 368 369 /* 370 * These are the definitions used for the Cogent EM100 371 * 21140 board. 372 */ 373 #define TULIP_GP_EM100_PINS 0x0000003F /* General Purpose Pin directions */ 374 #define TULIP_GP_EM100_INIT 0x00000009 /* No loopback --- point-to-point */ 375 #define TULIP_OUI_COGENT_0 0x00 376 #define TULIP_OUI_COGENT_1 0x00 377 #define TULIP_OUI_COGENT_2 0x92 378 #define TULIP_COGENT_EM100TX_ID 0x12 379 #define TULIP_COGENT_EM100FX_ID 0x15 380 381 382 /* 383 * These are the definitions used for the Znyx ZX342 384 * 10/100 board 385 */ 386 #define TULIP_OUI_ZNYX_0 0x00 387 #define TULIP_OUI_ZNYX_1 0xC0 388 #define TULIP_OUI_ZNYX_2 0x95 389 390 #define TULIP_ZNYX_ID_ZX312 0x0602 391 #define TULIP_ZNYX_ID_ZX312T 0x0622 392 #define TULIP_ZNYX_ID_ZX314_INTA 0x0701 393 #define TULIP_ZNYX_ID_ZX314 0x0711 394 #define TULIP_ZNYX_ID_ZX315_INTA 0x0801 395 #define TULIP_ZNYX_ID_ZX315 0x0811 396 #define TULIP_ZNYX_ID_ZX342 0x0901 397 #define TULIP_ZNYX_ID_ZX342B 0x0921 398 #define TULIP_ZNYX_ID_ZX342_X3 0x0902 399 #define TULIP_ZNYX_ID_ZX342_X4 0x0903 400 #define TULIP_ZNYX_ID_ZX344 0x0A01 401 #define TULIP_ZNYX_ID_ZX351 0x0B01 402 #define TULIP_ZNYX_ID_ZX345 0x0C01 403 #define TULIP_ZNYX_ID_ZX311 0x0D01 404 #define TULIP_ZNYX_ID_ZX346 0x0E01 405 406 #define TULIP_GP_ZX34X_PINS 0x0000001F /* General Purpose Pin directions */ 407 #define TULIP_GP_ZX344_PINS 0x0000000B /* General Purpose Pin directions */ 408 #define TULIP_GP_ZX345_PINS 0x00000003 /* General Purpose Pin directions */ 409 #define TULIP_GP_ZX346_PINS 0x00000043 /* General Purpose Pin directions */ 410 #define TULIP_GP_ZX34X_LNKFAIL 0x00000080 /* 10Mb/s Link Failure */ 411 #define TULIP_GP_ZX34X_SYMDET 0x00000040 /* 100Mb/s Symbol Detect */ 412 #define TULIP_GP_ZX345_PHYACT 0x00000040 /* PHY Activity */ 413 #define TULIP_GP_ZX34X_SIGDET 0x00000020 /* 100Mb/s Signal Detect */ 414 #define TULIP_GP_ZX346_AUTONEG_ENABLED 0x00000020 /* 802.3u autoneg enabled */ 415 #define TULIP_GP_ZX342_COLENA 0x00000008 /* 10t Ext LB */ 416 #define TULIP_GP_ZX344_ROTINT 0x00000008 /* PPB IRQ rotation */ 417 #define TULIP_GP_ZX345_SPEED10 0x00000008 /* 10Mb speed detect */ 418 #define TULIP_GP_ZX346_SPEED100 0x00000008 /* 100Mb speed detect */ 419 #define TULIP_GP_ZX34X_NCOLENA 0x00000004 /* 10t Int LB */ 420 #define TULIP_GP_ZX34X_RXMATCH 0x00000004 /* RX Match */ 421 #define TULIP_GP_ZX346_FULLDUPLEX 0x00000004 /* Full Duplex Sensed */ 422 #define TULIP_GP_ZX34X_LB102 0x00000002 /* 100tx twister LB */ 423 #define TULIP_GP_ZX34X_NLB101 0x00000001 /* PDT/PDR LB */ 424 #define TULIP_GP_ZX34X_INIT 0x00000009 425 426 /* 427 * Compex's OUI. We need to twiddle a bit on their 21041 card. 428 */ 429 #define TULIP_OUI_COMPEX_0 0x00 430 #define TULIP_OUI_COMPEX_1 0x80 431 #define TULIP_OUI_COMPEX_2 0x48 432 #define TULIP_21041_COMPEX_XREGDATA 1 433 434 /* 435 * Asante's OUI and stuff... 436 */ 437 #define TULIP_OUI_ASANTE_0 0x00 438 #define TULIP_OUI_ASANTE_1 0x00 439 #define TULIP_OUI_ASANTE_2 0x94 440 #define TULIP_GP_ASANTE_PINS 0x000000bf /* GP pin config */ 441 #define TULIP_GP_ASANTE_PHYRESET 0x00000008 /* Reset PHY */ 442 443 /* 444 * ACCTON EN1207 specialties 445 */ 446 447 #define TULIP_OUI_EN1207_0 0x00 448 #define TULIP_OUI_EN1207_1 0x00 449 #define TULIP_OUI_EN1207_2 0xE8 450 451 #define TULIP_CSR8_EN1207 0x08 452 #define TULIP_CSR9_EN1207 0x00 453 #define TULIP_CSR10_EN1207 0x03 454 #define TULIP_CSR11_EN1207 0x1F 455 456 #define TULIP_GP_EN1207_BNC_INIT 0x0000011B 457 #define TULIP_GP_EN1207_UTP_INIT 0x9E00000B 458 #define TULIP_GP_EN1207_100_INIT 0x6D00031B 459 460 /* 461 * SROM definitions for the 21140 and 21041. 462 */ 463 #define SROMXREG 0x0400 464 #define SROMSEL 0x0800 465 #define SROMRD 0x4000 466 #define SROMWR 0x2000 467 #define SROMDIN 0x0008 468 #define SROMDOUT 0x0004 469 #define SROMDOUTON 0x0004 470 #define SROMDOUTOFF 0x0004 471 #define SROMCLKON 0x0002 472 #define SROMCLKOFF 0x0002 473 #define SROMCSON 0x0001 474 #define SROMCSOFF 0x0001 475 #define SROMCS 0x0001 476 477 #define SROMCMD_MODE 4 478 #define SROMCMD_WR 5 479 #define SROMCMD_RD 6 480 481 #define SROM_BITWIDTH 6 482 483 /* 484 * MII Definitions for the 21041 and 21140/21140A/21142 485 */ 486 #define MII_PREAMBLE (~0) 487 #define MII_TEST 0xAAAAAAAA 488 #define MII_RDCMD 0xF6 /* 1111.0110 */ 489 #define MII_WRCMD 0xF5 /* 1111.0101 */ 490 #define MII_DIN 0x00080000 491 #define MII_RD 0x00040000 492 #define MII_WR 0x00000000 493 #define MII_DOUT 0x00020000 494 #define MII_CLK 0x00010000 495 #define MII_CLKON MII_CLK 496 #define MII_CLKOFF MII_CLK 497 498 #define PHYREG_CONTROL 0 499 #define PHYREG_STATUS 1 500 #define PHYREG_IDLOW 2 501 #define PHYREG_IDHIGH 3 502 #define PHYREG_AUTONEG_ADVERTISEMENT 4 503 #define PHYREG_AUTONEG_ABILITIES 5 504 #define PHYREG_AUTONEG_EXPANSION 6 505 #define PHYREG_AUTONEG_NEXTPAGE 7 506 507 #define PHYSTS_100BASET4 0x8000 508 #define PHYSTS_100BASETX_FD 0x4000 509 #define PHYSTS_100BASETX 0x2000 510 #define PHYSTS_10BASET_FD 0x1000 511 #define PHYSTS_10BASET 0x0800 512 #define PHYSTS_AUTONEG_DONE 0x0020 513 #define PHYSTS_REMOTE_FAULT 0x0010 514 #define PHYSTS_CAN_AUTONEG 0x0008 515 #define PHYSTS_LINK_UP 0x0004 516 #define PHYSTS_JABBER_DETECT 0x0002 517 #define PHYSTS_EXTENDED_REGS 0x0001 518 519 #define PHYCTL_RESET 0x8000 520 #define PHYCTL_SELECT_100MB 0x2000 521 #define PHYCTL_AUTONEG_ENABLE 0x1000 522 #define PHYCTL_ISOLATE 0x0400 523 #define PHYCTL_AUTONEG_RESTART 0x0200 524 #define PHYCTL_FULL_DUPLEX 0x0100 525 526 /* 527 * Definitions for the DE425. 528 */ 529 #define DE425_CFID 0x08 /* Configuration Id */ 530 #define DE425_CFCS 0x0C /* Configuration Command-Status */ 531 #define DE425_CFRV 0x18 /* Configuration Revision */ 532 #define DE425_CFLT 0x1C /* Configuration Latency Timer */ 533 #define DE425_CBIO 0x28 /* Configuration Base IO Address */ 534 #define DE425_CFDA 0x2C /* Configuration Driver Area */ 535 #define DE425_ENETROM_OFFSET 0xC90 /* Offset in I/O space for ENETROM */ 536 #define DE425_CFG0 0xC88 /* IRQ register */ 537 #define DE425_EISAID 0x10a34250 /* EISA device id */ 538 #define DE425_EISA_IOSIZE 0x100 539 540 #define DEC_VENDORID 0x1011 541 #define CHIPID_21040 0x0002 542 #define CHIPID_21140 0x0009 543 #define CHIPID_21041 0x0014 544 #define CHIPID_21142 0x0019 545 #define PCI_VENDORID(x) ((x) & 0xFFFF) 546 #define PCI_CHIPID(x) (((x) >> 16) & 0xFFFF) 547 548 /* 549 * Generic SROM Format 550 * 551 * 552 */ 553 554 typedef struct { 555 u_int8_t sh_idbuf[18]; 556 u_int8_t sh_version; 557 u_int8_t sh_adapter_count; 558 u_int8_t sh_ieee802_address[6]; 559 } tulip_srom_header_t; 560 561 typedef struct { 562 u_int8_t sai_device; 563 u_int8_t sai_leaf_offset_lowbyte; 564 u_int8_t sai_leaf_offset_highbyte; 565 } tulip_srom_adapter_info_t; 566 567 typedef enum { 568 TULIP_SROM_CONNTYPE_10BASET =0x0000, 569 TULIP_SROM_CONNTYPE_BNC =0x0001, 570 TULIP_SROM_CONNTYPE_AUI =0x0002, 571 TULIP_SROM_CONNTYPE_100BASETX =0x0003, 572 TULIP_SROM_CONNTYPE_100BASET4 =0x0006, 573 TULIP_SROM_CONNTYPE_100BASEFX =0x0007, 574 TULIP_SROM_CONNTYPE_MII_10BASET =0x0009, 575 TULIP_SROM_CONNTYPE_MII_100BASETX =0x000D, 576 TULIP_SROM_CONNTYPE_MII_100BASET4 =0x000F, 577 TULIP_SROM_CONNTYPE_MII_100BASEFX =0x0010, 578 TULIP_SROM_CONNTYPE_10BASET_NWAY =0x0100, 579 TULIP_SROM_CONNTYPE_10BASET_FD =0x0204, 580 TULIP_SROM_CONNTYPE_MII_10BASET_FD =0x020A, 581 TULIP_SROM_CONNTYPE_100BASETX_FD =0x020E, 582 TULIP_SROM_CONNTYPE_MII_100BASETX_FD =0x0211, 583 TULIP_SROM_CONNTYPE_10BASET_NOLINKPASS =0x0400, 584 TULIP_SROM_CONNTYPE_AUTOSENSE =0x0800, 585 TULIP_SROM_CONNTYPE_AUTOSENSE_POWERUP =0x8800, 586 TULIP_SROM_CONNTYPE_AUTOSENSE_NWAY =0x9000, 587 TULIP_SROM_CONNTYPE_NOT_USED =0xFFFF 588 } tulip_srom_connection_t; 589 590 typedef enum { 591 TULIP_SROM_MEDIA_10BASET =0x0000, 592 TULIP_SROM_MEDIA_BNC =0x0001, 593 TULIP_SROM_MEDIA_AUI =0x0002, 594 TULIP_SROM_MEDIA_100BASETX =0x0003, 595 TULIP_SROM_MEDIA_10BASET_FD =0x0004, 596 TULIP_SROM_MEDIA_100BASETX_FD =0x0005, 597 TULIP_SROM_MEDIA_100BASET4 =0x0006, 598 TULIP_SROM_MEDIA_100BASEFX =0x0007, 599 TULIP_SROM_MEDIA_100BASEFX_FD =0x0008 600 } tulip_srom_media_t; 601 602 #define TULIP_SROM_21041_EXTENDED 0x40 603 604 #define TULIP_SROM_2114X_NOINDICATOR 0x8000 605 #define TULIP_SROM_2114X_DEFAULT 0x4000 606 #define TULIP_SROM_2114X_POLARITY 0x0080 607 #define TULIP_SROM_2114X_CMDBITS(n) (((n) & 0x0071) << 18) 608 #define TULIP_SROM_2114X_BITPOS(b) (1 << (((b) & 0x0E) >> 1)) 609 610 611 612 #endif /* !defined(_DC21040_H) */ 613