1 /* $OpenBSD: dwqevar.h,v 1.8 2023/10/10 07:11:50 stsp Exp $ */ 2 /* 3 * Copyright (c) 2008, 2019 Mark Kettenis <kettenis@openbsd.org> 4 * Copyright (c) 2017, 2022 Patrick Wildt <patrick@blueri.se> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 enum dwqe_phy_mode { 20 DWQE_PHY_MODE_UNKNOWN, 21 DWQE_PHY_MODE_RGMII, 22 DWQE_PHY_MODE_RGMII_ID, 23 DWQE_PHY_MODE_RGMII_TXID, 24 DWQE_PHY_MODE_RGMII_RXID, 25 }; 26 27 struct dwqe_buf { 28 bus_dmamap_t tb_map; 29 struct mbuf *tb_m; 30 }; 31 32 #define DWQE_NTXDESC 256 33 #define DWQE_NTXSEGS 16 34 35 #define DWQE_NRXDESC 256 36 37 struct dwqe_dmamem { 38 bus_dmamap_t tdm_map; 39 bus_dma_segment_t tdm_seg; 40 size_t tdm_size; 41 caddr_t tdm_kva; 42 }; 43 #define DWQE_DMA_MAP(_tdm) ((_tdm)->tdm_map) 44 #define DWQE_DMA_LEN(_tdm) ((_tdm)->tdm_size) 45 #define DWQE_DMA_DVA(_tdm) ((_tdm)->tdm_map->dm_segs[0].ds_addr) 46 #define DWQE_DMA_KVA(_tdm) ((void *)(_tdm)->tdm_kva) 47 48 struct dwqe_softc { 49 struct device sc_dev; 50 int sc_node; 51 bus_space_tag_t sc_iot; 52 bus_space_handle_t sc_ioh; 53 bus_dma_tag_t sc_dmat; 54 void *sc_ih; 55 56 struct arpcom sc_ac; 57 #define sc_lladdr sc_ac.ac_enaddr 58 struct mii_data sc_mii; 59 #define sc_media sc_mii.mii_media 60 int sc_link; 61 int sc_phyloc; 62 enum dwqe_phy_mode sc_phy_mode; 63 struct timeout sc_phy_tick; 64 int sc_fixed_link; 65 66 struct dwqe_dmamem *sc_txring; 67 struct dwqe_buf *sc_txbuf; 68 struct dwqe_desc *sc_txdesc; 69 int sc_tx_prod; 70 int sc_tx_cons; 71 72 struct dwqe_dmamem *sc_rxring; 73 struct dwqe_buf *sc_rxbuf; 74 struct dwqe_desc *sc_rxdesc; 75 int sc_rx_prod; 76 struct if_rxring sc_rx_ring; 77 int sc_rx_cons; 78 79 struct timeout sc_rxto; 80 struct task sc_statchg_task; 81 82 uint32_t sc_clk; 83 uint32_t sc_clkrate; 84 85 bus_size_t sc_clk_sel; 86 uint32_t sc_clk_sel_125; 87 uint32_t sc_clk_sel_25; 88 uint32_t sc_clk_sel_2_5; 89 90 int sc_hw_feature[4]; 91 92 int sc_force_thresh_dma_mode; 93 int sc_fixed_burst; 94 int sc_mixed_burst; 95 int sc_aal; 96 int sc_8xpbl; 97 int sc_pbl; 98 int sc_txpbl; 99 int sc_rxpbl; 100 int sc_axi_config; 101 int sc_lpi_en; 102 int sc_xit_frm; 103 int sc_wr_osr_lmt; 104 int sc_rd_osr_lmt; 105 106 uint32_t sc_blen[7]; 107 }; 108 109 #define DEVNAME(_s) ((_s)->sc_dev.dv_xname) 110 111 int dwqe_attach(struct dwqe_softc *); 112 void dwqe_reset(struct dwqe_softc *); 113 int dwqe_intr(void *); 114 uint32_t dwqe_read(struct dwqe_softc *, bus_addr_t); 115 void dwqe_write(struct dwqe_softc *, bus_addr_t, uint32_t); 116 void dwqe_lladdr_read(struct dwqe_softc *, uint8_t *); 117 void dwqe_lladdr_write(struct dwqe_softc *); 118 void dwqe_mii_statchg(struct device *); 119