1 /* $OpenBSD: elink3reg.h,v 1.16 2015/02/28 11:25:49 miod Exp $ */ 2 /* $NetBSD: elink3reg.h,v 1.13 1997/04/27 09:42:34 veego Exp $ */ 3 4 /* 5 * Copyright (c) 1995 Herb Peyerl <hpeyerl@beer.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Herb Peyerl. 19 * 4. The name of Herb Peyerl may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * These define the EEPROM data structure. They are used in the probe 37 * function to verify the existence of the adapter after having sent 38 * the ID_Sequence. 39 * 40 * There are others but only the ones we use are defined here. 41 */ 42 #define EEPROM_NODE_ADDR_0 0x0 /* Word */ 43 #define EEPROM_NODE_ADDR_1 0x1 /* Word */ 44 #define EEPROM_NODE_ADDR_2 0x2 /* Word */ 45 #define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ 46 #define EEPROM_MFG_ID 0x7 /* 0x6d50 */ 47 #define EEPROM_ADDR_CFG 0x8 /* Base addr */ 48 #define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ 49 #define EEPROM_OEM_ADDR0 0xa 50 #define EEPROM_PNP 0x13 /* PNP mode and such? */ 51 52 /* 53 * These are the registers for the 3Com 3c509 and their bit patterns when 54 * applicable. They have been taken out of the "EtherLink III Parallel 55 * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual 56 * from 3com. 57 */ 58 #define EP_COMMAND 0x0e /* Write. BASE+0x0e is always a command reg. */ 59 #define EP_STATUS 0x0e /* Read. BASE+0x0e is always status reg. */ 60 #define EP_WINDOW 0x0f /* Read. BASE+0x0f is always window reg. */ 61 62 /* 63 * Window 0 registers. Setup. 64 */ 65 /* Write */ 66 #define EP_W0_EEPROM_DATA 0x0c 67 #define EP_W0_EEPROM_COMMAND 0x0a 68 #define EP_W0_RESOURCE_CFG 0x08 69 #define EP_W0_ADDRESS_CFG 0x06 70 #define EP_W0_CONFIG_CTRL 0x04 71 /* Read */ 72 #define EP_W0_PRODUCT_ID 0x02 73 #define EP_W0_MFG_ID 0x00 74 75 /* 76 * Window 1 registers. Operating Set. 77 */ 78 /* Write */ 79 #define EP_W1_TX_PIO_WR_2 0x02 80 #define EP_W1_TX_PIO_WR_1 0x00 81 /* Read */ 82 #define EP_W1_FREE_TX 0x0c 83 #define EP_W1_TX_STATUS 0x0b /* byte */ 84 #define EP_W1_TIMER 0x0a /* byte */ 85 #define EP_W1_RX_STATUS 0x08 86 #define EP_W1_RX_PIO_RD_2 0x02 87 #define EP_W1_RX_PIO_RD_1 0x00 88 89 /* Special registers used by the RoadRunner. These are used to program 90 * a FIFO buffer to reduce the PCMCIA->PCI bridge latency during PIO. 91 */ 92 #define EP_W1_RUNNER_RDCTL 0x16 93 #define EP_W1_RUNNER_WRCTL 0x1c 94 95 /* 96 * Window 2 registers. Station Address Setup/Read 97 */ 98 /* Read/Write */ 99 #define EP_W2_RECVMASK_0 0x06 100 #define EP_W2_ADDR_5 0x05 101 #define EP_W2_ADDR_4 0x04 102 #define EP_W2_ADDR_3 0x03 103 #define EP_W2_ADDR_2 0x02 104 #define EP_W2_ADDR_1 0x01 105 #define EP_W2_ADDR_0 0x00 106 107 /* 108 * Window 3 registers. FIFO Management. 109 */ 110 /* Read */ 111 #define EP_W3_FREE_TX 0x0c 112 #define EP_W3_FREE_RX 0x0a 113 /* Read/Write, at least on busmastering cards. */ 114 #define EP_W3_INTERNAL_CONFIG 0x00 /* 32 bits */ 115 #define EP_W3_OTHER_INT 0x04 /* 8 bits */ 116 #define EP_W3_PIO_RESERVED 0x05 /* 8 bits */ 117 #define EP_W3_MAC_CONTROL 0x06 /* 16 bits */ 118 #define EP_W3_RESET_OPTIONS 0x08 /* 16 bits */ 119 120 /* 121 * Window 4 registers. Diagnostics. 122 */ 123 /* Read/Write */ 124 #define EP_W4_MEDIA_TYPE 0x0a 125 #define EP_W4_CTRLR_STATUS 0x08 126 #define EP_W4_NET_DIAG 0x06 127 #define EP_W4_FIFO_DIAG 0x04 128 #define EP_W4_HOST_DIAG 0x02 129 #define EP_W4_TX_DIAG 0x00 130 131 /* 132 * Window 4 offset 8 is the PHY Management register on the 133 * 3c90x. 134 */ 135 #define EP_W4_BOOM_PHYSMGMT 0x08 136 #define PHYSMGMT_CLK 0x0001 137 #define PHYSMGMT_DATA 0x0002 138 #define PHYSMGMT_DIR 0x0004 139 140 /* 141 * Window 5 Registers. Results and Internal status. 142 */ 143 /* Read */ 144 #define EP_W5_READ_0_MASK 0x0c 145 #define EP_W5_INTR_MASK 0x0a 146 #define EP_W5_RX_FILTER 0x08 147 #define EP_W5_RX_EARLY_THRESH 0x06 148 #define EP_W5_TX_AVAIL_THRESH 0x02 149 #define EP_W5_TX_START_THRESH 0x00 150 151 /* 152 * Window 6 registers. Statistics. 153 */ 154 /* Read/Write */ 155 #define TX_TOTAL_OK 0x0c 156 #define RX_TOTAL_OK 0x0a 157 #define TX_DEFERRALS 0x08 158 #define RX_FRAMES_OK 0x07 159 #define TX_FRAMES_OK 0x06 160 #define RX_OVERRUNS 0x05 161 #define TX_COLLISIONS 0x04 162 #define TX_AFTER_1_COLLISION 0x03 163 #define TX_AFTER_X_COLLISIONS 0x02 164 #define TX_NO_SQE 0x01 165 #define TX_CD_LOST 0x00 166 167 /* 168 * Window 7 registers. 169 * Address and length for a single bus-master DMA transfer. 170 */ 171 #define EP_W7_MASTER_ADDDRES 0x00 172 #define EP_W7_RX_ERROR 0x04 173 #define EP_W7_MASTER_LEN 0x06 174 #define EP_W7_RX_STATUS 0x08 175 #define EP_W7_TIMER 0x0a 176 #define EP_W7_TX_STATUS 0x0b 177 #define EP_W7_MASTER_STATUS 0x0c 178 179 /* 180 * Register definitions. 181 */ 182 183 /* 184 * Command register. All windows. 185 * 186 * 16 bit register. 187 * 15-11: 5-bit code for command to be executed. 188 * 10-0: 11-bit arg if any. For commands with no args; 189 * this can be set to anything. 190 */ 191 #define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms after issuing */ 192 #define WINDOW_SELECT (u_short) (0x1<<11) 193 #define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to determine 194 whether this is needed. If so; 195 wait 800 uSec before using trans- 196 ceiver. */ 197 #define RX_DISABLE (u_short) (0x3<<11) /* state disabled on power-up */ 198 #define RX_ENABLE (u_short) (0x4<<11) 199 #define RX_RESET (u_short) (0x5<<11) 200 #define RX_DISCARD_TOP_PACK (u_short) (0x8<<11) 201 #define TX_ENABLE (u_short) (0x9<<11) 202 #define TX_DISABLE (u_short) (0xa<<11) 203 #define TX_RESET (u_short) (0xb<<11) 204 #define REQ_INTR (u_short) (0xc<<11) 205 206 /* 207 * The following C_* acknowledge the various interrupts. 208 * Some of them don't do anything. See the manual. 209 */ 210 #define ACK_INTR (u_short) (0x6800) 211 # define C_INTR_LATCH (u_short) (ACK_INTR|0x01) 212 # define C_CARD_FAILURE (u_short) (ACK_INTR|0x02) 213 # define C_TX_COMPLETE (u_short) (ACK_INTR|0x04) 214 # define C_TX_AVAIL (u_short) (ACK_INTR|0x08) 215 # define C_RX_COMPLETE (u_short) (ACK_INTR|0x10) 216 # define C_RX_EARLY (u_short) (ACK_INTR|0x20) 217 # define C_INT_RQD (u_short) (ACK_INTR|0x40) 218 # define C_UPD_STATS (u_short) (ACK_INTR|0x80) 219 220 #define SET_INTR_MASK (u_short) (0x0e<<11) 221 222 /* busmastering-cards only? */ 223 #define STATUS_ENABLE (u_short) (0x0f<<11) 224 225 #define SET_RD_0_MASK (u_short) (0x0f<<11) 226 227 #define SET_RX_FILTER (u_short) (0x10<<11) 228 # define FIL_INDIVIDUAL (u_short) (0x01) 229 # define FIL_MULTICAST (u_short) (0x02) 230 # define FIL_BRDCST (u_short) (0x04) 231 # define FIL_PROMISC (u_short) (0x08) 232 233 #define SET_RX_EARLY_THRESH (u_short) (0x11<<11) 234 #define SET_TX_AVAIL_THRESH (u_short) (0x12<<11) 235 #define SET_TX_START_THRESH (u_short) (0x13<<11) 236 #define START_DMA (u_short) (0x14<<11) /* busmaster-only */ 237 # define START_DMA_TX (START_DMA | 0x0)) /* busmaster-only */ 238 # define START_DMA_RX (START_DMA | 0x1) /* busmaster-only */ 239 #define STATS_ENABLE (u_short) (0x15<<11) 240 #define STATS_DISABLE (u_short) (0x16<<11) 241 #define STOP_TRANSCEIVER (u_short) (0x17<<11) 242 243 /* Only on adapters that support power management: */ 244 #define POWERUP (u_short) (0x1b<<11) 245 #define POWERDOWN (u_short) (0x1c<<11) 246 #define POWERAUTO (u_short) (0x1d<<11) 247 248 /* 249 * Command parameter that disables threshold interrupts 250 * PIO (3c509) cards use 2044. The fifo word-oriented and 2044--2047 work. 251 * "busmastering" cards need 8188. 252 * The implicit two-bit upshift done by busmastering cards means 253 * a value of 2047 disables threshold interrupts on both. 254 */ 255 #define EP_THRESH_DISABLE 2047 256 257 /* 258 * Status register. All windows. 259 * 260 * 15-13: Window number(0-7). 261 * 12: Command_in_progress. 262 * 11: reserved / DMA in progress on busmaster cards. 263 * 10: reserved. 264 * 9: reserved. 265 * 8: reserved / DMA done on busmaster cards. 266 * 7: Update Statistics. 267 * 6: Interrupt Requested. 268 * 5: RX Early. 269 * 4: RX Complete. 270 * 3: TX Available. 271 * 2: TX Complete. 272 * 1: Adapter Failure. 273 * 0: Interrupt Latch. 274 */ 275 #define S_INTR_LATCH (u_short) (0x0001) 276 #define S_CARD_FAILURE (u_short) (0x0002) 277 #define S_TX_COMPLETE (u_short) (0x0004) 278 #define S_TX_AVAIL (u_short) (0x0008) 279 #define S_RX_COMPLETE (u_short) (0x0010) 280 #define S_RX_EARLY (u_short) (0x0020) 281 #define S_INT_RQD (u_short) (0x0040) 282 #define S_UPD_STATS (u_short) (0x0080) 283 #define S_DMA_DONE (u_short) (0x0100) /* DMA cards only */ 284 #define S_DOWN_COMPLETE (u_short) (0x0200) /* DMA cards only */ 285 #define S_UP_COMPLETE (u_short) (0x0400) /* DMA cards only */ 286 #define S_DMA_IN_PROGRESS (u_short) (0x0800) /* DMA cards only */ 287 #define S_COMMAND_IN_PROGRESS (u_short) (0x1000) 288 289 /* 290 * FIFO Registers. RX Status. 291 * 292 * 15: Incomplete or FIFO empty. 293 * 14: 1: Error in RX Packet 0: Incomplete or no error. 294 * 14-11: Type of error. [14-11] 295 * 1000 = Overrun. 296 * 1011 = Run Packet Error. 297 * 1100 = Alignment Error. 298 * 1101 = CRC Error. 299 * 1001 = Oversize Packet Error (>1514 bytes) 300 * 0010 = Dribble Bits. 301 * (all other error codes, no errors.) 302 * 303 * 10-0: RX Bytes (0-1514) 304 */ 305 #define ERR_INCOMPLETE (u_short) (0x8000) 306 #define ERR_RX (u_short) (0x4000) 307 #define ERR_MASK (u_short) (0x7800) 308 #define ERR_OVERRUN (u_short) (0x4000) 309 #define ERR_RUNT (u_short) (0x5800) 310 #define ERR_ALIGNMENT (u_short) (0x6000) 311 #define ERR_CRC (u_short) (0x6800) 312 #define ERR_OVERSIZE (u_short) (0x4800) 313 #define ERR_DRIBBLE (u_short) (0x1000) 314 315 /* 316 * TX Status 317 * 318 * Reports the transmit status of a completed transmission. Writing this 319 * register pops the transmit completion stack. 320 * 321 * Window 1/Port 0x0b. 322 * 323 * 7: Complete 324 * 6: Interrupt on successful transmission requested. 325 * 5: Jabber Error (TP Only, TX Reset required. ) 326 * 4: Underrun (TX Reset required. ) 327 * 3: Maximum Collisions. 328 * 2: TX Status Overflow. 329 * 1-0: Undefined. 330 * 331 */ 332 #define TXS_COMPLETE 0x80 333 #define TXS_INTR_REQ 0x40 334 #define TXS_JABBER 0x20 335 #define TXS_UNDERRUN 0x10 336 #define TXS_MAX_COLLISION 0x08 337 #define TXS_STATUS_OVERFLOW 0x04 338 339 /* 340 * RX status 341 * Window 1/Port 0x08. 342 */ 343 #define RX_BYTES_MASK (u_short) (0x07ff) 344 345 /* 346 * Internal Config and MAC control (Window 3) 347 * Window 3 / Port 0: 32-bit internal config register: 348 * bits 0-2: fifo buffer ram size 349 * 3: ram width (word/byte) (ro) 350 * 4-5: ram speed 351 * 6-7: rom size 352 * 8-15: reserved 353 * 354 * 16-17: ram split (5:3, 3:1, or 1:1). 355 * 18-19: reserved 356 * 20-22: selected media type 357 * 21: unused 358 * 24: (nonvolatile) driver should autoselect media 359 * 25-31: reserved 360 * 361 * The low-order 16 bits should generally not be changed by software. 362 * Offsets defined for two 16-bit words, to help out 16-bit busses. 363 */ 364 #define CONFIG_RAMSIZE (u_short) 0x0007 365 #define CONFIG_RAMSIZE_SHIFT (u_short) 0 366 367 #define CONFIG_RAMWIDTH (u_short) 0x0008 368 #define CONFIG_RAMWIDTH_SHIFT (u_short) 3 369 370 #define CONFIG_RAMSPEED (u_short) 0x0030 371 #define CONFIG_RAMSPEED_SHIFT (u_short) 4 372 #define CONFIG_ROMSIZE (u_short) 0x00c0 373 #define CONFIG_ROMSIZE_SHIFT (u_short) 6 374 375 /* Window 3/port 2 */ 376 #define CONFIG_RAMSPLIT (u_short) 0x0003 377 #define CONFIG_RAMSPLIT_SHIFT (u_short) 0 378 #define CONFIG_MEDIAMASK (u_short) 0x0070 379 #define CONFIG_MEDIAMASK_SHIFT (u_short) 4 380 381 /* 382 * MAC_CONTROL (Window 3) 383 */ 384 #define MAC_CONTROL_FDX 0x20 /* full-duplex mode */ 385 386 /* Active media in EP_W3_RESET_OPTIONS mediamask bits */ 387 388 #define EPMEDIA_10BASE_T (u_short) 0x00 389 #define EPMEDIA_AUI (u_short) 0x01 390 #define EPMEDIA_RESV1 (u_short) 0x02 391 #define EPMEDIA_10BASE_2 (u_short) 0x03 392 #define EPMEDIA_100BASE_TX (u_short) 0x04 393 #define EPMEDIA_100BASE_FX (u_short) 0x05 394 #define EPMEDIA_MII (u_short) 0x06 395 #define EPMEDIA_100BASE_T4 (u_short) 0x07 396 397 398 #define CONFIG_AUTOSELECT (u_short) 0x0100 399 #define CONFIG_AUTOSELECT_SHIFT (u_short) 8 400 401 /* 402 * RESET_OPTIONS (Window 4, on Demon/Vortex/Boomerang only) 403 * also mapped to PCI configuration space on PCI adaptors. 404 * 405 * (same register as Vortex EP_W3_RESET_OPTIONS, mapped to pci-config space) 406 */ 407 #define EP_PCI_100BASE_T4 (1<<0) 408 #define EP_PCI_100BASE_TX (1<<1) 409 #define EP_PCI_100BASE_FX (1<<2) 410 #define EP_PCI_10BASE_T (1<<3) 411 # define EP_PCI_UTP EP_PCI_10BASE_T 412 #define EP_PCI_BNC (1<<4) 413 #define EP_PCI_AUI (1<<5) 414 #define EP_PCI_100BASE_MII (1<<6) 415 #define EP_PCI_INTERNAL_VCO (1<<8) 416 417 #define EP_RUNNER_MII_RESET 0x4000 418 #define EP_RUNNER_ENABLE_MII 0x8000 419 420 /* 421 * FIFO Status (Window 4) 422 * 423 * Supports FIFO diagnostics 424 * 425 * Window 4/Port 0x04.1 426 * 427 * 15: 1=RX receiving (RO). Set when a packet is being received 428 * into the RX FIFO. 429 * 14: Reserved 430 * 13: 1=RX underrun (RO). Generates Adapter Failure interrupt. 431 * Requires RX Reset or Global Reset command to recover. 432 * It is generated when you read past the end of a packet - 433 * reading past what has been received so far will give bad 434 * data. 435 * 12: 1=RX status overrun (RO). Set when there are already 8 436 * packets in the RX FIFO. While this bit is set, no additional 437 * packets are received. Requires no action on the part of 438 * the host. The condition is cleared once a packet has been 439 * read out of the RX FIFO. 440 * 11: 1=RX overrun (RO). Set when the RX FIFO is full (there 441 * may not be an overrun packet yet). While this bit is set, 442 * no additional packets will be received (some additional 443 * bytes can still be pending between the wire and the RX 444 * FIFO). Requires no action on the part of the host. The 445 * condition is cleared once a few bytes have been read out 446 * from the RX FIFO. 447 * 10: 1=TX overrun (RO). Generates adapter failure interrupt. 448 * Requires TX Reset or Global Reset command to recover. 449 * Disables Transmitter. 450 * 9-8: Unassigned. 451 * 7-0: Built in self test bits for the RX and TX FIFO's. 452 */ 453 #define FIFOS_RX_RECEIVING (u_short) 0x8000 454 #define FIFOS_RX_UNDERRUN (u_short) 0x2000 455 #define FIFOS_RX_STATUS_OVERRUN (u_short) 0x1000 456 #define FIFOS_RX_OVERRUN (u_short) 0x0800 457 #define FIFOS_TX_OVERRUN (u_short) 0x0400 458 459 /* 460 * ISA/eisa CONFIG_CNTRL media-present bits. 461 */ 462 #define EP_W0_CC_AUI (1<<13) 463 #define EP_W0_CC_BNC (1<<12) 464 #define EP_W0_CC_UTP (1<<9) 465 466 467 /* EEPROM state flags/commands */ 468 #define EEPROM_BUSY (1<<15) 469 #define EEPROM_TST_MODE (1<<14) 470 #define READ_EEPROM (1<<7) 471 472 /* For the RoadRunner chips... */ 473 #define WRITE_EEPROM_RR 0x100 474 #define READ_EEPROM_RR 0x200 475 #define ERASE_EEPROM_RR 0x300 476 477 /* window 4, MEDIA_STATUS bits */ 478 #define SQE_ENABLE 0x08 /* Enables SQE on AUI ports */ 479 #define JABBER_GUARD_ENABLE 0x40 480 #define LINKBEAT_ENABLE 0x80 481 #define ENABLE_UTP (JABBER_GUARD_ENABLE|LINKBEAT_ENABLE) 482 #define DISABLE_UTP 0x0 483 #define LINKBEAT_DETECT 0x800 484 #define MEDIA_LED 0x0001 /* Link LED for 3C589E */ 485 486 /* 487 * ep_connectors softc media-preset bitflags 488 */ 489 #define EPC_AUI 0x01 490 #define EPC_BNC 0x02 491 #define EPC_RESERVED 0x04 492 #define EPC_UTP 0x08 493 #define EPC_100TX 0x10 494 #define EPC_100FX 0x20 495 #define EPC_MII 0x40 496 #define EPC_100T4 0x80 497 498 /* 499 * Misc defines for various things. 500 */ 501 #define TAG_ADAPTER 0xd0 502 #define ACTIVATE_ADAPTER_TO_CONFIG 0xff 503 #define ENABLE_DRQ_IRQ 0x0001 504 #define MFG_ID 0x506d /* `TCM' */ 505 #define PROD_ID_3C509 0x5090 /* 509[0-f] */ 506 #define GO_WINDOW(x) bus_space_write_2(sc->sc_iot, \ 507 sc->sc_ioh, EP_COMMAND, WINDOW_SELECT|x) 508 509 /* Used to probe for large-packet support. */ 510 #define EP_LARGEWIN_PROBE EP_THRESH_DISABLE 511 #define EP_LARGEWIN_MASK 0xffc 512