1 /* $OpenBSD: lsi64854.c,v 1.11 2017/09/08 05:36:52 deraadt Exp $ */ 2 /* $NetBSD: lsi64854.c,v 1.18 2001/06/04 20:56:51 mrg Exp $ */ 3 4 /*- 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/errno.h> 37 #include <sys/device.h> 38 39 #include <machine/bus.h> 40 #include <machine/autoconf.h> 41 #include <machine/cpu.h> 42 43 #include <scsi/scsi_all.h> 44 #include <scsi/scsiconf.h> 45 46 #include <dev/ic/lsi64854reg.h> 47 #include <dev/ic/lsi64854var.h> 48 49 #include <dev/ic/ncr53c9xreg.h> 50 #include <dev/ic/ncr53c9xvar.h> 51 52 void lsi64854_reset(struct lsi64854_softc *); 53 int lsi64854_setup(struct lsi64854_softc *, caddr_t *, size_t *, 54 int, size_t *); 55 int lsi64854_setup_pp(struct lsi64854_softc *, caddr_t *, size_t *, 56 int, size_t *); 57 int lsi64854_scsi_intr(void *); 58 int lsi64854_pp_intr(void *); 59 60 #ifdef DEBUG 61 #define LDB_SCSI 1 62 #define LDB_ENET 2 63 #define LDB_PP 4 64 #define LDB_ANY 0xff 65 int lsi64854debug = 0; 66 #define DPRINTF(a,x) do { if (lsi64854debug & (a)) printf x ; } while (0) 67 #else 68 #define DPRINTF(a,x) 69 #endif 70 71 #define MAX_DMA_SZ (16*1024*1024) 72 73 /* 74 * Finish attaching this DMA device. 75 * Front-end must fill in these fields: 76 * sc_bustag 77 * sc_dmatag 78 * sc_regs 79 * sc_burst 80 * sc_channel (one of SCSI, ENET, PP) 81 * sc_client (one of SCSI, ENET, PP `soft_c' pointers) 82 */ 83 int 84 lsi64854_attach(sc) 85 struct lsi64854_softc *sc; 86 { 87 u_int32_t csr; 88 int rc; 89 90 /* Indirect functions */ 91 switch (sc->sc_channel) { 92 case L64854_CHANNEL_SCSI: 93 sc->intr = lsi64854_scsi_intr; 94 sc->setup = lsi64854_setup; 95 break; 96 case L64854_CHANNEL_ENET: 97 sc->intr = lsi64854_enet_intr; 98 sc->setup = lsi64854_setup; 99 break; 100 case L64854_CHANNEL_PP: 101 sc->intr = lsi64854_pp_intr; 102 sc->setup = lsi64854_setup_pp; 103 break; 104 default: 105 printf("%s: unknown channel\n", sc->sc_dev.dv_xname); 106 } 107 sc->reset = lsi64854_reset; 108 109 /* Allocate a dmamap */ 110 if ((rc = bus_dmamap_create(sc->sc_dmatag, MAX_DMA_SZ, 1, MAX_DMA_SZ, 111 0, BUS_DMA_WAITOK, &sc->sc_dmamap)) != 0) { 112 printf(": dma map create failed\n"); 113 return (rc); 114 } 115 116 printf(": dma rev "); 117 csr = L64854_GCSR(sc); 118 sc->sc_rev = csr & L64854_DEVID; 119 switch (sc->sc_rev) { 120 case DMAREV_0: 121 printf("0"); 122 break; 123 case DMAREV_ESC: 124 printf("esc"); 125 break; 126 case DMAREV_1: 127 printf("1"); 128 break; 129 case DMAREV_PLUS: 130 printf("1+"); 131 break; 132 case DMAREV_2: 133 printf("2"); 134 break; 135 case DMAREV_HME: 136 printf("fas"); 137 break; 138 default: 139 printf("unknown (0x%x)", sc->sc_rev); 140 } 141 142 DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr)); 143 printf("\n"); 144 145 return (0); 146 } 147 148 /* 149 * DMAWAIT waits while condition is true 150 */ 151 #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \ 152 int count = 500000; \ 153 while ((COND) && --count > 0) DELAY(1); \ 154 if (count == 0) { \ 155 printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \ 156 (u_long)L64854_GCSR(SC)); \ 157 if (DONTPANIC) \ 158 printf(MSG); \ 159 else \ 160 panic(MSG); \ 161 } \ 162 } while (0) 163 164 #define DMA_DRAIN(sc, dontpanic) do { \ 165 u_int32_t csr; \ 166 /* \ 167 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 168 * and "drain" bits while it is still thinking about a \ 169 * request. \ 170 * other revs: D_ESC_R_PEND bit reads as 0 \ 171 */ \ 172 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 173 if (sc->sc_rev != DMAREV_HME) { \ 174 /* \ 175 * Select drain bit based on revision \ 176 * also clears errors and D_TC flag \ 177 */ \ 178 csr = L64854_GCSR(sc); \ 179 if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \ 180 csr |= D_ESC_DRAIN; \ 181 else \ 182 csr |= L64854_INVALIDATE; \ 183 \ 184 L64854_SCSR(sc,csr); \ 185 } \ 186 /* \ 187 * Wait for draining to finish \ 188 * rev0 & rev1 call this PACKCNT \ 189 */ \ 190 DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\ 191 } while(0) 192 193 #define DMA_FLUSH(sc, dontpanic) do { \ 194 u_int32_t csr; \ 195 /* \ 196 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 197 * and "drain" bits while it is still thinking about a \ 198 * request. \ 199 * other revs: D_ESC_R_PEND bit reads as 0 \ 200 */ \ 201 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 202 csr = L64854_GCSR(sc); \ 203 csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \ 204 csr |= L64854_INVALIDATE; /* XXX FAS ? */ \ 205 L64854_SCSR(sc,csr); \ 206 } while(0) 207 208 void 209 lsi64854_reset(sc) 210 struct lsi64854_softc *sc; 211 { 212 u_int32_t csr; 213 214 DMA_FLUSH(sc, 1); 215 csr = L64854_GCSR(sc); 216 217 DPRINTF(LDB_ANY, ("lsi64854_reset: csr 0x%x\n", csr)); 218 219 /* 220 * XXX is sync needed? 221 */ 222 if (sc->sc_dmamap->dm_nsegs > 0) 223 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 224 225 if (sc->sc_rev == DMAREV_HME) 226 L64854_SCSR(sc, csr | D_HW_RESET_FAS366); 227 228 229 csr |= L64854_RESET; /* reset DMA */ 230 L64854_SCSR(sc, csr); 231 DELAY(200); /* > 10 Sbus clocks(?) */ 232 233 /*DMAWAIT1(sc); why was this here? */ 234 csr = L64854_GCSR(sc); 235 csr &= ~L64854_RESET; /* de-assert reset line */ 236 L64854_SCSR(sc, csr); 237 DELAY(5); /* allow a few ticks to settle */ 238 239 csr = L64854_GCSR(sc); 240 csr |= L64854_INT_EN; /* enable interrupts */ 241 if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) { 242 if (sc->sc_rev == DMAREV_HME) 243 csr |= D_TWO_CYCLE; 244 else 245 csr |= D_FASTER; 246 } 247 248 /* Set burst */ 249 switch (sc->sc_rev) { 250 case DMAREV_HME: 251 case DMAREV_2: 252 csr &= ~L64854_BURST_SIZE; 253 if (sc->sc_burst == 32) { 254 csr |= L64854_BURST_32; 255 } else if (sc->sc_burst == 16) { 256 csr |= L64854_BURST_16; 257 } else { 258 csr |= L64854_BURST_0; 259 } 260 break; 261 case DMAREV_ESC: 262 csr |= D_ESC_AUTODRAIN; /* Auto-drain */ 263 if (sc->sc_burst == 32) { 264 csr &= ~D_ESC_BURST; 265 } else 266 csr |= D_ESC_BURST; 267 break; 268 default: 269 break; 270 } 271 L64854_SCSR(sc, csr); 272 273 if (sc->sc_rev == DMAREV_HME) { 274 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 0); 275 sc->sc_dmactl = csr; 276 } 277 sc->sc_active = 0; 278 279 DPRINTF(LDB_ANY, ("lsi64854_reset: done, csr 0x%x\n", csr)); 280 } 281 282 283 #define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1))) 284 /* 285 * setup a dma transfer 286 */ 287 int 288 lsi64854_setup(sc, addr, len, datain, dmasize) 289 struct lsi64854_softc *sc; 290 caddr_t *addr; 291 size_t *len; 292 int datain; 293 size_t *dmasize; /* IN-OUT */ 294 { 295 u_int32_t csr; 296 297 DMA_FLUSH(sc, 0); 298 299 #if 0 300 DMACSR(sc) &= ~D_INT_EN; 301 #endif 302 sc->sc_dmaaddr = addr; 303 sc->sc_dmalen = len; 304 305 /* 306 * the rules say we cannot transfer more than the limit 307 * of this DMA chip (64k for old and 16Mb for new), 308 * and we cannot cross a 16Mb boundary. 309 */ 310 *dmasize = sc->sc_dmasize = 311 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 312 313 DPRINTF(LDB_ANY, ("dma_setup: dmasize = %ld\n", (long)sc->sc_dmasize)); 314 315 /* 316 * XXX what length? 317 */ 318 if (sc->sc_rev == DMAREV_HME) { 319 320 L64854_SCSR(sc, sc->sc_dmactl | L64854_RESET); 321 L64854_SCSR(sc, sc->sc_dmactl); 322 323 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, *dmasize); 324 } 325 326 /* Program the DMA address */ 327 if (sc->sc_dmasize) { 328 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 329 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 330 *sc->sc_dmaaddr, sc->sc_dmasize, 331 NULL /* kernel address */, 332 BUS_DMA_NOWAIT | BUS_DMA_STREAMING)) 333 panic("%s: cannot allocate DVMA address", 334 sc->sc_dev.dv_xname); 335 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 336 datain 337 ? BUS_DMASYNC_PREREAD 338 : BUS_DMASYNC_PREWRITE); 339 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 340 sc->sc_dmamap->dm_segs[0].ds_addr); 341 } 342 343 if (sc->sc_rev == DMAREV_ESC) { 344 /* DMA ESC chip bug work-around */ 345 long bcnt = sc->sc_dmasize; 346 long eaddr = bcnt + (long)*sc->sc_dmaaddr; 347 if ((eaddr & PGOFSET) != 0) 348 bcnt = roundup(bcnt, PAGE_SIZE); 349 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 350 bcnt); 351 } 352 353 /* Setup DMA control register */ 354 csr = L64854_GCSR(sc); 355 356 if (datain) 357 csr |= L64854_WRITE; 358 else 359 csr &= ~L64854_WRITE; 360 csr |= L64854_INT_EN; 361 362 if (sc->sc_rev == DMAREV_HME) { 363 csr |= (D_DSBL_SCSI_DRN | D_EN_DMA); 364 } 365 366 L64854_SCSR(sc, csr); 367 368 return (0); 369 } 370 371 /* 372 * Pseudo (chained) interrupt from the esp driver to kick the 373 * current running DMA transfer. Called from ncr53c9x_intr() 374 * for now. 375 * 376 * return 1 if it was a DMA continue. 377 */ 378 int 379 lsi64854_scsi_intr(arg) 380 void *arg; 381 { 382 struct lsi64854_softc *sc = arg; 383 struct ncr53c9x_softc *nsc = sc->sc_client; 384 char bits[64]; 385 int trans, resid; 386 u_int32_t csr; 387 388 csr = L64854_GCSR(sc); 389 390 DPRINTF(LDB_SCSI, ("%s: dmaintr: addr 0x%x, csr %b\n", sc->sc_dev.dv_xname, 391 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 392 csr, DDMACSR_BITS)); 393 394 if (csr & (D_ERR_PEND|D_SLAVE_ERR)) { 395 snprintf(bits, sizeof(bits), "%b", csr, DDMACSR_BITS); 396 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, bits); 397 csr &= ~D_EN_DMA; /* Stop DMA */ 398 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 399 csr |= D_INVALIDATE|D_SLAVE_ERR; 400 L64854_SCSR(sc, csr); 401 return (-1); 402 } 403 404 /* This is an "assertion" :) */ 405 if (sc->sc_active == 0) 406 panic("dmaintr: DMA wasn't active"); 407 408 DMA_DRAIN(sc, 0); 409 410 /* DMA has stopped */ 411 csr &= ~D_EN_DMA; 412 L64854_SCSR(sc, csr); 413 sc->sc_active = 0; 414 415 if (sc->sc_dmasize == 0) { 416 /* A "Transfer Pad" operation completed */ 417 DPRINTF(LDB_SCSI, ("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 418 NCR_READ_REG(nsc, NCR_TCL) | 419 (NCR_READ_REG(nsc, NCR_TCM) << 8), 420 NCR_READ_REG(nsc, NCR_TCL), 421 NCR_READ_REG(nsc, NCR_TCM))); 422 return 0; 423 } 424 425 resid = 0; 426 /* 427 * If a transfer onto the SCSI bus gets interrupted by the device 428 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 429 * as residual since the NCR53C9X counter registers get decremented 430 * as bytes are clocked into the FIFO. 431 */ 432 if (!(csr & D_WRITE) && 433 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 434 DPRINTF(LDB_SCSI, ("dmaintr: empty esp FIFO of %d ", resid)); 435 if (nsc->sc_rev == NCR_VARIANT_FAS366 && 436 (NCR_READ_REG(nsc, NCR_CFG3) & NCRFASCFG3_EWIDE)) 437 resid <<= 1; 438 } 439 440 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 441 /* 442 * `Terminal count' is off, so read the residue 443 * out of the NCR53C9X counter registers. 444 */ 445 resid += (NCR_READ_REG(nsc, NCR_TCL) | 446 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 447 ((nsc->sc_cfg2 & NCRCFG2_FE) 448 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) 449 : 0)); 450 451 if (resid == 0 && sc->sc_dmasize == 65536 && 452 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 453 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 454 resid = 65536; 455 } 456 457 trans = sc->sc_dmasize - resid; 458 if (trans < 0) { /* transferred < 0 ? */ 459 #if 0 460 /* 461 * This situation can happen in perfectly normal operation 462 * if the ESP is reselected while using DMA to select 463 * another target. As such, don't print the warning. 464 */ 465 printf("%s: xfer (%d) > req (%d)\n", 466 sc->sc_dev.dv_xname, trans, sc->sc_dmasize); 467 #endif 468 trans = sc->sc_dmasize; 469 } 470 471 DPRINTF(LDB_SCSI, ("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 472 NCR_READ_REG(nsc, NCR_TCL), 473 NCR_READ_REG(nsc, NCR_TCM), 474 (nsc->sc_cfg2 & NCRCFG2_FE) 475 ? NCR_READ_REG(nsc, NCR_TCH) : 0, 476 trans, resid)); 477 478 if (sc->sc_dmamap->dm_nsegs > 0) { 479 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 480 (csr & D_WRITE) != 0 481 ? BUS_DMASYNC_POSTREAD 482 : BUS_DMASYNC_POSTWRITE); 483 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 484 } 485 486 *sc->sc_dmalen -= trans; 487 *sc->sc_dmaaddr += trans; 488 489 #if 0 /* this is not normal operation just yet */ 490 if (*sc->sc_dmalen == 0 || 491 nsc->sc_phase != nsc->sc_prevphase) 492 return 0; 493 494 /* and again */ 495 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 496 return 1; 497 #endif 498 return 0; 499 } 500 501 /* 502 * Pseudo (chained) interrupt to le driver to handle DMA errors. 503 */ 504 int 505 lsi64854_enet_intr(arg) 506 void *arg; 507 { 508 struct lsi64854_softc *sc = arg; 509 char bits[64]; 510 u_int32_t csr; 511 static int dodrain = 0; 512 int rv; 513 514 csr = L64854_GCSR(sc); 515 516 /* If the DMA logic shows an interrupt, claim it */ 517 rv = ((csr & E_INT_PEND) != 0) ? 1 : 0; 518 519 if (csr & (E_ERR_PEND|E_SLAVE_ERR)) { 520 snprintf(bits, sizeof(bits), "%b", csr, EDMACSR_BITS); 521 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, bits); 522 csr &= ~L64854_EN_DMA; /* Stop DMA */ 523 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 524 csr |= E_INVALIDATE|E_SLAVE_ERR; 525 L64854_SCSR(sc, csr); 526 DMA_RESET(sc); 527 dodrain = 1; 528 return (1); 529 } 530 531 if (dodrain) { /* XXX - is this necessary with D_DSBL_WRINVAL on? */ 532 int i = 10; 533 csr |= E_DRAIN; 534 L64854_SCSR(sc, csr); 535 while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING)) 536 delay(1); 537 } 538 539 return (rv | (*sc->sc_intrchain)(sc->sc_intrchainarg)); 540 } 541 542 /* 543 * setup a dma transfer 544 */ 545 int 546 lsi64854_setup_pp(sc, addr, len, datain, dmasize) 547 struct lsi64854_softc *sc; 548 caddr_t *addr; 549 size_t *len; 550 int datain; 551 size_t *dmasize; /* IN-OUT */ 552 { 553 u_int32_t csr; 554 555 DMA_FLUSH(sc, 0); 556 557 sc->sc_dmaaddr = addr; 558 sc->sc_dmalen = len; 559 560 DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", sc->sc_dev.dv_xname, 561 (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 562 563 /* 564 * the rules say we cannot transfer more than the limit 565 * of this DMA chip (64k for old and 16Mb for new), 566 * and we cannot cross a 16Mb boundary. 567 */ 568 *dmasize = sc->sc_dmasize = 569 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 570 571 DPRINTF(LDB_PP, ("dma_setup_pp: dmasize = %ld\n", (long)sc->sc_dmasize)); 572 573 /* Program the DMA address */ 574 if (sc->sc_dmasize) { 575 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 576 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 577 *sc->sc_dmaaddr, sc->sc_dmasize, 578 NULL /* kernel address */, 579 BUS_DMA_NOWAIT/*|BUS_DMA_COHERENT*/)) 580 panic("%s: pp cannot allocate DVMA address", 581 sc->sc_dev.dv_xname); 582 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 583 datain 584 ? BUS_DMASYNC_PREREAD 585 : BUS_DMASYNC_PREWRITE); 586 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 587 sc->sc_dmamap->dm_segs[0].ds_addr); 588 589 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 590 sc->sc_dmasize); 591 } 592 593 /* Setup DMA control register */ 594 csr = L64854_GCSR(sc); 595 csr &= ~L64854_BURST_SIZE; 596 if (sc->sc_burst == 32) { 597 csr |= L64854_BURST_32; 598 } else if (sc->sc_burst == 16) { 599 csr |= L64854_BURST_16; 600 } else { 601 csr |= L64854_BURST_0; 602 } 603 csr |= P_EN_DMA|P_INT_EN|P_EN_CNT; 604 #if 0 605 /* This bit is read-only in PP csr register */ 606 if (datain) 607 csr |= P_WRITE; 608 else 609 csr &= ~P_WRITE; 610 #endif 611 L64854_SCSR(sc, csr); 612 613 return (0); 614 } 615 /* 616 * Parallel port DMA interrupt. 617 */ 618 int 619 lsi64854_pp_intr(arg) 620 void *arg; 621 { 622 struct lsi64854_softc *sc = arg; 623 int ret, trans, resid = 0; 624 u_int32_t csr; 625 626 csr = L64854_GCSR(sc); 627 628 DPRINTF(LDB_PP, ("%s: pp intr: addr 0x%x, csr %b\n", sc->sc_dev.dv_xname, 629 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 630 csr, PDMACSR_BITS)); 631 632 if (csr & (P_ERR_PEND|P_SLAVE_ERR)) { 633 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 634 L64854_REG_CNT); 635 printf("%s: pp error: resid %d csr=%b\n", sc->sc_dev.dv_xname, 636 resid, csr, PDMACSR_BITS); 637 csr &= ~P_EN_DMA; /* Stop DMA */ 638 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 639 csr |= P_INVALIDATE|P_SLAVE_ERR; 640 L64854_SCSR(sc, csr); 641 return (1); 642 } 643 644 ret = (csr & P_INT_PEND) != 0; 645 646 if (sc->sc_active != 0) { 647 DMA_DRAIN(sc, 0); 648 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 649 L64854_REG_CNT); 650 } 651 652 /* DMA has stopped */ 653 csr &= ~D_EN_DMA; 654 L64854_SCSR(sc, csr); 655 sc->sc_active = 0; 656 657 trans = sc->sc_dmasize - resid; 658 if (trans < 0) { /* transferred < 0 ? */ 659 trans = sc->sc_dmasize; 660 } 661 *sc->sc_dmalen -= trans; 662 *sc->sc_dmaaddr += trans; 663 664 if (sc->sc_dmamap->dm_nsegs > 0) { 665 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 666 (csr & D_WRITE) != 0 667 ? BUS_DMASYNC_POSTREAD 668 : BUS_DMASYNC_POSTWRITE); 669 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 670 } 671 672 return (ret != 0); 673 } 674