1 /* $OpenBSD: mfireg.h,v 1.38 2013/05/01 01:56:29 dlg Exp $ */ 2 /* 3 * Copyright (c) 2006 Marco Peereboom <marco@peereboom.us> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 /* management interface constants */ 19 #define MFI_MGMT_VD 0x01 20 #define MFI_MGMT_SD 0x02 21 22 /* generic constants */ 23 #define MFI_FRAME_SIZE 64 24 #define MFI_SENSE_SIZE 128 25 #define MFI_OSTS_INTR_VALID 0x00000002 /* valid interrupt */ 26 #define MFI_OSTS_PPC_INTR_VALID 0x80000000 27 #define MFI_OSTS_GEN2_INTR_VALID (0x00000001 | 0x00000004) 28 #define MFI_INVALID_CTX 0xffffffff 29 #define MFI_ENABLE_INTR 0x01 30 #define MFI_MAXFER MAXPHYS /* XXX bogus */ 31 32 /* register offsets */ 33 #define MFI_IMSG0 0x10 /* inbound msg 0 */ 34 #define MFI_IMSG1 0x14 /* inbound msg 1 */ 35 #define MFI_OMSG0 0x18 /* outbound msg 0 */ 36 #define MFI_OMSG1 0x1c /* outbound msg 1 */ 37 #define MFI_IDB 0x20 /* inbound doorbell */ 38 #define MFI_ISTS 0x24 /* inbound intr stat */ 39 #define MFI_IMSK 0x28 /* inbound intr mask */ 40 #define MFI_ODB 0x2c /* outbound doorbell */ 41 #define MFI_OSTS 0x30 /* outbound intr stat */ 42 #define MFI_OMSK 0x34 /* outbound inter mask */ 43 #define MFI_IQP 0x40 /* inbound queue port */ 44 #define MFI_OQP 0x44 /* outbound queue port */ 45 #define MFI_ODC 0xa0 /* outbound doorbell clr */ 46 #define MFI_OSP 0xb0 /* outbound scratch pad */ 47 48 /* 49 * skinny specific changes 50 */ 51 #define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 52 #define MFI_IQPL 0x000000c0 53 #define MFI_IQPH 0x000000c4 54 #define MFI_OSTS_SKINNY_INTR_VALID 0x00000001 55 56 /* * firmware states */ 57 #define MFI_STATE_MASK 0xf0000000 58 #define MFI_STATE_UNDEFINED 0x00000000 59 #define MFI_STATE_BB_INIT 0x10000000 60 #define MFI_STATE_FW_INIT 0x40000000 61 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 62 #define MFI_STATE_FW_INIT_2 0x70000000 63 #define MFI_STATE_DEVICE_SCAN 0x80000000 64 #define MFI_STATE_FLUSH_CACHE 0xa0000000 65 #define MFI_STATE_READY 0xb0000000 66 #define MFI_STATE_OPERATIONAL 0xc0000000 67 #define MFI_STATE_FAULT 0xf0000000 68 #define MFI_STATE_MAXSGL_MASK 0x00ff0000 69 #define MFI_STATE_MAXCMD_MASK 0x0000ffff 70 71 /* command reset register */ 72 #define MFI_INIT_ABORT 0x00000000 73 #define MFI_INIT_READY 0x00000002 74 #define MFI_INIT_MFIMODE 0x00000004 75 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 76 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE 77 78 /* mfi Frame flags */ 79 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 80 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 81 #define MFI_FRAME_SGL32 0x0000 82 #define MFI_FRAME_SGL64 0x0002 83 #define MFI_FRAME_SENSE32 0x0000 84 #define MFI_FRAME_SENSE64 0x0004 85 #define MFI_FRAME_DIR_NONE 0x0000 86 #define MFI_FRAME_DIR_WRITE 0x0008 87 #define MFI_FRAME_DIR_READ 0x0010 88 #define MFI_FRAME_DIR_BOTH 0x0018 89 90 /* mfi command opcodes */ 91 #define MFI_CMD_INIT 0x00 92 #define MFI_CMD_LD_READ 0x01 93 #define MFI_CMD_LD_WRITE 0x02 94 #define MFI_CMD_LD_SCSI_IO 0x03 95 #define MFI_CMD_PD_SCSI_IO 0x04 96 #define MFI_CMD_DCMD 0x05 97 #define MFI_CMD_ABORT 0x06 98 #define MFI_CMD_SMP 0x07 99 #define MFI_CMD_STP 0x08 100 101 /* direct commands */ 102 #define MR_DCMD_CTRL_GET_INFO 0x01010000 103 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 104 #define MR_FLUSH_CTRL_CACHE 0x01 105 #define MR_FLUSH_DISK_CACHE 0x02 106 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 107 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 108 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 109 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 110 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 111 #define MR_DCMD_PD_GET_LIST 0x02010000 112 #define MR_DCMD_PD_GET_INFO 0x02020000 113 #define MR_DCMD_PD_SET_STATE 0x02030100 114 #define MR_DCMD_PD_REBUILD 0x02040100 115 #define MR_DCMD_PD_BLINK 0x02070100 116 #define MR_DCMD_PD_UNBLINK 0x02070200 117 #define MR_DCMD_PD_GET_ALLOWED_OPS_LIST 0x020a0100 118 #define MR_DCMD_LD_GET_LIST 0x03010000 119 #define MR_DCMD_LD_GET_INFO 0x03020000 120 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 121 #define MR_DCMD_CONF_GET 0x04010000 122 #define MR_DCMD_BBU_GET_STATUS 0x05010000 123 #define MR_DCMD_BBU_GET_CAPACITY_INFO 0x05020000 124 #define MR_DCMD_BBU_GET_DESIGN_INFO 0x05030000 125 #define MR_DCMD_BBU_START_LEARN 0x05040000 126 #define MR_DCMD_BBU_GET_PROP 0x05050100 127 #define MR_DCMD_BBU_SET_PROP 0x05050200 128 #define MR_DCMD_CLUSTER 0x08000000 129 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 130 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 131 132 #define MR_DCMD_SPEAKER_GET 0x01030100 133 #define MR_DCMD_SPEAKER_ENABLE 0x01030200 134 #define MR_DCMD_SPEAKER_DISABLE 0x01030300 135 #define MR_DCMD_SPEAKER_SILENCE 0x01030400 136 #define MR_DCMD_SPEAKER_TEST 0x01030500 137 138 /* mailbox bytes in direct command */ 139 #define MFI_MBOX_SIZE 12 140 141 /* mfi completion codes */ 142 typedef enum { 143 MFI_STAT_OK = 0x00, 144 MFI_STAT_INVALID_CMD = 0x01, 145 MFI_STAT_INVALID_DCMD = 0x02, 146 MFI_STAT_INVALID_PARAMETER = 0x03, 147 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 148 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 149 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 150 MFI_STAT_APP_IN_USE = 0x07, 151 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 152 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 153 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 154 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 155 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 156 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 157 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 158 MFI_STAT_FLASH_BUSY = 0x0f, 159 MFI_STAT_FLASH_ERROR = 0x10, 160 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 161 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 162 MFI_STAT_FLASH_NOT_OPEN = 0x13, 163 MFI_STAT_FLASH_NOT_STARTED = 0x14, 164 MFI_STAT_FLUSH_FAILED = 0x15, 165 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 166 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 167 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 168 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 169 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 170 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 171 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 172 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 173 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 174 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 175 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 176 MFI_STAT_MFC_HW_ERROR = 0x21, 177 MFI_STAT_NO_HW_PRESENT = 0x22, 178 MFI_STAT_NOT_FOUND = 0x23, 179 MFI_STAT_NOT_IN_ENCL = 0x24, 180 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 181 MFI_STAT_PD_TYPE_WRONG = 0x26, 182 MFI_STAT_PR_DISABLED = 0x27, 183 MFI_STAT_ROW_INDEX_INVALID = 0x28, 184 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 185 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 186 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 187 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 188 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 189 MFI_STAT_SCSI_IO_FAILED = 0x2e, 190 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 191 MFI_STAT_SHUTDOWN_FAILED = 0x30, 192 MFI_STAT_TIME_NOT_SET = 0x31, 193 MFI_STAT_WRONG_STATE = 0x32, 194 MFI_STAT_LD_OFFLINE = 0x33, 195 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 196 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 197 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 198 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 199 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 200 MFI_STAT_INVALID_STATUS = 0xff 201 } mfi_status_t; 202 203 typedef enum { 204 MFI_EVT_CLASS_DEBUG = -2, 205 MFI_EVT_CLASS_PROGRESS = -1, 206 MFI_EVT_CLASS_INFO = 0, 207 MFI_EVT_CLASS_WARNING = 1, 208 MFI_EVT_CLASS_CRITICAL = 2, 209 MFI_EVT_CLASS_FATAL = 3, 210 MFI_EVT_CLASS_DEAD = 4 211 } mfi_evt_class_t; 212 213 typedef enum { 214 MFI_EVT_LOCALE_LD = 0x0001, 215 MFI_EVT_LOCALE_PD = 0x0002, 216 MFI_EVT_LOCALE_ENCL = 0x0004, 217 MFI_EVT_LOCALE_BBU = 0x0008, 218 MFI_EVT_LOCALE_SAS = 0x0010, 219 MFI_EVT_LOCALE_CTRL = 0x0020, 220 MFI_EVT_LOCALE_CONFIG = 0x0040, 221 MFI_EVT_LOCALE_CLUSTER = 0x0080, 222 MFI_EVT_LOCALE_ALL = 0xffff 223 } mfi_evt_locale_t; 224 225 typedef enum { 226 MR_EVT_ARGS_NONE = 0x00, 227 MR_EVT_ARGS_CDB_SENSE, 228 MR_EVT_ARGS_LD, 229 MR_EVT_ARGS_LD_COUNT, 230 MR_EVT_ARGS_LD_LBA, 231 MR_EVT_ARGS_LD_OWNER, 232 MR_EVT_ARGS_LD_LBA_PD_LBA, 233 MR_EVT_ARGS_LD_PROG, 234 MR_EVT_ARGS_LD_STATE, 235 MR_EVT_ARGS_LD_STRIP, 236 MR_EVT_ARGS_PD, 237 MR_EVT_ARGS_PD_ERR, 238 MR_EVT_ARGS_PD_LBA, 239 MR_EVT_ARGS_PD_LBA_LD, 240 MR_EVT_ARGS_PD_PROG, 241 MR_EVT_ARGS_PD_STATE, 242 MR_EVT_ARGS_PCI, 243 MR_EVT_ARGS_RATE, 244 MR_EVT_ARGS_STR, 245 MR_EVT_ARGS_TIME, 246 MR_EVT_ARGS_ECC 247 } mfi_evt_args; 248 249 /* driver definitions */ 250 #define MFI_MAX_PD_CHANNELS 2 251 #define MFI_MAX_PD_ARRAY 32 252 #define MFI_MAX_LD_CHANNELS 2 253 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 254 #define MFI_MAX_CHANNEL_DEVS 128 255 #define MFI_DEFAULT_ID -1 256 #define MFI_MAX_LUN 8 257 #define MFI_MAX_LD 64 258 #define MFI_MAX_SPAN 8 259 #define MFI_MAX_ARRAY_DEDICATED 16 260 #define MFI_MAX_PD 256 261 262 /* sense buffer */ 263 struct mfi_sense { 264 uint8_t mse_data[MFI_SENSE_SIZE]; 265 } __packed; 266 267 /* scatter gather elements */ 268 struct mfi_sg32 { 269 uint32_t addr; 270 uint32_t len; 271 } __packed; 272 273 struct mfi_sg64 { 274 uint64_t addr; 275 uint32_t len; 276 } __packed; 277 278 union mfi_sgl { 279 struct mfi_sg32 sg32[1]; 280 struct mfi_sg64 sg64[1]; 281 } __packed; 282 283 /* message frame */ 284 struct mfi_frame_header { 285 uint8_t mfh_cmd; 286 uint8_t mfh_sense_len; 287 uint8_t mfh_cmd_status; 288 uint8_t mfh_scsi_status; 289 uint8_t mfh_target_id; 290 uint8_t mfh_lun_id; 291 uint8_t mfh_cdb_len; 292 uint8_t mfh_sg_count; 293 uint32_t mfh_context; 294 uint32_t mfh_pad0; 295 uint16_t mfh_flags; 296 uint16_t mfh_timeout; 297 uint32_t mfh_data_len; 298 } __packed; 299 300 union mfi_sgl_frame { 301 struct mfi_sg32 sge32[8]; 302 struct mfi_sg64 sge64[5]; 303 304 } __packed; 305 306 struct mfi_init_frame { 307 struct mfi_frame_header mif_header; 308 uint64_t mif_qinfo_new_addr; 309 uint64_t mif_qinfo_old_addr; 310 uint32_t mif_reserved[6]; 311 } __packed; 312 313 /* queue init structure */ 314 struct mfi_init_qinfo { 315 uint32_t miq_flags; 316 uint32_t miq_rq_entries; 317 uint64_t miq_rq_addr; 318 uint64_t miq_pi_addr; 319 uint64_t miq_ci_addr; 320 } __packed; 321 322 #define MFI_IO_FRAME_SIZE 40 323 struct mfi_io_frame { 324 struct mfi_frame_header mif_header; 325 uint64_t mif_sense_addr; 326 uint64_t mif_lba; 327 union mfi_sgl mif_sgl; 328 } __packed; 329 330 #define MFI_PASS_FRAME_SIZE 48 331 struct mfi_pass_frame { 332 struct mfi_frame_header mpf_header; 333 uint64_t mpf_sense_addr; 334 uint8_t mpf_cdb[16]; 335 union mfi_sgl mpf_sgl; 336 } __packed; 337 338 #define MFI_DCMD_FRAME_SIZE 40 339 struct mfi_dcmd_frame { 340 struct mfi_frame_header mdf_header; 341 uint32_t mdf_opcode; 342 uint8_t mdf_mbox[MFI_MBOX_SIZE]; 343 union mfi_sgl mdf_sgl; 344 } __packed; 345 346 struct mfi_abort_frame { 347 struct mfi_frame_header maf_header; 348 uint32_t maf_abort_context; 349 uint32_t maf_pad; 350 uint64_t maf_abort_mfi_addr; 351 uint32_t maf_reserved[6]; 352 } __packed; 353 354 struct mfi_smp_frame { 355 struct mfi_frame_header msf_header; 356 uint64_t msf_sas_addr; 357 union { 358 struct mfi_sg32 sg32[2]; 359 struct mfi_sg64 sg64[2]; 360 } msf_sgl; 361 } __packed; 362 363 struct mfi_stp_frame { 364 struct mfi_frame_header msf_header; 365 uint16_t msf_fis[10]; 366 uint32_t msf_stp_flags; 367 union { 368 struct mfi_sg32 sg32[2]; 369 struct mfi_sg64 sg64[2]; 370 } msf_sgl; 371 } __packed; 372 373 union mfi_frame { 374 struct mfi_frame_header mfr_header; 375 struct mfi_init_frame mfr_init; 376 struct mfi_io_frame mfr_io; 377 struct mfi_pass_frame mfr_pass; 378 struct mfi_dcmd_frame mfr_dcmd; 379 struct mfi_abort_frame mfr_abort; 380 struct mfi_smp_frame mfr_smp; 381 struct mfi_stp_frame mfr_stp; 382 uint8_t mfr_bytes[MFI_FRAME_SIZE]; 383 }; 384 385 union mfi_evt_class_locale { 386 struct { 387 uint16_t locale; 388 uint8_t reserved; 389 int8_t class; 390 } __packed mec_members; 391 392 uint32_t mec_word; 393 } __packed; 394 395 struct mfi_evt_log_info { 396 uint32_t mel_newest_seq_num; 397 uint32_t mel_oldest_seq_num; 398 uint32_t mel_clear_seq_num; 399 uint32_t mel_shutdown_seq_num; 400 uint32_t mel_boot_seq_num; 401 } __packed; 402 403 struct mfi_progress { 404 uint16_t mp_progress; 405 uint16_t mp_elapsed_seconds; 406 } __packed; 407 408 struct mfi_evtarg_ld { 409 uint16_t mel_target_id; 410 uint8_t mel_ld_index; 411 uint8_t mel_reserved; 412 } __packed; 413 414 struct mfi_evtarg_pd { 415 uint16_t mep_device_id; 416 uint8_t mep_encl_index; 417 uint8_t mep_slot_number; 418 } __packed; 419 420 struct mfi_evt_detail { 421 uint32_t med_seq_num; 422 uint32_t med_time_stamp; 423 uint32_t med_code; 424 union mfi_evt_class_locale med_cl; 425 uint8_t med_arg_type; 426 uint8_t med_reserved1[15]; 427 428 union { 429 struct { 430 struct mfi_evtarg_pd pd; 431 uint8_t cdb_length; 432 uint8_t sense_length; 433 uint8_t reserved[2]; 434 uint8_t cdb[16]; 435 uint8_t sense[64]; 436 } __packed cdb_sense; 437 438 struct mfi_evtarg_ld ld; 439 440 struct { 441 struct mfi_evtarg_ld ld; 442 uint64_t count; 443 } __packed ld_count; 444 445 struct { 446 uint64_t lba; 447 struct mfi_evtarg_ld ld; 448 } __packed ld_lba; 449 450 struct { 451 struct mfi_evtarg_ld ld; 452 uint32_t prev_owner; 453 uint32_t new_owner; 454 } __packed ld_owner; 455 456 struct { 457 uint64_t ld_lba; 458 uint64_t pd_lba; 459 struct mfi_evtarg_ld ld; 460 struct mfi_evtarg_pd pd; 461 } __packed ld_lba_pd_lba; 462 463 struct { 464 struct mfi_evtarg_ld ld; 465 struct mfi_progress prog; 466 } __packed ld_prog; 467 468 struct { 469 struct mfi_evtarg_ld ld; 470 uint32_t prev_state; 471 uint32_t new_state; 472 } __packed ld_state; 473 474 struct { 475 uint64_t strip; 476 struct mfi_evtarg_ld ld; 477 } __packed ld_strip; 478 479 struct mfi_evtarg_pd pd; 480 481 struct { 482 struct mfi_evtarg_pd pd; 483 uint32_t err; 484 } __packed pd_err; 485 486 struct { 487 uint64_t lba; 488 struct mfi_evtarg_pd pd; 489 } __packed pd_lba; 490 491 struct { 492 uint64_t lba; 493 struct mfi_evtarg_pd pd; 494 struct mfi_evtarg_ld ld; 495 } __packed pd_lba_ld; 496 497 struct { 498 struct mfi_evtarg_pd pd; 499 struct mfi_progress prog; 500 } __packed pd_prog; 501 502 struct { 503 struct mfi_evtarg_pd pd; 504 uint32_t prev_state; 505 uint32_t new_state; 506 } __packed pd_state; 507 508 struct { 509 uint16_t vendor_id; 510 uint16_t device_id; 511 uint16_t subvendor_id; 512 uint16_t subdevice_id; 513 } __packed pci; 514 515 uint32_t rate; 516 char str[96]; 517 518 struct { 519 uint32_t rtc; 520 uint32_t elapsed_seconds; 521 } __packed time; 522 523 struct { 524 uint32_t ecar; 525 uint32_t elog; 526 char str[64]; 527 } __packed ecc; 528 529 uint8_t b[96]; 530 uint16_t s[48]; 531 uint32_t w[24]; 532 uint64_t d[12]; 533 } args; 534 535 char med_description[128]; 536 } __packed; 537 538 /* controller properties from mfi_ctrl_info */ 539 struct mfi_ctrl_props { 540 uint16_t mcp_seq_num; 541 uint16_t mcp_pred_fail_poll_interval; 542 uint16_t mcp_intr_throttle_cnt; 543 uint16_t mcp_intr_throttle_timeout; 544 uint8_t mcp_rebuild_rate; 545 uint8_t mcp_patrol_read_rate; 546 uint8_t mcp_bgi_rate; 547 uint8_t mcp_cc_rate; 548 uint8_t mcp_recon_rate; 549 uint8_t mcp_cache_flush_interval; 550 uint8_t mcp_spinup_drv_cnt; 551 uint8_t mcp_spinup_delay; 552 uint8_t mcp_cluster_enable; 553 uint8_t mcp_coercion_mode; 554 uint8_t mcp_alarm_enable; 555 uint8_t mcp_disable_auto_rebuild; 556 uint8_t mcp_disable_battery_warn; 557 uint8_t mcp_ecc_bucket_size; 558 uint16_t mcp_ecc_bucket_leak_rate; 559 uint8_t mcp_restore_hotspare_on_insertion; 560 uint8_t mcp_expose_encl_devices; 561 uint8_t mcp_reserved[38]; 562 } __packed; 563 564 /* pci info */ 565 struct mfi_info_pci { 566 uint16_t mip_vendor; 567 uint16_t mip_device; 568 uint16_t mip_subvendor; 569 uint16_t mip_subdevice; 570 uint8_t mip_reserved[24]; 571 } __packed; 572 573 /* host interface infor */ 574 struct mfi_info_host { 575 uint8_t mih_type; 576 #define MFI_INFO_HOST_PCIX 0x01 577 #define MFI_INFO_HOST_PCIE 0x02 578 #define MFI_INFO_HOST_ISCSI 0x04 579 #define MFI_INFO_HOST_SAS3G 0x08 580 uint8_t mih_reserved[6]; 581 uint8_t mih_port_count; 582 uint64_t mih_port_addr[8]; 583 } __packed; 584 585 /* device interface info */ 586 struct mfi_info_device { 587 uint8_t mid_type; 588 #define MFI_INFO_DEV_SPI 0x01 589 #define MFI_INFO_DEV_SAS3G 0x02 590 #define MFI_INFO_DEV_SATA1 0x04 591 #define MFI_INFO_DEV_SATA3G 0x08 592 uint8_t mid_reserved[6]; 593 uint8_t mid_port_count; 594 uint64_t mid_port_addr[8]; 595 } __packed; 596 597 /* firmware component info */ 598 struct mfi_info_component { 599 char mic_name[8]; 600 char mic_version[32]; 601 char mic_build_date[16]; 602 char mic_build_time[16]; 603 } __packed; 604 605 /* controller info from MFI_DCMD_CTRL_GETINFO. */ 606 struct mfi_ctrl_info { 607 struct mfi_info_pci mci_pci; 608 struct mfi_info_host mci_host; 609 struct mfi_info_device mci_device; 610 611 /* Firmware components that are present and active. */ 612 uint32_t mci_image_check_word; 613 uint32_t mci_image_component_count; 614 struct mfi_info_component mci_image_component[8]; 615 616 /* Firmware components that have been flashed but are inactive */ 617 uint32_t mci_pending_image_component_count; 618 struct mfi_info_component mci_pending_image_component[8]; 619 620 uint8_t mci_max_arms; 621 uint8_t mci_max_spans; 622 uint8_t mci_max_arrays; 623 uint8_t mci_max_lds; 624 char mci_product_name[80]; 625 char mci_serial_number[32]; 626 uint32_t mci_hw_present; 627 #define MFI_INFO_HW_BBU 0x01 628 #define MFI_INFO_HW_ALARM 0x02 629 #define MFI_INFO_HW_NVRAM 0x04 630 #define MFI_INFO_HW_UART 0x08 631 #define MFI_INFO_HW_FMT "\020" "\001BBU" "\002ALARM" "\003NVRAM" \ 632 "\004UART" 633 634 uint32_t mci_current_fw_time; 635 uint16_t mci_max_cmds; 636 uint16_t mci_max_sg_elements; 637 uint32_t mci_max_request_size; 638 uint16_t mci_lds_present; 639 uint16_t mci_lds_degraded; 640 uint16_t mci_lds_offline; 641 uint16_t mci_pd_present; 642 uint16_t mci_pd_disks_present; 643 uint16_t mci_pd_disks_pred_failure; 644 uint16_t mci_pd_disks_failed; 645 uint16_t mci_nvram_size; 646 uint16_t mci_memory_size; 647 uint16_t mci_flash_size; 648 uint16_t mci_ram_correctable_errors; 649 uint16_t mci_ram_uncorrectable_errors; 650 uint8_t mci_cluster_allowed; 651 uint8_t mci_cluster_active; 652 uint16_t mci_max_strips_per_io; 653 654 uint32_t mci_raid_levels; 655 #define MFI_INFO_RAID_0 0x01 656 #define MFI_INFO_RAID_1 0x02 657 #define MFI_INFO_RAID_5 0x04 658 #define MFI_INFO_RAID_1E 0x08 659 #define MFI_INFO_RAID_6 0x10 660 661 uint32_t mci_adapter_ops; 662 #define MFI_INFO_AOPS_RBLD_RATE 0x0001 663 #define MFI_INFO_AOPS_CC_RATE 0x0002 664 #define MFI_INFO_AOPS_BGI_RATE 0x0004 665 #define MFI_INFO_AOPS_RECON_RATE 0x0008 666 #define MFI_INFO_AOPS_PATROL_RATE 0x0010 667 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 668 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 669 #define MFI_INFO_AOPS_BBU 0x0080 670 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 671 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 672 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 673 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 674 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 675 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 676 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 677 #define MFI_INFO_AOPS_FMT "\020" "\001RBLD_RATE" "\002CC_RATE" \ 678 "\003BGI_RATE" "\004RECON_RATE" \ 679 "\005PATROL_RATE" "\006ALARM_CONTROL" \ 680 "\007CLUSTER_SUPPORT" "\010BBU" \ 681 "\011SPANNING_ALLOWED" \ 682 "\012DEDICATED_SPARES" \ 683 "\013REVERTIBLE_SPARES" \ 684 "\014FOREIGN_IMPORT" "\015SELF_DIAGNOSTIC" \ 685 "\016MIXED_ARRAY" "\017GLOBAL_SPARES" 686 687 uint32_t mci_ld_ops; 688 #define MFI_INFO_LDOPS_READ_POLICY 0x01 689 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02 690 #define MFI_INFO_LDOPS_IO_POLICY 0x04 691 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 692 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 693 694 struct { 695 uint8_t min; 696 uint8_t max; 697 uint8_t reserved[2]; 698 } __packed mci_stripe_sz_ops; 699 700 uint32_t mci_pd_ops; 701 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 702 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 703 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 704 705 uint32_t mci_pd_mix_support; 706 #define MFI_INFO_PDMIX_SAS 0x01 707 #define MFI_INFO_PDMIX_SATA 0x02 708 #define MFI_INFO_PDMIX_ENCL 0x04 709 #define MFI_INFO_PDMIX_LD 0x08 710 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 711 712 uint8_t mci_ecc_bucket_count; 713 uint8_t mci_reserved2[11]; 714 struct mfi_ctrl_props mci_properties; 715 char mci_package_version[0x60]; 716 uint8_t mci_pad[0x800 - 0x6a0]; 717 } __packed; 718 719 /* logical disk info from MR_DCMD_LD_GET_LIST */ 720 struct mfi_ld { 721 uint8_t mld_target; 722 uint8_t mld_res; 723 uint16_t mld_seq; 724 } __packed; 725 726 struct mfi_ld_list { 727 uint32_t mll_no_ld; 728 uint32_t mll_res; 729 struct { 730 struct mfi_ld mll_ld; 731 uint8_t mll_state; 732 #define MFI_LD_OFFLINE 0x00 733 #define MFI_LD_PART_DEGRADED 0x01 734 #define MFI_LD_DEGRADED 0x02 735 #define MFI_LD_ONLINE 0x03 736 uint8_t mll_res2; 737 uint8_t mll_res3; 738 uint8_t mll_res4; 739 u_quad_t mll_size; 740 } mll_list[MFI_MAX_LD]; 741 } __packed; 742 743 /* logicl disk details from MR_DCMD_LD_GET_INFO */ 744 struct mfi_ld_prop { 745 struct mfi_ld mlp_ld; 746 char mlp_name[16]; 747 uint8_t mlp_cache_policy; 748 uint8_t mlp_acces_policy; 749 uint8_t mlp_diskcache_policy; 750 uint8_t mlp_cur_cache_policy; 751 uint8_t mlp_disable_bgi; 752 uint8_t mlp_res[7]; 753 } __packed; 754 755 struct mfi_ld_parm { 756 uint8_t mpa_pri_raid; /* SNIA DDF PRL */ 757 #define MFI_DDF_PRL_RAID0 0x00 758 #define MFI_DDF_PRL_RAID1 0x01 759 #define MFI_DDF_PRL_RAID3 0x03 760 #define MFI_DDF_PRL_RAID4 0x04 761 #define MFI_DDF_PRL_RAID5 0x05 762 #define MFI_DDF_PRL_RAID1E 0x11 763 #define MFI_DDF_PRL_JBOD 0x0f 764 #define MFI_DDF_PRL_CONCAT 0x1f 765 #define MFI_DDF_PRL_RAID5E 0x15 766 #define MFI_DDF_PRL_RAID5EE 0x25 767 #define MFI_DDF_PRL_RAID6 0x16 768 uint8_t mpa_raid_qual; /* SNIA DDF RLQ */ 769 uint8_t mpa_sec_raid; /* SNIA DDF SRL */ 770 #define MFI_DDF_SRL_STRIPED 0x00 771 #define MFI_DDF_SRL_MIRRORED 0x01 772 #define MFI_DDF_SRL_CONCAT 0x02 773 #define MFI_DDF_SRL_SPANNED 0x03 774 uint8_t mpa_stripe_size; 775 uint8_t mpa_no_drv_per_span; 776 uint8_t mpa_span_depth; 777 uint8_t mpa_state; 778 uint8_t mpa_init_state; 779 uint8_t mpa_res[24]; 780 } __packed; 781 782 struct mfi_ld_span { 783 u_quad_t mls_start_block; 784 u_quad_t mls_no_blocks; 785 uint16_t mls_index; 786 uint8_t mls_res[6]; 787 } __packed; 788 789 struct mfi_ld_cfg { 790 struct mfi_ld_prop mlc_prop; 791 struct mfi_ld_parm mlc_parm; 792 struct mfi_ld_span mlc_span[MFI_MAX_SPAN]; 793 } __packed; 794 795 struct mfi_ld_progress { 796 uint32_t mlp_in_prog; 797 #define MFI_LD_PROG_CC 0x01 798 #define MFI_LD_PROG_BGI 0x02 799 #define MFI_LD_PROG_FGI 0x04 800 #define MFI_LD_PROG_RECONSTRUCT 0x08 801 struct mfi_progress mlp_cc; 802 struct mfi_progress mlp_bgi; 803 struct mfi_progress mlp_fgi; 804 struct mfi_progress mlp_reconstruct; 805 struct mfi_progress mlp_res[4]; 806 } __packed; 807 808 struct mfi_ld_details { 809 struct mfi_ld_cfg mld_cfg; 810 u_quad_t mld_size; 811 struct mfi_ld_progress mld_progress; 812 uint16_t mld_clust_own_id; 813 uint8_t mld_res1; 814 uint8_t mld_res2; 815 uint8_t mld_inq_page83[64]; 816 uint8_t mld_res[16]; 817 } __packed; 818 819 /* physical disk info from MR_DCMD_PD_GET_LIST */ 820 struct mfi_pd_address { 821 uint16_t mpa_pd_id; 822 uint16_t mpa_enc_id; 823 uint8_t mpa_enc_index; 824 uint8_t mpa_enc_slot; 825 uint8_t mpa_scsi_type; 826 uint8_t mpa_port; 827 u_quad_t mpa_sas_address[2]; 828 } __packed; 829 830 struct mfi_pd_list { 831 uint32_t mpl_size; 832 uint32_t mpl_no_pd; 833 struct mfi_pd_address mpl_address[MFI_MAX_PD]; 834 } __packed; 835 836 struct mfi_pd { 837 uint16_t mfp_id; 838 uint16_t mfp_seq; 839 } __packed; 840 841 struct mfi_pd_progress { 842 uint32_t mfp_in_prog; 843 #define MFI_PD_PROG_RBLD 0x01 844 #define MFI_PD_PROG_PR 0x02 845 #define MFI_PD_PROG_CLEAR 0x04 846 struct mfi_progress mfp_rebuild; 847 struct mfi_progress mfp_patrol_read; 848 struct mfi_progress mfp_clear; 849 struct mfi_progress mfp_res[4]; 850 } __packed; 851 852 struct mfi_pd_details { 853 struct mfi_pd mpd_pd; 854 uint8_t mpd_inq_data[96]; 855 uint8_t mpd_inq_page83[64]; 856 uint8_t mpd_no_support; 857 uint8_t mpd_scsi_type; 858 uint8_t mpd_port; 859 uint8_t mpd_speed; 860 uint32_t mpd_mediaerr_cnt; 861 uint32_t mpd_othererr_cnt; 862 uint32_t mpd_predfail_cnt; 863 uint32_t mpd_last_pred_event; 864 uint16_t mpd_fw_state; 865 uint8_t mpd_rdy_for_remove; 866 uint8_t mpd_link_speed; 867 uint32_t mpd_ddf_state; 868 #define MFI_DDF_GUID_FORCED 0x01 869 #define MFI_DDF_PART_OF_VD 0x02 870 #define MFI_DDF_GLOB_HOTSPARE 0x04 871 #define MFI_DDF_HOTSPARE 0x08 872 #define MFI_DDF_FOREIGN 0x10 873 #define MFI_DDF_TYPE_MASK 0xf000 874 #define MFI_DDF_TYPE_UNKNOWN 0x0000 875 #define MFI_DDF_TYPE_PAR_SCSI 0x1000 876 #define MFI_DDF_TYPE_SAS 0x2000 877 #define MFI_DDF_TYPE_SATA 0x3000 878 #define MFI_DDF_TYPE_FC 0x4000 879 struct { 880 uint8_t mpp_cnt; 881 uint8_t mpp_severed; 882 uint8_t mpp_connector_idx[2]; 883 uint8_t mpp_res[4]; 884 u_quad_t mpp_sas_addr[2]; 885 uint8_t mpp_res2[16]; 886 } __packed mpd_path; 887 u_quad_t mpd_size; 888 u_quad_t mpd_no_coerce_size; 889 u_quad_t mpd_coerce_size; 890 uint16_t mpd_enc_id; 891 uint8_t mpd_enc_idx; 892 uint8_t mpd_enc_slot; 893 struct mfi_pd_progress mpd_progress; 894 uint8_t mpd_bblock_full; 895 uint8_t mpd_unusable; 896 uint8_t mpd_inq_page83_ext[64]; 897 uint8_t mpd_power_state; /* XXX */ 898 uint8_t mpd_enc_pos; 899 uint32_t mpd_allowed_ops; 900 #define MFI_PD_A_ONLINE (1<<0) 901 #define MFI_PD_A_OFFLINE (1<<1) 902 #define MFI_PD_A_FAILED (1<<2) 903 #define MFI_PD_A_BAD (1<<3) 904 #define MFI_PD_A_UNCONFIG (1<<4) 905 #define MFI_PD_A_HOTSPARE (1<<5) 906 #define MFI_PD_A_REMOVEHOTSPARE (1<<6) 907 #define MFI_PD_A_REPLACEMISSING (1<<7) 908 #define MFI_PD_A_MARKMISSING (1<<8) 909 #define MFI_PD_A_STARTREBUILD (1<<9) 910 #define MFI_PD_A_STOPREBUILD (1<<10) 911 #define MFI_PD_A_BLINK (1<<11) 912 #define MFI_PD_A_CLEAR (1<<12) 913 #define MFI_PD_A_FOREIGNIMPORNOTALLOWED (1<<13) 914 #define MFI_PD_A_STARTCOPYBACK (1<<14) 915 #define MFI_PD_A_STOPCOPYBACK (1<<15) 916 #define MFI_PD_A_FWDOWNLOADDNOTALLOWED (1<<16) 917 #define MFI_PD_A_REPROVISION (1<<17) 918 uint16_t mpd_copyback_partner_id; 919 uint16_t mpd_enc_partner_devid; 920 uint16_t mpd_security; 921 #define MFI_PD_FDE_CAPABLE (1<<0) 922 #define MFI_PD_FDE_ENABLED (1<<1) 923 #define MFI_PD_FDE_SECURED (1<<2) 924 #define MFI_PD_FDE_LOCKED (1<<3) 925 #define MFI_PD_FDE_FOREIGNLOCK (1<<4) 926 uint8_t mpd_media; 927 uint8_t mpd_res[141]; /* size is 512 */ 928 } __packed; 929 930 struct mfi_pd_allowedops_list { 931 uint32_t mpo_no_entries; 932 uint32_t mpo_res; 933 uint32_t mpo_allowedops_list[MFI_MAX_PD]; 934 } __packed; 935 936 /* array configuration from MR_DCMD_CONF_GET */ 937 struct mfi_array { 938 u_quad_t mar_smallest_pd; 939 uint8_t mar_no_disk; 940 uint8_t mar_res1; 941 uint16_t mar_array_ref; 942 uint8_t mar_res2[20]; 943 struct { 944 struct mfi_pd mar_pd; 945 uint16_t mar_pd_state; 946 #define MFI_PD_UNCONFIG_GOOD 0x00 947 #define MFI_PD_UNCONFIG_BAD 0x01 948 #define MFI_PD_HOTSPARE 0x02 949 #define MFI_PD_OFFLINE 0x10 950 #define MFI_PD_FAILED 0x11 951 #define MFI_PD_REBUILD 0x14 952 #define MFI_PD_ONLINE 0x18 953 #define MFI_PD_COPYBACK 0x20 954 #define MFI_PD_SYSTEM 0x40 955 uint8_t mar_enc_pd; 956 uint8_t mar_enc_slot; 957 } pd[MFI_MAX_PD_ARRAY]; 958 } __packed; 959 960 struct mfi_hotspare { 961 struct mfi_pd mhs_pd; 962 uint8_t mhs_type; 963 #define MFI_PD_HS_DEDICATED 0x01 964 #define MFI_PD_HS_REVERTIBLE 0x02 965 #define MFI_PD_HS_ENC_AFFINITY 0x04 966 uint8_t mhs_res[2]; 967 uint8_t mhs_array_max; 968 uint16_t mhs_array_ref[MFI_MAX_ARRAY_DEDICATED]; 969 } __packed; 970 971 struct mfi_conf { 972 uint32_t mfc_size; 973 uint16_t mfc_no_array; 974 uint16_t mfc_array_size; 975 uint16_t mfc_no_ld; 976 uint16_t mfc_ld_size; 977 uint16_t mfc_no_hs; 978 uint16_t mfc_hs_size; 979 uint8_t mfc_res[16]; 980 /* 981 * XXX this is a ridiculous hack and does not reflect reality 982 * Structures are actually indexed and therefore need pointer 983 * math to reach. We need the size of this structure first so 984 * call it with the size of this structure and then use the returned 985 * values to allocate memory and do the transfer of the whole structure 986 * then calculate pointers to each of these structures. 987 */ 988 struct mfi_array mfc_array[1]; 989 struct mfi_ld_cfg mfc_ld[1]; 990 struct mfi_hotspare mfc_hs[1]; 991 } __packed; 992 993 struct mfi_bbu_capacity_info { 994 uint16_t relative_charge; 995 uint16_t absolute_charge; 996 uint16_t remaining_capacity; 997 uint16_t full_charge_capacity; 998 uint16_t run_time_to_empty; 999 uint16_t average_time_to_empty; 1000 uint16_t average_time_to_full; 1001 uint16_t cycle_count; 1002 uint16_t max_error; 1003 uint16_t remaining_capacity_alarm; 1004 uint16_t remaining_time_alarm; 1005 uint8_t reserved[26]; 1006 } __packed; 1007 1008 struct mfi_bbu_design_info { 1009 uint32_t mfg_date; 1010 uint16_t design_capacity; 1011 uint16_t design_voltage; 1012 uint16_t spec_info; 1013 uint16_t serial_number; 1014 uint16_t pack_stat_config; 1015 uint8_t mfg_name[12]; 1016 uint8_t device_name[8]; 1017 uint8_t device_chemistry[8]; 1018 uint8_t mfg_data[8]; 1019 uint8_t reserved[17]; 1020 } __packed; 1021 1022 struct mfi_ibbu_state { 1023 uint16_t gas_guage_status; 1024 uint16_t relative_charge; 1025 uint16_t charger_system_state; 1026 uint16_t charger_system_ctrl; 1027 uint16_t charging_current; 1028 uint16_t absolute_charge; 1029 uint16_t max_error; 1030 uint8_t reserved[18]; 1031 } __packed; 1032 1033 struct mfi_bbu_state { 1034 uint16_t gas_guage_status; 1035 uint16_t relative_charge; 1036 uint16_t charger_status; 1037 uint16_t remaining_capacity; 1038 uint16_t full_charge_capacity; 1039 uint8_t is_SOH_good; 1040 uint8_t reserved[21]; 1041 } __packed; 1042 1043 struct mfi_bbu_properties { 1044 uint32_t auto_learn_period; 1045 uint32_t next_learn_time; 1046 uint8_t learn_delay_interval; 1047 uint8_t auto_learn_mode; 1048 uint8_t bbu_mode; 1049 uint8_t reserved[21]; 1050 } __packed; 1051 1052 union mfi_bbu_status_detail { 1053 struct mfi_ibbu_state ibbu; 1054 struct mfi_bbu_state bbu; 1055 }; 1056 1057 struct mfi_bbu_status { 1058 uint8_t battery_type; 1059 #define MFI_BBU_TYPE_NONE 0 1060 #define MFI_BBU_TYPE_IBBU 1 1061 #define MFI_BBU_TYPE_BBU 2 1062 uint8_t reserved; 1063 uint16_t voltage; 1064 int16_t current; 1065 uint16_t temperature; 1066 uint32_t fw_status; 1067 #define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1068 #define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1069 #define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1070 #define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 3) 1071 #define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 4) 1072 #define MFI_BBU_STATE_LEARN_CYC_REQ (1 << 5) 1073 #define MFI_BBU_STATE_LEARN_CYC_ACTIVE (1 << 6) 1074 #define MFI_BBU_STATE_LEARN_CYC_FAIL (1 << 7) 1075 #define MFI_BBU_STATE_LEARN_CYC_TIMEOUT (1 << 8) 1076 #define MFI_BBU_STATE_I2C_ERR_DETECT (1 << 9) 1077 #define MFI_BBU_STATE_REPLACE_PACK (1 << 10) 1078 #define MFI_BBU_STATE_CAPACITY_LOW (1 << 11) 1079 #define MFI_BBU_STATE_LEARN_REQUIRED (1 << 12) 1080 #define MFI_BBU_STATE_FMT "\020" \ 1081 "\001PACK_MISSING" \ 1082 "\002VOLTAGE_LOW" \ 1083 "\003TEMP_HIGH" \ 1084 "\004CHARGE_ACTIVE" \ 1085 "\005DISCHARGE_ACTIVE" \ 1086 "\006LEARN_CYC_REQ" \ 1087 "\007LEARN_CYC_ACTIVE" \ 1088 "\010LEARN_CYC_FAIL" \ 1089 "\011LEARN_CYC_TIMEOUT" \ 1090 "\012I2C_ERR_DETECT" \ 1091 "\013REPLACE_PACK" \ 1092 "\014CAPACITY_LOW" \ 1093 "\015LEARN_REQUIRED" 1094 1095 uint8_t pad[20]; 1096 union mfi_bbu_status_detail detail; 1097 } __packed; 1098 1099