1 /* $OpenBSD: mfireg.h,v 1.50 2020/02/13 15:11:32 krw Exp $ */ 2 /* 3 * Copyright (c) 2006 Marco Peereboom <marco@peereboom.us> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 /* management interface constants */ 19 #define MFI_MGMT_VD 0x01 20 #define MFI_MGMT_SD 0x02 21 22 /* generic constants */ 23 #define MFI_FRAME_SIZE 64 24 #define MFI_SENSE_SIZE 128 25 #define MFI_OSTS_INTR_VALID 0x00000002 /* valid interrupt */ 26 #define MFI_OSTS_PPC_INTR_VALID 0x80000000 27 #define MFI_OSTS_GEN2_INTR_VALID (0x00000001 | 0x00000004) 28 #define MFI_INVALID_CTX 0xffffffff 29 #define MFI_ENABLE_INTR 0x01 30 31 /* register offsets */ 32 #define MFI_IMSG0 0x10 /* inbound msg 0 */ 33 #define MFI_IMSG1 0x14 /* inbound msg 1 */ 34 #define MFI_OMSG0 0x18 /* outbound msg 0 */ 35 #define MFI_OMSG1 0x1c /* outbound msg 1 */ 36 #define MFI_IDB 0x20 /* inbound doorbell */ 37 #define MFI_ISTS 0x24 /* inbound intr stat */ 38 #define MFI_IMSK 0x28 /* inbound intr mask */ 39 #define MFI_ODB 0x2c /* outbound doorbell */ 40 #define MFI_OSTS 0x30 /* outbound intr stat */ 41 #define MFI_OMSK 0x34 /* outbound inter mask */ 42 #define MFI_IQP 0x40 /* inbound queue port */ 43 #define MFI_OQP 0x44 /* outbound queue port */ 44 #define MFI_ODC 0xa0 /* outbound doorbell clr */ 45 #define MFI_OSP 0xb0 /* outbound scratch pad */ 46 47 /* 48 * skinny specific changes 49 */ 50 #define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 51 #define MFI_IQPL 0x000000c0 52 #define MFI_IQPH 0x000000c4 53 #define MFI_OSTS_SKINNY_INTR_VALID 0x00000001 54 55 /* * firmware states */ 56 #define MFI_STATE_MASK 0xf0000000 57 #define MFI_STATE_UNDEFINED 0x00000000 58 #define MFI_STATE_BB_INIT 0x10000000 59 #define MFI_STATE_FW_INIT 0x40000000 60 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 61 #define MFI_STATE_FW_INIT_2 0x70000000 62 #define MFI_STATE_DEVICE_SCAN 0x80000000 63 #define MFI_STATE_FLUSH_CACHE 0xa0000000 64 #define MFI_STATE_READY 0xb0000000 65 #define MFI_STATE_OPERATIONAL 0xc0000000 66 #define MFI_STATE_FAULT 0xf0000000 67 #define MFI_STATE_MAXSGL_MASK 0x00ff0000 68 #define MFI_STATE_MAXCMD_MASK 0x0000ffff 69 70 /* command reset register */ 71 #define MFI_INIT_ABORT 0x00000000 72 #define MFI_INIT_READY 0x00000002 73 #define MFI_INIT_MFIMODE 0x00000004 74 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 75 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE 76 77 /* mfi Frame flags */ 78 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 79 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 80 #define MFI_FRAME_SGL32 0x0000 81 #define MFI_FRAME_SGL64 0x0002 82 #define MFI_FRAME_SENSE32 0x0000 83 #define MFI_FRAME_SENSE64 0x0004 84 #define MFI_FRAME_DIR_NONE 0x0000 85 #define MFI_FRAME_DIR_WRITE 0x0008 86 #define MFI_FRAME_DIR_READ 0x0010 87 #define MFI_FRAME_DIR_BOTH 0x0018 88 #define MFI_FRAME_IEEE 0x0020 89 90 /* mfi command opcodes */ 91 #define MFI_CMD_INIT 0x00 92 #define MFI_CMD_LD_READ 0x01 93 #define MFI_CMD_LD_WRITE 0x02 94 #define MFI_CMD_LD_SCSI_IO 0x03 95 #define MFI_CMD_PD_SCSI_IO 0x04 96 #define MFI_CMD_DCMD 0x05 97 #define MFI_CMD_ABORT 0x06 98 #define MFI_CMD_SMP 0x07 99 #define MFI_CMD_STP 0x08 100 101 #define MFI_PR_STATE_STOPPED 0 102 #define MFI_PR_STATE_READY 1 103 #define MFI_PR_STATE_ACTIVE 2 104 #define MFI_PR_STATE_ABORTED 0xff 105 106 #define MFI_PR_OPMODE_AUTO 0x00 107 #define MFI_PR_OPMODE_MANUAL 0x01 108 #define MFI_PR_OPMODE_DISABLED 0x02 109 110 /* direct commands */ 111 #define MR_DCMD_CTRL_GET_INFO 0x01010000 112 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 113 #define MR_FLUSH_CTRL_CACHE 0x01 114 #define MR_FLUSH_DISK_CACHE 0x02 115 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 116 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 117 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 118 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 119 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 120 #define MR_DCMD_PR_GET_STATUS 0x01070100 121 #define MR_DCMD_PR_GET_PROPERTIES 0x01070200 122 #define MR_DCMD_PR_SET_PROPERTIES 0x01070300 123 #define MR_DCMD_PR_START 0x01070400 124 #define MR_DCMD_PR_STOP 0x01070500 125 #define MR_DCMD_TIME_SECS_GET 0x01080201 126 #define MR_DCMD_PD_GET_LIST 0x02010000 127 #define MR_DCMD_PD_GET_INFO 0x02020000 128 #define MR_DCMD_PD_SET_STATE 0x02030100 129 #define MR_DCMD_PD_REBUILD 0x02040100 130 #define MR_DCMD_PD_BLINK 0x02070100 131 #define MR_DCMD_PD_UNBLINK 0x02070200 132 #define MR_DCMD_PD_GET_ALLOWED_OPS_LIST 0x020a0100 133 #define MR_DCMD_LD_GET_LIST 0x03010000 134 #define MR_DCMD_LD_GET_INFO 0x03020000 135 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 136 #define MR_DCMD_LD_SET_PROPERTIES 0x03040000 137 #define MR_DCMD_LD_DELETE 0x03090000 138 #define MR_DCMD_CONF_GET 0x04010000 139 #define MR_DCMD_CFG_ADD 0x04020000 140 #define MR_DCMD_CFG_CLEAR 0x04030000 141 #define MR_DCMD_CFG_MAKE_SPARE 0x04040000 142 #define MR_DCMD_CFG_FOREIGN_SCAN 0x04060100 143 #define MR_DCMD_CFG_FOREIGN_CLEAR 0x04060500 144 #define MR_DCMD_BBU_GET_STATUS 0x05010000 145 #define MR_DCMD_BBU_GET_CAPACITY_INFO 0x05020000 146 #define MR_DCMD_BBU_GET_DESIGN_INFO 0x05030000 147 #define MR_DCMD_BBU_START_LEARN 0x05040000 148 #define MR_DCMD_BBU_GET_PROP 0x05050100 149 #define MR_DCMD_BBU_SET_PROP 0x05050200 150 #define MR_DCMD_CLUSTER 0x08000000 151 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 152 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 153 154 #define MR_DCMD_SPEAKER_GET 0x01030100 155 #define MR_DCMD_SPEAKER_ENABLE 0x01030200 156 #define MR_DCMD_SPEAKER_DISABLE 0x01030300 157 #define MR_DCMD_SPEAKER_SILENCE 0x01030400 158 #define MR_DCMD_SPEAKER_TEST 0x01030500 159 160 #define MR_LD_CACHE_WRITE_BACK 0x01 161 #define MR_LD_CACHE_WRITE_ADAPTIVE 0x02 162 #define MR_LD_CACHE_READ_AHEAD 0x04 163 #define MR_LD_CACHE_READ_ADAPTIVE 0x08 164 #define MR_LD_CACHE_WRITE_CACHE_BAD_BBU 0x10 165 #define MR_LD_CACHE_ALLOW_WRITE_CACHE 0x20 166 #define MR_LD_CACHE_ALLOW_READ_CACHE 0x40 167 168 #define MR_LD_DISK_CACHE_ENABLE 0x01 169 #define MR_LD_DISK_CACHE_DISABLE 0x02 170 171 /* mailbox bytes in direct command */ 172 #define MFI_MBOX_SIZE 12 173 174 union mfi_mbox { 175 uint8_t b[MFI_MBOX_SIZE]; 176 uint16_t s[6]; 177 uint32_t w[3]; 178 } __packed __aligned(4); 179 180 /* mfi completion codes */ 181 typedef enum { 182 MFI_STAT_OK = 0x00, 183 MFI_STAT_INVALID_CMD = 0x01, 184 MFI_STAT_INVALID_DCMD = 0x02, 185 MFI_STAT_INVALID_PARAMETER = 0x03, 186 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 187 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 188 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 189 MFI_STAT_APP_IN_USE = 0x07, 190 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 191 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 192 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 193 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 194 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 195 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 196 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 197 MFI_STAT_FLASH_BUSY = 0x0f, 198 MFI_STAT_FLASH_ERROR = 0x10, 199 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 200 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 201 MFI_STAT_FLASH_NOT_OPEN = 0x13, 202 MFI_STAT_FLASH_NOT_STARTED = 0x14, 203 MFI_STAT_FLUSH_FAILED = 0x15, 204 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 205 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 206 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 207 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 208 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 209 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 210 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 211 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 212 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 213 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 214 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 215 MFI_STAT_MFC_HW_ERROR = 0x21, 216 MFI_STAT_NO_HW_PRESENT = 0x22, 217 MFI_STAT_NOT_FOUND = 0x23, 218 MFI_STAT_NOT_IN_ENCL = 0x24, 219 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 220 MFI_STAT_PD_TYPE_WRONG = 0x26, 221 MFI_STAT_PR_DISABLED = 0x27, 222 MFI_STAT_ROW_INDEX_INVALID = 0x28, 223 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 224 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 225 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 226 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 227 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 228 MFI_STAT_SCSI_IO_FAILED = 0x2e, 229 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 230 MFI_STAT_SHUTDOWN_FAILED = 0x30, 231 MFI_STAT_TIME_NOT_SET = 0x31, 232 MFI_STAT_WRONG_STATE = 0x32, 233 MFI_STAT_LD_OFFLINE = 0x33, 234 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 235 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 236 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 237 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 238 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 239 MFI_STAT_INVALID_STATUS = 0xff 240 } mfi_status_t; 241 242 typedef enum { 243 MFI_EVT_CLASS_DEBUG = -2, 244 MFI_EVT_CLASS_PROGRESS = -1, 245 MFI_EVT_CLASS_INFO = 0, 246 MFI_EVT_CLASS_WARNING = 1, 247 MFI_EVT_CLASS_CRITICAL = 2, 248 MFI_EVT_CLASS_FATAL = 3, 249 MFI_EVT_CLASS_DEAD = 4 250 } mfi_evt_class_t; 251 252 typedef enum { 253 MFI_EVT_LOCALE_LD = 0x0001, 254 MFI_EVT_LOCALE_PD = 0x0002, 255 MFI_EVT_LOCALE_ENCL = 0x0004, 256 MFI_EVT_LOCALE_BBU = 0x0008, 257 MFI_EVT_LOCALE_SAS = 0x0010, 258 MFI_EVT_LOCALE_CTRL = 0x0020, 259 MFI_EVT_LOCALE_CONFIG = 0x0040, 260 MFI_EVT_LOCALE_CLUSTER = 0x0080, 261 MFI_EVT_LOCALE_ALL = 0xffff 262 } mfi_evt_locale_t; 263 264 #define MFI_EVT_ARGS_NONE 0x00 265 #define MFI_EVT_ARGS_CDB_SENSE 0x01 266 #define MFI_EVT_ARGS_LD 0x02 267 #define MFI_EVT_ARGS_LD_COUNT 0x03 268 #define MFI_EVT_ARGS_LD_LBA 0x04 269 #define MFI_EVT_ARGS_LD_OWNER 0x05 270 #define MFI_EVT_ARGS_LD_LBA_PD_LBA 0x06 271 #define MFI_EVT_ARGS_LD_PROG 0x07 272 #define MFI_EVT_ARGS_LD_STATE 0x08 273 #define MFI_EVT_ARGS_LD_STRIP 0x09 274 #define MFI_EVT_ARGS_PD 0x0a 275 #define MFI_EVT_ARGS_PD_ERR 0x0b 276 #define MFI_EVT_ARGS_PD_LBA 0x0c 277 #define MFI_EVT_ARGS_PD_LBA_LD 0x0d 278 #define MFI_EVT_ARGS_PD_PROG 0x0e 279 #define MFI_EVT_ARGS_PD_STATE 0x0f 280 #define MFI_EVT_ARGS_PCI 0x10 281 #define MFI_EVT_ARGS_RATE 0x11 282 #define MFI_EVT_ARGS_STR 0x12 283 #define MFI_EVT_ARGS_TIME 0x13 284 #define MFI_EVT_ARGS_ECC 0x14 285 #define MFI_EVT_ARGS_LD_PROP 0x15 286 #define MFI_EVT_ARGS_PD_SPARE 0x16 287 #define MFI_EVT_ARGS_PD_INDEX 0x17 288 #define MFI_EVT_ARGS_DIAG_PASS 0x18 289 #define MFI_EVT_ARGS_DIAG_FAIL 0x19 290 #define MFI_EVT_ARGS_PD_LBA_LBA 0x1a 291 #define MFI_EVT_ARGS_PORT_PHY 0x1b 292 #define MFI_EVT_ARGS_PD_MISSING 0x1c 293 #define MFI_EVT_ARGS_PD_ADDRESS 0x1d 294 #define MFI_EVT_ARGS_BITMAP 0x1e 295 #define MFI_EVT_ARGS_CONNECTOR 0x1f 296 #define MFI_EVT_ARGS_PD_PD 0x20 297 #define MFI_EVT_ARGS_PD_FRU 0x21 298 #define MFI_EVT_ARGS_PD_PATHINFO 0x22 299 #define MFI_EVT_ARGS_PD_POWER_STATE 0x23 300 #define MFI_EVT_ARGS_GENERIC 0x24 301 302 #define MFI_EVT_CFG_CLEARED 0x0004 303 #define MFI_EVT_LD_STATE_CHANGE 0x0051 304 #define MFI_EVT_PD_INSERTED 0x005b 305 #define MFI_EVT_PD_REMOVED 0x0070 306 #define MFI_EVT_PD_STATE_CHANGE 0x0072 307 #define MFI_EVT_LD_CREATED 0x008a 308 #define MFI_EVT_LD_DELETED 0x008b 309 #define MFI_EVT_FOREIGN_CFG_IMPORTED 0x00db 310 #define MFI_EVT_PD_REMOVED_EXT 0x00f8 311 #define MFI_EVT_PD_INSERTED_EXT 0x00f7 312 #define MFI_EVT_LD_OFFLINE 0x00fc 313 #define MFI_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 314 #define MFI_EVT_CTRL_PROP_CHANGED 0x012f 315 316 /* driver definitions */ 317 #define MFI_MAX_PD_CHANNELS 2 318 #define MFI_MAX_PD_ARRAY 32 319 #define MFI_MAX_LD_CHANNELS 2 320 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 321 #define MFI_MAX_CHANNEL_DEVS 128 322 #define MFI_DEFAULT_ID -1 323 #define MFI_MAX_LUN 8 324 #define MFI_MAX_LD 64 325 #define MFI_MAX_SPAN 8 326 #define MFI_MAX_ARRAY_DEDICATED 16 327 #define MFI_MAX_PD 256 328 329 /* sense buffer */ 330 struct mfi_sense { 331 uint8_t mse_data[MFI_SENSE_SIZE]; 332 } __packed; 333 334 /* scatter gather elements */ 335 struct mfi_sg32 { 336 uint32_t addr; 337 uint32_t len; 338 } __packed; 339 340 struct mfi_sg64 { 341 uint64_t addr; 342 uint32_t len; 343 } __packed; 344 345 struct mfi_sg_skinny { 346 uint64_t addr; 347 uint32_t len; 348 uint32_t flag; 349 } __packed; 350 351 union mfi_sgl { 352 struct mfi_sg32 sg32[1]; 353 struct mfi_sg64 sg64[1]; 354 struct mfi_sg_skinny sg_skinny[1]; 355 } __packed; 356 357 /* message frame */ 358 struct mfi_frame_header { 359 uint8_t mfh_cmd; 360 uint8_t mfh_sense_len; 361 uint8_t mfh_cmd_status; 362 uint8_t mfh_scsi_status; 363 uint8_t mfh_target_id; 364 uint8_t mfh_lun_id; 365 uint8_t mfh_cdb_len; 366 uint8_t mfh_sg_count; 367 uint32_t mfh_context; 368 uint32_t mfh_pad0; 369 uint16_t mfh_flags; 370 uint16_t mfh_timeout; 371 uint32_t mfh_data_len; 372 } __packed; 373 374 union mfi_sgl_frame { 375 struct mfi_sg32 sge32[8]; 376 struct mfi_sg64 sge64[5]; 377 378 } __packed; 379 380 struct mfi_init_frame { 381 struct mfi_frame_header mif_header; 382 uint64_t mif_qinfo_new_addr; 383 uint64_t mif_qinfo_old_addr; 384 uint32_t mif_reserved[6]; 385 } __packed; 386 387 /* queue init structure */ 388 struct mfi_init_qinfo { 389 uint32_t miq_flags; 390 uint32_t miq_rq_entries; 391 uint64_t miq_rq_addr; 392 uint64_t miq_pi_addr; 393 uint64_t miq_ci_addr; 394 } __packed; 395 396 #define MFI_IO_FRAME_SIZE 40 397 struct mfi_io_frame { 398 struct mfi_frame_header mif_header; 399 uint64_t mif_sense_addr; 400 uint64_t mif_lba; 401 union mfi_sgl mif_sgl; 402 } __packed; 403 404 #define MFI_PASS_FRAME_SIZE 48 405 struct mfi_pass_frame { 406 struct mfi_frame_header mpf_header; 407 uint64_t mpf_sense_addr; 408 uint8_t mpf_cdb[16]; 409 union mfi_sgl mpf_sgl; 410 } __packed; 411 412 #define MFI_DCMD_FRAME_SIZE 40 413 struct mfi_dcmd_frame { 414 struct mfi_frame_header mdf_header; 415 uint32_t mdf_opcode; 416 union mfi_mbox mdf_mbox; 417 union mfi_sgl mdf_sgl; 418 } __packed; 419 420 struct mfi_abort_frame { 421 struct mfi_frame_header maf_header; 422 uint32_t maf_abort_context; 423 uint32_t maf_pad; 424 uint64_t maf_abort_mfi_addr; 425 uint32_t maf_reserved[6]; 426 } __packed; 427 428 struct mfi_smp_frame { 429 struct mfi_frame_header msf_header; 430 uint64_t msf_sas_addr; 431 union { 432 struct mfi_sg32 sg32[2]; 433 struct mfi_sg64 sg64[2]; 434 } msf_sgl; 435 } __packed; 436 437 struct mfi_stp_frame { 438 struct mfi_frame_header msf_header; 439 uint16_t msf_fis[10]; 440 uint32_t msf_stp_flags; 441 union { 442 struct mfi_sg32 sg32[2]; 443 struct mfi_sg64 sg64[2]; 444 } msf_sgl; 445 } __packed; 446 447 union mfi_frame { 448 struct mfi_frame_header mfr_header; 449 struct mfi_init_frame mfr_init; 450 struct mfi_io_frame mfr_io; 451 struct mfi_pass_frame mfr_pass; 452 struct mfi_dcmd_frame mfr_dcmd; 453 struct mfi_abort_frame mfr_abort; 454 struct mfi_smp_frame mfr_smp; 455 struct mfi_stp_frame mfr_stp; 456 uint8_t mfr_bytes[MFI_FRAME_SIZE]; 457 }; 458 459 union mfi_evt_class_locale { 460 struct { 461 uint16_t locale; 462 uint8_t reserved; 463 int8_t class; 464 } __packed mec_members; 465 466 uint32_t mec_word; 467 } __packed; 468 469 struct mfi_evt_log_info { 470 uint32_t mel_newest_seq_num; 471 uint32_t mel_oldest_seq_num; 472 uint32_t mel_clear_seq_num; 473 uint32_t mel_shutdown_seq_num; 474 uint32_t mel_boot_seq_num; 475 } __packed; 476 477 struct mfi_progress { 478 uint16_t mp_progress; 479 uint16_t mp_elapsed_seconds; 480 } __packed; 481 482 struct mfi_evtarg_ld { 483 uint16_t mel_target_id; 484 uint8_t mel_ld_index; 485 uint8_t mel_reserved; 486 } __packed; 487 488 struct mfi_evtarg_pd { 489 uint16_t mep_device_id; 490 uint8_t mep_encl_index; 491 uint8_t mep_slot_number; 492 } __packed; 493 494 struct mfi_evtarg_pd_state { 495 struct mfi_evtarg_pd pd; 496 uint32_t prev_state; 497 uint32_t new_state; 498 } __packed; 499 500 struct mfi_evtarg_pd_address { 501 uint16_t device_id; 502 uint16_t encl_id; 503 504 union { 505 struct { 506 uint8_t encl_index; 507 uint8_t slot_number; 508 } __packed pd_address; 509 struct { 510 uint8_t encl_position; 511 uint8_t encl_connector_index; 512 } __packed encl_address; 513 } __packed address; 514 515 uint8_t scsi_dev_type; 516 517 union { 518 uint8_t port_bitmap; 519 uint8_t port_numbers; 520 } __packed connected; 521 522 uint64_t sas_addr[2]; 523 } __packed __aligned(8); 524 525 struct mfi_evt_detail { 526 uint32_t med_seq_num; 527 uint32_t med_time_stamp; 528 uint32_t med_code; 529 union mfi_evt_class_locale med_cl; 530 uint8_t med_arg_type; 531 uint8_t med_reserved1[15]; 532 533 union { 534 struct { 535 struct mfi_evtarg_pd pd; 536 uint8_t cdb_length; 537 uint8_t sense_length; 538 uint8_t reserved[2]; 539 uint8_t cdb[16]; 540 uint8_t sense[64]; 541 } __packed cdb_sense; 542 543 struct mfi_evtarg_ld ld; 544 545 struct { 546 struct mfi_evtarg_ld ld; 547 uint64_t count; 548 } __packed ld_count; 549 550 struct { 551 uint64_t lba; 552 struct mfi_evtarg_ld ld; 553 } __packed ld_lba; 554 555 struct { 556 struct mfi_evtarg_ld ld; 557 uint32_t prev_owner; 558 uint32_t new_owner; 559 } __packed ld_owner; 560 561 struct { 562 uint64_t ld_lba; 563 uint64_t pd_lba; 564 struct mfi_evtarg_ld ld; 565 struct mfi_evtarg_pd pd; 566 } __packed ld_lba_pd_lba; 567 568 struct { 569 struct mfi_evtarg_ld ld; 570 struct mfi_progress prog; 571 } __packed ld_prog; 572 573 struct { 574 struct mfi_evtarg_ld ld; 575 uint32_t prev_state; 576 uint32_t new_state; 577 } __packed ld_state; 578 579 struct { 580 uint64_t strip; 581 struct mfi_evtarg_ld ld; 582 } __packed ld_strip; 583 584 struct mfi_evtarg_pd pd; 585 586 struct { 587 struct mfi_evtarg_pd pd; 588 uint32_t err; 589 } __packed pd_err; 590 591 struct { 592 uint64_t lba; 593 struct mfi_evtarg_pd pd; 594 } __packed pd_lba; 595 596 struct { 597 uint64_t lba; 598 struct mfi_evtarg_pd pd; 599 struct mfi_evtarg_ld ld; 600 } __packed pd_lba_ld; 601 602 struct { 603 struct mfi_evtarg_pd pd; 604 struct mfi_progress prog; 605 } __packed pd_prog; 606 607 struct mfi_evtarg_pd_state pd_state; 608 609 struct { 610 uint16_t vendor_id; 611 uint16_t device_id; 612 uint16_t subvendor_id; 613 uint16_t subdevice_id; 614 } __packed pci; 615 616 uint32_t rate; 617 char str[96]; 618 619 struct { 620 uint32_t rtc; 621 uint32_t elapsed_seconds; 622 } __packed time; 623 624 struct { 625 uint32_t ecar; 626 uint32_t elog; 627 char str[64]; 628 } __packed ecc; 629 630 struct mfi_evtarg_pd_address pd_address; 631 632 uint8_t b[96]; 633 uint16_t s[48]; 634 uint32_t w[24]; 635 uint64_t d[12]; 636 } args; 637 638 char med_description[128]; 639 } __packed; 640 641 /* controller properties from mfi_ctrl_info */ 642 struct mfi_ctrl_props { 643 uint16_t mcp_seq_num; 644 uint16_t mcp_pred_fail_poll_interval; 645 uint16_t mcp_intr_throttle_cnt; 646 uint16_t mcp_intr_throttle_timeout; 647 uint8_t mcp_rebuild_rate; 648 uint8_t mcp_patrol_read_rate; 649 uint8_t mcp_bgi_rate; 650 uint8_t mcp_cc_rate; 651 uint8_t mcp_recon_rate; 652 uint8_t mcp_cache_flush_interval; 653 uint8_t mcp_spinup_drv_cnt; 654 uint8_t mcp_spinup_delay; 655 uint8_t mcp_cluster_enable; 656 uint8_t mcp_coercion_mode; 657 uint8_t mcp_alarm_enable; 658 uint8_t mcp_disable_auto_rebuild; 659 uint8_t mcp_disable_battery_warn; 660 uint8_t mcp_ecc_bucket_size; 661 uint16_t mcp_ecc_bucket_leak_rate; 662 uint8_t mcp_restore_hotspare_on_insertion; 663 uint8_t mcp_expose_encl_devices; 664 uint8_t mcp_reserved[38]; 665 } __packed; 666 667 /* pci info */ 668 struct mfi_info_pci { 669 uint16_t mip_vendor; 670 uint16_t mip_device; 671 uint16_t mip_subvendor; 672 uint16_t mip_subdevice; 673 uint8_t mip_reserved[24]; 674 } __packed; 675 676 /* host interface infor */ 677 struct mfi_info_host { 678 uint8_t mih_type; 679 #define MFI_INFO_HOST_PCIX 0x01 680 #define MFI_INFO_HOST_PCIE 0x02 681 #define MFI_INFO_HOST_ISCSI 0x04 682 #define MFI_INFO_HOST_SAS3G 0x08 683 uint8_t mih_reserved[6]; 684 uint8_t mih_port_count; 685 uint64_t mih_port_addr[8]; 686 } __packed; 687 688 /* device interface info */ 689 struct mfi_info_device { 690 uint8_t mid_type; 691 #define MFI_INFO_DEV_SPI 0x01 692 #define MFI_INFO_DEV_SAS3G 0x02 693 #define MFI_INFO_DEV_SATA1 0x04 694 #define MFI_INFO_DEV_SATA3G 0x08 695 uint8_t mid_reserved[6]; 696 uint8_t mid_port_count; 697 uint64_t mid_port_addr[8]; 698 } __packed; 699 700 /* firmware component info */ 701 struct mfi_info_component { 702 char mic_name[8]; 703 char mic_version[32]; 704 char mic_build_date[16]; 705 char mic_build_time[16]; 706 } __packed; 707 708 /* controller info from MFI_DCMD_CTRL_GETINFO. */ 709 struct mfi_ctrl_info { 710 struct mfi_info_pci mci_pci; 711 struct mfi_info_host mci_host; 712 struct mfi_info_device mci_device; 713 714 /* Firmware components that are present and active. */ 715 uint32_t mci_image_check_word; 716 uint32_t mci_image_component_count; 717 struct mfi_info_component mci_image_component[8]; 718 719 /* Firmware components that have been flashed but are inactive */ 720 uint32_t mci_pending_image_component_count; 721 struct mfi_info_component mci_pending_image_component[8]; 722 723 uint8_t mci_max_arms; 724 uint8_t mci_max_spans; 725 uint8_t mci_max_arrays; 726 uint8_t mci_max_lds; 727 char mci_product_name[80]; 728 char mci_serial_number[32]; 729 uint32_t mci_hw_present; 730 #define MFI_INFO_HW_BBU 0x01 731 #define MFI_INFO_HW_ALARM 0x02 732 #define MFI_INFO_HW_NVRAM 0x04 733 #define MFI_INFO_HW_UART 0x08 734 #define MFI_INFO_HW_FMT "\020" "\001BBU" "\002ALARM" "\003NVRAM" \ 735 "\004UART" 736 737 uint32_t mci_current_fw_time; 738 uint16_t mci_max_cmds; 739 uint16_t mci_max_sg_elements; 740 uint32_t mci_max_request_size; 741 uint16_t mci_lds_present; 742 uint16_t mci_lds_degraded; 743 uint16_t mci_lds_offline; 744 uint16_t mci_pd_present; 745 uint16_t mci_pd_disks_present; 746 uint16_t mci_pd_disks_pred_failure; 747 uint16_t mci_pd_disks_failed; 748 uint16_t mci_nvram_size; 749 uint16_t mci_memory_size; 750 uint16_t mci_flash_size; 751 uint16_t mci_ram_correctable_errors; 752 uint16_t mci_ram_uncorrectable_errors; 753 uint8_t mci_cluster_allowed; 754 uint8_t mci_cluster_active; 755 uint16_t mci_max_strips_per_io; 756 757 uint32_t mci_raid_levels; 758 #define MFI_INFO_RAID_0 0x01 759 #define MFI_INFO_RAID_1 0x02 760 #define MFI_INFO_RAID_5 0x04 761 #define MFI_INFO_RAID_1E 0x08 762 #define MFI_INFO_RAID_6 0x10 763 764 uint32_t mci_adapter_ops; 765 #define MFI_INFO_AOPS_RBLD_RATE 0x0001 766 #define MFI_INFO_AOPS_CC_RATE 0x0002 767 #define MFI_INFO_AOPS_BGI_RATE 0x0004 768 #define MFI_INFO_AOPS_RECON_RATE 0x0008 769 #define MFI_INFO_AOPS_PATROL_RATE 0x0010 770 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 771 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 772 #define MFI_INFO_AOPS_BBU 0x0080 773 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 774 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 775 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 776 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 777 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 778 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 779 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 780 #define MFI_INFO_AOPS_FMT "\020" "\001RBLD_RATE" "\002CC_RATE" \ 781 "\003BGI_RATE" "\004RECON_RATE" \ 782 "\005PATROL_RATE" "\006ALARM_CONTROL" \ 783 "\007CLUSTER_SUPPORT" "\010BBU" \ 784 "\011SPANNING_ALLOWED" \ 785 "\012DEDICATED_SPARES" \ 786 "\013REVERTIBLE_SPARES" \ 787 "\014FOREIGN_IMPORT" "\015SELF_DIAGNOSTIC" \ 788 "\016MIXED_ARRAY" "\017GLOBAL_SPARES" 789 790 uint32_t mci_ld_ops; 791 #define MFI_INFO_LDOPS_READ_POLICY 0x01 792 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02 793 #define MFI_INFO_LDOPS_IO_POLICY 0x04 794 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 795 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 796 797 struct { 798 uint8_t min; 799 uint8_t max; 800 uint8_t reserved[2]; 801 } __packed mci_stripe_sz_ops; 802 803 uint32_t mci_pd_ops; 804 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 805 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 806 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 807 808 uint32_t mci_pd_mix_support; 809 #define MFI_INFO_PDMIX_SAS 0x01 810 #define MFI_INFO_PDMIX_SATA 0x02 811 #define MFI_INFO_PDMIX_ENCL 0x04 812 #define MFI_INFO_PDMIX_LD 0x08 813 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 814 815 uint8_t mci_ecc_bucket_count; 816 uint8_t mci_reserved2[11]; 817 struct mfi_ctrl_props mci_properties; 818 char mci_package_version[0x60]; 819 uint8_t mci_pad[0x800 - 0x6a0]; 820 } __packed; 821 822 /* logical disk info from MR_DCMD_LD_GET_LIST */ 823 struct mfi_ld { 824 uint8_t mld_target; 825 uint8_t mld_res; 826 uint16_t mld_seq; 827 } __packed; 828 829 struct mfi_ld_list { 830 uint32_t mll_no_ld; 831 uint32_t mll_res; 832 struct { 833 struct mfi_ld mll_ld; 834 uint8_t mll_state; 835 #define MFI_LD_OFFLINE 0x00 836 #define MFI_LD_PART_DEGRADED 0x01 837 #define MFI_LD_DEGRADED 0x02 838 #define MFI_LD_ONLINE 0x03 839 uint8_t mll_res2; 840 uint8_t mll_res3; 841 uint8_t mll_res4; 842 uint64_t mll_size; 843 } mll_list[MFI_MAX_LD]; 844 } __packed; 845 846 /* logicl disk details from MR_DCMD_LD_GET_INFO */ 847 struct mfi_ld_prop { 848 struct mfi_ld mlp_ld; 849 char mlp_name[16]; 850 uint8_t mlp_cache_policy; 851 uint8_t mlp_acces_policy; 852 uint8_t mlp_diskcache_policy; 853 uint8_t mlp_cur_cache_policy; 854 uint8_t mlp_disable_bgi; 855 uint8_t mlp_res[7]; 856 } __packed; 857 858 struct mfi_ld_parm { 859 uint8_t mpa_pri_raid; /* SNIA DDF PRL */ 860 #define MFI_DDF_PRL_RAID0 0x00 861 #define MFI_DDF_PRL_RAID1 0x01 862 #define MFI_DDF_PRL_RAID3 0x03 863 #define MFI_DDF_PRL_RAID4 0x04 864 #define MFI_DDF_PRL_RAID5 0x05 865 #define MFI_DDF_PRL_RAID1E 0x11 866 #define MFI_DDF_PRL_JBOD 0x0f 867 #define MFI_DDF_PRL_CONCAT 0x1f 868 #define MFI_DDF_PRL_RAID5E 0x15 869 #define MFI_DDF_PRL_RAID5EE 0x25 870 #define MFI_DDF_PRL_RAID6 0x16 871 uint8_t mpa_raid_qual; /* SNIA DDF RLQ */ 872 uint8_t mpa_sec_raid; /* SNIA DDF SRL */ 873 #define MFI_DDF_SRL_STRIPED 0x00 874 #define MFI_DDF_SRL_MIRRORED 0x01 875 #define MFI_DDF_SRL_CONCAT 0x02 876 #define MFI_DDF_SRL_SPANNED 0x03 877 uint8_t mpa_stripe_size; 878 uint8_t mpa_no_drv_per_span; 879 uint8_t mpa_span_depth; 880 uint8_t mpa_state; 881 uint8_t mpa_init_state; 882 uint8_t mpa_res[24]; 883 } __packed; 884 885 struct mfi_ld_span { 886 uint64_t mls_start_block; 887 uint64_t mls_no_blocks; 888 uint16_t mls_index; 889 uint8_t mls_res[6]; 890 } __packed; 891 892 struct mfi_ld_cfg { 893 struct mfi_ld_prop mlc_prop; 894 struct mfi_ld_parm mlc_parm; 895 struct mfi_ld_span mlc_span[MFI_MAX_SPAN]; 896 } __packed; 897 898 struct mfi_ld_progress { 899 uint32_t mlp_in_prog; 900 #define MFI_LD_PROG_CC 0x01 901 #define MFI_LD_PROG_BGI 0x02 902 #define MFI_LD_PROG_FGI 0x04 903 #define MFI_LD_PROG_RECONSTRUCT 0x08 904 struct mfi_progress mlp_cc; 905 struct mfi_progress mlp_bgi; 906 struct mfi_progress mlp_fgi; 907 struct mfi_progress mlp_reconstruct; 908 struct mfi_progress mlp_res[4]; 909 } __packed; 910 911 struct mfi_ld_details { 912 struct mfi_ld_cfg mld_cfg; 913 uint64_t mld_size; 914 struct mfi_ld_progress mld_progress; 915 uint16_t mld_clust_own_id; 916 uint8_t mld_res1; 917 uint8_t mld_res2; 918 uint8_t mld_inq_page83[64]; 919 uint8_t mld_res[16]; 920 } __packed; 921 922 /* physical disk info from MR_DCMD_PD_GET_LIST */ 923 struct mfi_pd_address { 924 uint16_t mpa_pd_id; 925 uint16_t mpa_enc_id; 926 uint8_t mpa_enc_index; 927 uint8_t mpa_enc_slot; 928 uint8_t mpa_scsi_type; 929 uint8_t mpa_port; 930 uint64_t mpa_sas_address[2]; 931 } __packed; 932 933 struct mfi_pd_list { 934 uint32_t mpl_size; 935 uint32_t mpl_no_pd; 936 struct mfi_pd_address mpl_address[MFI_MAX_PD]; 937 } __packed; 938 939 struct mfi_pd { 940 uint16_t mfp_id; 941 uint16_t mfp_seq; 942 } __packed; 943 944 struct mfi_pd_progress { 945 uint32_t mfp_in_prog; 946 #define MFI_PD_PROG_RBLD 0x01 947 #define MFI_PD_PROG_PR 0x02 948 #define MFI_PD_PROG_CLEAR 0x04 949 struct mfi_progress mfp_rebuild; 950 struct mfi_progress mfp_patrol_read; 951 struct mfi_progress mfp_clear; 952 struct mfi_progress mfp_res[4]; 953 } __packed; 954 955 struct mfi_pd_details { 956 struct mfi_pd mpd_pd; 957 uint8_t mpd_inq_data[96]; 958 uint8_t mpd_inq_page83[64]; 959 uint8_t mpd_no_support; 960 uint8_t mpd_scsi_type; 961 uint8_t mpd_port; 962 uint8_t mpd_speed; 963 uint32_t mpd_mediaerr_cnt; 964 uint32_t mpd_othererr_cnt; 965 uint32_t mpd_predfail_cnt; 966 uint32_t mpd_last_pred_event; 967 uint16_t mpd_fw_state; 968 uint8_t mpd_rdy_for_remove; 969 uint8_t mpd_link_speed; 970 uint32_t mpd_ddf_state; 971 #define MFI_DDF_GUID_FORCED 0x01 972 #define MFI_DDF_PART_OF_VD 0x02 973 #define MFI_DDF_GLOB_HOTSPARE 0x04 974 #define MFI_DDF_HOTSPARE 0x08 975 #define MFI_DDF_FOREIGN 0x10 976 #define MFI_DDF_TYPE_MASK 0xf000 977 #define MFI_DDF_TYPE_UNKNOWN 0x0000 978 #define MFI_DDF_TYPE_PAR_SCSI 0x1000 979 #define MFI_DDF_TYPE_SAS 0x2000 980 #define MFI_DDF_TYPE_SATA 0x3000 981 #define MFI_DDF_TYPE_FC 0x4000 982 struct { 983 uint8_t mpp_cnt; 984 uint8_t mpp_severed; 985 uint8_t mpp_connector_idx[2]; 986 uint8_t mpp_res[4]; 987 uint64_t mpp_sas_addr[2]; 988 uint8_t mpp_res2[16]; 989 } __packed mpd_path; 990 uint64_t mpd_size; 991 uint64_t mpd_no_coerce_size; 992 uint64_t mpd_coerce_size; 993 uint16_t mpd_enc_id; 994 uint8_t mpd_enc_idx; 995 uint8_t mpd_enc_slot; 996 struct mfi_pd_progress mpd_progress; 997 uint8_t mpd_bblock_full; 998 uint8_t mpd_unusable; 999 uint8_t mpd_inq_page83_ext[64]; 1000 uint8_t mpd_power_state; /* XXX */ 1001 uint8_t mpd_enc_pos; 1002 uint32_t mpd_allowed_ops; 1003 #define MFI_PD_A_ONLINE (1<<0) 1004 #define MFI_PD_A_OFFLINE (1<<1) 1005 #define MFI_PD_A_FAILED (1<<2) 1006 #define MFI_PD_A_BAD (1<<3) 1007 #define MFI_PD_A_UNCONFIG (1<<4) 1008 #define MFI_PD_A_HOTSPARE (1<<5) 1009 #define MFI_PD_A_REMOVEHOTSPARE (1<<6) 1010 #define MFI_PD_A_REPLACEMISSING (1<<7) 1011 #define MFI_PD_A_MARKMISSING (1<<8) 1012 #define MFI_PD_A_STARTREBUILD (1<<9) 1013 #define MFI_PD_A_STOPREBUILD (1<<10) 1014 #define MFI_PD_A_BLINK (1<<11) 1015 #define MFI_PD_A_CLEAR (1<<12) 1016 #define MFI_PD_A_FOREIGNIMPORNOTALLOWED (1<<13) 1017 #define MFI_PD_A_STARTCOPYBACK (1<<14) 1018 #define MFI_PD_A_STOPCOPYBACK (1<<15) 1019 #define MFI_PD_A_FWDOWNLOADDNOTALLOWED (1<<16) 1020 #define MFI_PD_A_REPROVISION (1<<17) 1021 uint16_t mpd_copyback_partner_id; 1022 uint16_t mpd_enc_partner_devid; 1023 uint16_t mpd_security; 1024 #define MFI_PD_FDE_CAPABLE (1<<0) 1025 #define MFI_PD_FDE_ENABLED (1<<1) 1026 #define MFI_PD_FDE_SECURED (1<<2) 1027 #define MFI_PD_FDE_LOCKED (1<<3) 1028 #define MFI_PD_FDE_FOREIGNLOCK (1<<4) 1029 uint8_t mpd_media; 1030 uint8_t mpd_res[141]; /* size is 512 */ 1031 } __packed; 1032 1033 struct mfi_pd_allowedops_list { 1034 uint32_t mpo_no_entries; 1035 uint32_t mpo_res; 1036 uint32_t mpo_allowedops_list[MFI_MAX_PD]; 1037 } __packed; 1038 1039 /* array configuration from MR_DCMD_CONF_GET */ 1040 struct mfi_array { 1041 uint64_t mar_smallest_pd; 1042 uint8_t mar_no_disk; 1043 uint8_t mar_res1; 1044 uint16_t mar_array_ref; 1045 uint8_t mar_res2[20]; 1046 struct { 1047 struct mfi_pd mar_pd; 1048 uint16_t mar_pd_state; 1049 #define MFI_PD_UNCONFIG_GOOD 0x00 1050 #define MFI_PD_UNCONFIG_BAD 0x01 1051 #define MFI_PD_HOTSPARE 0x02 1052 #define MFI_PD_OFFLINE 0x10 1053 #define MFI_PD_FAILED 0x11 1054 #define MFI_PD_REBUILD 0x14 1055 #define MFI_PD_ONLINE 0x18 1056 #define MFI_PD_COPYBACK 0x20 1057 #define MFI_PD_SYSTEM 0x40 1058 uint8_t mar_enc_pd; 1059 uint8_t mar_enc_slot; 1060 } pd[MFI_MAX_PD_ARRAY]; 1061 } __packed; 1062 1063 struct mfi_hotspare { 1064 struct mfi_pd mhs_pd; 1065 uint8_t mhs_type; 1066 #define MFI_PD_HS_DEDICATED 0x01 1067 #define MFI_PD_HS_REVERTIBLE 0x02 1068 #define MFI_PD_HS_ENC_AFFINITY 0x04 1069 uint8_t mhs_res[2]; 1070 uint8_t mhs_array_max; 1071 uint16_t mhs_array_ref[MFI_MAX_ARRAY_DEDICATED]; 1072 } __packed; 1073 1074 struct mfi_conf { 1075 uint32_t mfc_size; 1076 uint16_t mfc_no_array; 1077 uint16_t mfc_array_size; 1078 uint16_t mfc_no_ld; 1079 uint16_t mfc_ld_size; 1080 uint16_t mfc_no_hs; 1081 uint16_t mfc_hs_size; 1082 uint8_t mfc_res[16]; 1083 /* 1084 * XXX this is a ridiculous hack and does not reflect reality 1085 * Structures are actually indexed and therefore need pointer 1086 * math to reach. We need the size of this structure first so 1087 * call it with the size of this structure and then use the returned 1088 * values to allocate memory and do the transfer of the whole structure 1089 * then calculate pointers to each of these structures. 1090 */ 1091 struct mfi_array mfc_array[1]; 1092 struct mfi_ld_cfg mfc_ld[1]; 1093 struct mfi_hotspare mfc_hs[1]; 1094 } __packed; 1095 1096 struct mfi_bbu_capacity_info { 1097 uint16_t relative_charge; 1098 uint16_t absolute_charge; 1099 uint16_t remaining_capacity; 1100 uint16_t full_charge_capacity; 1101 uint16_t run_time_to_empty; 1102 uint16_t average_time_to_empty; 1103 uint16_t average_time_to_full; 1104 uint16_t cycle_count; 1105 uint16_t max_error; 1106 uint16_t remaining_capacity_alarm; 1107 uint16_t remaining_time_alarm; 1108 uint8_t reserved[26]; 1109 } __packed; 1110 1111 struct mfi_bbu_design_info { 1112 uint32_t mfg_date; 1113 uint16_t design_capacity; 1114 uint16_t design_voltage; 1115 uint16_t spec_info; 1116 uint16_t serial_number; 1117 uint16_t pack_stat_config; 1118 uint8_t mfg_name[12]; 1119 uint8_t device_name[8]; 1120 uint8_t device_chemistry[8]; 1121 uint8_t mfg_data[8]; 1122 uint8_t reserved[17]; 1123 } __packed; 1124 1125 struct mfi_ibbu_state { 1126 uint16_t gas_guage_status; 1127 uint16_t relative_charge; 1128 uint16_t charger_system_state; 1129 uint16_t charger_system_ctrl; 1130 uint16_t charging_current; 1131 uint16_t absolute_charge; 1132 uint16_t max_error; 1133 uint8_t reserved[18]; 1134 } __packed; 1135 1136 struct mfi_bbu_state { 1137 uint16_t gas_guage_status; 1138 uint16_t relative_charge; 1139 uint16_t charger_status; 1140 uint16_t remaining_capacity; 1141 uint16_t full_charge_capacity; 1142 uint8_t is_SOH_good; 1143 uint8_t reserved[21]; 1144 } __packed; 1145 1146 struct mfi_bbu_properties { 1147 uint32_t auto_learn_period; 1148 uint32_t next_learn_time; 1149 uint8_t learn_delay_interval; 1150 uint8_t auto_learn_mode; 1151 uint8_t bbu_mode; 1152 uint8_t reserved[21]; 1153 } __packed; 1154 1155 union mfi_bbu_status_detail { 1156 struct mfi_ibbu_state ibbu; 1157 struct mfi_bbu_state bbu; 1158 }; 1159 1160 struct mfi_bbu_status { 1161 uint8_t battery_type; 1162 #define MFI_BBU_TYPE_NONE 0 1163 #define MFI_BBU_TYPE_IBBU 1 1164 #define MFI_BBU_TYPE_BBU 2 1165 uint8_t reserved; 1166 uint16_t voltage; /* mV */ 1167 int16_t current; /* mA */ 1168 uint16_t temperature; /* degC */ 1169 uint32_t fw_status; 1170 #define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1171 #define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1172 #define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1173 #define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 3) 1174 #define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 4) 1175 #define MFI_BBU_STATE_LEARN_CYC_REQ (1 << 5) 1176 #define MFI_BBU_STATE_LEARN_CYC_ACTIVE (1 << 6) 1177 #define MFI_BBU_STATE_LEARN_CYC_FAIL (1 << 7) 1178 #define MFI_BBU_STATE_LEARN_CYC_TIMEOUT (1 << 8) 1179 #define MFI_BBU_STATE_I2C_ERR_DETECT (1 << 9) 1180 #define MFI_BBU_STATE_REPLACE_PACK (1 << 10) 1181 #define MFI_BBU_STATE_CAPACITY_LOW (1 << 11) 1182 #define MFI_BBU_STATE_LEARN_REQUIRED (1 << 12) 1183 #define MFI_BBU_STATE_FMT "\020" \ 1184 "\001PACK_MISSING" \ 1185 "\002VOLTAGE_LOW" \ 1186 "\003TEMP_HIGH" \ 1187 "\004CHARGE_ACTIVE" \ 1188 "\005DISCHARGE_ACTIVE" \ 1189 "\006LEARN_CYC_REQ" \ 1190 "\007LEARN_CYC_ACTIVE" \ 1191 "\010LEARN_CYC_FAIL" \ 1192 "\011LEARN_CYC_TIMEOUT" \ 1193 "\012I2C_ERR_DETECT" \ 1194 "\013REPLACE_PACK" \ 1195 "\014CAPACITY_LOW" \ 1196 "\015LEARN_REQUIRED" 1197 #define MFI_BBU_STATE_BAD_IBBU ( \ 1198 MFI_BBU_STATE_PACK_MISSING | \ 1199 MFI_BBU_STATE_VOLTAGE_LOW | \ 1200 MFI_BBU_STATE_DISCHARGE_ACTIVE | \ 1201 MFI_BBU_STATE_LEARN_CYC_REQ | \ 1202 MFI_BBU_STATE_LEARN_CYC_ACTIVE | \ 1203 MFI_BBU_STATE_REPLACE_PACK | \ 1204 MFI_BBU_STATE_CAPACITY_LOW) 1205 #define MFI_BBU_STATE_BAD_BBU ( \ 1206 MFI_BBU_STATE_PACK_MISSING | \ 1207 MFI_BBU_STATE_REPLACE_PACK | \ 1208 MFI_BBU_STATE_CAPACITY_LOW) 1209 1210 uint8_t pad[20]; 1211 union mfi_bbu_status_detail detail; 1212 } __packed; 1213 1214 struct mfi_pr_status { 1215 uint32_t num_iteration; 1216 uint8_t state; 1217 uint8_t num_pd_done; 1218 uint8_t reserved[10]; 1219 } __packed; 1220 1221 struct mfi_pr_properties { 1222 uint8_t op_mode; 1223 uint8_t max_pd; 1224 uint8_t reserved; 1225 uint8_t exclude_ld_count; 1226 uint16_t excluded_ld[MFI_MAX_LD]; 1227 uint8_t cur_pd_map[MFI_MAX_PD / 8]; 1228 uint8_t last_pd_map[MFI_MAX_PD / 8]; 1229 uint32_t next_exec; 1230 uint32_t exec_freq; 1231 uint32_t clear_freq; 1232 } __packed; 1233 1234 /* We currently don't know the full details of the following struct */ 1235 struct mfii_foreign_scan_cfg { 1236 char data[24]; 1237 }; 1238 1239 struct mfii_foreign_scan_info { 1240 uint32_t count; /* Number of foreign configs found */ 1241 struct mfii_foreign_scan_cfg cfgs[8]; 1242 }; 1243