1 /* $OpenBSD: mtd8xxreg.h,v 1.2 2003/10/21 18:58:49 jmc Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Oleg Safiullin <form@pdp11.org.ru> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 31 #ifndef __DEV_IC_MTD8XXREG_H__ 32 #define __DEV_IC_MTD8XXREG_H__ 33 34 #define MTD_PCI_LOIO 0x10 /* PCI I/O base address register */ 35 #define MTD_PCI_LOMEM 0x14 /* PCI memory base address register */ 36 37 #define MTD_TIMEOUT 1000 /* Software reset timeout */ 38 39 #define MII_OPCODE_RD 0x6000 40 #define MII_OPCODE_WR 0x5002 41 42 /* 43 * MTD8xx command and status register. 44 */ 45 #define MTD_PAR0 0x00 /* Physical address register 0*/ 46 #define MTD_PAR4 0x04 /* Physical address register 4 */ 47 #define MTD_MAR0 0x08 /* Multicast address register 0 */ 48 #define MTD_MAR4 0x0C /* Multicast address register 4 */ 49 #define MTD_TCRRCR 0x18 /* Transmit/receive config */ 50 #define MTD_BCR 0x1C /* Bus configuration register */ 51 #define MTD_TXPDR 0x20 /* Transmit poll demand */ 52 #define MTD_RXPDR 0x24 /* Receive poll demand */ 53 #define MTD_RXCWP 0x28 /* Receive current word pointer */ 54 #define MTD_TXLBA 0x2C /* Transmit list base address */ 55 #define MTD_RXLBA 0x30 /* Receive list base address */ 56 #define MTD_ISR 0x34 /* Interrupt status register */ 57 #define MTD_IMR 0x38 /* Interrupt mask register */ 58 #define MTD_TSR 0x48 /* Tally counter register */ 59 #define MTD_MIIMGT 0x40 /* MII management register */ 60 #define MTD_PHYCSR 0x4C /* PHY control status register */ 61 62 63 /* 64 * Receive configuration register. 65 */ 66 #define RCR_RXS 0x00008000U /* Receive process is running */ 67 #define RCR_EIEN 0x00004000U /* Early interrupt enabled */ 68 #define RCR_RFCEN 0x00002000U /* Receive flow control enabled */ 69 #define RCR_NDFA 0x00001000U /* Not defined flow control address */ 70 #define RCR_RBLEN 0x00000800U /* Receive burst length enable */ 71 #define RCR_RPBL1 0x00000000U /* 1 word */ 72 #define RCR_RPBL4 0x00000100U /* 4 words */ 73 #define RCR_RPBL8 0x00000200U /* 8 words */ 74 #define RCR_RPBL16 0x00000300U /* 16 words */ 75 #define RCR_RPBL32 0x00000400U /* 32 words */ 76 #define RCR_RPBL64 0x00000500U /* 64 words */ 77 #define RCR_RPBL128 0x00000600U /* 128 words */ 78 #define RCR_RPBL512 0x00000700U /* 512 words */ 79 #define RCR_PROM 0x00000080U /* Promiscuous mode */ 80 #define RCR_AB 0x00000040U /* Accept broadcast addresses */ 81 #define RCR_AM 0x00000020U /* Accept multicast addresses */ 82 #define RCR_ARP 0x00000008U /* Accept runt packets */ 83 #define RCR_ALP 0x00000004U /* Accept long packets */ 84 #define RCR_SEP 0x00000002U /* Accept packets w/ receive errors */ 85 #define RCR_RE 0x00000001U /* Receive enable */ 86 87 88 /* 89 * Transmit configuration register. 90 */ 91 #define TCR_TXS 0x80000000U /* Tx process is running */ 92 #define TCR_BACKOPT 0x10000000U /* Optional back-off */ 93 #define TCR_FBACK 0x08000000U /* Fast back-off */ 94 #define TCR_ENHANCED 0x02000000U /* Enhanced transmit mode */ 95 #define TCR_TFCEN 0x01000000U /* Ttansmit flow control enable */ 96 #define TCR_TFT64 0x00000000U /* 64 bytes */ 97 #define TCR_TFT32 0x00200000U /* 32 bytes */ 98 #define TCR_TFT128 0x00400000U /* 128 bytes */ 99 #define TCR_TFT256 0x00600000U /* 256 bytes */ 100 #define TCR_TFT512 0x00800000U /* 512 bytes */ 101 #define TCR_TFT768 0x00A00000U /* 768 bytes */ 102 #define TCR_TFT1024 0x00C00000U /* 1024 bytes */ 103 #define TCR_TFTSF 0x00E00000U /* Transmit store and forward */ 104 #define TCR_FD 0x00100000U /* Full-duplex mode */ 105 #define TCR_PS 0x00080000U /* Port speed is 10Mbit/s */ 106 #define TCR_TE 0x00040000U /* Transmit enable */ 107 #define TCR_LB 0x00020000U /* MII loopback on */ 108 109 110 /* 111 * Bus configuration register. 112 */ 113 #define BCR_PROG 0x00000200U /* Programming */ 114 #define BCR_RLE 0x00000100U /* Read line cmd enable */ 115 #define BCR_RME 0x00000080U /* Read multiple cmd enable */ 116 #define BCR_WIE 0x00000040U /* Write and invalidate cmd enable */ 117 /* Programmable burst length */ 118 #define BCR_PBL1 0x00000000U /* 1 dword */ 119 #define BCR_PBL4 0x00000008U /* 4 dwords */ 120 #define BCR_PBL8 0x00000010U /* 8 dwords */ 121 #define BCR_PBL16 0x00000018U /* 16 dwords */ 122 #define BCR_PBL32 0x00000020U /* 32 dwords */ 123 #define BCR_PBL64 0x00000028U /* 64 dwords */ 124 #define BCR_PBL128 0x00000030U /* 128 dwords */ 125 #define BCR_PBL512 0x00000038U /* 512 dwords */ 126 #define BCR_SWR 0x00000001U /* Software reset */ 127 128 129 /* 130 * Interrupt status register. 131 */ 132 #define ISR_PDF 0x00040000U /* Parallel detection fault */ 133 #define ISR_RFCON 0x00020000U /* Receive flow control XON */ 134 #define ISR_RFCOFF 0x00010000U /* Receive flow control XOFF */ 135 #define ISR_LSC 0x00008000U /* Link status change */ 136 #define ISR_ANC 0x00004000U /* Auto-negotiation completed */ 137 #define ISR_FBE 0x00002000U /* Fatal bus error */ 138 #define ISR_ETMASK 0x00001800U /* Error type mask */ 139 #define ISR_ET(x) ((x) & ISR_ETMASK) 140 #define ISR_ETPARITY 0x00000000U /* Parity error */ 141 #define ISR_ETMASTER 0x00000800U /* Master abort */ 142 #define ISR_ETTARGET 0x00001000U /* Target abort */ 143 #define ISR_TUNF 0x00000400U /* Transmit underflow */ 144 #define ISR_ROVF 0x00000200U /* Receive overflow */ 145 #define ISR_ETI 0x00000100U /* Early transfer interrupt */ 146 #define ISR_ERI 0x00000080U /* Early receive interrupt */ 147 #define ISR_CNTOVF 0x00000040U /* CRC or MPA tally ounter overflow */ 148 #define ISR_RBU 0x00000020U /* Receive buffer unavailable */ 149 #define ISR_TBU 0x00000010U /* Transmit buffer unavailable */ 150 #define ISR_TI 0x00000008U /* Transmit interrupt */ 151 #define ISR_RI 0x00000004U /* Receive interrupt */ 152 #define ISR_RXERI 0x00000002U /* Receive error interrupt */ 153 154 #define ISR_INTRS (ISR_RBU | ISR_TBU | ISR_TI | ISR_RI | ISR_ETI) 155 156 157 /* 158 * Interrupt mask register. 159 */ 160 #define IMR_MPDF 0x00040000U /* Parallel detection fault */ 161 #define IMR_MRFCON 0x00020000U /* Receive flow control XON */ 162 #define IMR_MRFCOFF 0x00010000U /* Receive flow control XOFF */ 163 #define IMR_MLSC 0x00008000U /* Link status change */ 164 #define IMR_MANC 0x00004000U /* Auto-negotiation completed */ 165 #define IMR_MFBE 0x00002000U /* Fatal bus error */ 166 #define IMR_MTUNF 0x00000400U /* Transmit underflow */ 167 #define IMR_MROVF 0x00000200U /* Receive overflow */ 168 #define IMR_METI 0x00000100U /* Early transfer interrupt */ 169 #define IMR_MERI 0x00000080U /* Early receive interrupt */ 170 #define IMR_MCNTOVF 0x00000040U /* CRC or MPA tally ounter overflow */ 171 #define IMR_MRBU 0x00000020U /* Receive buffer unavailable */ 172 #define IMR_MTBU 0x00000010U /* Transmit buffer unavailable */ 173 #define IMR_MTI 0x00000008U /* Transmit interrupt */ 174 #define IMR_MRI 0x00000004U /* Receive interrupt */ 175 #define IMR_MRXERI 0x00000002U /* Receive error interrupt */ 176 177 #define IMR_INTRS (IMR_MRBU | IMR_MTBU | IMR_MTI | IMR_MRI | IMR_METI) 178 179 /* 180 * Transmit status register. 181 */ 182 #define TSR_NCR_MASK 0x0000FFFFU 183 #define TSR_NCR_SHIFT 0 184 #define TSR_NCR_GET(x) (((x) & TSR_NCR_MASK) >> TSR_NCR_SHIFT) 185 /* Retry collisions count */ 186 187 /* 188 * MII management register. 189 */ 190 #define MIIMGT_READ 0x00000000U 191 #define MIIMGT_WRITE 0x00000008U 192 #define MIIMGT_MDO 0x00000004U 193 #define MIIMGT_MDI 0x00000002U 194 #define MIIMGT_MDC 0x00000001U 195 #define MIIMGT_MASK 0x0000000FU 196 197 /* 198 * Command and status register space access macros. 199 */ 200 #define CSR_READ_1(reg) bus_space_read_1(sc->sc_bust, sc->sc_bush, reg) 201 #define CSR_WRITE_1(reg, val) \ 202 bus_space_write_1(sc->sc_bust, sc->sc_bush, reg, val) 203 204 #define CSR_READ_2(reg) bus_space_read_2(sc->sc_bust, sc->sc_bush, reg) 205 #define CSR_WRITE_2(reg, vat) \ 206 bus_space_write_2(sc->sc_bust, sc->sc_bush, reg, val) 207 208 #define CSR_READ_4(reg) bus_space_read_4(sc->sc_bust, sc->sc_bush, reg) 209 #define CSR_WRITE_4(reg, val) \ 210 bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val) 211 212 #define CSR_SETBIT(reg, val) CSR_WRITE_4(reg, CSR_READ_4(reg) | (val)) 213 #define CSR_CLRBIT(reg, val) CSR_WRITE_4(reg, CSR_READ_4(reg) & ~(val)) 214 215 #endif /* __DEV_IC_MTD8XXREG_H__ */ 216