1 /* $OpenBSD: qwxreg.h,v 1.2 2024/01/25 10:11:04 stsp Exp $ */ 2 3 /* 4 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. 5 * Copyright (c) 2018-2021 The Linux Foundation. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted (subject to the limitations in the disclaimer 10 * below) provided that the following conditions are met: 11 * 12 * * Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * * Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * * Neither the name of [Owner Organization] nor the names of its 20 * contributors may be used to endorse or promote products derived from 21 * this software without specific prior written permission. 22 * 23 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY 24 * THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 25 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT 26 * NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 27 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER 28 * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 31 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 33 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 34 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * core.h 39 */ 40 41 enum ath11k_hw_rev { 42 ATH11K_HW_IPQ8074, 43 ATH11K_HW_QCA6390_HW20, 44 ATH11K_HW_IPQ6018_HW10, 45 ATH11K_HW_QCN9074_HW10, 46 ATH11K_HW_WCN6855_HW20, 47 ATH11K_HW_WCN6855_HW21, 48 ATH11K_HW_WCN6750_HW10, 49 }; 50 51 enum ath11k_firmware_mode { 52 /* the default mode, standard 802.11 functionality */ 53 ATH11K_FIRMWARE_MODE_NORMAL, 54 55 /* factory tests etc */ 56 ATH11K_FIRMWARE_MODE_FTM, 57 58 /* Cold boot calibration */ 59 ATH11K_FIRMWARE_MODE_COLD_BOOT = 7, 60 }; 61 62 enum ath11k_crypt_mode { 63 /* Only use hardware crypto engine */ 64 ATH11K_CRYPT_MODE_HW, 65 /* Only use software crypto */ 66 ATH11K_CRYPT_MODE_SW, 67 }; 68 69 /* IPQ8074 HW channel counters frequency value in hertz */ 70 #define IPQ8074_CC_FREQ_HERTZ 320000 71 72 #define ATH11K_MIN_5G_FREQ 4150 73 #define ATH11K_MIN_6G_FREQ 5925 74 #define ATH11K_MAX_6G_FREQ 7115 75 #define ATH11K_NUM_CHANS 102 76 #define ATH11K_MAX_5G_CHAN 177 77 78 /* Antenna noise floor */ 79 #define ATH11K_DEFAULT_NOISE_FLOOR -95 80 81 /* 82 * wmi.h 83 */ 84 85 #define PSOC_HOST_MAX_NUM_SS (8) 86 87 /* defines to set Packet extension values which can be 0 us, 8 usec or 16 usec */ 88 #define MAX_HE_NSS 8 89 #define MAX_HE_MODULATION 8 90 #define MAX_HE_RU 4 91 #define HE_MODULATION_NONE 7 92 #define HE_PET_0_USEC 0 93 #define HE_PET_8_USEC 1 94 #define HE_PET_16_USEC 2 95 96 #define WMI_MAX_CHAINS 8 97 98 #define WMI_MAX_NUM_SS MAX_HE_NSS 99 #define WMI_MAX_NUM_RU MAX_HE_RU 100 101 #define WMI_TLV_CMD(grp_id) (((grp_id) << 12) | 0x1) 102 #define WMI_TLV_EV(grp_id) (((grp_id) << 12) | 0x1) 103 #define WMI_TLV_CMD_UNSUPPORTED 0 104 #define WMI_TLV_PDEV_PARAM_UNSUPPORTED 0 105 #define WMI_TLV_VDEV_PARAM_UNSUPPORTED 0 106 107 struct wmi_cmd_hdr { 108 uint32_t cmd_id; 109 } __packed; 110 111 struct wmi_tlv { 112 uint32_t header; 113 uint8_t value[]; 114 } __packed; 115 116 #define WMI_TLV_LEN GENMASK(15, 0) 117 #define WMI_TLV_TAG GENMASK(31, 16) 118 #define TLV_HDR_SIZE sizeof(uint32_t) /* wmi_tlv.header */ 119 120 #define WMI_CMD_HDR_CMD_ID GENMASK(23, 0) 121 #define WMI_MAX_MEM_REQS 32 122 #define ATH11K_MAX_HW_LISTEN_INTERVAL 5 123 124 #define WLAN_SCAN_MAX_HINT_S_SSID 10 125 #define WLAN_SCAN_MAX_HINT_BSSID 10 126 #define MAX_RNR_BSS 5 127 128 #define WLAN_SCAN_MAX_HINT_S_SSID 10 129 #define WLAN_SCAN_MAX_HINT_BSSID 10 130 #define MAX_RNR_BSS 5 131 132 #define WLAN_SCAN_PARAMS_MAX_SSID 16 133 #define WLAN_SCAN_PARAMS_MAX_BSSID 4 134 #define WLAN_SCAN_PARAMS_MAX_IE_LEN 256 135 136 #define WMI_APPEND_TO_EXISTING_CHAN_LIST_FLAG 1 137 138 #define MAX_WMI_UTF_LEN 252 139 #define WMI_BA_MODE_BUFFER_SIZE_256 3 140 141 /* 142 * HW mode config type replicated from FW header 143 * @WMI_HOST_HW_MODE_SINGLE: Only one PHY is active. 144 * @WMI_HOST_HW_MODE_DBS: Both PHYs are active in different bands, 145 * one in 2G and another in 5G. 146 * @WMI_HOST_HW_MODE_SBS_PASSIVE: Both PHYs are in passive mode (only rx) in 147 * same band; no tx allowed. 148 * @WMI_HOST_HW_MODE_SBS: Both PHYs are active in the same band. 149 * Support for both PHYs within one band is planned 150 * for 5G only(as indicated in WMI_MAC_PHY_CAPABILITIES), 151 * but could be extended to other bands in the future. 152 * The separation of the band between the two PHYs needs 153 * to be communicated separately. 154 * @WMI_HOST_HW_MODE_DBS_SBS: 3 PHYs, with 2 on the same band doing SBS 155 * as in WMI_HW_MODE_SBS, and 3rd on the other band 156 * @WMI_HOST_HW_MODE_DBS_OR_SBS: Two PHY with one PHY capabale of both 2G and 157 * 5G. It can support SBS (5G + 5G) OR DBS (5G + 2G). 158 * @WMI_HOST_HW_MODE_MAX: Max hw_mode_id. Used to indicate invalid mode. 159 */ 160 enum wmi_host_hw_mode_config_type { 161 WMI_HOST_HW_MODE_SINGLE = 0, 162 WMI_HOST_HW_MODE_DBS = 1, 163 WMI_HOST_HW_MODE_SBS_PASSIVE = 2, 164 WMI_HOST_HW_MODE_SBS = 3, 165 WMI_HOST_HW_MODE_DBS_SBS = 4, 166 WMI_HOST_HW_MODE_DBS_OR_SBS = 5, 167 168 /* keep last */ 169 WMI_HOST_HW_MODE_MAX 170 }; 171 172 /* HW mode priority values used to detect the preferred HW mode 173 * on the available modes. 174 */ 175 enum wmi_host_hw_mode_priority { 176 WMI_HOST_HW_MODE_DBS_SBS_PRI, 177 WMI_HOST_HW_MODE_DBS_PRI, 178 WMI_HOST_HW_MODE_DBS_OR_SBS_PRI, 179 WMI_HOST_HW_MODE_SBS_PRI, 180 WMI_HOST_HW_MODE_SBS_PASSIVE_PRI, 181 WMI_HOST_HW_MODE_SINGLE_PRI, 182 183 /* keep last the lowest priority */ 184 WMI_HOST_HW_MODE_MAX_PRI 185 }; 186 187 enum WMI_HOST_WLAN_BAND { 188 WMI_HOST_WLAN_2G_CAP = 0x1, 189 WMI_HOST_WLAN_5G_CAP = 0x2, 190 WMI_HOST_WLAN_2G_5G_CAP = WMI_HOST_WLAN_2G_CAP | WMI_HOST_WLAN_5G_CAP, 191 }; 192 193 /* Parameters used for WMI_VDEV_PARAM_AUTORATE_MISC_CFG command. 194 * Used only for HE auto rate mode. 195 */ 196 enum { 197 /* HE LTF related configuration */ 198 WMI_HE_AUTORATE_LTF_1X = BIT(0), 199 WMI_HE_AUTORATE_LTF_2X = BIT(1), 200 WMI_HE_AUTORATE_LTF_4X = BIT(2), 201 202 /* HE GI related configuration */ 203 WMI_AUTORATE_400NS_GI = BIT(8), 204 WMI_AUTORATE_800NS_GI = BIT(9), 205 WMI_AUTORATE_1600NS_GI = BIT(10), 206 WMI_AUTORATE_3200NS_GI = BIT(11), 207 }; 208 209 enum { 210 WMI_HOST_VDEV_FLAGS_NON_MBSSID_AP = 0x00000001, 211 WMI_HOST_VDEV_FLAGS_TRANSMIT_AP = 0x00000002, 212 WMI_HOST_VDEV_FLAGS_NON_TRANSMIT_AP = 0x00000004, 213 WMI_HOST_VDEV_FLAGS_EMA_MODE = 0x00000008, 214 WMI_HOST_VDEV_FLAGS_SCAN_MODE_VAP = 0x00000010, 215 }; 216 217 /* 218 * wmi command groups. 219 */ 220 enum wmi_cmd_group { 221 /* 0 to 2 are reserved */ 222 WMI_GRP_START = 0x3, 223 WMI_GRP_SCAN = WMI_GRP_START, 224 WMI_GRP_PDEV = 0x4, 225 WMI_GRP_VDEV = 0x5, 226 WMI_GRP_PEER = 0x6, 227 WMI_GRP_MGMT = 0x7, 228 WMI_GRP_BA_NEG = 0x8, 229 WMI_GRP_STA_PS = 0x9, 230 WMI_GRP_DFS = 0xa, 231 WMI_GRP_ROAM = 0xb, 232 WMI_GRP_OFL_SCAN = 0xc, 233 WMI_GRP_P2P = 0xd, 234 WMI_GRP_AP_PS = 0xe, 235 WMI_GRP_RATE_CTRL = 0xf, 236 WMI_GRP_PROFILE = 0x10, 237 WMI_GRP_SUSPEND = 0x11, 238 WMI_GRP_BCN_FILTER = 0x12, 239 WMI_GRP_WOW = 0x13, 240 WMI_GRP_RTT = 0x14, 241 WMI_GRP_SPECTRAL = 0x15, 242 WMI_GRP_STATS = 0x16, 243 WMI_GRP_ARP_NS_OFL = 0x17, 244 WMI_GRP_NLO_OFL = 0x18, 245 WMI_GRP_GTK_OFL = 0x19, 246 WMI_GRP_CSA_OFL = 0x1a, 247 WMI_GRP_CHATTER = 0x1b, 248 WMI_GRP_TID_ADDBA = 0x1c, 249 WMI_GRP_MISC = 0x1d, 250 WMI_GRP_GPIO = 0x1e, 251 WMI_GRP_FWTEST = 0x1f, 252 WMI_GRP_TDLS = 0x20, 253 WMI_GRP_RESMGR = 0x21, 254 WMI_GRP_STA_SMPS = 0x22, 255 WMI_GRP_WLAN_HB = 0x23, 256 WMI_GRP_RMC = 0x24, 257 WMI_GRP_MHF_OFL = 0x25, 258 WMI_GRP_LOCATION_SCAN = 0x26, 259 WMI_GRP_OEM = 0x27, 260 WMI_GRP_NAN = 0x28, 261 WMI_GRP_COEX = 0x29, 262 WMI_GRP_OBSS_OFL = 0x2a, 263 WMI_GRP_LPI = 0x2b, 264 WMI_GRP_EXTSCAN = 0x2c, 265 WMI_GRP_DHCP_OFL = 0x2d, 266 WMI_GRP_IPA = 0x2e, 267 WMI_GRP_MDNS_OFL = 0x2f, 268 WMI_GRP_SAP_OFL = 0x30, 269 WMI_GRP_OCB = 0x31, 270 WMI_GRP_SOC = 0x32, 271 WMI_GRP_PKT_FILTER = 0x33, 272 WMI_GRP_MAWC = 0x34, 273 WMI_GRP_PMF_OFFLOAD = 0x35, 274 WMI_GRP_BPF_OFFLOAD = 0x36, 275 WMI_GRP_NAN_DATA = 0x37, 276 WMI_GRP_PROTOTYPE = 0x38, 277 WMI_GRP_MONITOR = 0x39, 278 WMI_GRP_REGULATORY = 0x3a, 279 WMI_GRP_HW_DATA_FILTER = 0x3b, 280 WMI_GRP_WLM = 0x3c, 281 WMI_GRP_11K_OFFLOAD = 0x3d, 282 WMI_GRP_TWT = 0x3e, 283 WMI_GRP_MOTION_DET = 0x3f, 284 WMI_GRP_SPATIAL_REUSE = 0x40, 285 }; 286 287 288 #define WMI_CMD_GRP(grp_id) (((grp_id) << 12) | 0x1) 289 #define WMI_EVT_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1) 290 291 #define WMI_CMD_UNSUPPORTED 0 292 293 enum wmi_tlv_cmd_id { 294 WMI_INIT_CMDID = 0x1, 295 WMI_START_SCAN_CMDID = WMI_TLV_CMD(WMI_GRP_SCAN), 296 WMI_STOP_SCAN_CMDID, 297 WMI_SCAN_CHAN_LIST_CMDID, 298 WMI_SCAN_SCH_PRIO_TBL_CMDID, 299 WMI_SCAN_UPDATE_REQUEST_CMDID, 300 WMI_SCAN_PROB_REQ_OUI_CMDID, 301 WMI_SCAN_ADAPTIVE_DWELL_CONFIG_CMDID, 302 WMI_PDEV_SET_REGDOMAIN_CMDID = WMI_TLV_CMD(WMI_GRP_PDEV), 303 WMI_PDEV_SET_CHANNEL_CMDID, 304 WMI_PDEV_SET_PARAM_CMDID, 305 WMI_PDEV_PKTLOG_ENABLE_CMDID, 306 WMI_PDEV_PKTLOG_DISABLE_CMDID, 307 WMI_PDEV_SET_WMM_PARAMS_CMDID, 308 WMI_PDEV_SET_HT_CAP_IE_CMDID, 309 WMI_PDEV_SET_VHT_CAP_IE_CMDID, 310 WMI_PDEV_SET_DSCP_TID_MAP_CMDID, 311 WMI_PDEV_SET_QUIET_MODE_CMDID, 312 WMI_PDEV_GREEN_AP_PS_ENABLE_CMDID, 313 WMI_PDEV_GET_TPC_CONFIG_CMDID, 314 WMI_PDEV_SET_BASE_MACADDR_CMDID, 315 WMI_PDEV_DUMP_CMDID, 316 WMI_PDEV_SET_LED_CONFIG_CMDID, 317 WMI_PDEV_GET_TEMPERATURE_CMDID, 318 WMI_PDEV_SET_LED_FLASHING_CMDID, 319 WMI_PDEV_SMART_ANT_ENABLE_CMDID, 320 WMI_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID, 321 WMI_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID, 322 WMI_PDEV_SET_CTL_TABLE_CMDID, 323 WMI_PDEV_SET_MIMOGAIN_TABLE_CMDID, 324 WMI_PDEV_FIPS_CMDID, 325 WMI_PDEV_GET_ANI_CCK_CONFIG_CMDID, 326 WMI_PDEV_GET_ANI_OFDM_CONFIG_CMDID, 327 WMI_PDEV_GET_NFCAL_POWER_CMDID, 328 WMI_PDEV_GET_TPC_CMDID, 329 WMI_MIB_STATS_ENABLE_CMDID, 330 WMI_PDEV_SET_PCL_CMDID, 331 WMI_PDEV_SET_HW_MODE_CMDID, 332 WMI_PDEV_SET_MAC_CONFIG_CMDID, 333 WMI_PDEV_SET_ANTENNA_MODE_CMDID, 334 WMI_SET_PERIODIC_CHANNEL_STATS_CONFIG_CMDID, 335 WMI_PDEV_WAL_POWER_DEBUG_CMDID, 336 WMI_PDEV_SET_REORDER_TIMEOUT_VAL_CMDID, 337 WMI_PDEV_SET_WAKEUP_CONFIG_CMDID, 338 WMI_PDEV_GET_ANTDIV_STATUS_CMDID, 339 WMI_PDEV_GET_CHIP_POWER_STATS_CMDID, 340 WMI_PDEV_SET_STATS_THRESHOLD_CMDID, 341 WMI_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMDID, 342 WMI_PDEV_UPDATE_PKT_ROUTING_CMDID, 343 WMI_PDEV_CHECK_CAL_VERSION_CMDID, 344 WMI_PDEV_SET_DIVERSITY_GAIN_CMDID, 345 WMI_PDEV_DIV_GET_RSSI_ANTID_CMDID, 346 WMI_PDEV_BSS_CHAN_INFO_REQUEST_CMDID, 347 WMI_PDEV_UPDATE_PMK_CACHE_CMDID, 348 WMI_PDEV_UPDATE_FILS_HLP_PKT_CMDID, 349 WMI_PDEV_UPDATE_CTLTABLE_REQUEST_CMDID, 350 WMI_PDEV_CONFIG_VENDOR_OUI_ACTION_CMDID, 351 WMI_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMDID, 352 WMI_PDEV_SET_RX_FILTER_PROMISCUOUS_CMDID, 353 WMI_PDEV_DMA_RING_CFG_REQ_CMDID, 354 WMI_PDEV_HE_TB_ACTION_FRM_CMDID, 355 WMI_PDEV_PKTLOG_FILTER_CMDID, 356 WMI_PDEV_SET_RAP_CONFIG_CMDID, 357 WMI_PDEV_DSM_FILTER_CMDID, 358 WMI_PDEV_FRAME_INJECT_CMDID, 359 WMI_PDEV_TBTT_OFFSET_SYNC_CMDID, 360 WMI_PDEV_SET_SRG_BSS_COLOR_BITMAP_CMDID, 361 WMI_PDEV_SET_SRG_PARTIAL_BSSID_BITMAP_CMDID, 362 WMI_PDEV_SET_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID, 363 WMI_PDEV_SET_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID, 364 WMI_PDEV_SET_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID, 365 WMI_PDEV_SET_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID, 366 WMI_PDEV_GET_TPC_STATS_CMDID, 367 WMI_PDEV_ENABLE_DURATION_BASED_TX_MODE_SELECTION_CMDID, 368 WMI_PDEV_GET_DPD_STATUS_CMDID, 369 WMI_PDEV_SET_BIOS_SAR_TABLE_CMDID, 370 WMI_PDEV_SET_BIOS_GEO_TABLE_CMDID, 371 WMI_VDEV_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_VDEV), 372 WMI_VDEV_DELETE_CMDID, 373 WMI_VDEV_START_REQUEST_CMDID, 374 WMI_VDEV_RESTART_REQUEST_CMDID, 375 WMI_VDEV_UP_CMDID, 376 WMI_VDEV_STOP_CMDID, 377 WMI_VDEV_DOWN_CMDID, 378 WMI_VDEV_SET_PARAM_CMDID, 379 WMI_VDEV_INSTALL_KEY_CMDID, 380 WMI_VDEV_WNM_SLEEPMODE_CMDID, 381 WMI_VDEV_WMM_ADDTS_CMDID, 382 WMI_VDEV_WMM_DELTS_CMDID, 383 WMI_VDEV_SET_WMM_PARAMS_CMDID, 384 WMI_VDEV_SET_GTX_PARAMS_CMDID, 385 WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID, 386 WMI_VDEV_PLMREQ_START_CMDID, 387 WMI_VDEV_PLMREQ_STOP_CMDID, 388 WMI_VDEV_TSF_TSTAMP_ACTION_CMDID, 389 WMI_VDEV_SET_IE_CMDID, 390 WMI_VDEV_RATEMASK_CMDID, 391 WMI_VDEV_ATF_REQUEST_CMDID, 392 WMI_VDEV_SET_DSCP_TID_MAP_CMDID, 393 WMI_VDEV_FILTER_NEIGHBOR_RX_PACKETS_CMDID, 394 WMI_VDEV_SET_QUIET_MODE_CMDID, 395 WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID, 396 WMI_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMDID, 397 WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMDID, 398 WMI_PEER_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_PEER), 399 WMI_PEER_DELETE_CMDID, 400 WMI_PEER_FLUSH_TIDS_CMDID, 401 WMI_PEER_SET_PARAM_CMDID, 402 WMI_PEER_ASSOC_CMDID, 403 WMI_PEER_ADD_WDS_ENTRY_CMDID, 404 WMI_PEER_REMOVE_WDS_ENTRY_CMDID, 405 WMI_PEER_MCAST_GROUP_CMDID, 406 WMI_PEER_INFO_REQ_CMDID, 407 WMI_PEER_GET_ESTIMATED_LINKSPEED_CMDID, 408 WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID, 409 WMI_PEER_UPDATE_WDS_ENTRY_CMDID, 410 WMI_PEER_ADD_PROXY_STA_ENTRY_CMDID, 411 WMI_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID, 412 WMI_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID, 413 WMI_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID, 414 WMI_PEER_ATF_REQUEST_CMDID, 415 WMI_PEER_BWF_REQUEST_CMDID, 416 WMI_PEER_REORDER_QUEUE_SETUP_CMDID, 417 WMI_PEER_REORDER_QUEUE_REMOVE_CMDID, 418 WMI_PEER_SET_RX_BLOCKSIZE_CMDID, 419 WMI_PEER_ANTDIV_INFO_REQ_CMDID, 420 WMI_BCN_TX_CMDID = WMI_TLV_CMD(WMI_GRP_MGMT), 421 WMI_PDEV_SEND_BCN_CMDID, 422 WMI_BCN_TMPL_CMDID, 423 WMI_BCN_FILTER_RX_CMDID, 424 WMI_PRB_REQ_FILTER_RX_CMDID, 425 WMI_MGMT_TX_CMDID, 426 WMI_PRB_TMPL_CMDID, 427 WMI_MGMT_TX_SEND_CMDID, 428 WMI_OFFCHAN_DATA_TX_SEND_CMDID, 429 WMI_PDEV_SEND_FD_CMDID, 430 WMI_BCN_OFFLOAD_CTRL_CMDID, 431 WMI_BSS_COLOR_CHANGE_ENABLE_CMDID, 432 WMI_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMDID, 433 WMI_FILS_DISCOVERY_TMPL_CMDID, 434 WMI_ADDBA_CLEAR_RESP_CMDID = WMI_TLV_CMD(WMI_GRP_BA_NEG), 435 WMI_ADDBA_SEND_CMDID, 436 WMI_ADDBA_STATUS_CMDID, 437 WMI_DELBA_SEND_CMDID, 438 WMI_ADDBA_SET_RESP_CMDID, 439 WMI_SEND_SINGLEAMSDU_CMDID, 440 WMI_STA_POWERSAVE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_PS), 441 WMI_STA_POWERSAVE_PARAM_CMDID, 442 WMI_STA_MIMO_PS_MODE_CMDID, 443 WMI_PDEV_DFS_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_DFS), 444 WMI_PDEV_DFS_DISABLE_CMDID, 445 WMI_DFS_PHYERR_FILTER_ENA_CMDID, 446 WMI_DFS_PHYERR_FILTER_DIS_CMDID, 447 WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMDID, 448 WMI_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMDID, 449 WMI_VDEV_ADFS_CH_CFG_CMDID, 450 WMI_VDEV_ADFS_OCAC_ABORT_CMDID, 451 WMI_ROAM_SCAN_MODE = WMI_TLV_CMD(WMI_GRP_ROAM), 452 WMI_ROAM_SCAN_RSSI_THRESHOLD, 453 WMI_ROAM_SCAN_PERIOD, 454 WMI_ROAM_SCAN_RSSI_CHANGE_THRESHOLD, 455 WMI_ROAM_AP_PROFILE, 456 WMI_ROAM_CHAN_LIST, 457 WMI_ROAM_SCAN_CMD, 458 WMI_ROAM_SYNCH_COMPLETE, 459 WMI_ROAM_SET_RIC_REQUEST_CMDID, 460 WMI_ROAM_INVOKE_CMDID, 461 WMI_ROAM_FILTER_CMDID, 462 WMI_ROAM_SUBNET_CHANGE_CONFIG_CMDID, 463 WMI_ROAM_CONFIGURE_MAWC_CMDID, 464 WMI_ROAM_SET_MBO_PARAM_CMDID, 465 WMI_ROAM_PER_CONFIG_CMDID, 466 WMI_ROAM_BTM_CONFIG_CMDID, 467 WMI_ENABLE_FILS_CMDID, 468 WMI_OFL_SCAN_ADD_AP_PROFILE = WMI_TLV_CMD(WMI_GRP_OFL_SCAN), 469 WMI_OFL_SCAN_REMOVE_AP_PROFILE, 470 WMI_OFL_SCAN_PERIOD, 471 WMI_P2P_DEV_SET_DEVICE_INFO = WMI_TLV_CMD(WMI_GRP_P2P), 472 WMI_P2P_DEV_SET_DISCOVERABILITY, 473 WMI_P2P_GO_SET_BEACON_IE, 474 WMI_P2P_GO_SET_PROBE_RESP_IE, 475 WMI_P2P_SET_VENDOR_IE_DATA_CMDID, 476 WMI_P2P_DISC_OFFLOAD_CONFIG_CMDID, 477 WMI_P2P_DISC_OFFLOAD_APPIE_CMDID, 478 WMI_P2P_DISC_OFFLOAD_PATTERN_CMDID, 479 WMI_P2P_SET_OPPPS_PARAM_CMDID, 480 WMI_P2P_LISTEN_OFFLOAD_START_CMDID, 481 WMI_P2P_LISTEN_OFFLOAD_STOP_CMDID, 482 WMI_AP_PS_PEER_PARAM_CMDID = WMI_TLV_CMD(WMI_GRP_AP_PS), 483 WMI_AP_PS_PEER_UAPSD_COEX_CMDID, 484 WMI_AP_PS_EGAP_PARAM_CMDID, 485 WMI_PEER_RATE_RETRY_SCHED_CMDID = WMI_TLV_CMD(WMI_GRP_RATE_CTRL), 486 WMI_WLAN_PROFILE_TRIGGER_CMDID = WMI_TLV_CMD(WMI_GRP_PROFILE), 487 WMI_WLAN_PROFILE_SET_HIST_INTVL_CMDID, 488 WMI_WLAN_PROFILE_GET_PROFILE_DATA_CMDID, 489 WMI_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID, 490 WMI_WLAN_PROFILE_LIST_PROFILE_ID_CMDID, 491 WMI_PDEV_SUSPEND_CMDID = WMI_TLV_CMD(WMI_GRP_SUSPEND), 492 WMI_PDEV_RESUME_CMDID, 493 WMI_ADD_BCN_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_BCN_FILTER), 494 WMI_RMV_BCN_FILTER_CMDID, 495 WMI_WOW_ADD_WAKE_PATTERN_CMDID = WMI_TLV_CMD(WMI_GRP_WOW), 496 WMI_WOW_DEL_WAKE_PATTERN_CMDID, 497 WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID, 498 WMI_WOW_ENABLE_CMDID, 499 WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID, 500 WMI_WOW_IOAC_ADD_KEEPALIVE_CMDID, 501 WMI_WOW_IOAC_DEL_KEEPALIVE_CMDID, 502 WMI_WOW_IOAC_ADD_WAKE_PATTERN_CMDID, 503 WMI_WOW_IOAC_DEL_WAKE_PATTERN_CMDID, 504 WMI_D0_WOW_ENABLE_DISABLE_CMDID, 505 WMI_EXTWOW_ENABLE_CMDID, 506 WMI_EXTWOW_SET_APP_TYPE1_PARAMS_CMDID, 507 WMI_EXTWOW_SET_APP_TYPE2_PARAMS_CMDID, 508 WMI_WOW_ENABLE_ICMPV6_NA_FLT_CMDID, 509 WMI_WOW_UDP_SVC_OFLD_CMDID, 510 WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMDID, 511 WMI_WOW_SET_ACTION_WAKE_UP_CMDID, 512 WMI_RTT_MEASREQ_CMDID = WMI_TLV_CMD(WMI_GRP_RTT), 513 WMI_RTT_TSF_CMDID, 514 WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID = WMI_TLV_CMD(WMI_GRP_SPECTRAL), 515 WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID, 516 WMI_REQUEST_STATS_CMDID = WMI_TLV_CMD(WMI_GRP_STATS), 517 WMI_MCC_SCHED_TRAFFIC_STATS_CMDID, 518 WMI_REQUEST_STATS_EXT_CMDID, 519 WMI_REQUEST_LINK_STATS_CMDID, 520 WMI_START_LINK_STATS_CMDID, 521 WMI_CLEAR_LINK_STATS_CMDID, 522 WMI_GET_FW_MEM_DUMP_CMDID, 523 WMI_DEBUG_MESG_FLUSH_CMDID, 524 WMI_DIAG_EVENT_LOG_CONFIG_CMDID, 525 WMI_REQUEST_WLAN_STATS_CMDID, 526 WMI_REQUEST_RCPI_CMDID, 527 WMI_REQUEST_PEER_STATS_INFO_CMDID, 528 WMI_REQUEST_RADIO_CHAN_STATS_CMDID, 529 WMI_SET_ARP_NS_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_ARP_NS_OFL), 530 WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMDID, 531 WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMDID, 532 WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_NLO_OFL), 533 WMI_APFIND_CMDID, 534 WMI_PASSPOINT_LIST_CONFIG_CMDID, 535 WMI_NLO_CONFIGURE_MAWC_CMDID, 536 WMI_GTK_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_GTK_OFL), 537 WMI_CSA_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_CSA_OFL), 538 WMI_CSA_OFFLOAD_CHANSWITCH_CMDID, 539 WMI_CHATTER_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_CHATTER), 540 WMI_CHATTER_ADD_COALESCING_FILTER_CMDID, 541 WMI_CHATTER_DELETE_COALESCING_FILTER_CMDID, 542 WMI_CHATTER_COALESCING_QUERY_CMDID, 543 WMI_PEER_TID_ADDBA_CMDID = WMI_TLV_CMD(WMI_GRP_TID_ADDBA), 544 WMI_PEER_TID_DELBA_CMDID, 545 WMI_STA_DTIM_PS_METHOD_CMDID, 546 WMI_STA_UAPSD_AUTO_TRIG_CMDID, 547 WMI_STA_KEEPALIVE_CMDID, 548 WMI_BA_REQ_SSN_CMDID, 549 WMI_ECHO_CMDID = WMI_TLV_CMD(WMI_GRP_MISC), 550 WMI_PDEV_UTF_CMDID, 551 WMI_DBGLOG_CFG_CMDID, 552 WMI_PDEV_QVIT_CMDID, 553 WMI_PDEV_FTM_INTG_CMDID, 554 WMI_VDEV_SET_KEEPALIVE_CMDID, 555 WMI_VDEV_GET_KEEPALIVE_CMDID, 556 WMI_FORCE_FW_HANG_CMDID, 557 WMI_SET_MCASTBCAST_FILTER_CMDID, 558 WMI_THERMAL_MGMT_CMDID, 559 WMI_HOST_AUTO_SHUTDOWN_CFG_CMDID, 560 WMI_TPC_CHAINMASK_CONFIG_CMDID, 561 WMI_SET_ANTENNA_DIVERSITY_CMDID, 562 WMI_OCB_SET_SCHED_CMDID, 563 WMI_RSSI_BREACH_MONITOR_CONFIG_CMDID, 564 WMI_LRO_CONFIG_CMDID, 565 WMI_TRANSFER_DATA_TO_FLASH_CMDID, 566 WMI_CONFIG_ENHANCED_MCAST_FILTER_CMDID, 567 WMI_VDEV_WISA_CMDID, 568 WMI_DBGLOG_TIME_STAMP_SYNC_CMDID, 569 WMI_SET_MULTIPLE_MCAST_FILTER_CMDID, 570 WMI_READ_DATA_FROM_FLASH_CMDID, 571 WMI_THERM_THROT_SET_CONF_CMDID, 572 WMI_RUNTIME_DPD_RECAL_CMDID, 573 WMI_GET_TPC_POWER_CMDID, 574 WMI_IDLE_TRIGGER_MONITOR_CMDID, 575 WMI_GPIO_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_GPIO), 576 WMI_GPIO_OUTPUT_CMDID, 577 WMI_TXBF_CMDID, 578 WMI_FWTEST_VDEV_MCC_SET_TBTT_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_FWTEST), 579 WMI_FWTEST_P2P_SET_NOA_PARAM_CMDID, 580 WMI_UNIT_TEST_CMDID, 581 WMI_FWTEST_CMDID, 582 WMI_QBOOST_CFG_CMDID, 583 WMI_TDLS_SET_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_TDLS), 584 WMI_TDLS_PEER_UPDATE_CMDID, 585 WMI_TDLS_SET_OFFCHAN_MODE_CMDID, 586 WMI_RESMGR_ADAPTIVE_OCS_EN_DIS_CMDID = WMI_TLV_CMD(WMI_GRP_RESMGR), 587 WMI_RESMGR_SET_CHAN_TIME_QUOTA_CMDID, 588 WMI_RESMGR_SET_CHAN_LATENCY_CMDID, 589 WMI_STA_SMPS_FORCE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_SMPS), 590 WMI_STA_SMPS_PARAM_CMDID, 591 WMI_HB_SET_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_WLAN_HB), 592 WMI_HB_SET_TCP_PARAMS_CMDID, 593 WMI_HB_SET_TCP_PKT_FILTER_CMDID, 594 WMI_HB_SET_UDP_PARAMS_CMDID, 595 WMI_HB_SET_UDP_PKT_FILTER_CMDID, 596 WMI_RMC_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_RMC), 597 WMI_RMC_SET_ACTION_PERIOD_CMDID, 598 WMI_RMC_CONFIG_CMDID, 599 WMI_RMC_SET_MANUAL_LEADER_CMDID, 600 WMI_MHF_OFFLOAD_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_MHF_OFL), 601 WMI_MHF_OFFLOAD_PLUMB_ROUTING_TBL_CMDID, 602 WMI_BATCH_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN), 603 WMI_BATCH_SCAN_DISABLE_CMDID, 604 WMI_BATCH_SCAN_TRIGGER_RESULT_CMDID, 605 WMI_OEM_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_OEM), 606 WMI_OEM_REQUEST_CMDID, 607 WMI_LPI_OEM_REQ_CMDID, 608 WMI_NAN_CMDID = WMI_TLV_CMD(WMI_GRP_NAN), 609 WMI_MODEM_POWER_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_COEX), 610 WMI_CHAN_AVOID_UPDATE_CMDID, 611 WMI_COEX_CONFIG_CMDID, 612 WMI_CHAN_AVOID_RPT_ALLOW_CMDID, 613 WMI_COEX_GET_ANTENNA_ISOLATION_CMDID, 614 WMI_SAR_LIMITS_CMDID, 615 WMI_OBSS_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_OBSS_OFL), 616 WMI_OBSS_SCAN_DISABLE_CMDID, 617 WMI_OBSS_COLOR_COLLISION_DET_CONFIG_CMDID, 618 WMI_LPI_MGMT_SNOOPING_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_LPI), 619 WMI_LPI_START_SCAN_CMDID, 620 WMI_LPI_STOP_SCAN_CMDID, 621 WMI_EXTSCAN_START_CMDID = WMI_TLV_CMD(WMI_GRP_EXTSCAN), 622 WMI_EXTSCAN_STOP_CMDID, 623 WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID, 624 WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID, 625 WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID, 626 WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID, 627 WMI_EXTSCAN_SET_CAPABILITIES_CMDID, 628 WMI_EXTSCAN_GET_CAPABILITIES_CMDID, 629 WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID, 630 WMI_EXTSCAN_CONFIGURE_MAWC_CMDID, 631 WMI_SET_DHCP_SERVER_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_DHCP_OFL), 632 WMI_IPA_OFFLOAD_ENABLE_DISABLE_CMDID = WMI_TLV_CMD(WMI_GRP_IPA), 633 WMI_MDNS_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL), 634 WMI_MDNS_SET_FQDN_CMDID, 635 WMI_MDNS_SET_RESPONSE_CMDID, 636 WMI_MDNS_GET_STATS_CMDID, 637 WMI_SAP_OFL_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_SAP_OFL), 638 WMI_SAP_SET_BLACKLIST_PARAM_CMDID, 639 WMI_OCB_SET_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_OCB), 640 WMI_OCB_SET_UTC_TIME_CMDID, 641 WMI_OCB_START_TIMING_ADVERT_CMDID, 642 WMI_OCB_STOP_TIMING_ADVERT_CMDID, 643 WMI_OCB_GET_TSF_TIMER_CMDID, 644 WMI_DCC_GET_STATS_CMDID, 645 WMI_DCC_CLEAR_STATS_CMDID, 646 WMI_DCC_UPDATE_NDL_CMDID, 647 WMI_SOC_SET_PCL_CMDID = WMI_TLV_CMD(WMI_GRP_SOC), 648 WMI_SOC_SET_HW_MODE_CMDID, 649 WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID, 650 WMI_SOC_SET_ANTENNA_MODE_CMDID, 651 WMI_PACKET_FILTER_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_PKT_FILTER), 652 WMI_PACKET_FILTER_ENABLE_CMDID, 653 WMI_MAWC_SENSOR_REPORT_IND_CMDID = WMI_TLV_CMD(WMI_GRP_MAWC), 654 WMI_PMF_OFFLOAD_SET_SA_QUERY_CMDID = WMI_TLV_CMD(WMI_GRP_PMF_OFFLOAD), 655 WMI_BPF_GET_CAPABILITY_CMDID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD), 656 WMI_BPF_GET_VDEV_STATS_CMDID, 657 WMI_BPF_SET_VDEV_INSTRUCTIONS_CMDID, 658 WMI_BPF_DEL_VDEV_INSTRUCTIONS_CMDID, 659 WMI_BPF_SET_VDEV_ACTIVE_MODE_CMDID, 660 WMI_MNT_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_MONITOR), 661 WMI_SET_CURRENT_COUNTRY_CMDID = WMI_TLV_CMD(WMI_GRP_REGULATORY), 662 WMI_11D_SCAN_START_CMDID, 663 WMI_11D_SCAN_STOP_CMDID, 664 WMI_SET_INIT_COUNTRY_CMDID, 665 WMI_NDI_GET_CAP_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE), 666 WMI_NDP_INITIATOR_REQ_CMDID, 667 WMI_NDP_RESPONDER_REQ_CMDID, 668 WMI_NDP_END_REQ_CMDID, 669 WMI_HW_DATA_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_HW_DATA_FILTER), 670 WMI_TWT_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_TWT), 671 WMI_TWT_DISABLE_CMDID, 672 WMI_TWT_ADD_DIALOG_CMDID, 673 WMI_TWT_DEL_DIALOG_CMDID, 674 WMI_TWT_PAUSE_DIALOG_CMDID, 675 WMI_TWT_RESUME_DIALOG_CMDID, 676 WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID = 677 WMI_TLV_CMD(WMI_GRP_SPATIAL_REUSE), 678 WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID, 679 }; 680 681 enum wmi_tlv_event_id { 682 WMI_SERVICE_READY_EVENTID = 0x1, 683 WMI_READY_EVENTID, 684 WMI_SERVICE_AVAILABLE_EVENTID, 685 WMI_SCAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SCAN), 686 WMI_PDEV_TPC_CONFIG_EVENTID = WMI_TLV_CMD(WMI_GRP_PDEV), 687 WMI_CHAN_INFO_EVENTID, 688 WMI_PHYERR_EVENTID, 689 WMI_PDEV_DUMP_EVENTID, 690 WMI_TX_PAUSE_EVENTID, 691 WMI_DFS_RADAR_EVENTID, 692 WMI_PDEV_L1SS_TRACK_EVENTID, 693 WMI_PDEV_TEMPERATURE_EVENTID, 694 WMI_SERVICE_READY_EXT_EVENTID, 695 WMI_PDEV_FIPS_EVENTID, 696 WMI_PDEV_CHANNEL_HOPPING_EVENTID, 697 WMI_PDEV_ANI_CCK_LEVEL_EVENTID, 698 WMI_PDEV_ANI_OFDM_LEVEL_EVENTID, 699 WMI_PDEV_TPC_EVENTID, 700 WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID, 701 WMI_PDEV_SET_HW_MODE_RESP_EVENTID, 702 WMI_PDEV_HW_MODE_TRANSITION_EVENTID, 703 WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID, 704 WMI_PDEV_ANTDIV_STATUS_EVENTID, 705 WMI_PDEV_CHIP_POWER_STATS_EVENTID, 706 WMI_PDEV_CHIP_POWER_SAVE_FAILURE_DETECTED_EVENTID, 707 WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID, 708 WMI_PDEV_CHECK_CAL_VERSION_EVENTID, 709 WMI_PDEV_DIV_RSSI_ANTID_EVENTID, 710 WMI_PDEV_BSS_CHAN_INFO_EVENTID, 711 WMI_PDEV_UPDATE_CTLTABLE_EVENTID, 712 WMI_PDEV_DMA_RING_CFG_RSP_EVENTID, 713 WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID, 714 WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID, 715 WMI_PDEV_CSC_SWITCH_COUNT_STATUS_EVENTID, 716 WMI_PDEV_COLD_BOOT_CAL_DATA_EVENTID, 717 WMI_PDEV_RAP_INFO_EVENTID, 718 WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID, 719 WMI_SERVICE_READY_EXT2_EVENTID, 720 WMI_VDEV_START_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_VDEV), 721 WMI_VDEV_STOPPED_EVENTID, 722 WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID, 723 WMI_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID, 724 WMI_VDEV_TSF_REPORT_EVENTID, 725 WMI_VDEV_DELETE_RESP_EVENTID, 726 WMI_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENTID, 727 WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENTID, 728 WMI_PEER_STA_KICKOUT_EVENTID = WMI_TLV_CMD(WMI_GRP_PEER), 729 WMI_PEER_INFO_EVENTID, 730 WMI_PEER_TX_FAIL_CNT_THR_EVENTID, 731 WMI_PEER_ESTIMATED_LINKSPEED_EVENTID, 732 WMI_PEER_STATE_EVENTID, 733 WMI_PEER_ASSOC_CONF_EVENTID, 734 WMI_PEER_DELETE_RESP_EVENTID, 735 WMI_PEER_RATECODE_LIST_EVENTID, 736 WMI_WDS_PEER_EVENTID, 737 WMI_PEER_STA_PS_STATECHG_EVENTID, 738 WMI_PEER_ANTDIV_INFO_EVENTID, 739 WMI_PEER_RESERVED0_EVENTID, 740 WMI_PEER_RESERVED1_EVENTID, 741 WMI_PEER_RESERVED2_EVENTID, 742 WMI_PEER_RESERVED3_EVENTID, 743 WMI_PEER_RESERVED4_EVENTID, 744 WMI_PEER_RESERVED5_EVENTID, 745 WMI_PEER_RESERVED6_EVENTID, 746 WMI_PEER_RESERVED7_EVENTID, 747 WMI_PEER_RESERVED8_EVENTID, 748 WMI_PEER_RESERVED9_EVENTID, 749 WMI_PEER_RESERVED10_EVENTID, 750 WMI_PEER_OPER_MODE_CHANGE_EVENTID, 751 WMI_PEER_TX_PN_RESPONSE_EVENTID, 752 WMI_PEER_CFR_CAPTURE_EVENTID, 753 WMI_PEER_CREATE_CONF_EVENTID, 754 WMI_MGMT_RX_EVENTID = WMI_TLV_CMD(WMI_GRP_MGMT), 755 WMI_HOST_SWBA_EVENTID, 756 WMI_TBTTOFFSET_UPDATE_EVENTID, 757 WMI_OFFLOAD_BCN_TX_STATUS_EVENTID, 758 WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID, 759 WMI_MGMT_TX_COMPLETION_EVENTID, 760 WMI_MGMT_TX_BUNDLE_COMPLETION_EVENTID, 761 WMI_TBTTOFFSET_EXT_UPDATE_EVENTID, 762 WMI_OFFCHAN_DATA_TX_COMPLETION_EVENTID, 763 WMI_HOST_FILS_DISCOVERY_EVENTID, 764 WMI_TX_DELBA_COMPLETE_EVENTID = WMI_TLV_CMD(WMI_GRP_BA_NEG), 765 WMI_TX_ADDBA_COMPLETE_EVENTID, 766 WMI_BA_RSP_SSN_EVENTID, 767 WMI_AGGR_STATE_TRIG_EVENTID, 768 WMI_ROAM_EVENTID = WMI_TLV_CMD(WMI_GRP_ROAM), 769 WMI_PROFILE_MATCH, 770 WMI_ROAM_SYNCH_EVENTID, 771 WMI_P2P_DISC_EVENTID = WMI_TLV_CMD(WMI_GRP_P2P), 772 WMI_P2P_NOA_EVENTID, 773 WMI_P2P_LISTEN_OFFLOAD_STOPPED_EVENTID, 774 WMI_AP_PS_EGAP_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_AP_PS), 775 WMI_PDEV_RESUME_EVENTID = WMI_TLV_CMD(WMI_GRP_SUSPEND), 776 WMI_WOW_WAKEUP_HOST_EVENTID = WMI_TLV_CMD(WMI_GRP_WOW), 777 WMI_D0_WOW_DISABLE_ACK_EVENTID, 778 WMI_WOW_INITIAL_WAKEUP_EVENTID, 779 WMI_RTT_MEASUREMENT_REPORT_EVENTID = WMI_TLV_CMD(WMI_GRP_RTT), 780 WMI_TSF_MEASUREMENT_REPORT_EVENTID, 781 WMI_RTT_ERROR_REPORT_EVENTID, 782 WMI_STATS_EXT_EVENTID = WMI_TLV_CMD(WMI_GRP_STATS), 783 WMI_IFACE_LINK_STATS_EVENTID, 784 WMI_PEER_LINK_STATS_EVENTID, 785 WMI_RADIO_LINK_STATS_EVENTID, 786 WMI_UPDATE_FW_MEM_DUMP_EVENTID, 787 WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID, 788 WMI_INST_RSSI_STATS_EVENTID, 789 WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID, 790 WMI_REPORT_STATS_EVENTID, 791 WMI_UPDATE_RCPI_EVENTID, 792 WMI_PEER_STATS_INFO_EVENTID, 793 WMI_RADIO_CHAN_STATS_EVENTID, 794 WMI_NLO_MATCH_EVENTID = WMI_TLV_CMD(WMI_GRP_NLO_OFL), 795 WMI_NLO_SCAN_COMPLETE_EVENTID, 796 WMI_APFIND_EVENTID, 797 WMI_PASSPOINT_MATCH_EVENTID, 798 WMI_GTK_OFFLOAD_STATUS_EVENTID = WMI_TLV_CMD(WMI_GRP_GTK_OFL), 799 WMI_GTK_REKEY_FAIL_EVENTID, 800 WMI_CSA_HANDLING_EVENTID = WMI_TLV_CMD(WMI_GRP_CSA_OFL), 801 WMI_CHATTER_PC_QUERY_EVENTID = WMI_TLV_CMD(WMI_GRP_CHATTER), 802 WMI_PDEV_DFS_RADAR_DETECTION_EVENTID = WMI_TLV_CMD(WMI_GRP_DFS), 803 WMI_VDEV_DFS_CAC_COMPLETE_EVENTID, 804 WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID, 805 WMI_ECHO_EVENTID = WMI_TLV_CMD(WMI_GRP_MISC), 806 WMI_PDEV_UTF_EVENTID, 807 WMI_DEBUG_MESG_EVENTID, 808 WMI_UPDATE_STATS_EVENTID, 809 WMI_DEBUG_PRINT_EVENTID, 810 WMI_DCS_INTERFERENCE_EVENTID, 811 WMI_PDEV_QVIT_EVENTID, 812 WMI_WLAN_PROFILE_DATA_EVENTID, 813 WMI_PDEV_FTM_INTG_EVENTID, 814 WMI_WLAN_FREQ_AVOID_EVENTID, 815 WMI_VDEV_GET_KEEPALIVE_EVENTID, 816 WMI_THERMAL_MGMT_EVENTID, 817 WMI_DIAG_DATA_CONTAINER_EVENTID, 818 WMI_HOST_AUTO_SHUTDOWN_EVENTID, 819 WMI_UPDATE_WHAL_MIB_STATS_EVENTID, 820 WMI_UPDATE_VDEV_RATE_STATS_EVENTID, 821 WMI_DIAG_EVENTID, 822 WMI_OCB_SET_SCHED_EVENTID, 823 WMI_DEBUG_MESG_FLUSH_COMPLETE_EVENTID, 824 WMI_RSSI_BREACH_EVENTID, 825 WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID, 826 WMI_PDEV_UTF_SCPC_EVENTID, 827 WMI_READ_DATA_FROM_FLASH_EVENTID, 828 WMI_REPORT_RX_AGGR_FAILURE_EVENTID, 829 WMI_PKGID_EVENTID, 830 WMI_GPIO_INPUT_EVENTID = WMI_TLV_CMD(WMI_GRP_GPIO), 831 WMI_UPLOADH_EVENTID, 832 WMI_CAPTUREH_EVENTID, 833 WMI_RFKILL_STATE_CHANGE_EVENTID, 834 WMI_TDLS_PEER_EVENTID = WMI_TLV_CMD(WMI_GRP_TDLS), 835 WMI_STA_SMPS_FORCE_MODE_COMPL_EVENTID = WMI_TLV_CMD(WMI_GRP_STA_SMPS), 836 WMI_BATCH_SCAN_ENABLED_EVENTID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN), 837 WMI_BATCH_SCAN_RESULT_EVENTID, 838 WMI_OEM_CAPABILITY_EVENTID = WMI_TLV_CMD(WMI_GRP_OEM), 839 WMI_OEM_MEASUREMENT_REPORT_EVENTID, 840 WMI_OEM_ERROR_REPORT_EVENTID, 841 WMI_OEM_RESPONSE_EVENTID, 842 WMI_NAN_EVENTID = WMI_TLV_CMD(WMI_GRP_NAN), 843 WMI_NAN_DISC_IFACE_CREATED_EVENTID, 844 WMI_NAN_DISC_IFACE_DELETED_EVENTID, 845 WMI_NAN_STARTED_CLUSTER_EVENTID, 846 WMI_NAN_JOINED_CLUSTER_EVENTID, 847 WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_TLV_CMD(WMI_GRP_COEX), 848 WMI_LPI_RESULT_EVENTID = WMI_TLV_CMD(WMI_GRP_LPI), 849 WMI_LPI_STATUS_EVENTID, 850 WMI_LPI_HANDOFF_EVENTID, 851 WMI_EXTSCAN_START_STOP_EVENTID = WMI_TLV_CMD(WMI_GRP_EXTSCAN), 852 WMI_EXTSCAN_OPERATION_EVENTID, 853 WMI_EXTSCAN_TABLE_USAGE_EVENTID, 854 WMI_EXTSCAN_CACHED_RESULTS_EVENTID, 855 WMI_EXTSCAN_WLAN_CHANGE_RESULTS_EVENTID, 856 WMI_EXTSCAN_HOTLIST_MATCH_EVENTID, 857 WMI_EXTSCAN_CAPABILITIES_EVENTID, 858 WMI_EXTSCAN_HOTLIST_SSID_MATCH_EVENTID, 859 WMI_MDNS_STATS_EVENTID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL), 860 WMI_SAP_OFL_ADD_STA_EVENTID = WMI_TLV_CMD(WMI_GRP_SAP_OFL), 861 WMI_SAP_OFL_DEL_STA_EVENTID, 862 WMI_OBSS_COLOR_COLLISION_DETECTION_EVENTID = 863 WMI_EVT_GRP_START_ID(WMI_GRP_OBSS_OFL), 864 WMI_OCB_SET_CONFIG_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_OCB), 865 WMI_OCB_GET_TSF_TIMER_RESP_EVENTID, 866 WMI_DCC_GET_STATS_RESP_EVENTID, 867 WMI_DCC_UPDATE_NDL_RESP_EVENTID, 868 WMI_DCC_STATS_EVENTID, 869 WMI_SOC_SET_HW_MODE_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_SOC), 870 WMI_SOC_HW_MODE_TRANSITION_EVENTID, 871 WMI_SOC_SET_DUAL_MAC_CONFIG_RESP_EVENTID, 872 WMI_MAWC_ENABLE_SENSOR_EVENTID = WMI_TLV_CMD(WMI_GRP_MAWC), 873 WMI_BPF_CAPABILIY_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD), 874 WMI_BPF_VDEV_STATS_INFO_EVENTID, 875 WMI_RMC_NEW_LEADER_EVENTID = WMI_TLV_CMD(WMI_GRP_RMC), 876 WMI_REG_CHAN_LIST_CC_EVENTID = WMI_TLV_CMD(WMI_GRP_REGULATORY), 877 WMI_11D_NEW_COUNTRY_EVENTID, 878 WMI_REG_CHAN_LIST_CC_EXT_EVENTID, 879 WMI_NDI_CAP_RSP_EVENTID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE), 880 WMI_NDP_INITIATOR_RSP_EVENTID, 881 WMI_NDP_RESPONDER_RSP_EVENTID, 882 WMI_NDP_END_RSP_EVENTID, 883 WMI_NDP_INDICATION_EVENTID, 884 WMI_NDP_CONFIRM_EVENTID, 885 WMI_NDP_END_INDICATION_EVENTID, 886 887 WMI_TWT_ENABLE_EVENTID = WMI_TLV_CMD(WMI_GRP_TWT), 888 WMI_TWT_DISABLE_EVENTID, 889 WMI_TWT_ADD_DIALOG_EVENTID, 890 WMI_TWT_DEL_DIALOG_EVENTID, 891 WMI_TWT_PAUSE_DIALOG_EVENTID, 892 WMI_TWT_RESUME_DIALOG_EVENTID, 893 }; 894 895 enum wmi_tlv_pdev_param { 896 WMI_PDEV_PARAM_TX_CHAIN_MASK = 0x1, 897 WMI_PDEV_PARAM_RX_CHAIN_MASK, 898 WMI_PDEV_PARAM_TXPOWER_LIMIT2G, 899 WMI_PDEV_PARAM_TXPOWER_LIMIT5G, 900 WMI_PDEV_PARAM_TXPOWER_SCALE, 901 WMI_PDEV_PARAM_BEACON_GEN_MODE, 902 WMI_PDEV_PARAM_BEACON_TX_MODE, 903 WMI_PDEV_PARAM_RESMGR_OFFCHAN_MODE, 904 WMI_PDEV_PARAM_PROTECTION_MODE, 905 WMI_PDEV_PARAM_DYNAMIC_BW, 906 WMI_PDEV_PARAM_NON_AGG_SW_RETRY_TH, 907 WMI_PDEV_PARAM_AGG_SW_RETRY_TH, 908 WMI_PDEV_PARAM_STA_KICKOUT_TH, 909 WMI_PDEV_PARAM_AC_AGGRSIZE_SCALING, 910 WMI_PDEV_PARAM_LTR_ENABLE, 911 WMI_PDEV_PARAM_LTR_AC_LATENCY_BE, 912 WMI_PDEV_PARAM_LTR_AC_LATENCY_BK, 913 WMI_PDEV_PARAM_LTR_AC_LATENCY_VI, 914 WMI_PDEV_PARAM_LTR_AC_LATENCY_VO, 915 WMI_PDEV_PARAM_LTR_AC_LATENCY_TIMEOUT, 916 WMI_PDEV_PARAM_LTR_SLEEP_OVERRIDE, 917 WMI_PDEV_PARAM_LTR_RX_OVERRIDE, 918 WMI_PDEV_PARAM_LTR_TX_ACTIVITY_TIMEOUT, 919 WMI_PDEV_PARAM_L1SS_ENABLE, 920 WMI_PDEV_PARAM_DSLEEP_ENABLE, 921 WMI_PDEV_PARAM_PCIELP_TXBUF_FLUSH, 922 WMI_PDEV_PARAM_PCIELP_TXBUF_WATERMARK, 923 WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_EN, 924 WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_VALUE, 925 WMI_PDEV_PARAM_PDEV_STATS_UPDATE_PERIOD, 926 WMI_PDEV_PARAM_VDEV_STATS_UPDATE_PERIOD, 927 WMI_PDEV_PARAM_PEER_STATS_UPDATE_PERIOD, 928 WMI_PDEV_PARAM_BCNFLT_STATS_UPDATE_PERIOD, 929 WMI_PDEV_PARAM_PMF_QOS, 930 WMI_PDEV_PARAM_ARP_AC_OVERRIDE, 931 WMI_PDEV_PARAM_DCS, 932 WMI_PDEV_PARAM_ANI_ENABLE, 933 WMI_PDEV_PARAM_ANI_POLL_PERIOD, 934 WMI_PDEV_PARAM_ANI_LISTEN_PERIOD, 935 WMI_PDEV_PARAM_ANI_OFDM_LEVEL, 936 WMI_PDEV_PARAM_ANI_CCK_LEVEL, 937 WMI_PDEV_PARAM_DYNTXCHAIN, 938 WMI_PDEV_PARAM_PROXY_STA, 939 WMI_PDEV_PARAM_IDLE_PS_CONFIG, 940 WMI_PDEV_PARAM_POWER_GATING_SLEEP, 941 WMI_PDEV_PARAM_RFKILL_ENABLE, 942 WMI_PDEV_PARAM_BURST_DUR, 943 WMI_PDEV_PARAM_BURST_ENABLE, 944 WMI_PDEV_PARAM_HW_RFKILL_CONFIG, 945 WMI_PDEV_PARAM_LOW_POWER_RF_ENABLE, 946 WMI_PDEV_PARAM_L1SS_TRACK, 947 WMI_PDEV_PARAM_HYST_EN, 948 WMI_PDEV_PARAM_POWER_COLLAPSE_ENABLE, 949 WMI_PDEV_PARAM_LED_SYS_STATE, 950 WMI_PDEV_PARAM_LED_ENABLE, 951 WMI_PDEV_PARAM_AUDIO_OVER_WLAN_LATENCY, 952 WMI_PDEV_PARAM_AUDIO_OVER_WLAN_ENABLE, 953 WMI_PDEV_PARAM_WHAL_MIB_STATS_UPDATE_ENABLE, 954 WMI_PDEV_PARAM_VDEV_RATE_STATS_UPDATE_PERIOD, 955 WMI_PDEV_PARAM_CTS_CBW, 956 WMI_PDEV_PARAM_WNTS_CONFIG, 957 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_ENABLE, 958 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_MIN_SLEEP_SLOP, 959 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_INC_DEC_STEP, 960 WMI_PDEV_PARAM_EARLY_RX_FIX_SLEEP_SLOP, 961 WMI_PDEV_PARAM_BMISS_BASED_ADAPTIVE_BTO_ENABLE, 962 WMI_PDEV_PARAM_BMISS_BTO_MIN_BCN_TIMEOUT, 963 WMI_PDEV_PARAM_BMISS_BTO_INC_DEC_STEP, 964 WMI_PDEV_PARAM_BTO_FIX_BCN_TIMEOUT, 965 WMI_PDEV_PARAM_CE_BASED_ADAPTIVE_BTO_ENABLE, 966 WMI_PDEV_PARAM_CE_BTO_COMBO_CE_VALUE, 967 WMI_PDEV_PARAM_TX_CHAIN_MASK_2G, 968 WMI_PDEV_PARAM_RX_CHAIN_MASK_2G, 969 WMI_PDEV_PARAM_TX_CHAIN_MASK_5G, 970 WMI_PDEV_PARAM_RX_CHAIN_MASK_5G, 971 WMI_PDEV_PARAM_TX_CHAIN_MASK_CCK, 972 WMI_PDEV_PARAM_TX_CHAIN_MASK_1SS, 973 WMI_PDEV_PARAM_CTS2SELF_FOR_P2P_GO_CONFIG, 974 WMI_PDEV_PARAM_TXPOWER_DECR_DB, 975 WMI_PDEV_PARAM_AGGR_BURST, 976 WMI_PDEV_PARAM_RX_DECAP_MODE, 977 WMI_PDEV_PARAM_FAST_CHANNEL_RESET, 978 WMI_PDEV_PARAM_SMART_ANTENNA_DEFAULT_ANTENNA, 979 WMI_PDEV_PARAM_ANTENNA_GAIN, 980 WMI_PDEV_PARAM_RX_FILTER, 981 WMI_PDEV_SET_MCAST_TO_UCAST_TID, 982 WMI_PDEV_PARAM_PROXY_STA_MODE, 983 WMI_PDEV_PARAM_SET_MCAST2UCAST_MODE, 984 WMI_PDEV_PARAM_SET_MCAST2UCAST_BUFFER, 985 WMI_PDEV_PARAM_REMOVE_MCAST2UCAST_BUFFER, 986 WMI_PDEV_PEER_STA_PS_STATECHG_ENABLE, 987 WMI_PDEV_PARAM_IGMPMLD_AC_OVERRIDE, 988 WMI_PDEV_PARAM_BLOCK_INTERBSS, 989 WMI_PDEV_PARAM_SET_DISABLE_RESET_CMDID, 990 WMI_PDEV_PARAM_SET_MSDU_TTL_CMDID, 991 WMI_PDEV_PARAM_SET_PPDU_DURATION_CMDID, 992 WMI_PDEV_PARAM_TXBF_SOUND_PERIOD_CMDID, 993 WMI_PDEV_PARAM_SET_PROMISC_MODE_CMDID, 994 WMI_PDEV_PARAM_SET_BURST_MODE_CMDID, 995 WMI_PDEV_PARAM_EN_STATS, 996 WMI_PDEV_PARAM_MU_GROUP_POLICY, 997 WMI_PDEV_PARAM_NOISE_DETECTION, 998 WMI_PDEV_PARAM_NOISE_THRESHOLD, 999 WMI_PDEV_PARAM_DPD_ENABLE, 1000 WMI_PDEV_PARAM_SET_MCAST_BCAST_ECHO, 1001 WMI_PDEV_PARAM_ATF_STRICT_SCH, 1002 WMI_PDEV_PARAM_ATF_SCHED_DURATION, 1003 WMI_PDEV_PARAM_ANT_PLZN, 1004 WMI_PDEV_PARAM_MGMT_RETRY_LIMIT, 1005 WMI_PDEV_PARAM_SENSITIVITY_LEVEL, 1006 WMI_PDEV_PARAM_SIGNED_TXPOWER_2G, 1007 WMI_PDEV_PARAM_SIGNED_TXPOWER_5G, 1008 WMI_PDEV_PARAM_ENABLE_PER_TID_AMSDU, 1009 WMI_PDEV_PARAM_ENABLE_PER_TID_AMPDU, 1010 WMI_PDEV_PARAM_CCA_THRESHOLD, 1011 WMI_PDEV_PARAM_RTS_FIXED_RATE, 1012 WMI_PDEV_PARAM_PDEV_RESET, 1013 WMI_PDEV_PARAM_WAPI_MBSSID_OFFSET, 1014 WMI_PDEV_PARAM_ARP_DBG_SRCADDR, 1015 WMI_PDEV_PARAM_ARP_DBG_DSTADDR, 1016 WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCH, 1017 WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCALING_FACTOR, 1018 WMI_PDEV_PARAM_CUST_TXPOWER_SCALE, 1019 WMI_PDEV_PARAM_ATF_DYNAMIC_ENABLE, 1020 WMI_PDEV_PARAM_CTRL_RETRY_LIMIT, 1021 WMI_PDEV_PARAM_PROPAGATION_DELAY, 1022 WMI_PDEV_PARAM_ENA_ANT_DIV, 1023 WMI_PDEV_PARAM_FORCE_CHAIN_ANT, 1024 WMI_PDEV_PARAM_ANT_DIV_SELFTEST, 1025 WMI_PDEV_PARAM_ANT_DIV_SELFTEST_INTVL, 1026 WMI_PDEV_PARAM_STATS_OBSERVATION_PERIOD, 1027 WMI_PDEV_PARAM_TX_PPDU_DELAY_BIN_SIZE_MS, 1028 WMI_PDEV_PARAM_TX_PPDU_DELAY_ARRAY_LEN, 1029 WMI_PDEV_PARAM_TX_MPDU_AGGR_ARRAY_LEN, 1030 WMI_PDEV_PARAM_RX_MPDU_AGGR_ARRAY_LEN, 1031 WMI_PDEV_PARAM_TX_SCH_DELAY, 1032 WMI_PDEV_PARAM_ENABLE_RTS_SIFS_BURSTING, 1033 WMI_PDEV_PARAM_MAX_MPDUS_IN_AMPDU, 1034 WMI_PDEV_PARAM_PEER_STATS_INFO_ENABLE, 1035 WMI_PDEV_PARAM_FAST_PWR_TRANSITION, 1036 WMI_PDEV_PARAM_RADIO_CHAN_STATS_ENABLE, 1037 WMI_PDEV_PARAM_RADIO_DIAGNOSIS_ENABLE, 1038 WMI_PDEV_PARAM_MESH_MCAST_ENABLE, 1039 WMI_PDEV_PARAM_SET_CMD_OBSS_PD_THRESHOLD = 0xbc, 1040 WMI_PDEV_PARAM_SET_CMD_OBSS_PD_PER_AC = 0xbe, 1041 WMI_PDEV_PARAM_ENABLE_SR_PROHIBIT = 0xc6, 1042 }; 1043 1044 enum wmi_tlv_vdev_param { 1045 WMI_VDEV_PARAM_RTS_THRESHOLD = 0x1, 1046 WMI_VDEV_PARAM_FRAGMENTATION_THRESHOLD, 1047 WMI_VDEV_PARAM_BEACON_INTERVAL, 1048 WMI_VDEV_PARAM_LISTEN_INTERVAL, 1049 WMI_VDEV_PARAM_MULTICAST_RATE, 1050 WMI_VDEV_PARAM_MGMT_TX_RATE, 1051 WMI_VDEV_PARAM_SLOT_TIME, 1052 WMI_VDEV_PARAM_PREAMBLE, 1053 WMI_VDEV_PARAM_SWBA_TIME, 1054 WMI_VDEV_STATS_UPDATE_PERIOD, 1055 WMI_VDEV_PWRSAVE_AGEOUT_TIME, 1056 WMI_VDEV_HOST_SWBA_INTERVAL, 1057 WMI_VDEV_PARAM_DTIM_PERIOD, 1058 WMI_VDEV_OC_SCHEDULER_AIR_TIME_LIMIT, 1059 WMI_VDEV_PARAM_WDS, 1060 WMI_VDEV_PARAM_ATIM_WINDOW, 1061 WMI_VDEV_PARAM_BMISS_COUNT_MAX, 1062 WMI_VDEV_PARAM_BMISS_FIRST_BCNT, 1063 WMI_VDEV_PARAM_BMISS_FINAL_BCNT, 1064 WMI_VDEV_PARAM_FEATURE_WMM, 1065 WMI_VDEV_PARAM_CHWIDTH, 1066 WMI_VDEV_PARAM_CHEXTOFFSET, 1067 WMI_VDEV_PARAM_DISABLE_HTPROTECTION, 1068 WMI_VDEV_PARAM_STA_QUICKKICKOUT, 1069 WMI_VDEV_PARAM_MGMT_RATE, 1070 WMI_VDEV_PARAM_PROTECTION_MODE, 1071 WMI_VDEV_PARAM_FIXED_RATE, 1072 WMI_VDEV_PARAM_SGI, 1073 WMI_VDEV_PARAM_LDPC, 1074 WMI_VDEV_PARAM_TX_STBC, 1075 WMI_VDEV_PARAM_RX_STBC, 1076 WMI_VDEV_PARAM_INTRA_BSS_FWD, 1077 WMI_VDEV_PARAM_DEF_KEYID, 1078 WMI_VDEV_PARAM_NSS, 1079 WMI_VDEV_PARAM_BCAST_DATA_RATE, 1080 WMI_VDEV_PARAM_MCAST_DATA_RATE, 1081 WMI_VDEV_PARAM_MCAST_INDICATE, 1082 WMI_VDEV_PARAM_DHCP_INDICATE, 1083 WMI_VDEV_PARAM_UNKNOWN_DEST_INDICATE, 1084 WMI_VDEV_PARAM_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS, 1085 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS, 1086 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS, 1087 WMI_VDEV_PARAM_AP_ENABLE_NAWDS, 1088 WMI_VDEV_PARAM_ENABLE_RTSCTS, 1089 WMI_VDEV_PARAM_TXBF, 1090 WMI_VDEV_PARAM_PACKET_POWERSAVE, 1091 WMI_VDEV_PARAM_DROP_UNENCRY, 1092 WMI_VDEV_PARAM_TX_ENCAP_TYPE, 1093 WMI_VDEV_PARAM_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS, 1094 WMI_VDEV_PARAM_EARLY_RX_ADJUST_ENABLE, 1095 WMI_VDEV_PARAM_EARLY_RX_TGT_BMISS_NUM, 1096 WMI_VDEV_PARAM_EARLY_RX_BMISS_SAMPLE_CYCLE, 1097 WMI_VDEV_PARAM_EARLY_RX_SLOP_STEP, 1098 WMI_VDEV_PARAM_EARLY_RX_INIT_SLOP, 1099 WMI_VDEV_PARAM_EARLY_RX_ADJUST_PAUSE, 1100 WMI_VDEV_PARAM_TX_PWRLIMIT, 1101 WMI_VDEV_PARAM_SNR_NUM_FOR_CAL, 1102 WMI_VDEV_PARAM_ROAM_FW_OFFLOAD, 1103 WMI_VDEV_PARAM_ENABLE_RMC, 1104 WMI_VDEV_PARAM_IBSS_MAX_BCN_LOST_MS, 1105 WMI_VDEV_PARAM_MAX_RATE, 1106 WMI_VDEV_PARAM_EARLY_RX_DRIFT_SAMPLE, 1107 WMI_VDEV_PARAM_SET_IBSS_TX_FAIL_CNT_THR, 1108 WMI_VDEV_PARAM_EBT_RESYNC_TIMEOUT, 1109 WMI_VDEV_PARAM_AGGR_TRIG_EVENT_ENABLE, 1110 WMI_VDEV_PARAM_IS_IBSS_POWER_SAVE_ALLOWED, 1111 WMI_VDEV_PARAM_IS_POWER_COLLAPSE_ALLOWED, 1112 WMI_VDEV_PARAM_IS_AWAKE_ON_TXRX_ENABLED, 1113 WMI_VDEV_PARAM_INACTIVITY_CNT, 1114 WMI_VDEV_PARAM_TXSP_END_INACTIVITY_TIME_MS, 1115 WMI_VDEV_PARAM_DTIM_POLICY, 1116 WMI_VDEV_PARAM_IBSS_PS_WARMUP_TIME_SECS, 1117 WMI_VDEV_PARAM_IBSS_PS_1RX_CHAIN_IN_ATIM_WINDOW_ENABLE, 1118 WMI_VDEV_PARAM_RX_LEAK_WINDOW, 1119 WMI_VDEV_PARAM_STATS_AVG_FACTOR, 1120 WMI_VDEV_PARAM_DISCONNECT_TH, 1121 WMI_VDEV_PARAM_RTSCTS_RATE, 1122 WMI_VDEV_PARAM_MCC_RTSCTS_PROTECTION_ENABLE, 1123 WMI_VDEV_PARAM_MCC_BROADCAST_PROBE_ENABLE, 1124 WMI_VDEV_PARAM_TXPOWER_SCALE, 1125 WMI_VDEV_PARAM_TXPOWER_SCALE_DECR_DB, 1126 WMI_VDEV_PARAM_MCAST2UCAST_SET, 1127 WMI_VDEV_PARAM_RC_NUM_RETRIES, 1128 WMI_VDEV_PARAM_CABQ_MAXDUR, 1129 WMI_VDEV_PARAM_MFPTEST_SET, 1130 WMI_VDEV_PARAM_RTS_FIXED_RATE, 1131 WMI_VDEV_PARAM_VHT_SGIMASK, 1132 WMI_VDEV_PARAM_VHT80_RATEMASK, 1133 WMI_VDEV_PARAM_PROXY_STA, 1134 WMI_VDEV_PARAM_VIRTUAL_CELL_MODE, 1135 WMI_VDEV_PARAM_RX_DECAP_TYPE, 1136 WMI_VDEV_PARAM_BW_NSS_RATEMASK, 1137 WMI_VDEV_PARAM_SENSOR_AP, 1138 WMI_VDEV_PARAM_BEACON_RATE, 1139 WMI_VDEV_PARAM_DTIM_ENABLE_CTS, 1140 WMI_VDEV_PARAM_STA_KICKOUT, 1141 WMI_VDEV_PARAM_CAPABILITIES, 1142 WMI_VDEV_PARAM_TSF_INCREMENT, 1143 WMI_VDEV_PARAM_AMPDU_PER_AC, 1144 WMI_VDEV_PARAM_RX_FILTER, 1145 WMI_VDEV_PARAM_MGMT_TX_POWER, 1146 WMI_VDEV_PARAM_NON_AGG_SW_RETRY_TH, 1147 WMI_VDEV_PARAM_AGG_SW_RETRY_TH, 1148 WMI_VDEV_PARAM_DISABLE_DYN_BW_RTS, 1149 WMI_VDEV_PARAM_ATF_SSID_SCHED_POLICY, 1150 WMI_VDEV_PARAM_HE_DCM, 1151 WMI_VDEV_PARAM_HE_RANGE_EXT, 1152 WMI_VDEV_PARAM_ENABLE_BCAST_PROBE_RESPONSE, 1153 WMI_VDEV_PARAM_FILS_MAX_CHANNEL_GUARD_TIME, 1154 WMI_VDEV_PARAM_HE_LTF = 0x74, 1155 WMI_VDEV_PARAM_ENABLE_DISABLE_RTT_RESPONDER_ROLE = 0x7d, 1156 WMI_VDEV_PARAM_BA_MODE = 0x7e, 1157 WMI_VDEV_PARAM_AUTORATE_MISC_CFG = 0x80, 1158 WMI_VDEV_PARAM_SET_HE_SOUNDING_MODE = 0x87, 1159 WMI_VDEV_PARAM_6GHZ_PARAMS = 0x99, 1160 WMI_VDEV_PARAM_PROTOTYPE = 0x8000, 1161 WMI_VDEV_PARAM_BSS_COLOR, 1162 WMI_VDEV_PARAM_SET_HEMU_MODE, 1163 WMI_VDEV_PARAM_HEOPS_0_31 = 0x8003, 1164 }; 1165 1166 enum wmi_tlv_peer_flags { 1167 WMI_TLV_PEER_AUTH = 0x00000001, 1168 WMI_TLV_PEER_QOS = 0x00000002, 1169 WMI_TLV_PEER_NEED_PTK_4_WAY = 0x00000004, 1170 WMI_TLV_PEER_NEED_GTK_2_WAY = 0x00000010, 1171 WMI_TLV_PEER_APSD = 0x00000800, 1172 WMI_TLV_PEER_HT = 0x00001000, 1173 WMI_TLV_PEER_40MHZ = 0x00002000, 1174 WMI_TLV_PEER_STBC = 0x00008000, 1175 WMI_TLV_PEER_LDPC = 0x00010000, 1176 WMI_TLV_PEER_DYN_MIMOPS = 0x00020000, 1177 WMI_TLV_PEER_STATIC_MIMOPS = 0x00040000, 1178 WMI_TLV_PEER_SPATIAL_MUX = 0x00200000, 1179 WMI_TLV_PEER_VHT = 0x02000000, 1180 WMI_TLV_PEER_80MHZ = 0x04000000, 1181 WMI_TLV_PEER_PMF = 0x08000000, 1182 WMI_PEER_IS_P2P_CAPABLE = 0x20000000, 1183 WMI_PEER_160MHZ = 0x40000000, 1184 WMI_PEER_SAFEMODE_EN = 0x80000000, 1185 1186 }; 1187 1188 /** Enum list of TLV Tags for each parameter structure type. */ 1189 enum wmi_tlv_tag { 1190 WMI_TAG_LAST_RESERVED = 15, 1191 WMI_TAG_FIRST_ARRAY_ENUM, 1192 WMI_TAG_ARRAY_UINT32 = WMI_TAG_FIRST_ARRAY_ENUM, 1193 WMI_TAG_ARRAY_BYTE, 1194 WMI_TAG_ARRAY_STRUCT, 1195 WMI_TAG_ARRAY_FIXED_STRUCT, 1196 WMI_TAG_LAST_ARRAY_ENUM = 31, 1197 WMI_TAG_SERVICE_READY_EVENT, 1198 WMI_TAG_HAL_REG_CAPABILITIES, 1199 WMI_TAG_WLAN_HOST_MEM_REQ, 1200 WMI_TAG_READY_EVENT, 1201 WMI_TAG_SCAN_EVENT, 1202 WMI_TAG_PDEV_TPC_CONFIG_EVENT, 1203 WMI_TAG_CHAN_INFO_EVENT, 1204 WMI_TAG_COMB_PHYERR_RX_HDR, 1205 WMI_TAG_VDEV_START_RESPONSE_EVENT, 1206 WMI_TAG_VDEV_STOPPED_EVENT, 1207 WMI_TAG_VDEV_INSTALL_KEY_COMPLETE_EVENT, 1208 WMI_TAG_PEER_STA_KICKOUT_EVENT, 1209 WMI_TAG_MGMT_RX_HDR, 1210 WMI_TAG_TBTT_OFFSET_EVENT, 1211 WMI_TAG_TX_DELBA_COMPLETE_EVENT, 1212 WMI_TAG_TX_ADDBA_COMPLETE_EVENT, 1213 WMI_TAG_ROAM_EVENT, 1214 WMI_TAG_WOW_EVENT_INFO, 1215 WMI_TAG_WOW_EVENT_INFO_SECTION_BITMAP, 1216 WMI_TAG_RTT_EVENT_HEADER, 1217 WMI_TAG_RTT_ERROR_REPORT_EVENT, 1218 WMI_TAG_RTT_MEAS_EVENT, 1219 WMI_TAG_ECHO_EVENT, 1220 WMI_TAG_FTM_INTG_EVENT, 1221 WMI_TAG_VDEV_GET_KEEPALIVE_EVENT, 1222 WMI_TAG_GPIO_INPUT_EVENT, 1223 WMI_TAG_CSA_EVENT, 1224 WMI_TAG_GTK_OFFLOAD_STATUS_EVENT, 1225 WMI_TAG_IGTK_INFO, 1226 WMI_TAG_DCS_INTERFERENCE_EVENT, 1227 WMI_TAG_ATH_DCS_CW_INT, 1228 WMI_TAG_WLAN_DCS_CW_INT = /* ALIAS */ 1229 WMI_TAG_ATH_DCS_CW_INT, 1230 WMI_TAG_ATH_DCS_WLAN_INT_STAT, 1231 WMI_TAG_WLAN_DCS_IM_TGT_STATS_T = /* ALIAS */ 1232 WMI_TAG_ATH_DCS_WLAN_INT_STAT, 1233 WMI_TAG_WLAN_PROFILE_CTX_T, 1234 WMI_TAG_WLAN_PROFILE_T, 1235 WMI_TAG_PDEV_QVIT_EVENT, 1236 WMI_TAG_HOST_SWBA_EVENT, 1237 WMI_TAG_TIM_INFO, 1238 WMI_TAG_P2P_NOA_INFO, 1239 WMI_TAG_STATS_EVENT, 1240 WMI_TAG_AVOID_FREQ_RANGES_EVENT, 1241 WMI_TAG_AVOID_FREQ_RANGE_DESC, 1242 WMI_TAG_GTK_REKEY_FAIL_EVENT, 1243 WMI_TAG_INIT_CMD, 1244 WMI_TAG_RESOURCE_CONFIG, 1245 WMI_TAG_WLAN_HOST_MEMORY_CHUNK, 1246 WMI_TAG_START_SCAN_CMD, 1247 WMI_TAG_STOP_SCAN_CMD, 1248 WMI_TAG_SCAN_CHAN_LIST_CMD, 1249 WMI_TAG_CHANNEL, 1250 WMI_TAG_PDEV_SET_REGDOMAIN_CMD, 1251 WMI_TAG_PDEV_SET_PARAM_CMD, 1252 WMI_TAG_PDEV_SET_WMM_PARAMS_CMD, 1253 WMI_TAG_WMM_PARAMS, 1254 WMI_TAG_PDEV_SET_QUIET_CMD, 1255 WMI_TAG_VDEV_CREATE_CMD, 1256 WMI_TAG_VDEV_DELETE_CMD, 1257 WMI_TAG_VDEV_START_REQUEST_CMD, 1258 WMI_TAG_P2P_NOA_DESCRIPTOR, 1259 WMI_TAG_P2P_GO_SET_BEACON_IE, 1260 WMI_TAG_GTK_OFFLOAD_CMD, 1261 WMI_TAG_VDEV_UP_CMD, 1262 WMI_TAG_VDEV_STOP_CMD, 1263 WMI_TAG_VDEV_DOWN_CMD, 1264 WMI_TAG_VDEV_SET_PARAM_CMD, 1265 WMI_TAG_VDEV_INSTALL_KEY_CMD, 1266 WMI_TAG_PEER_CREATE_CMD, 1267 WMI_TAG_PEER_DELETE_CMD, 1268 WMI_TAG_PEER_FLUSH_TIDS_CMD, 1269 WMI_TAG_PEER_SET_PARAM_CMD, 1270 WMI_TAG_PEER_ASSOC_COMPLETE_CMD, 1271 WMI_TAG_VHT_RATE_SET, 1272 WMI_TAG_BCN_TMPL_CMD, 1273 WMI_TAG_PRB_TMPL_CMD, 1274 WMI_TAG_BCN_PRB_INFO, 1275 WMI_TAG_PEER_TID_ADDBA_CMD, 1276 WMI_TAG_PEER_TID_DELBA_CMD, 1277 WMI_TAG_STA_POWERSAVE_MODE_CMD, 1278 WMI_TAG_STA_POWERSAVE_PARAM_CMD, 1279 WMI_TAG_STA_DTIM_PS_METHOD_CMD, 1280 WMI_TAG_ROAM_SCAN_MODE, 1281 WMI_TAG_ROAM_SCAN_RSSI_THRESHOLD, 1282 WMI_TAG_ROAM_SCAN_PERIOD, 1283 WMI_TAG_ROAM_SCAN_RSSI_CHANGE_THRESHOLD, 1284 WMI_TAG_PDEV_SUSPEND_CMD, 1285 WMI_TAG_PDEV_RESUME_CMD, 1286 WMI_TAG_ADD_BCN_FILTER_CMD, 1287 WMI_TAG_RMV_BCN_FILTER_CMD, 1288 WMI_TAG_WOW_ENABLE_CMD, 1289 WMI_TAG_WOW_HOSTWAKEUP_FROM_SLEEP_CMD, 1290 WMI_TAG_STA_UAPSD_AUTO_TRIG_CMD, 1291 WMI_TAG_STA_UAPSD_AUTO_TRIG_PARAM, 1292 WMI_TAG_SET_ARP_NS_OFFLOAD_CMD, 1293 WMI_TAG_ARP_OFFLOAD_TUPLE, 1294 WMI_TAG_NS_OFFLOAD_TUPLE, 1295 WMI_TAG_FTM_INTG_CMD, 1296 WMI_TAG_STA_KEEPALIVE_CMD, 1297 WMI_TAG_STA_KEEPALIVE_ARP_RESPONSE, 1298 WMI_TAG_P2P_SET_VENDOR_IE_DATA_CMD, 1299 WMI_TAG_AP_PS_PEER_CMD, 1300 WMI_TAG_PEER_RATE_RETRY_SCHED_CMD, 1301 WMI_TAG_WLAN_PROFILE_TRIGGER_CMD, 1302 WMI_TAG_WLAN_PROFILE_SET_HIST_INTVL_CMD, 1303 WMI_TAG_WLAN_PROFILE_GET_PROF_DATA_CMD, 1304 WMI_TAG_WLAN_PROFILE_ENABLE_PROFILE_ID_CMD, 1305 WMI_TAG_WOW_DEL_PATTERN_CMD, 1306 WMI_TAG_WOW_ADD_DEL_EVT_CMD, 1307 WMI_TAG_RTT_MEASREQ_HEAD, 1308 WMI_TAG_RTT_MEASREQ_BODY, 1309 WMI_TAG_RTT_TSF_CMD, 1310 WMI_TAG_VDEV_SPECTRAL_CONFIGURE_CMD, 1311 WMI_TAG_VDEV_SPECTRAL_ENABLE_CMD, 1312 WMI_TAG_REQUEST_STATS_CMD, 1313 WMI_TAG_NLO_CONFIG_CMD, 1314 WMI_TAG_NLO_CONFIGURED_PARAMETERS, 1315 WMI_TAG_CSA_OFFLOAD_ENABLE_CMD, 1316 WMI_TAG_CSA_OFFLOAD_CHANSWITCH_CMD, 1317 WMI_TAG_CHATTER_SET_MODE_CMD, 1318 WMI_TAG_ECHO_CMD, 1319 WMI_TAG_VDEV_SET_KEEPALIVE_CMD, 1320 WMI_TAG_VDEV_GET_KEEPALIVE_CMD, 1321 WMI_TAG_FORCE_FW_HANG_CMD, 1322 WMI_TAG_GPIO_CONFIG_CMD, 1323 WMI_TAG_GPIO_OUTPUT_CMD, 1324 WMI_TAG_PEER_ADD_WDS_ENTRY_CMD, 1325 WMI_TAG_PEER_REMOVE_WDS_ENTRY_CMD, 1326 WMI_TAG_BCN_TX_HDR, 1327 WMI_TAG_BCN_SEND_FROM_HOST_CMD, 1328 WMI_TAG_MGMT_TX_HDR, 1329 WMI_TAG_ADDBA_CLEAR_RESP_CMD, 1330 WMI_TAG_ADDBA_SEND_CMD, 1331 WMI_TAG_DELBA_SEND_CMD, 1332 WMI_TAG_ADDBA_SETRESPONSE_CMD, 1333 WMI_TAG_SEND_SINGLEAMSDU_CMD, 1334 WMI_TAG_PDEV_PKTLOG_ENABLE_CMD, 1335 WMI_TAG_PDEV_PKTLOG_DISABLE_CMD, 1336 WMI_TAG_PDEV_SET_HT_IE_CMD, 1337 WMI_TAG_PDEV_SET_VHT_IE_CMD, 1338 WMI_TAG_PDEV_SET_DSCP_TID_MAP_CMD, 1339 WMI_TAG_PDEV_GREEN_AP_PS_ENABLE_CMD, 1340 WMI_TAG_PDEV_GET_TPC_CONFIG_CMD, 1341 WMI_TAG_PDEV_SET_BASE_MACADDR_CMD, 1342 WMI_TAG_PEER_MCAST_GROUP_CMD, 1343 WMI_TAG_ROAM_AP_PROFILE, 1344 WMI_TAG_AP_PROFILE, 1345 WMI_TAG_SCAN_SCH_PRIORITY_TABLE_CMD, 1346 WMI_TAG_PDEV_DFS_ENABLE_CMD, 1347 WMI_TAG_PDEV_DFS_DISABLE_CMD, 1348 WMI_TAG_WOW_ADD_PATTERN_CMD, 1349 WMI_TAG_WOW_BITMAP_PATTERN_T, 1350 WMI_TAG_WOW_IPV4_SYNC_PATTERN_T, 1351 WMI_TAG_WOW_IPV6_SYNC_PATTERN_T, 1352 WMI_TAG_WOW_MAGIC_PATTERN_CMD, 1353 WMI_TAG_SCAN_UPDATE_REQUEST_CMD, 1354 WMI_TAG_CHATTER_PKT_COALESCING_FILTER, 1355 WMI_TAG_CHATTER_COALESCING_ADD_FILTER_CMD, 1356 WMI_TAG_CHATTER_COALESCING_DELETE_FILTER_CMD, 1357 WMI_TAG_CHATTER_COALESCING_QUERY_CMD, 1358 WMI_TAG_TXBF_CMD, 1359 WMI_TAG_DEBUG_LOG_CONFIG_CMD, 1360 WMI_TAG_NLO_EVENT, 1361 WMI_TAG_CHATTER_QUERY_REPLY_EVENT, 1362 WMI_TAG_UPLOAD_H_HDR, 1363 WMI_TAG_CAPTURE_H_EVENT_HDR, 1364 WMI_TAG_VDEV_WNM_SLEEPMODE_CMD, 1365 WMI_TAG_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD, 1366 WMI_TAG_VDEV_WMM_ADDTS_CMD, 1367 WMI_TAG_VDEV_WMM_DELTS_CMD, 1368 WMI_TAG_VDEV_SET_WMM_PARAMS_CMD, 1369 WMI_TAG_TDLS_SET_STATE_CMD, 1370 WMI_TAG_TDLS_PEER_UPDATE_CMD, 1371 WMI_TAG_TDLS_PEER_EVENT, 1372 WMI_TAG_TDLS_PEER_CAPABILITIES, 1373 WMI_TAG_VDEV_MCC_SET_TBTT_MODE_CMD, 1374 WMI_TAG_ROAM_CHAN_LIST, 1375 WMI_TAG_VDEV_MCC_BCN_INTVL_CHANGE_EVENT, 1376 WMI_TAG_RESMGR_ADAPTIVE_OCS_ENABLE_DISABLE_CMD, 1377 WMI_TAG_RESMGR_SET_CHAN_TIME_QUOTA_CMD, 1378 WMI_TAG_RESMGR_SET_CHAN_LATENCY_CMD, 1379 WMI_TAG_BA_REQ_SSN_CMD, 1380 WMI_TAG_BA_RSP_SSN_EVENT, 1381 WMI_TAG_STA_SMPS_FORCE_MODE_CMD, 1382 WMI_TAG_SET_MCASTBCAST_FILTER_CMD, 1383 WMI_TAG_P2P_SET_OPPPS_CMD, 1384 WMI_TAG_P2P_SET_NOA_CMD, 1385 WMI_TAG_BA_REQ_SSN_CMD_SUB_STRUCT_PARAM, 1386 WMI_TAG_BA_REQ_SSN_EVENT_SUB_STRUCT_PARAM, 1387 WMI_TAG_STA_SMPS_PARAM_CMD, 1388 WMI_TAG_VDEV_SET_GTX_PARAMS_CMD, 1389 WMI_TAG_MCC_SCHED_TRAFFIC_STATS_CMD, 1390 WMI_TAG_MCC_SCHED_STA_TRAFFIC_STATS, 1391 WMI_TAG_OFFLOAD_BCN_TX_STATUS_EVENT, 1392 WMI_TAG_P2P_NOA_EVENT, 1393 WMI_TAG_HB_SET_ENABLE_CMD, 1394 WMI_TAG_HB_SET_TCP_PARAMS_CMD, 1395 WMI_TAG_HB_SET_TCP_PKT_FILTER_CMD, 1396 WMI_TAG_HB_SET_UDP_PARAMS_CMD, 1397 WMI_TAG_HB_SET_UDP_PKT_FILTER_CMD, 1398 WMI_TAG_HB_IND_EVENT, 1399 WMI_TAG_TX_PAUSE_EVENT, 1400 WMI_TAG_RFKILL_EVENT, 1401 WMI_TAG_DFS_RADAR_EVENT, 1402 WMI_TAG_DFS_PHYERR_FILTER_ENA_CMD, 1403 WMI_TAG_DFS_PHYERR_FILTER_DIS_CMD, 1404 WMI_TAG_BATCH_SCAN_RESULT_SCAN_LIST, 1405 WMI_TAG_BATCH_SCAN_RESULT_NETWORK_INFO, 1406 WMI_TAG_BATCH_SCAN_ENABLE_CMD, 1407 WMI_TAG_BATCH_SCAN_DISABLE_CMD, 1408 WMI_TAG_BATCH_SCAN_TRIGGER_RESULT_CMD, 1409 WMI_TAG_BATCH_SCAN_ENABLED_EVENT, 1410 WMI_TAG_BATCH_SCAN_RESULT_EVENT, 1411 WMI_TAG_VDEV_PLMREQ_START_CMD, 1412 WMI_TAG_VDEV_PLMREQ_STOP_CMD, 1413 WMI_TAG_THERMAL_MGMT_CMD, 1414 WMI_TAG_THERMAL_MGMT_EVENT, 1415 WMI_TAG_PEER_INFO_REQ_CMD, 1416 WMI_TAG_PEER_INFO_EVENT, 1417 WMI_TAG_PEER_INFO, 1418 WMI_TAG_PEER_TX_FAIL_CNT_THR_EVENT, 1419 WMI_TAG_RMC_SET_MODE_CMD, 1420 WMI_TAG_RMC_SET_ACTION_PERIOD_CMD, 1421 WMI_TAG_RMC_CONFIG_CMD, 1422 WMI_TAG_MHF_OFFLOAD_SET_MODE_CMD, 1423 WMI_TAG_MHF_OFFLOAD_PLUMB_ROUTING_TABLE_CMD, 1424 WMI_TAG_ADD_PROACTIVE_ARP_RSP_PATTERN_CMD, 1425 WMI_TAG_DEL_PROACTIVE_ARP_RSP_PATTERN_CMD, 1426 WMI_TAG_NAN_CMD_PARAM, 1427 WMI_TAG_NAN_EVENT_HDR, 1428 WMI_TAG_PDEV_L1SS_TRACK_EVENT, 1429 WMI_TAG_DIAG_DATA_CONTAINER_EVENT, 1430 WMI_TAG_MODEM_POWER_STATE_CMD_PARAM, 1431 WMI_TAG_PEER_GET_ESTIMATED_LINKSPEED_CMD, 1432 WMI_TAG_PEER_ESTIMATED_LINKSPEED_EVENT, 1433 WMI_TAG_AGGR_STATE_TRIG_EVENT, 1434 WMI_TAG_MHF_OFFLOAD_ROUTING_TABLE_ENTRY, 1435 WMI_TAG_ROAM_SCAN_CMD, 1436 WMI_TAG_REQ_STATS_EXT_CMD, 1437 WMI_TAG_STATS_EXT_EVENT, 1438 WMI_TAG_OBSS_SCAN_ENABLE_CMD, 1439 WMI_TAG_OBSS_SCAN_DISABLE_CMD, 1440 WMI_TAG_OFFLOAD_PRB_RSP_TX_STATUS_EVENT, 1441 WMI_TAG_PDEV_SET_LED_CONFIG_CMD, 1442 WMI_TAG_HOST_AUTO_SHUTDOWN_CFG_CMD, 1443 WMI_TAG_HOST_AUTO_SHUTDOWN_EVENT, 1444 WMI_TAG_UPDATE_WHAL_MIB_STATS_EVENT, 1445 WMI_TAG_CHAN_AVOID_UPDATE_CMD_PARAM, 1446 WMI_TAG_WOW_IOAC_PKT_PATTERN_T, 1447 WMI_TAG_WOW_IOAC_TMR_PATTERN_T, 1448 WMI_TAG_WOW_IOAC_ADD_KEEPALIVE_CMD, 1449 WMI_TAG_WOW_IOAC_DEL_KEEPALIVE_CMD, 1450 WMI_TAG_WOW_IOAC_KEEPALIVE_T, 1451 WMI_TAG_WOW_IOAC_ADD_PATTERN_CMD, 1452 WMI_TAG_WOW_IOAC_DEL_PATTERN_CMD, 1453 WMI_TAG_START_LINK_STATS_CMD, 1454 WMI_TAG_CLEAR_LINK_STATS_CMD, 1455 WMI_TAG_REQUEST_LINK_STATS_CMD, 1456 WMI_TAG_IFACE_LINK_STATS_EVENT, 1457 WMI_TAG_RADIO_LINK_STATS_EVENT, 1458 WMI_TAG_PEER_STATS_EVENT, 1459 WMI_TAG_CHANNEL_STATS, 1460 WMI_TAG_RADIO_LINK_STATS, 1461 WMI_TAG_RATE_STATS, 1462 WMI_TAG_PEER_LINK_STATS, 1463 WMI_TAG_WMM_AC_STATS, 1464 WMI_TAG_IFACE_LINK_STATS, 1465 WMI_TAG_LPI_MGMT_SNOOPING_CONFIG_CMD, 1466 WMI_TAG_LPI_START_SCAN_CMD, 1467 WMI_TAG_LPI_STOP_SCAN_CMD, 1468 WMI_TAG_LPI_RESULT_EVENT, 1469 WMI_TAG_PEER_STATE_EVENT, 1470 WMI_TAG_EXTSCAN_BUCKET_CMD, 1471 WMI_TAG_EXTSCAN_BUCKET_CHANNEL_EVENT, 1472 WMI_TAG_EXTSCAN_START_CMD, 1473 WMI_TAG_EXTSCAN_STOP_CMD, 1474 WMI_TAG_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMD, 1475 WMI_TAG_EXTSCAN_WLAN_CHANGE_BSSID_PARAM_CMD, 1476 WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMD, 1477 WMI_TAG_EXTSCAN_GET_CACHED_RESULTS_CMD, 1478 WMI_TAG_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMD, 1479 WMI_TAG_EXTSCAN_SET_CAPABILITIES_CMD, 1480 WMI_TAG_EXTSCAN_GET_CAPABILITIES_CMD, 1481 WMI_TAG_EXTSCAN_OPERATION_EVENT, 1482 WMI_TAG_EXTSCAN_START_STOP_EVENT, 1483 WMI_TAG_EXTSCAN_TABLE_USAGE_EVENT, 1484 WMI_TAG_EXTSCAN_WLAN_DESCRIPTOR_EVENT, 1485 WMI_TAG_EXTSCAN_RSSI_INFO_EVENT, 1486 WMI_TAG_EXTSCAN_CACHED_RESULTS_EVENT, 1487 WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULTS_EVENT, 1488 WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULT_BSSID_EVENT, 1489 WMI_TAG_EXTSCAN_HOTLIST_MATCH_EVENT, 1490 WMI_TAG_EXTSCAN_CAPABILITIES_EVENT, 1491 WMI_TAG_EXTSCAN_CACHE_CAPABILITIES_EVENT, 1492 WMI_TAG_EXTSCAN_WLAN_CHANGE_MONITOR_CAPABILITIES_EVENT, 1493 WMI_TAG_EXTSCAN_HOTLIST_MONITOR_CAPABILITIES_EVENT, 1494 WMI_TAG_D0_WOW_ENABLE_DISABLE_CMD, 1495 WMI_TAG_D0_WOW_DISABLE_ACK_EVENT, 1496 WMI_TAG_UNIT_TEST_CMD, 1497 WMI_TAG_ROAM_OFFLOAD_TLV_PARAM, 1498 WMI_TAG_ROAM_11I_OFFLOAD_TLV_PARAM, 1499 WMI_TAG_ROAM_11R_OFFLOAD_TLV_PARAM, 1500 WMI_TAG_ROAM_ESE_OFFLOAD_TLV_PARAM, 1501 WMI_TAG_ROAM_SYNCH_EVENT, 1502 WMI_TAG_ROAM_SYNCH_COMPLETE, 1503 WMI_TAG_EXTWOW_ENABLE_CMD, 1504 WMI_TAG_EXTWOW_SET_APP_TYPE1_PARAMS_CMD, 1505 WMI_TAG_EXTWOW_SET_APP_TYPE2_PARAMS_CMD, 1506 WMI_TAG_LPI_STATUS_EVENT, 1507 WMI_TAG_LPI_HANDOFF_EVENT, 1508 WMI_TAG_VDEV_RATE_STATS_EVENT, 1509 WMI_TAG_VDEV_RATE_HT_INFO, 1510 WMI_TAG_RIC_REQUEST, 1511 WMI_TAG_PDEV_GET_TEMPERATURE_CMD, 1512 WMI_TAG_PDEV_TEMPERATURE_EVENT, 1513 WMI_TAG_SET_DHCP_SERVER_OFFLOAD_CMD, 1514 WMI_TAG_TPC_CHAINMASK_CONFIG_CMD, 1515 WMI_TAG_RIC_TSPEC, 1516 WMI_TAG_TPC_CHAINMASK_CONFIG, 1517 WMI_TAG_IPA_OFFLOAD_ENABLE_DISABLE_CMD, 1518 WMI_TAG_SCAN_PROB_REQ_OUI_CMD, 1519 WMI_TAG_KEY_MATERIAL, 1520 WMI_TAG_TDLS_SET_OFFCHAN_MODE_CMD, 1521 WMI_TAG_SET_LED_FLASHING_CMD, 1522 WMI_TAG_MDNS_OFFLOAD_CMD, 1523 WMI_TAG_MDNS_SET_FQDN_CMD, 1524 WMI_TAG_MDNS_SET_RESP_CMD, 1525 WMI_TAG_MDNS_GET_STATS_CMD, 1526 WMI_TAG_MDNS_STATS_EVENT, 1527 WMI_TAG_ROAM_INVOKE_CMD, 1528 WMI_TAG_PDEV_RESUME_EVENT, 1529 WMI_TAG_PDEV_SET_ANTENNA_DIVERSITY_CMD, 1530 WMI_TAG_SAP_OFL_ENABLE_CMD, 1531 WMI_TAG_SAP_OFL_ADD_STA_EVENT, 1532 WMI_TAG_SAP_OFL_DEL_STA_EVENT, 1533 WMI_TAG_APFIND_CMD_PARAM, 1534 WMI_TAG_APFIND_EVENT_HDR, 1535 WMI_TAG_OCB_SET_SCHED_CMD, 1536 WMI_TAG_OCB_SET_SCHED_EVENT, 1537 WMI_TAG_OCB_SET_CONFIG_CMD, 1538 WMI_TAG_OCB_SET_CONFIG_RESP_EVENT, 1539 WMI_TAG_OCB_SET_UTC_TIME_CMD, 1540 WMI_TAG_OCB_START_TIMING_ADVERT_CMD, 1541 WMI_TAG_OCB_STOP_TIMING_ADVERT_CMD, 1542 WMI_TAG_OCB_GET_TSF_TIMER_CMD, 1543 WMI_TAG_OCB_GET_TSF_TIMER_RESP_EVENT, 1544 WMI_TAG_DCC_GET_STATS_CMD, 1545 WMI_TAG_DCC_CHANNEL_STATS_REQUEST, 1546 WMI_TAG_DCC_GET_STATS_RESP_EVENT, 1547 WMI_TAG_DCC_CLEAR_STATS_CMD, 1548 WMI_TAG_DCC_UPDATE_NDL_CMD, 1549 WMI_TAG_DCC_UPDATE_NDL_RESP_EVENT, 1550 WMI_TAG_DCC_STATS_EVENT, 1551 WMI_TAG_OCB_CHANNEL, 1552 WMI_TAG_OCB_SCHEDULE_ELEMENT, 1553 WMI_TAG_DCC_NDL_STATS_PER_CHANNEL, 1554 WMI_TAG_DCC_NDL_CHAN, 1555 WMI_TAG_QOS_PARAMETER, 1556 WMI_TAG_DCC_NDL_ACTIVE_STATE_CONFIG, 1557 WMI_TAG_ROAM_SCAN_EXTENDED_THRESHOLD_PARAM, 1558 WMI_TAG_ROAM_FILTER, 1559 WMI_TAG_PASSPOINT_CONFIG_CMD, 1560 WMI_TAG_PASSPOINT_EVENT_HDR, 1561 WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMD, 1562 WMI_TAG_EXTSCAN_HOTLIST_SSID_MATCH_EVENT, 1563 WMI_TAG_VDEV_TSF_TSTAMP_ACTION_CMD, 1564 WMI_TAG_VDEV_TSF_REPORT_EVENT, 1565 WMI_TAG_GET_FW_MEM_DUMP, 1566 WMI_TAG_UPDATE_FW_MEM_DUMP, 1567 WMI_TAG_FW_MEM_DUMP_PARAMS, 1568 WMI_TAG_DEBUG_MESG_FLUSH, 1569 WMI_TAG_DEBUG_MESG_FLUSH_COMPLETE, 1570 WMI_TAG_PEER_SET_RATE_REPORT_CONDITION, 1571 WMI_TAG_ROAM_SUBNET_CHANGE_CONFIG, 1572 WMI_TAG_VDEV_SET_IE_CMD, 1573 WMI_TAG_RSSI_BREACH_MONITOR_CONFIG, 1574 WMI_TAG_RSSI_BREACH_EVENT, 1575 WMI_TAG_WOW_EVENT_INITIAL_WAKEUP, 1576 WMI_TAG_SOC_SET_PCL_CMD, 1577 WMI_TAG_SOC_SET_HW_MODE_CMD, 1578 WMI_TAG_SOC_SET_HW_MODE_RESPONSE_EVENT, 1579 WMI_TAG_SOC_HW_MODE_TRANSITION_EVENT, 1580 WMI_TAG_VDEV_TXRX_STREAMS, 1581 WMI_TAG_SOC_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY, 1582 WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_CMD, 1583 WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_RESPONSE_EVENT, 1584 WMI_TAG_WOW_IOAC_SOCK_PATTERN_T, 1585 WMI_TAG_WOW_ENABLE_ICMPV6_NA_FLT_CMD, 1586 WMI_TAG_DIAG_EVENT_LOG_CONFIG, 1587 WMI_TAG_DIAG_EVENT_LOG_SUPPORTED_EVENT_FIXED_PARAMS, 1588 WMI_TAG_PACKET_FILTER_CONFIG, 1589 WMI_TAG_PACKET_FILTER_ENABLE, 1590 WMI_TAG_SAP_SET_BLACKLIST_PARAM_CMD, 1591 WMI_TAG_MGMT_TX_SEND_CMD, 1592 WMI_TAG_MGMT_TX_COMPL_EVENT, 1593 WMI_TAG_SOC_SET_ANTENNA_MODE_CMD, 1594 WMI_TAG_WOW_UDP_SVC_OFLD_CMD, 1595 WMI_TAG_LRO_INFO_CMD, 1596 WMI_TAG_ROAM_EARLYSTOP_RSSI_THRES_PARAM, 1597 WMI_TAG_SERVICE_READY_EXT_EVENT, 1598 WMI_TAG_MAWC_SENSOR_REPORT_IND_CMD, 1599 WMI_TAG_MAWC_ENABLE_SENSOR_EVENT, 1600 WMI_TAG_ROAM_CONFIGURE_MAWC_CMD, 1601 WMI_TAG_NLO_CONFIGURE_MAWC_CMD, 1602 WMI_TAG_EXTSCAN_CONFIGURE_MAWC_CMD, 1603 WMI_TAG_PEER_ASSOC_CONF_EVENT, 1604 WMI_TAG_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMD, 1605 WMI_TAG_AP_PS_EGAP_PARAM_CMD, 1606 WMI_TAG_AP_PS_EGAP_INFO_EVENT, 1607 WMI_TAG_PMF_OFFLOAD_SET_SA_QUERY_CMD, 1608 WMI_TAG_TRANSFER_DATA_TO_FLASH_CMD, 1609 WMI_TAG_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENT, 1610 WMI_TAG_SCPC_EVENT, 1611 WMI_TAG_AP_PS_EGAP_INFO_CHAINMASK_LIST, 1612 WMI_TAG_STA_SMPS_FORCE_MODE_COMPLETE_EVENT, 1613 WMI_TAG_BPF_GET_CAPABILITY_CMD, 1614 WMI_TAG_BPF_CAPABILITY_INFO_EVT, 1615 WMI_TAG_BPF_GET_VDEV_STATS_CMD, 1616 WMI_TAG_BPF_VDEV_STATS_INFO_EVT, 1617 WMI_TAG_BPF_SET_VDEV_INSTRUCTIONS_CMD, 1618 WMI_TAG_BPF_DEL_VDEV_INSTRUCTIONS_CMD, 1619 WMI_TAG_VDEV_DELETE_RESP_EVENT, 1620 WMI_TAG_PEER_DELETE_RESP_EVENT, 1621 WMI_TAG_ROAM_DENSE_THRES_PARAM, 1622 WMI_TAG_ENLO_CANDIDATE_SCORE_PARAM, 1623 WMI_TAG_PEER_UPDATE_WDS_ENTRY_CMD, 1624 WMI_TAG_VDEV_CONFIG_RATEMASK, 1625 WMI_TAG_PDEV_FIPS_CMD, 1626 WMI_TAG_PDEV_SMART_ANT_ENABLE_CMD, 1627 WMI_TAG_PDEV_SMART_ANT_SET_RX_ANTENNA_CMD, 1628 WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_CMD, 1629 WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_CMD, 1630 WMI_TAG_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMD, 1631 WMI_TAG_PDEV_SET_ANT_SWITCH_TBL_CMD, 1632 WMI_TAG_PDEV_SET_CTL_TABLE_CMD, 1633 WMI_TAG_PDEV_SET_MIMOGAIN_TABLE_CMD, 1634 WMI_TAG_FWTEST_SET_PARAM_CMD, 1635 WMI_TAG_PEER_ATF_REQUEST, 1636 WMI_TAG_VDEV_ATF_REQUEST, 1637 WMI_TAG_PDEV_GET_ANI_CCK_CONFIG_CMD, 1638 WMI_TAG_PDEV_GET_ANI_OFDM_CONFIG_CMD, 1639 WMI_TAG_INST_RSSI_STATS_RESP, 1640 WMI_TAG_MED_UTIL_REPORT_EVENT, 1641 WMI_TAG_PEER_STA_PS_STATECHANGE_EVENT, 1642 WMI_TAG_WDS_ADDR_EVENT, 1643 WMI_TAG_PEER_RATECODE_LIST_EVENT, 1644 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENT, 1645 WMI_TAG_PDEV_TPC_EVENT, 1646 WMI_TAG_ANI_OFDM_EVENT, 1647 WMI_TAG_ANI_CCK_EVENT, 1648 WMI_TAG_PDEV_CHANNEL_HOPPING_EVENT, 1649 WMI_TAG_PDEV_FIPS_EVENT, 1650 WMI_TAG_ATF_PEER_INFO, 1651 WMI_TAG_PDEV_GET_TPC_CMD, 1652 WMI_TAG_VDEV_FILTER_NRP_CONFIG_CMD, 1653 WMI_TAG_QBOOST_CFG_CMD, 1654 WMI_TAG_PDEV_SMART_ANT_GPIO_HANDLE, 1655 WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_SERIES, 1656 WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_PARAM, 1657 WMI_TAG_PDEV_SET_ANT_CTRL_CHAIN, 1658 WMI_TAG_PEER_CCK_OFDM_RATE_INFO, 1659 WMI_TAG_PEER_MCS_RATE_INFO, 1660 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBR, 1661 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBM, 1662 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_FREQNUM, 1663 WMI_TAG_MU_REPORT_TOTAL_MU, 1664 WMI_TAG_VDEV_SET_DSCP_TID_MAP_CMD, 1665 WMI_TAG_ROAM_SET_MBO, 1666 WMI_TAG_MIB_STATS_ENABLE_CMD, 1667 WMI_TAG_NAN_DISC_IFACE_CREATED_EVENT, 1668 WMI_TAG_NAN_DISC_IFACE_DELETED_EVENT, 1669 WMI_TAG_NAN_STARTED_CLUSTER_EVENT, 1670 WMI_TAG_NAN_JOINED_CLUSTER_EVENT, 1671 WMI_TAG_NDI_GET_CAP_REQ, 1672 WMI_TAG_NDP_INITIATOR_REQ, 1673 WMI_TAG_NDP_RESPONDER_REQ, 1674 WMI_TAG_NDP_END_REQ, 1675 WMI_TAG_NDI_CAP_RSP_EVENT, 1676 WMI_TAG_NDP_INITIATOR_RSP_EVENT, 1677 WMI_TAG_NDP_RESPONDER_RSP_EVENT, 1678 WMI_TAG_NDP_END_RSP_EVENT, 1679 WMI_TAG_NDP_INDICATION_EVENT, 1680 WMI_TAG_NDP_CONFIRM_EVENT, 1681 WMI_TAG_NDP_END_INDICATION_EVENT, 1682 WMI_TAG_VDEV_SET_QUIET_CMD, 1683 WMI_TAG_PDEV_SET_PCL_CMD, 1684 WMI_TAG_PDEV_SET_HW_MODE_CMD, 1685 WMI_TAG_PDEV_SET_MAC_CONFIG_CMD, 1686 WMI_TAG_PDEV_SET_ANTENNA_MODE_CMD, 1687 WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_EVENT, 1688 WMI_TAG_PDEV_HW_MODE_TRANSITION_EVENT, 1689 WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY, 1690 WMI_TAG_PDEV_SET_MAC_CONFIG_RESPONSE_EVENT, 1691 WMI_TAG_COEX_CONFIG_CMD, 1692 WMI_TAG_CONFIG_ENHANCED_MCAST_FILTER, 1693 WMI_TAG_CHAN_AVOID_RPT_ALLOW_CMD, 1694 WMI_TAG_SET_PERIODIC_CHANNEL_STATS_CONFIG, 1695 WMI_TAG_VDEV_SET_CUSTOM_AGGR_SIZE_CMD, 1696 WMI_TAG_PDEV_WAL_POWER_DEBUG_CMD, 1697 WMI_TAG_MAC_PHY_CAPABILITIES, 1698 WMI_TAG_HW_MODE_CAPABILITIES, 1699 WMI_TAG_SOC_MAC_PHY_HW_MODE_CAPS, 1700 WMI_TAG_HAL_REG_CAPABILITIES_EXT, 1701 WMI_TAG_SOC_HAL_REG_CAPABILITIES, 1702 WMI_TAG_VDEV_WISA_CMD, 1703 WMI_TAG_TX_POWER_LEVEL_STATS_EVT, 1704 WMI_TAG_SCAN_ADAPTIVE_DWELL_PARAMETERS_TLV, 1705 WMI_TAG_SCAN_ADAPTIVE_DWELL_CONFIG, 1706 WMI_TAG_WOW_SET_ACTION_WAKE_UP_CMD, 1707 WMI_TAG_NDP_END_RSP_PER_NDI, 1708 WMI_TAG_PEER_BWF_REQUEST, 1709 WMI_TAG_BWF_PEER_INFO, 1710 WMI_TAG_DBGLOG_TIME_STAMP_SYNC_CMD, 1711 WMI_TAG_RMC_SET_LEADER_CMD, 1712 WMI_TAG_RMC_MANUAL_LEADER_EVENT, 1713 WMI_TAG_PER_CHAIN_RSSI_STATS, 1714 WMI_TAG_RSSI_STATS, 1715 WMI_TAG_P2P_LO_START_CMD, 1716 WMI_TAG_P2P_LO_STOP_CMD, 1717 WMI_TAG_P2P_LO_STOPPED_EVENT, 1718 WMI_TAG_REORDER_QUEUE_SETUP_CMD, 1719 WMI_TAG_REORDER_QUEUE_REMOVE_CMD, 1720 WMI_TAG_SET_MULTIPLE_MCAST_FILTER_CMD, 1721 WMI_TAG_MGMT_TX_COMPL_BUNDLE_EVENT, 1722 WMI_TAG_READ_DATA_FROM_FLASH_CMD, 1723 WMI_TAG_READ_DATA_FROM_FLASH_EVENT, 1724 WMI_TAG_PDEV_SET_REORDER_TIMEOUT_VAL_CMD, 1725 WMI_TAG_PEER_SET_RX_BLOCKSIZE_CMD, 1726 WMI_TAG_PDEV_SET_WAKEUP_CONFIG_CMDID, 1727 WMI_TAG_TLV_BUF_LEN_PARAM, 1728 WMI_TAG_SERVICE_AVAILABLE_EVENT, 1729 WMI_TAG_PEER_ANTDIV_INFO_REQ_CMD, 1730 WMI_TAG_PEER_ANTDIV_INFO_EVENT, 1731 WMI_TAG_PEER_ANTDIV_INFO, 1732 WMI_TAG_PDEV_GET_ANTDIV_STATUS_CMD, 1733 WMI_TAG_PDEV_ANTDIV_STATUS_EVENT, 1734 WMI_TAG_MNT_FILTER_CMD, 1735 WMI_TAG_GET_CHIP_POWER_STATS_CMD, 1736 WMI_TAG_PDEV_CHIP_POWER_STATS_EVENT, 1737 WMI_TAG_COEX_GET_ANTENNA_ISOLATION_CMD, 1738 WMI_TAG_COEX_REPORT_ISOLATION_EVENT, 1739 WMI_TAG_CHAN_CCA_STATS, 1740 WMI_TAG_PEER_SIGNAL_STATS, 1741 WMI_TAG_TX_STATS, 1742 WMI_TAG_PEER_AC_TX_STATS, 1743 WMI_TAG_RX_STATS, 1744 WMI_TAG_PEER_AC_RX_STATS, 1745 WMI_TAG_REPORT_STATS_EVENT, 1746 WMI_TAG_CHAN_CCA_STATS_THRESH, 1747 WMI_TAG_PEER_SIGNAL_STATS_THRESH, 1748 WMI_TAG_TX_STATS_THRESH, 1749 WMI_TAG_RX_STATS_THRESH, 1750 WMI_TAG_PDEV_SET_STATS_THRESHOLD_CMD, 1751 WMI_TAG_REQUEST_WLAN_STATS_CMD, 1752 WMI_TAG_RX_AGGR_FAILURE_EVENT, 1753 WMI_TAG_RX_AGGR_FAILURE_INFO, 1754 WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMD, 1755 WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENT, 1756 WMI_TAG_PDEV_BAND_TO_MAC, 1757 WMI_TAG_TBTT_OFFSET_INFO, 1758 WMI_TAG_TBTT_OFFSET_EXT_EVENT, 1759 WMI_TAG_SAR_LIMITS_CMD, 1760 WMI_TAG_SAR_LIMIT_CMD_ROW, 1761 WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMD, 1762 WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMD, 1763 WMI_TAG_VDEV_ADFS_CH_CFG_CMD, 1764 WMI_TAG_VDEV_ADFS_OCAC_ABORT_CMD, 1765 WMI_TAG_PDEV_DFS_RADAR_DETECTION_EVENT, 1766 WMI_TAG_VDEV_ADFS_OCAC_COMPLETE_EVENT, 1767 WMI_TAG_VDEV_DFS_CAC_COMPLETE_EVENT, 1768 WMI_TAG_VENDOR_OUI, 1769 WMI_TAG_REQUEST_RCPI_CMD, 1770 WMI_TAG_UPDATE_RCPI_EVENT, 1771 WMI_TAG_REQUEST_PEER_STATS_INFO_CMD, 1772 WMI_TAG_PEER_STATS_INFO, 1773 WMI_TAG_PEER_STATS_INFO_EVENT, 1774 WMI_TAG_PKGID_EVENT, 1775 WMI_TAG_CONNECTED_NLO_RSSI_PARAMS, 1776 WMI_TAG_SET_CURRENT_COUNTRY_CMD, 1777 WMI_TAG_REGULATORY_RULE_STRUCT, 1778 WMI_TAG_REG_CHAN_LIST_CC_EVENT, 1779 WMI_TAG_11D_SCAN_START_CMD, 1780 WMI_TAG_11D_SCAN_STOP_CMD, 1781 WMI_TAG_11D_NEW_COUNTRY_EVENT, 1782 WMI_TAG_REQUEST_RADIO_CHAN_STATS_CMD, 1783 WMI_TAG_RADIO_CHAN_STATS, 1784 WMI_TAG_RADIO_CHAN_STATS_EVENT, 1785 WMI_TAG_ROAM_PER_CONFIG, 1786 WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMD, 1787 WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENT, 1788 WMI_TAG_BPF_SET_VDEV_ACTIVE_MODE_CMD, 1789 WMI_TAG_HW_DATA_FILTER_CMD, 1790 WMI_TAG_CONNECTED_NLO_BSS_BAND_RSSI_PREF, 1791 WMI_TAG_PEER_OPER_MODE_CHANGE_EVENT, 1792 WMI_TAG_CHIP_POWER_SAVE_FAILURE_DETECTED, 1793 WMI_TAG_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMD, 1794 WMI_TAG_PDEV_CSA_SWITCH_COUNT_STATUS_EVENT, 1795 WMI_TAG_PDEV_UPDATE_PKT_ROUTING_CMD, 1796 WMI_TAG_PDEV_CHECK_CAL_VERSION_CMD, 1797 WMI_TAG_PDEV_CHECK_CAL_VERSION_EVENT, 1798 WMI_TAG_PDEV_SET_DIVERSITY_GAIN_CMD, 1799 WMI_TAG_MAC_PHY_CHAINMASK_COMBO, 1800 WMI_TAG_MAC_PHY_CHAINMASK_CAPABILITY, 1801 WMI_TAG_VDEV_SET_ARP_STATS_CMD, 1802 WMI_TAG_VDEV_GET_ARP_STATS_CMD, 1803 WMI_TAG_VDEV_GET_ARP_STATS_EVENT, 1804 WMI_TAG_IFACE_OFFLOAD_STATS, 1805 WMI_TAG_REQUEST_STATS_CMD_SUB_STRUCT_PARAM, 1806 WMI_TAG_RSSI_CTL_EXT, 1807 WMI_TAG_SINGLE_PHYERR_EXT_RX_HDR, 1808 WMI_TAG_COEX_BT_ACTIVITY_EVENT, 1809 WMI_TAG_VDEV_GET_TX_POWER_CMD, 1810 WMI_TAG_VDEV_TX_POWER_EVENT, 1811 WMI_TAG_OFFCHAN_DATA_TX_COMPL_EVENT, 1812 WMI_TAG_OFFCHAN_DATA_TX_SEND_CMD, 1813 WMI_TAG_TX_SEND_PARAMS, 1814 WMI_TAG_HE_RATE_SET, 1815 WMI_TAG_CONGESTION_STATS, 1816 WMI_TAG_SET_INIT_COUNTRY_CMD, 1817 WMI_TAG_SCAN_DBS_DUTY_CYCLE, 1818 WMI_TAG_SCAN_DBS_DUTY_CYCLE_PARAM_TLV, 1819 WMI_TAG_PDEV_DIV_GET_RSSI_ANTID, 1820 WMI_TAG_THERM_THROT_CONFIG_REQUEST, 1821 WMI_TAG_THERM_THROT_LEVEL_CONFIG_INFO, 1822 WMI_TAG_THERM_THROT_STATS_EVENT, 1823 WMI_TAG_THERM_THROT_LEVEL_STATS_INFO, 1824 WMI_TAG_PDEV_DIV_RSSI_ANTID_EVENT, 1825 WMI_TAG_OEM_DMA_RING_CAPABILITIES, 1826 WMI_TAG_OEM_DMA_RING_CFG_REQ, 1827 WMI_TAG_OEM_DMA_RING_CFG_RSP, 1828 WMI_TAG_OEM_INDIRECT_DATA, 1829 WMI_TAG_OEM_DMA_BUF_RELEASE, 1830 WMI_TAG_OEM_DMA_BUF_RELEASE_ENTRY, 1831 WMI_TAG_PDEV_BSS_CHAN_INFO_REQUEST, 1832 WMI_TAG_PDEV_BSS_CHAN_INFO_EVENT, 1833 WMI_TAG_ROAM_LCA_DISALLOW_CONFIG, 1834 WMI_TAG_VDEV_LIMIT_OFFCHAN_CMD, 1835 WMI_TAG_ROAM_RSSI_REJECTION_OCE_CONFIG, 1836 WMI_TAG_UNIT_TEST_EVENT, 1837 WMI_TAG_ROAM_FILS_OFFLOAD, 1838 WMI_TAG_PDEV_UPDATE_PMK_CACHE_CMD, 1839 WMI_TAG_PMK_CACHE, 1840 WMI_TAG_PDEV_UPDATE_FILS_HLP_PKT_CMD, 1841 WMI_TAG_ROAM_FILS_SYNCH, 1842 WMI_TAG_GTK_OFFLOAD_EXTENDED, 1843 WMI_TAG_ROAM_BG_SCAN_ROAMING, 1844 WMI_TAG_OIC_PING_OFFLOAD_PARAMS_CMD, 1845 WMI_TAG_OIC_PING_OFFLOAD_SET_ENABLE_CMD, 1846 WMI_TAG_OIC_PING_HANDOFF_EVENT, 1847 WMI_TAG_DHCP_LEASE_RENEW_OFFLOAD_CMD, 1848 WMI_TAG_DHCP_LEASE_RENEW_EVENT, 1849 WMI_TAG_BTM_CONFIG, 1850 WMI_TAG_DEBUG_MESG_FW_DATA_STALL, 1851 WMI_TAG_WLM_CONFIG_CMD, 1852 WMI_TAG_PDEV_UPDATE_CTLTABLE_REQUEST, 1853 WMI_TAG_PDEV_UPDATE_CTLTABLE_EVENT, 1854 WMI_TAG_ROAM_CND_SCORING_PARAM, 1855 WMI_TAG_PDEV_CONFIG_VENDOR_OUI_ACTION, 1856 WMI_TAG_VENDOR_OUI_EXT, 1857 WMI_TAG_ROAM_SYNCH_FRAME_EVENT, 1858 WMI_TAG_FD_SEND_FROM_HOST_CMD, 1859 WMI_TAG_ENABLE_FILS_CMD, 1860 WMI_TAG_HOST_SWFDA_EVENT, 1861 WMI_TAG_BCN_OFFLOAD_CTRL_CMD, 1862 WMI_TAG_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMD, 1863 WMI_TAG_STATS_PERIOD, 1864 WMI_TAG_NDL_SCHEDULE_UPDATE, 1865 WMI_TAG_PEER_TID_MSDUQ_QDEPTH_THRESH_UPDATE_CMD, 1866 WMI_TAG_MSDUQ_QDEPTH_THRESH_UPDATE, 1867 WMI_TAG_PDEV_SET_RX_FILTER_PROMISCUOUS_CMD, 1868 WMI_TAG_SAR2_RESULT_EVENT, 1869 WMI_TAG_SAR_CAPABILITIES, 1870 WMI_TAG_SAP_OBSS_DETECTION_CFG_CMD, 1871 WMI_TAG_SAP_OBSS_DETECTION_INFO_EVT, 1872 WMI_TAG_DMA_RING_CAPABILITIES, 1873 WMI_TAG_DMA_RING_CFG_REQ, 1874 WMI_TAG_DMA_RING_CFG_RSP, 1875 WMI_TAG_DMA_BUF_RELEASE, 1876 WMI_TAG_DMA_BUF_RELEASE_ENTRY, 1877 WMI_TAG_SAR_GET_LIMITS_CMD, 1878 WMI_TAG_SAR_GET_LIMITS_EVENT, 1879 WMI_TAG_SAR_GET_LIMITS_EVENT_ROW, 1880 WMI_TAG_OFFLOAD_11K_REPORT, 1881 WMI_TAG_INVOKE_NEIGHBOR_REPORT, 1882 WMI_TAG_NEIGHBOR_REPORT_OFFLOAD, 1883 WMI_TAG_VDEV_SET_CONNECTIVITY_CHECK_STATS, 1884 WMI_TAG_VDEV_GET_CONNECTIVITY_CHECK_STATS, 1885 WMI_TAG_BPF_SET_VDEV_ENABLE_CMD, 1886 WMI_TAG_BPF_SET_VDEV_WORK_MEMORY_CMD, 1887 WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_CMD, 1888 WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_RESP_EVT, 1889 WMI_TAG_PDEV_GET_NFCAL_POWER, 1890 WMI_TAG_BSS_COLOR_CHANGE_ENABLE, 1891 WMI_TAG_OBSS_COLOR_COLLISION_DET_CONFIG, 1892 WMI_TAG_OBSS_COLOR_COLLISION_EVT, 1893 WMI_TAG_RUNTIME_DPD_RECAL_CMD, 1894 WMI_TAG_TWT_ENABLE_CMD, 1895 WMI_TAG_TWT_DISABLE_CMD, 1896 WMI_TAG_TWT_ADD_DIALOG_CMD, 1897 WMI_TAG_TWT_DEL_DIALOG_CMD, 1898 WMI_TAG_TWT_PAUSE_DIALOG_CMD, 1899 WMI_TAG_TWT_RESUME_DIALOG_CMD, 1900 WMI_TAG_TWT_ENABLE_COMPLETE_EVENT, 1901 WMI_TAG_TWT_DISABLE_COMPLETE_EVENT, 1902 WMI_TAG_TWT_ADD_DIALOG_COMPLETE_EVENT, 1903 WMI_TAG_TWT_DEL_DIALOG_COMPLETE_EVENT, 1904 WMI_TAG_TWT_PAUSE_DIALOG_COMPLETE_EVENT, 1905 WMI_TAG_TWT_RESUME_DIALOG_COMPLETE_EVENT, 1906 WMI_TAG_REQUEST_ROAM_SCAN_STATS_CMD, 1907 WMI_TAG_ROAM_SCAN_STATS_EVENT, 1908 WMI_TAG_PEER_TID_CONFIGURATIONS_CMD, 1909 WMI_TAG_VDEV_SET_CUSTOM_SW_RETRY_TH_CMD, 1910 WMI_TAG_GET_TPC_POWER_CMD, 1911 WMI_TAG_GET_TPC_POWER_EVENT, 1912 WMI_TAG_DMA_BUF_RELEASE_SPECTRAL_META_DATA, 1913 WMI_TAG_MOTION_DET_CONFIG_PARAMS_CMD, 1914 WMI_TAG_MOTION_DET_BASE_LINE_CONFIG_PARAMS_CMD, 1915 WMI_TAG_MOTION_DET_START_STOP_CMD, 1916 WMI_TAG_MOTION_DET_BASE_LINE_START_STOP_CMD, 1917 WMI_TAG_MOTION_DET_EVENT, 1918 WMI_TAG_MOTION_DET_BASE_LINE_EVENT, 1919 WMI_TAG_NDP_TRANSPORT_IP, 1920 WMI_TAG_OBSS_SPATIAL_REUSE_SET_CMD, 1921 WMI_TAG_ESP_ESTIMATE_EVENT, 1922 WMI_TAG_NAN_HOST_CONFIG, 1923 WMI_TAG_SPECTRAL_BIN_SCALING_PARAMS, 1924 WMI_TAG_PEER_CFR_CAPTURE_CMD, 1925 WMI_TAG_PEER_CHAN_WIDTH_SWITCH_CMD, 1926 WMI_TAG_CHAN_WIDTH_PEER_LIST, 1927 WMI_TAG_OBSS_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMD, 1928 WMI_TAG_PDEV_HE_TB_ACTION_FRM_CMD, 1929 WMI_TAG_PEER_EXTD2_STATS, 1930 WMI_TAG_HPCS_PULSE_START_CMD, 1931 WMI_TAG_PDEV_CTL_FAILSAFE_CHECK_EVENT, 1932 WMI_TAG_VDEV_CHAINMASK_CONFIG_CMD, 1933 WMI_TAG_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMD, 1934 WMI_TAG_NAN_EVENT_INFO, 1935 WMI_TAG_NDP_CHANNEL_INFO, 1936 WMI_TAG_NDP_CMD, 1937 WMI_TAG_NDP_EVENT, 1938 WMI_TAG_PDEV_PEER_PKTLOG_FILTER_CMD = 0x301, 1939 WMI_TAG_PDEV_PEER_PKTLOG_FILTER_INFO, 1940 WMI_TAG_FILS_DISCOVERY_TMPL_CMD = 0x344, 1941 WMI_TAG_PDEV_SRG_BSS_COLOR_BITMAP_CMD = 0x37b, 1942 WMI_TAG_PDEV_SRG_PARTIAL_BSSID_BITMAP_CMD, 1943 WMI_TAG_PDEV_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD = 0x381, 1944 WMI_TAG_PDEV_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD, 1945 WMI_TAG_PDEV_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD, 1946 WMI_TAG_PDEV_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD, 1947 WMI_TAG_REGULATORY_RULE_EXT_STRUCT = 0x3A9, 1948 WMI_TAG_REG_CHAN_LIST_CC_EXT_EVENT, 1949 WMI_TAG_PDEV_SET_BIOS_SAR_TABLE_CMD = 0x3D8, 1950 WMI_TAG_PDEV_SET_BIOS_GEO_TABLE_CMD, 1951 WMI_TAG_MAX 1952 }; 1953 1954 enum wmi_tlv_service { 1955 WMI_TLV_SERVICE_BEACON_OFFLOAD = 0, 1956 WMI_TLV_SERVICE_SCAN_OFFLOAD = 1, 1957 WMI_TLV_SERVICE_ROAM_SCAN_OFFLOAD = 2, 1958 WMI_TLV_SERVICE_BCN_MISS_OFFLOAD = 3, 1959 WMI_TLV_SERVICE_STA_PWRSAVE = 4, 1960 WMI_TLV_SERVICE_STA_ADVANCED_PWRSAVE = 5, 1961 WMI_TLV_SERVICE_AP_UAPSD = 6, 1962 WMI_TLV_SERVICE_AP_DFS = 7, 1963 WMI_TLV_SERVICE_11AC = 8, 1964 WMI_TLV_SERVICE_BLOCKACK = 9, 1965 WMI_TLV_SERVICE_PHYERR = 10, 1966 WMI_TLV_SERVICE_BCN_FILTER = 11, 1967 WMI_TLV_SERVICE_RTT = 12, 1968 WMI_TLV_SERVICE_WOW = 13, 1969 WMI_TLV_SERVICE_RATECTRL_CACHE = 14, 1970 WMI_TLV_SERVICE_IRAM_TIDS = 15, 1971 WMI_TLV_SERVICE_ARPNS_OFFLOAD = 16, 1972 WMI_TLV_SERVICE_NLO = 17, 1973 WMI_TLV_SERVICE_GTK_OFFLOAD = 18, 1974 WMI_TLV_SERVICE_SCAN_SCH = 19, 1975 WMI_TLV_SERVICE_CSA_OFFLOAD = 20, 1976 WMI_TLV_SERVICE_CHATTER = 21, 1977 WMI_TLV_SERVICE_COEX_FREQAVOID = 22, 1978 WMI_TLV_SERVICE_PACKET_POWER_SAVE = 23, 1979 WMI_TLV_SERVICE_FORCE_FW_HANG = 24, 1980 WMI_TLV_SERVICE_GPIO = 25, 1981 WMI_TLV_SERVICE_STA_DTIM_PS_MODULATED_DTIM = 26, 1982 WMI_STA_UAPSD_BASIC_AUTO_TRIG = 27, 1983 WMI_STA_UAPSD_VAR_AUTO_TRIG = 28, 1984 WMI_TLV_SERVICE_STA_KEEP_ALIVE = 29, 1985 WMI_TLV_SERVICE_TX_ENCAP = 30, 1986 WMI_TLV_SERVICE_AP_PS_DETECT_OUT_OF_SYNC = 31, 1987 WMI_TLV_SERVICE_EARLY_RX = 32, 1988 WMI_TLV_SERVICE_STA_SMPS = 33, 1989 WMI_TLV_SERVICE_FWTEST = 34, 1990 WMI_TLV_SERVICE_STA_WMMAC = 35, 1991 WMI_TLV_SERVICE_TDLS = 36, 1992 WMI_TLV_SERVICE_BURST = 37, 1993 WMI_TLV_SERVICE_MCC_BCN_INTERVAL_CHANGE = 38, 1994 WMI_TLV_SERVICE_ADAPTIVE_OCS = 39, 1995 WMI_TLV_SERVICE_BA_SSN_SUPPORT = 40, 1996 WMI_TLV_SERVICE_FILTER_IPSEC_NATKEEPALIVE = 41, 1997 WMI_TLV_SERVICE_WLAN_HB = 42, 1998 WMI_TLV_SERVICE_LTE_ANT_SHARE_SUPPORT = 43, 1999 WMI_TLV_SERVICE_BATCH_SCAN = 44, 2000 WMI_TLV_SERVICE_QPOWER = 45, 2001 WMI_TLV_SERVICE_PLMREQ = 46, 2002 WMI_TLV_SERVICE_THERMAL_MGMT = 47, 2003 WMI_TLV_SERVICE_RMC = 48, 2004 WMI_TLV_SERVICE_MHF_OFFLOAD = 49, 2005 WMI_TLV_SERVICE_COEX_SAR = 50, 2006 WMI_TLV_SERVICE_BCN_TXRATE_OVERRIDE = 51, 2007 WMI_TLV_SERVICE_NAN = 52, 2008 WMI_TLV_SERVICE_L1SS_STAT = 53, 2009 WMI_TLV_SERVICE_ESTIMATE_LINKSPEED = 54, 2010 WMI_TLV_SERVICE_OBSS_SCAN = 55, 2011 WMI_TLV_SERVICE_TDLS_OFFCHAN = 56, 2012 WMI_TLV_SERVICE_TDLS_UAPSD_BUFFER_STA = 57, 2013 WMI_TLV_SERVICE_TDLS_UAPSD_SLEEP_STA = 58, 2014 WMI_TLV_SERVICE_IBSS_PWRSAVE = 59, 2015 WMI_TLV_SERVICE_LPASS = 60, 2016 WMI_TLV_SERVICE_EXTSCAN = 61, 2017 WMI_TLV_SERVICE_D0WOW = 62, 2018 WMI_TLV_SERVICE_HSOFFLOAD = 63, 2019 WMI_TLV_SERVICE_ROAM_HO_OFFLOAD = 64, 2020 WMI_TLV_SERVICE_RX_FULL_REORDER = 65, 2021 WMI_TLV_SERVICE_DHCP_OFFLOAD = 66, 2022 WMI_TLV_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT = 67, 2023 WMI_TLV_SERVICE_MDNS_OFFLOAD = 68, 2024 WMI_TLV_SERVICE_SAP_AUTH_OFFLOAD = 69, 2025 WMI_TLV_SERVICE_DUAL_BAND_SIMULTANEOUS_SUPPORT = 70, 2026 WMI_TLV_SERVICE_OCB = 71, 2027 WMI_TLV_SERVICE_AP_ARPNS_OFFLOAD = 72, 2028 WMI_TLV_SERVICE_PER_BAND_CHAINMASK_SUPPORT = 73, 2029 WMI_TLV_SERVICE_PACKET_FILTER_OFFLOAD = 74, 2030 WMI_TLV_SERVICE_MGMT_TX_HTT = 75, 2031 WMI_TLV_SERVICE_MGMT_TX_WMI = 76, 2032 WMI_TLV_SERVICE_EXT_MSG = 77, 2033 WMI_TLV_SERVICE_MAWC = 78, 2034 WMI_TLV_SERVICE_PEER_ASSOC_CONF = 79, 2035 WMI_TLV_SERVICE_EGAP = 80, 2036 WMI_TLV_SERVICE_STA_PMF_OFFLOAD = 81, 2037 WMI_TLV_SERVICE_UNIFIED_WOW_CAPABILITY = 82, 2038 WMI_TLV_SERVICE_ENHANCED_PROXY_STA = 83, 2039 WMI_TLV_SERVICE_ATF = 84, 2040 WMI_TLV_SERVICE_COEX_GPIO = 85, 2041 WMI_TLV_SERVICE_AUX_SPECTRAL_INTF = 86, 2042 WMI_TLV_SERVICE_AUX_CHAN_LOAD_INTF = 87, 2043 WMI_TLV_SERVICE_BSS_CHANNEL_INFO_64 = 88, 2044 WMI_TLV_SERVICE_ENTERPRISE_MESH = 89, 2045 WMI_TLV_SERVICE_RESTRT_CHNL_SUPPORT = 90, 2046 WMI_TLV_SERVICE_BPF_OFFLOAD = 91, 2047 WMI_TLV_SERVICE_SYNC_DELETE_CMDS = 92, 2048 WMI_TLV_SERVICE_SMART_ANTENNA_SW_SUPPORT = 93, 2049 WMI_TLV_SERVICE_SMART_ANTENNA_HW_SUPPORT = 94, 2050 WMI_TLV_SERVICE_RATECTRL_LIMIT_MAX_MIN_RATES = 95, 2051 WMI_TLV_SERVICE_NAN_DATA = 96, 2052 WMI_TLV_SERVICE_NAN_RTT = 97, 2053 WMI_TLV_SERVICE_11AX = 98, 2054 WMI_TLV_SERVICE_DEPRECATED_REPLACE = 99, 2055 WMI_TLV_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE = 100, 2056 WMI_TLV_SERVICE_ENHANCED_MCAST_FILTER = 101, 2057 WMI_TLV_SERVICE_PERIODIC_CHAN_STAT_SUPPORT = 102, 2058 WMI_TLV_SERVICE_MESH_11S = 103, 2059 WMI_TLV_SERVICE_HALF_RATE_QUARTER_RATE_SUPPORT = 104, 2060 WMI_TLV_SERVICE_VDEV_RX_FILTER = 105, 2061 WMI_TLV_SERVICE_P2P_LISTEN_OFFLOAD_SUPPORT = 106, 2062 WMI_TLV_SERVICE_MARK_FIRST_WAKEUP_PACKET = 107, 2063 WMI_TLV_SERVICE_MULTIPLE_MCAST_FILTER_SET = 108, 2064 WMI_TLV_SERVICE_HOST_MANAGED_RX_REORDER = 109, 2065 WMI_TLV_SERVICE_FLASH_RDWR_SUPPORT = 110, 2066 WMI_TLV_SERVICE_WLAN_STATS_REPORT = 111, 2067 WMI_TLV_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT = 112, 2068 WMI_TLV_SERVICE_DFS_PHYERR_OFFLOAD = 113, 2069 WMI_TLV_SERVICE_RCPI_SUPPORT = 114, 2070 WMI_TLV_SERVICE_FW_MEM_DUMP_SUPPORT = 115, 2071 WMI_TLV_SERVICE_PEER_STATS_INFO = 116, 2072 WMI_TLV_SERVICE_REGULATORY_DB = 117, 2073 WMI_TLV_SERVICE_11D_OFFLOAD = 118, 2074 WMI_TLV_SERVICE_HW_DATA_FILTERING = 119, 2075 WMI_TLV_SERVICE_MULTIPLE_VDEV_RESTART = 120, 2076 WMI_TLV_SERVICE_PKT_ROUTING = 121, 2077 WMI_TLV_SERVICE_CHECK_CAL_VERSION = 122, 2078 WMI_TLV_SERVICE_OFFCHAN_TX_WMI = 123, 2079 WMI_TLV_SERVICE_8SS_TX_BFEE = 124, 2080 WMI_TLV_SERVICE_EXTENDED_NSS_SUPPORT = 125, 2081 WMI_TLV_SERVICE_ACK_TIMEOUT = 126, 2082 WMI_TLV_SERVICE_PDEV_BSS_CHANNEL_INFO_64 = 127, 2083 2084 /* The first 128 bits */ 2085 WMI_MAX_SERVICE = 128, 2086 2087 WMI_TLV_SERVICE_CHAN_LOAD_INFO = 128, 2088 WMI_TLV_SERVICE_TX_PPDU_INFO_STATS_SUPPORT = 129, 2089 WMI_TLV_SERVICE_VDEV_LIMIT_OFFCHAN_SUPPORT = 130, 2090 WMI_TLV_SERVICE_FILS_SUPPORT = 131, 2091 WMI_TLV_SERVICE_WLAN_OIC_PING_OFFLOAD = 132, 2092 WMI_TLV_SERVICE_WLAN_DHCP_RENEW = 133, 2093 WMI_TLV_SERVICE_MAWC_SUPPORT = 134, 2094 WMI_TLV_SERVICE_VDEV_LATENCY_CONFIG = 135, 2095 WMI_TLV_SERVICE_PDEV_UPDATE_CTLTABLE_SUPPORT = 136, 2096 WMI_TLV_SERVICE_PKTLOG_SUPPORT_OVER_HTT = 137, 2097 WMI_TLV_SERVICE_VDEV_MULTI_GROUP_KEY_SUPPORT = 138, 2098 WMI_TLV_SERVICE_SCAN_PHYMODE_SUPPORT = 139, 2099 WMI_TLV_SERVICE_THERM_THROT = 140, 2100 WMI_TLV_SERVICE_BCN_OFFLOAD_START_STOP_SUPPORT = 141, 2101 WMI_TLV_SERVICE_WOW_WAKEUP_BY_TIMER_PATTERN = 142, 2102 WMI_TLV_SERVICE_PEER_MAP_UNMAP_V2_SUPPORT = 143, 2103 WMI_TLV_SERVICE_OFFCHAN_DATA_TID_SUPPORT = 144, 2104 WMI_TLV_SERVICE_RX_PROMISC_ENABLE_SUPPORT = 145, 2105 WMI_TLV_SERVICE_SUPPORT_DIRECT_DMA = 146, 2106 WMI_TLV_SERVICE_AP_OBSS_DETECTION_OFFLOAD = 147, 2107 WMI_TLV_SERVICE_11K_NEIGHBOUR_REPORT_SUPPORT = 148, 2108 WMI_TLV_SERVICE_LISTEN_INTERVAL_OFFLOAD_SUPPORT = 149, 2109 WMI_TLV_SERVICE_BSS_COLOR_OFFLOAD = 150, 2110 WMI_TLV_SERVICE_RUNTIME_DPD_RECAL = 151, 2111 WMI_TLV_SERVICE_STA_TWT = 152, 2112 WMI_TLV_SERVICE_AP_TWT = 153, 2113 WMI_TLV_SERVICE_GMAC_OFFLOAD_SUPPORT = 154, 2114 WMI_TLV_SERVICE_SPOOF_MAC_SUPPORT = 155, 2115 WMI_TLV_SERVICE_PEER_TID_CONFIGS_SUPPORT = 156, 2116 WMI_TLV_SERVICE_VDEV_SWRETRY_PER_AC_CONFIG_SUPPORT = 157, 2117 WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_SCC_SUPPORT = 158, 2118 WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_MCC_SUPPORT = 159, 2119 WMI_TLV_SERVICE_MOTION_DET = 160, 2120 WMI_TLV_SERVICE_INFRA_MBSSID = 161, 2121 WMI_TLV_SERVICE_OBSS_SPATIAL_REUSE = 162, 2122 WMI_TLV_SERVICE_VDEV_DIFFERENT_BEACON_INTERVAL_SUPPORT = 163, 2123 WMI_TLV_SERVICE_NAN_DBS_SUPPORT = 164, 2124 WMI_TLV_SERVICE_NDI_DBS_SUPPORT = 165, 2125 WMI_TLV_SERVICE_NAN_SAP_SUPPORT = 166, 2126 WMI_TLV_SERVICE_NDI_SAP_SUPPORT = 167, 2127 WMI_TLV_SERVICE_CFR_CAPTURE_SUPPORT = 168, 2128 WMI_TLV_SERVICE_CFR_CAPTURE_IND_MSG_TYPE_1 = 169, 2129 WMI_TLV_SERVICE_ESP_SUPPORT = 170, 2130 WMI_TLV_SERVICE_PEER_CHWIDTH_CHANGE = 171, 2131 WMI_TLV_SERVICE_WLAN_HPCS_PULSE = 172, 2132 WMI_TLV_SERVICE_PER_VDEV_CHAINMASK_CONFIG_SUPPORT = 173, 2133 WMI_TLV_SERVICE_TX_DATA_MGMT_ACK_RSSI = 174, 2134 WMI_TLV_SERVICE_NAN_DISABLE_SUPPORT = 175, 2135 WMI_TLV_SERVICE_HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN = 176, 2136 WMI_TLV_SERVICE_COEX_SUPPORT_UNEQUAL_ISOLATION = 177, 2137 WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT = 178, 2138 WMI_TLV_SERVICE_SUPPORT_EXTEND_ADDRESS = 179, 2139 WMI_TLV_SERVICE_BEACON_RECEPTION_STATS = 180, 2140 WMI_TLV_SERVICE_FETCH_TX_PN = 181, 2141 WMI_TLV_SERVICE_PEER_UNMAP_RESPONSE_SUPPORT = 182, 2142 WMI_TLV_SERVICE_TX_PER_PEER_AMPDU_SIZE = 183, 2143 WMI_TLV_SERVICE_BSS_COLOR_SWITCH_COUNT = 184, 2144 WMI_TLV_SERVICE_HTT_PEER_STATS_SUPPORT = 185, 2145 WMI_TLV_SERVICE_UL_RU26_ALLOWED = 186, 2146 WMI_TLV_SERVICE_GET_MWS_COEX_STATE = 187, 2147 WMI_TLV_SERVICE_GET_MWS_DPWB_STATE = 188, 2148 WMI_TLV_SERVICE_GET_MWS_TDM_STATE = 189, 2149 WMI_TLV_SERVICE_GET_MWS_IDRX_STATE = 190, 2150 WMI_TLV_SERVICE_GET_MWS_ANTENNA_SHARING_STATE = 191, 2151 WMI_TLV_SERVICE_ENHANCED_TPC_CONFIG_EVENT = 192, 2152 WMI_TLV_SERVICE_WLM_STATS_REQUEST = 193, 2153 WMI_TLV_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT = 194, 2154 WMI_TLV_SERVICE_WPA3_FT_SAE_SUPPORT = 195, 2155 WMI_TLV_SERVICE_WPA3_FT_SUITE_B_SUPPORT = 196, 2156 WMI_TLV_SERVICE_VOW_ENABLE = 197, 2157 WMI_TLV_SERVICE_CFR_CAPTURE_IND_EVT_TYPE_1 = 198, 2158 WMI_TLV_SERVICE_BROADCAST_TWT = 199, 2159 WMI_TLV_SERVICE_RAP_DETECTION_SUPPORT = 200, 2160 WMI_TLV_SERVICE_PS_TDCC = 201, 2161 WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_LEGACY = 202, 2162 WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_OVERRIDE = 203, 2163 WMI_TLV_SERVICE_TX_PWR_PER_PEER = 204, 2164 WMI_TLV_SERVICE_STA_PLUS_STA_SUPPORT = 205, 2165 WMI_TLV_SERVICE_WPA3_FT_FILS = 206, 2166 WMI_TLV_SERVICE_ADAPTIVE_11R_ROAM = 207, 2167 WMI_TLV_SERVICE_CHAN_RF_CHARACTERIZATION_INFO = 208, 2168 WMI_TLV_SERVICE_FW_IFACE_COMBINATION_SUPPORT = 209, 2169 WMI_TLV_SERVICE_TX_COMPL_TSF64 = 210, 2170 WMI_TLV_SERVICE_DSM_ROAM_FILTER = 211, 2171 WMI_TLV_SERVICE_PACKET_CAPTURE_SUPPORT = 212, 2172 WMI_TLV_SERVICE_PER_PEER_HTT_STATS_RESET = 213, 2173 WMI_TLV_SERVICE_FREQINFO_IN_METADATA = 219, 2174 WMI_TLV_SERVICE_EXT2_MSG = 220, 2175 WMI_TLV_SERVICE_PEER_POWER_SAVE_DURATION_SUPPORT = 246, 2176 WMI_TLV_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT = 249, 2177 WMI_TLV_SERVICE_MBSS_PARAM_IN_VDEV_START_SUPPORT = 253, 2178 WMI_TLV_SERVICE_PASSIVE_SCAN_START_TIME_ENHANCE = 263, 2179 2180 /* The second 128 bits */ 2181 WMI_MAX_EXT_SERVICE = 256, 2182 WMI_TLV_SERVICE_SCAN_CONFIG_PER_CHANNEL = 265, 2183 WMI_TLV_SERVICE_REG_CC_EXT_EVENT_SUPPORT = 281, 2184 WMI_TLV_SERVICE_BIOS_SAR_SUPPORT = 326, 2185 WMI_TLV_SERVICE_SUPPORT_11D_FOR_HOST_SCAN = 357, 2186 2187 /* The third 128 bits */ 2188 WMI_MAX_EXT2_SERVICE = 384 2189 }; 2190 2191 enum { 2192 WMI_SMPS_FORCED_MODE_NONE = 0, 2193 WMI_SMPS_FORCED_MODE_DISABLED, 2194 WMI_SMPS_FORCED_MODE_STATIC, 2195 WMI_SMPS_FORCED_MODE_DYNAMIC 2196 }; 2197 2198 #define WMI_TPC_CHAINMASK_CONFIG_BAND_2G 0 2199 #define WMI_TPC_CHAINMASK_CONFIG_BAND_5G 1 2200 #define WMI_NUM_SUPPORTED_BAND_MAX 2 2201 2202 #define WMI_PEER_MIMO_PS_STATE 0x1 2203 #define WMI_PEER_AMPDU 0x2 2204 #define WMI_PEER_AUTHORIZE 0x3 2205 #define WMI_PEER_CHWIDTH 0x4 2206 #define WMI_PEER_NSS 0x5 2207 #define WMI_PEER_USE_4ADDR 0x6 2208 #define WMI_PEER_MEMBERSHIP 0x7 2209 #define WMI_PEER_USERPOS 0x8 2210 #define WMI_PEER_CRIT_PROTO_HINT_ENABLED 0x9 2211 #define WMI_PEER_TX_FAIL_CNT_THR 0xA 2212 #define WMI_PEER_SET_HW_RETRY_CTS2S 0xB 2213 #define WMI_PEER_IBSS_ATIM_WINDOW_LENGTH 0xC 2214 #define WMI_PEER_PHYMODE 0xD 2215 #define WMI_PEER_USE_FIXED_PWR 0xE 2216 #define WMI_PEER_PARAM_FIXED_RATE 0xF 2217 #define WMI_PEER_SET_MU_WHITELIST 0x10 2218 #define WMI_PEER_SET_MAX_TX_RATE 0x11 2219 #define WMI_PEER_SET_MIN_TX_RATE 0x12 2220 #define WMI_PEER_SET_DEFAULT_ROUTING 0x13 2221 2222 /* slot time long */ 2223 #define WMI_VDEV_SLOT_TIME_LONG 0x1 2224 /* slot time short */ 2225 #define WMI_VDEV_SLOT_TIME_SHORT 0x2 2226 /* preablbe long */ 2227 #define WMI_VDEV_PREAMBLE_LONG 0x1 2228 /* preablbe short */ 2229 #define WMI_VDEV_PREAMBLE_SHORT 0x2 2230 2231 enum wmi_peer_smps_state { 2232 WMI_PEER_SMPS_PS_NONE = 0x0, 2233 WMI_PEER_SMPS_STATIC = 0x1, 2234 WMI_PEER_SMPS_DYNAMIC = 0x2 2235 }; 2236 2237 enum wmi_peer_chwidth { 2238 WMI_PEER_CHWIDTH_20MHZ = 0, 2239 WMI_PEER_CHWIDTH_40MHZ = 1, 2240 WMI_PEER_CHWIDTH_80MHZ = 2, 2241 WMI_PEER_CHWIDTH_160MHZ = 3, 2242 }; 2243 2244 enum wmi_beacon_gen_mode { 2245 WMI_BEACON_STAGGERED_MODE = 0, 2246 WMI_BEACON_BURST_MODE = 1 2247 }; 2248 2249 enum wmi_direct_buffer_module { 2250 WMI_DIRECT_BUF_SPECTRAL = 0, 2251 WMI_DIRECT_BUF_CFR = 1, 2252 2253 /* keep it last */ 2254 WMI_DIRECT_BUF_MAX 2255 }; 2256 2257 /* enum wmi_nss_ratio - NSS ratio received from FW during service ready ext 2258 * event 2259 * WMI_NSS_RATIO_1BY2_NSS -Max nss of 160MHz is equals to half of the max nss 2260 * of 80MHz 2261 * WMI_NSS_RATIO_3BY4_NSS - Max nss of 160MHz is equals to 3/4 of the max nss 2262 * of 80MHz 2263 * WMI_NSS_RATIO_1_NSS - Max nss of 160MHz is equals to the max nss of 80MHz 2264 * WMI_NSS_RATIO_2_NSS - Max nss of 160MHz is equals to two times the max 2265 * nss of 80MHz 2266 */ 2267 2268 enum wmi_nss_ratio { 2269 WMI_NSS_RATIO_1BY2_NSS = 0x0, 2270 WMI_NSS_RATIO_3BY4_NSS = 0x1, 2271 WMI_NSS_RATIO_1_NSS = 0x2, 2272 WMI_NSS_RATIO_2_NSS = 0x3, 2273 }; 2274 2275 enum wmi_dtim_policy { 2276 WMI_DTIM_POLICY_IGNORE = 1, 2277 WMI_DTIM_POLICY_NORMAL = 2, 2278 WMI_DTIM_POLICY_STICK = 3, 2279 WMI_DTIM_POLICY_AUTO = 4, 2280 }; 2281 2282 struct wmi_host_pdev_band_to_mac { 2283 uint32_t pdev_id; 2284 uint32_t start_freq; 2285 uint32_t end_freq; 2286 }; 2287 2288 struct ath11k_ppe_threshold { 2289 uint32_t numss_m1; 2290 uint32_t ru_bit_mask; 2291 uint32_t ppet16_ppet8_ru3_ru0[PSOC_HOST_MAX_NUM_SS]; 2292 }; 2293 2294 struct ath11k_service_ext_param { 2295 uint32_t default_conc_scan_config_bits; 2296 uint32_t default_fw_config_bits; 2297 struct ath11k_ppe_threshold ppet; 2298 uint32_t he_cap_info; 2299 uint32_t mpdu_density; 2300 uint32_t max_bssid_rx_filters; 2301 uint32_t num_hw_modes; 2302 uint32_t num_phy; 2303 }; 2304 2305 struct ath11k_hw_mode_caps { 2306 uint32_t hw_mode_id; 2307 uint32_t phy_id_map; 2308 uint32_t hw_mode_config_type; 2309 }; 2310 2311 #define PSOC_HOST_MAX_PHY_SIZE (3) 2312 #define ATH11K_11B_SUPPORT BIT(0) 2313 #define ATH11K_11G_SUPPORT BIT(1) 2314 #define ATH11K_11A_SUPPORT BIT(2) 2315 #define ATH11K_11N_SUPPORT BIT(3) 2316 #define ATH11K_11AC_SUPPORT BIT(4) 2317 #define ATH11K_11AX_SUPPORT BIT(5) 2318 2319 struct ath11k_hal_reg_capabilities_ext { 2320 uint32_t phy_id; 2321 uint32_t eeprom_reg_domain; 2322 uint32_t eeprom_reg_domain_ext; 2323 uint32_t regcap1; 2324 uint32_t regcap2; 2325 uint32_t wireless_modes; 2326 uint32_t low_2ghz_chan; 2327 uint32_t high_2ghz_chan; 2328 uint32_t low_5ghz_chan; 2329 uint32_t high_5ghz_chan; 2330 }; 2331 2332 #define WMI_HOST_MAX_PDEV 3 2333 2334 struct wlan_host_mem_chunk { 2335 uint32_t tlv_header; 2336 uint32_t req_id; 2337 uint32_t ptr; 2338 uint32_t size; 2339 } __packed; 2340 2341 struct wmi_host_mem_chunk { 2342 void *vaddr; 2343 bus_addr_t paddr; 2344 uint32_t len; 2345 uint32_t req_id; 2346 }; 2347 2348 struct wmi_init_cmd_param { 2349 uint32_t tlv_header; 2350 struct target_resource_config *res_cfg; 2351 uint8_t num_mem_chunks; 2352 struct wmi_host_mem_chunk *mem_chunks; 2353 uint32_t hw_mode_id; 2354 uint32_t num_band_to_mac; 2355 struct wmi_host_pdev_band_to_mac band_to_mac[WMI_HOST_MAX_PDEV]; 2356 }; 2357 2358 struct wmi_pdev_band_to_mac { 2359 uint32_t tlv_header; 2360 uint32_t pdev_id; 2361 uint32_t start_freq; 2362 uint32_t end_freq; 2363 } __packed; 2364 2365 struct wmi_pdev_set_hw_mode_cmd_param { 2366 uint32_t tlv_header; 2367 uint32_t pdev_id; 2368 uint32_t hw_mode_index; 2369 uint32_t num_band_to_mac; 2370 } __packed; 2371 2372 struct wmi_ppe_threshold { 2373 uint32_t numss_m1; /** NSS - 1*/ 2374 union { 2375 uint32_t ru_count; 2376 uint32_t ru_mask; 2377 } __packed; 2378 uint32_t ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS]; 2379 } __packed; 2380 2381 #define HW_BD_INFO_SIZE 5 2382 2383 struct wmi_abi_version { 2384 uint32_t abi_version_0; 2385 uint32_t abi_version_1; 2386 uint32_t abi_version_ns_0; 2387 uint32_t abi_version_ns_1; 2388 uint32_t abi_version_ns_2; 2389 uint32_t abi_version_ns_3; 2390 } __packed; 2391 2392 struct wmi_init_cmd { 2393 uint32_t tlv_header; 2394 struct wmi_abi_version host_abi_vers; 2395 uint32_t num_host_mem_chunks; 2396 } __packed; 2397 2398 #define WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64 BIT(5) 2399 #define WMI_RSRC_CFG_FLAG2_CALC_NEXT_DTIM_COUNT_SET BIT(9) 2400 #define WMI_RSRC_CFG_FLAG1_ACK_RSSI BIT(18) 2401 2402 #define WMI_CFG_HOST_SERVICE_FLAG_REG_CC_EXT 4 2403 2404 struct wmi_resource_config { 2405 uint32_t tlv_header; 2406 uint32_t num_vdevs; 2407 uint32_t num_peers; 2408 uint32_t num_offload_peers; 2409 uint32_t num_offload_reorder_buffs; 2410 uint32_t num_peer_keys; 2411 uint32_t num_tids; 2412 uint32_t ast_skid_limit; 2413 uint32_t tx_chain_mask; 2414 uint32_t rx_chain_mask; 2415 uint32_t rx_timeout_pri[4]; 2416 uint32_t rx_decap_mode; 2417 uint32_t scan_max_pending_req; 2418 uint32_t bmiss_offload_max_vdev; 2419 uint32_t roam_offload_max_vdev; 2420 uint32_t roam_offload_max_ap_profiles; 2421 uint32_t num_mcast_groups; 2422 uint32_t num_mcast_table_elems; 2423 uint32_t mcast2ucast_mode; 2424 uint32_t tx_dbg_log_size; 2425 uint32_t num_wds_entries; 2426 uint32_t dma_burst_size; 2427 uint32_t mac_aggr_delim; 2428 uint32_t rx_skip_defrag_timeout_dup_detection_check; 2429 uint32_t vow_config; 2430 uint32_t gtk_offload_max_vdev; 2431 uint32_t num_msdu_desc; 2432 uint32_t max_frag_entries; 2433 uint32_t num_tdls_vdevs; 2434 uint32_t num_tdls_conn_table_entries; 2435 uint32_t beacon_tx_offload_max_vdev; 2436 uint32_t num_multicast_filter_entries; 2437 uint32_t num_wow_filters; 2438 uint32_t num_keep_alive_pattern; 2439 uint32_t keep_alive_pattern_size; 2440 uint32_t max_tdls_concurrent_sleep_sta; 2441 uint32_t max_tdls_concurrent_buffer_sta; 2442 uint32_t wmi_send_separate; 2443 uint32_t num_ocb_vdevs; 2444 uint32_t num_ocb_channels; 2445 uint32_t num_ocb_schedules; 2446 uint32_t flag1; 2447 uint32_t smart_ant_cap; 2448 uint32_t bk_minfree; 2449 uint32_t be_minfree; 2450 uint32_t vi_minfree; 2451 uint32_t vo_minfree; 2452 uint32_t alloc_frag_desc_for_data_pkt; 2453 uint32_t num_ns_ext_tuples_cfg; 2454 uint32_t bpf_instruction_size; 2455 uint32_t max_bssid_rx_filters; 2456 uint32_t use_pdev_id; 2457 uint32_t max_num_dbs_scan_duty_cycle; 2458 uint32_t max_num_group_keys; 2459 uint32_t peer_map_unmap_v2_support; 2460 uint32_t sched_params; 2461 uint32_t twt_ap_pdev_count; 2462 uint32_t twt_ap_sta_count; 2463 #ifdef notyet /* 6 GHz support */ 2464 uint32_t max_nlo_ssids; 2465 uint32_t num_pkt_filters; 2466 uint32_t num_max_sta_vdevs; 2467 uint32_t max_bssid_indicator; 2468 uint32_t ul_resp_config; 2469 uint32_t msdu_flow_override_config0; 2470 uint32_t msdu_flow_override_config1; 2471 uint32_t flags2; 2472 uint32_t host_service_flags; 2473 uint32_t max_rnr_neighbours; 2474 uint32_t ema_max_vap_cnt; 2475 uint32_t ema_max_profile_period; 2476 #endif 2477 } __packed; 2478 2479 struct wmi_service_ready_event { 2480 uint32_t fw_build_vers; 2481 struct wmi_abi_version fw_abi_vers; 2482 uint32_t phy_capability; 2483 uint32_t max_frag_entry; 2484 uint32_t num_rf_chains; 2485 uint32_t ht_cap_info; 2486 uint32_t vht_cap_info; 2487 uint32_t vht_supp_mcs; 2488 uint32_t hw_min_tx_power; 2489 uint32_t hw_max_tx_power; 2490 uint32_t sys_cap_info; 2491 uint32_t min_pkt_size_enable; 2492 uint32_t max_bcn_ie_size; 2493 uint32_t num_mem_reqs; 2494 uint32_t max_num_scan_channels; 2495 uint32_t hw_bd_id; 2496 uint32_t hw_bd_info[HW_BD_INFO_SIZE]; 2497 uint32_t max_supported_macs; 2498 uint32_t wmi_fw_sub_feat_caps; 2499 uint32_t num_dbs_hw_modes; 2500 /* txrx_chainmask 2501 * [7:0] - 2G band tx chain mask 2502 * [15:8] - 2G band rx chain mask 2503 * [23:16] - 5G band tx chain mask 2504 * [31:24] - 5G band rx chain mask 2505 */ 2506 uint32_t txrx_chainmask; 2507 uint32_t default_dbs_hw_mode_index; 2508 uint32_t num_msdu_desc; 2509 } __packed; 2510 2511 #define WMI_SERVICE_BM_SIZE ((WMI_MAX_SERVICE + sizeof(uint32_t) - 1) / sizeof(uint32_t)) 2512 2513 #define WMI_SERVICE_SEGMENT_BM_SIZE32 4 /* 4x uint32_t = 128 bits */ 2514 #define WMI_SERVICE_EXT_BM_SIZE (WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(uint32_t)) 2515 #define WMI_AVAIL_SERVICE_BITS_IN_SIZE32 32 2516 #define WMI_SERVICE_BITS_IN_SIZE32 4 2517 2518 struct wmi_service_ready_ext_event { 2519 uint32_t default_conc_scan_config_bits; 2520 uint32_t default_fw_config_bits; 2521 struct wmi_ppe_threshold ppet; 2522 uint32_t he_cap_info; 2523 uint32_t mpdu_density; 2524 uint32_t max_bssid_rx_filters; 2525 uint32_t fw_build_vers_ext; 2526 uint32_t max_nlo_ssids; 2527 uint32_t max_bssid_indicator; 2528 uint32_t he_cap_info_ext; 2529 } __packed; 2530 2531 struct wmi_soc_mac_phy_hw_mode_caps { 2532 uint32_t num_hw_modes; 2533 uint32_t num_chainmask_tables; 2534 } __packed; 2535 2536 struct wmi_hw_mode_capabilities { 2537 uint32_t tlv_header; 2538 uint32_t hw_mode_id; 2539 uint32_t phy_id_map; 2540 uint32_t hw_mode_config_type; 2541 } __packed; 2542 2543 #define WMI_MAX_HECAP_PHY_SIZE (3) 2544 #define WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS BIT(0) 2545 #define WMI_NSS_RATIO_ENABLE_DISABLE_GET(_val) \ 2546 FIELD_GET(WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS, _val) 2547 #define WMI_NSS_RATIO_INFO_BITPOS GENMASK(4, 1) 2548 #define WMI_NSS_RATIO_INFO_GET(_val) \ 2549 FIELD_GET(WMI_NSS_RATIO_INFO_BITPOS, _val) 2550 2551 struct wmi_mac_phy_capabilities { 2552 uint32_t hw_mode_id; 2553 uint32_t pdev_id; 2554 uint32_t phy_id; 2555 uint32_t supported_flags; 2556 uint32_t supported_bands; 2557 uint32_t ampdu_density; 2558 uint32_t max_bw_supported_2g; 2559 uint32_t ht_cap_info_2g; 2560 uint32_t vht_cap_info_2g; 2561 uint32_t vht_supp_mcs_2g; 2562 uint32_t he_cap_info_2g; 2563 uint32_t he_supp_mcs_2g; 2564 uint32_t tx_chain_mask_2g; 2565 uint32_t rx_chain_mask_2g; 2566 uint32_t max_bw_supported_5g; 2567 uint32_t ht_cap_info_5g; 2568 uint32_t vht_cap_info_5g; 2569 uint32_t vht_supp_mcs_5g; 2570 uint32_t he_cap_info_5g; 2571 uint32_t he_supp_mcs_5g; 2572 uint32_t tx_chain_mask_5g; 2573 uint32_t rx_chain_mask_5g; 2574 uint32_t he_cap_phy_info_2g[WMI_MAX_HECAP_PHY_SIZE]; 2575 uint32_t he_cap_phy_info_5g[WMI_MAX_HECAP_PHY_SIZE]; 2576 struct wmi_ppe_threshold he_ppet2g; 2577 struct wmi_ppe_threshold he_ppet5g; 2578 uint32_t chainmask_table_id; 2579 uint32_t lmac_id; 2580 uint32_t he_cap_info_2g_ext; 2581 uint32_t he_cap_info_5g_ext; 2582 uint32_t he_cap_info_internal; 2583 uint32_t wireless_modes; 2584 uint32_t low_2ghz_chan_freq; 2585 uint32_t high_2ghz_chan_freq; 2586 uint32_t low_5ghz_chan_freq; 2587 uint32_t high_5ghz_chan_freq; 2588 uint32_t nss_ratio; 2589 } __packed; 2590 2591 struct wmi_hal_reg_capabilities_ext { 2592 uint32_t tlv_header; 2593 uint32_t phy_id; 2594 uint32_t eeprom_reg_domain; 2595 uint32_t eeprom_reg_domain_ext; 2596 uint32_t regcap1; 2597 uint32_t regcap2; 2598 uint32_t wireless_modes; 2599 uint32_t low_2ghz_chan; 2600 uint32_t high_2ghz_chan; 2601 uint32_t low_5ghz_chan; 2602 uint32_t high_5ghz_chan; 2603 } __packed; 2604 2605 struct wmi_soc_hal_reg_capabilities { 2606 uint32_t num_phy; 2607 } __packed; 2608 2609 /* 2 word representation of MAC addr */ 2610 struct wmi_mac_addr { 2611 union { 2612 uint8_t addr[6]; 2613 struct { 2614 uint32_t word0; 2615 uint32_t word1; 2616 } __packed; 2617 } __packed; 2618 } __packed; 2619 2620 struct wmi_dma_ring_capabilities { 2621 uint32_t tlv_header; 2622 uint32_t pdev_id; 2623 uint32_t module_id; 2624 uint32_t min_elem; 2625 uint32_t min_buf_sz; 2626 uint32_t min_buf_align; 2627 } __packed; 2628 2629 struct wmi_ready_event_min { 2630 struct wmi_abi_version fw_abi_vers; 2631 struct wmi_mac_addr mac_addr; 2632 uint32_t status; 2633 uint32_t num_dscp_table; 2634 uint32_t num_extra_mac_addr; 2635 uint32_t num_total_peers; 2636 uint32_t num_extra_peers; 2637 } __packed; 2638 2639 struct wmi_ready_event { 2640 struct wmi_ready_event_min ready_event_min; 2641 uint32_t max_ast_index; 2642 uint32_t pktlog_defs_checksum; 2643 } __packed; 2644 2645 struct wmi_service_available_event { 2646 uint32_t wmi_service_segment_offset; 2647 uint32_t wmi_service_segment_bitmap[WMI_SERVICE_SEGMENT_BM_SIZE32]; 2648 } __packed; 2649 2650 struct vdev_create_params { 2651 uint8_t if_id; 2652 uint32_t type; 2653 uint32_t subtype; 2654 struct { 2655 uint8_t tx; 2656 uint8_t rx; 2657 } chains[2]; 2658 uint32_t pdev_id; 2659 uint32_t mbssid_flags; 2660 uint32_t mbssid_tx_vdev_id; 2661 }; 2662 2663 struct wmi_vdev_create_cmd { 2664 uint32_t tlv_header; 2665 uint32_t vdev_id; 2666 uint32_t vdev_type; 2667 uint32_t vdev_subtype; 2668 struct wmi_mac_addr vdev_macaddr; 2669 uint32_t num_cfg_txrx_streams; 2670 uint32_t pdev_id; 2671 uint32_t mbssid_flags; 2672 uint32_t mbssid_tx_vdev_id; 2673 } __packed; 2674 2675 struct wmi_vdev_txrx_streams { 2676 uint32_t tlv_header; 2677 uint32_t band; 2678 uint32_t supported_tx_streams; 2679 uint32_t supported_rx_streams; 2680 } __packed; 2681 2682 struct wmi_vdev_delete_cmd { 2683 uint32_t tlv_header; 2684 uint32_t vdev_id; 2685 } __packed; 2686 2687 struct wmi_vdev_up_cmd { 2688 uint32_t tlv_header; 2689 uint32_t vdev_id; 2690 uint32_t vdev_assoc_id; 2691 struct wmi_mac_addr vdev_bssid; 2692 struct wmi_mac_addr tx_vdev_bssid; 2693 uint32_t nontx_profile_idx; 2694 uint32_t nontx_profile_cnt; 2695 } __packed; 2696 2697 struct wmi_vdev_stop_cmd { 2698 uint32_t tlv_header; 2699 uint32_t vdev_id; 2700 } __packed; 2701 2702 struct wmi_vdev_down_cmd { 2703 uint32_t tlv_header; 2704 uint32_t vdev_id; 2705 } __packed; 2706 2707 #define WMI_VDEV_START_HIDDEN_SSID BIT(0) 2708 #define WMI_VDEV_START_PMF_ENABLED BIT(1) 2709 #define WMI_VDEV_START_LDPC_RX_ENABLED BIT(3) 2710 #define WMI_VDEV_START_HW_ENCRYPTION_DISABLED BIT(4) 2711 2712 struct wmi_ssid { 2713 uint32_t ssid_len; 2714 uint32_t ssid[8]; 2715 } __packed; 2716 2717 #define ATH11K_VDEV_SETUP_TIMEOUT_HZ (1 * HZ) 2718 2719 struct wmi_vdev_start_request_cmd { 2720 uint32_t tlv_header; 2721 uint32_t vdev_id; 2722 uint32_t requestor_id; 2723 uint32_t beacon_interval; 2724 uint32_t dtim_period; 2725 uint32_t flags; 2726 struct wmi_ssid ssid; 2727 uint32_t bcn_tx_rate; 2728 uint32_t bcn_txpower; 2729 uint32_t num_noa_descriptors; 2730 uint32_t disable_hw_ack; 2731 uint32_t preferred_tx_streams; 2732 uint32_t preferred_rx_streams; 2733 uint32_t he_ops; 2734 uint32_t cac_duration_ms; 2735 uint32_t regdomain; 2736 uint32_t min_data_rate; 2737 uint32_t mbssid_flags; 2738 uint32_t mbssid_tx_vdev_id; 2739 } __packed; 2740 2741 #define MGMT_TX_DL_FRM_LEN 64 2742 #define WMI_MAC_MAX_SSID_LENGTH 32 2743 struct mac_ssid { 2744 uint8_t length; 2745 uint8_t mac_ssid[WMI_MAC_MAX_SSID_LENGTH]; 2746 } __packed; 2747 2748 struct wmi_p2p_noa_descriptor { 2749 uint32_t type_count; 2750 uint32_t duration; 2751 uint32_t interval; 2752 uint32_t start_time; 2753 }; 2754 2755 struct channel_param { 2756 uint8_t chan_id; 2757 uint8_t pwr; 2758 uint32_t mhz; 2759 uint32_t half_rate:1, 2760 quarter_rate:1, 2761 dfs_set:1, 2762 dfs_set_cfreq2:1, 2763 is_chan_passive:1, 2764 allow_ht:1, 2765 allow_vht:1, 2766 allow_he:1, 2767 set_agile:1, 2768 psc_channel:1; 2769 uint32_t phy_mode; 2770 uint32_t cfreq1; 2771 uint32_t cfreq2; 2772 char maxpower; 2773 char minpower; 2774 char maxregpower; 2775 uint8_t antennamax; 2776 uint8_t reg_class_id; 2777 } __packed; 2778 2779 enum wmi_phy_mode { 2780 MODE_11A = 0, 2781 MODE_11G = 1, /* 11b/g Mode */ 2782 MODE_11B = 2, /* 11b Mode */ 2783 MODE_11GONLY = 3, /* 11g only Mode */ 2784 MODE_11NA_HT20 = 4, 2785 MODE_11NG_HT20 = 5, 2786 MODE_11NA_HT40 = 6, 2787 MODE_11NG_HT40 = 7, 2788 MODE_11AC_VHT20 = 8, 2789 MODE_11AC_VHT40 = 9, 2790 MODE_11AC_VHT80 = 10, 2791 MODE_11AC_VHT20_2G = 11, 2792 MODE_11AC_VHT40_2G = 12, 2793 MODE_11AC_VHT80_2G = 13, 2794 MODE_11AC_VHT80_80 = 14, 2795 MODE_11AC_VHT160 = 15, 2796 MODE_11AX_HE20 = 16, 2797 MODE_11AX_HE40 = 17, 2798 MODE_11AX_HE80 = 18, 2799 MODE_11AX_HE80_80 = 19, 2800 MODE_11AX_HE160 = 20, 2801 MODE_11AX_HE20_2G = 21, 2802 MODE_11AX_HE40_2G = 22, 2803 MODE_11AX_HE80_2G = 23, 2804 MODE_UNKNOWN = 24, 2805 MODE_MAX = 24 2806 }; 2807 2808 static inline const char *qwx_wmi_phymode_str(enum wmi_phy_mode mode) 2809 { 2810 switch (mode) { 2811 case MODE_11A: 2812 return "11a"; 2813 case MODE_11G: 2814 return "11g"; 2815 case MODE_11B: 2816 return "11b"; 2817 case MODE_11GONLY: 2818 return "11gonly"; 2819 case MODE_11NA_HT20: 2820 return "11na-ht20"; 2821 case MODE_11NG_HT20: 2822 return "11ng-ht20"; 2823 case MODE_11NA_HT40: 2824 return "11na-ht40"; 2825 case MODE_11NG_HT40: 2826 return "11ng-ht40"; 2827 case MODE_11AC_VHT20: 2828 return "11ac-vht20"; 2829 case MODE_11AC_VHT40: 2830 return "11ac-vht40"; 2831 case MODE_11AC_VHT80: 2832 return "11ac-vht80"; 2833 case MODE_11AC_VHT160: 2834 return "11ac-vht160"; 2835 case MODE_11AC_VHT80_80: 2836 return "11ac-vht80+80"; 2837 case MODE_11AC_VHT20_2G: 2838 return "11ac-vht20-2g"; 2839 case MODE_11AC_VHT40_2G: 2840 return "11ac-vht40-2g"; 2841 case MODE_11AC_VHT80_2G: 2842 return "11ac-vht80-2g"; 2843 case MODE_11AX_HE20: 2844 return "11ax-he20"; 2845 case MODE_11AX_HE40: 2846 return "11ax-he40"; 2847 case MODE_11AX_HE80: 2848 return "11ax-he80"; 2849 case MODE_11AX_HE80_80: 2850 return "11ax-he80+80"; 2851 case MODE_11AX_HE160: 2852 return "11ax-he160"; 2853 case MODE_11AX_HE20_2G: 2854 return "11ax-he20-2g"; 2855 case MODE_11AX_HE40_2G: 2856 return "11ax-he40-2g"; 2857 case MODE_11AX_HE80_2G: 2858 return "11ax-he80-2g"; 2859 case MODE_UNKNOWN: 2860 /* skip */ 2861 break; 2862 2863 /* no default handler to allow compiler to check that the 2864 * enum is fully handled 2865 */ 2866 } 2867 2868 return "<unknown>"; 2869 } 2870 2871 struct wmi_channel_arg { 2872 uint32_t freq; 2873 uint32_t band_center_freq1; 2874 uint32_t band_center_freq2; 2875 bool passive; 2876 bool allow_ibss; 2877 bool allow_ht; 2878 bool allow_vht; 2879 bool ht40plus; 2880 bool chan_radar; 2881 bool freq2_radar; 2882 bool allow_he; 2883 uint32_t min_power; 2884 uint32_t max_power; 2885 uint32_t max_reg_power; 2886 uint32_t max_antenna_gain; 2887 enum wmi_phy_mode mode; 2888 }; 2889 2890 struct wmi_vdev_start_req_arg { 2891 uint32_t vdev_id; 2892 struct wmi_channel_arg channel; 2893 uint32_t bcn_intval; 2894 uint32_t dtim_period; 2895 uint8_t *ssid; 2896 uint32_t ssid_len; 2897 uint32_t bcn_tx_rate; 2898 uint32_t bcn_tx_power; 2899 bool disable_hw_ack; 2900 bool hidden_ssid; 2901 bool pmf_enabled; 2902 uint32_t he_ops; 2903 uint32_t cac_duration_ms; 2904 uint32_t regdomain; 2905 uint32_t pref_rx_streams; 2906 uint32_t pref_tx_streams; 2907 uint32_t num_noa_descriptors; 2908 uint32_t min_data_rate; 2909 uint32_t mbssid_flags; 2910 uint32_t mbssid_tx_vdev_id; 2911 }; 2912 2913 struct peer_create_params { 2914 uint8_t *peer_addr; 2915 uint32_t peer_type; 2916 uint32_t vdev_id; 2917 }; 2918 2919 struct peer_delete_params { 2920 uint8_t vdev_id; 2921 }; 2922 2923 struct peer_flush_params { 2924 uint32_t peer_tid_bitmap; 2925 uint8_t vdev_id; 2926 }; 2927 2928 struct pdev_set_regdomain_params { 2929 uint16_t current_rd_in_use; 2930 uint16_t current_rd_2g; 2931 uint16_t current_rd_5g; 2932 uint32_t ctl_2g; 2933 uint32_t ctl_5g; 2934 uint8_t dfs_domain; 2935 uint32_t pdev_id; 2936 }; 2937 2938 struct rx_reorder_queue_remove_params { 2939 uint8_t *peer_macaddr; 2940 uint16_t vdev_id; 2941 uint32_t peer_tid_bitmap; 2942 }; 2943 2944 #define WMI_HOST_PDEV_ID_SOC 0xFF 2945 #define WMI_HOST_PDEV_ID_0 0 2946 #define WMI_HOST_PDEV_ID_1 1 2947 #define WMI_HOST_PDEV_ID_2 2 2948 2949 #define WMI_PDEV_ID_SOC 0 2950 #define WMI_PDEV_ID_1ST 1 2951 #define WMI_PDEV_ID_2ND 2 2952 #define WMI_PDEV_ID_3RD 3 2953 2954 /* Freq units in MHz */ 2955 #define REG_RULE_START_FREQ 0x0000ffff 2956 #define REG_RULE_END_FREQ 0xffff0000 2957 #define REG_RULE_FLAGS 0x0000ffff 2958 #define REG_RULE_MAX_BW 0x0000ffff 2959 #define REG_RULE_REG_PWR 0x00ff0000 2960 #define REG_RULE_ANT_GAIN 0xff000000 2961 #define REG_RULE_PSD_INFO BIT(0) 2962 #define REG_RULE_PSD_EIRP 0xff0000 2963 2964 #define WMI_VDEV_PARAM_TXBF_SU_TX_BFEE BIT(0) 2965 #define WMI_VDEV_PARAM_TXBF_MU_TX_BFEE BIT(1) 2966 #define WMI_VDEV_PARAM_TXBF_SU_TX_BFER BIT(2) 2967 #define WMI_VDEV_PARAM_TXBF_MU_TX_BFER BIT(3) 2968 2969 #define HE_PHYCAP_BYTE_0 0 2970 #define HE_PHYCAP_BYTE_1 1 2971 #define HE_PHYCAP_BYTE_2 2 2972 #define HE_PHYCAP_BYTE_3 3 2973 #define HE_PHYCAP_BYTE_4 4 2974 2975 #define HECAP_PHY_SU_BFER BIT(7) 2976 #define HECAP_PHY_SU_BFEE BIT(0) 2977 #define HECAP_PHY_MU_BFER BIT(1) 2978 #define HECAP_PHY_UL_MUMIMO BIT(6) 2979 #define HECAP_PHY_UL_MUOFDMA BIT(7) 2980 2981 #define HECAP_PHY_SUBFMR_GET(hecap_phy) \ 2982 FIELD_GET(HECAP_PHY_SU_BFER, hecap_phy[HE_PHYCAP_BYTE_3]) 2983 2984 #define HECAP_PHY_SUBFME_GET(hecap_phy) \ 2985 FIELD_GET(HECAP_PHY_SU_BFEE, hecap_phy[HE_PHYCAP_BYTE_4]) 2986 2987 #define HECAP_PHY_MUBFMR_GET(hecap_phy) \ 2988 FIELD_GET(HECAP_PHY_MU_BFER, hecap_phy[HE_PHYCAP_BYTE_4]) 2989 2990 #define HECAP_PHY_ULMUMIMO_GET(hecap_phy) \ 2991 FIELD_GET(HECAP_PHY_UL_MUMIMO, hecap_phy[HE_PHYCAP_BYTE_2]) 2992 2993 #define HECAP_PHY_ULOFDMA_GET(hecap_phy) \ 2994 FIELD_GET(HECAP_PHY_UL_MUOFDMA, hecap_phy[HE_PHYCAP_BYTE_2]) 2995 2996 #define HE_MODE_SU_TX_BFEE BIT(0) 2997 #define HE_MODE_SU_TX_BFER BIT(1) 2998 #define HE_MODE_MU_TX_BFEE BIT(2) 2999 #define HE_MODE_MU_TX_BFER BIT(3) 3000 #define HE_MODE_DL_OFDMA BIT(4) 3001 #define HE_MODE_UL_OFDMA BIT(5) 3002 #define HE_MODE_UL_MUMIMO BIT(6) 3003 3004 #define HE_DL_MUOFDMA_ENABLE 1 3005 #define HE_UL_MUOFDMA_ENABLE 1 3006 #define HE_DL_MUMIMO_ENABLE 1 3007 #define HE_UL_MUMIMO_ENABLE 1 3008 #define HE_MU_BFEE_ENABLE 1 3009 #define HE_SU_BFEE_ENABLE 1 3010 #define HE_MU_BFER_ENABLE 1 3011 #define HE_SU_BFER_ENABLE 1 3012 3013 #define HE_VHT_SOUNDING_MODE_ENABLE 1 3014 #define HE_SU_MU_SOUNDING_MODE_ENABLE 1 3015 #define HE_TRIG_NONTRIG_SOUNDING_MODE_ENABLE 1 3016 3017 /* HE or VHT Sounding */ 3018 #define HE_VHT_SOUNDING_MODE BIT(0) 3019 /* SU or MU Sounding */ 3020 #define HE_SU_MU_SOUNDING_MODE BIT(2) 3021 /* Trig or Non-Trig Sounding */ 3022 #define HE_TRIG_NONTRIG_SOUNDING_MODE BIT(3) 3023 3024 #define WMI_TXBF_STS_CAP_OFFSET_LSB 4 3025 #define WMI_TXBF_STS_CAP_OFFSET_MASK 0x70 3026 #define WMI_BF_SOUND_DIM_OFFSET_LSB 8 3027 #define WMI_BF_SOUND_DIM_OFFSET_MASK 0x700 3028 3029 struct pdev_params { 3030 uint32_t param_id; 3031 uint32_t param_value; 3032 }; 3033 3034 enum wmi_peer_type { 3035 WMI_PEER_TYPE_DEFAULT = 0, 3036 WMI_PEER_TYPE_BSS = 1, 3037 WMI_PEER_TYPE_TDLS = 2, 3038 }; 3039 3040 struct wmi_peer_create_cmd { 3041 uint32_t tlv_header; 3042 uint32_t vdev_id; 3043 struct wmi_mac_addr peer_macaddr; 3044 uint32_t peer_type; 3045 } __packed; 3046 3047 struct wmi_peer_delete_cmd { 3048 uint32_t tlv_header; 3049 uint32_t vdev_id; 3050 struct wmi_mac_addr peer_macaddr; 3051 } __packed; 3052 3053 struct wmi_peer_reorder_queue_setup_cmd { 3054 uint32_t tlv_header; 3055 uint32_t vdev_id; 3056 struct wmi_mac_addr peer_macaddr; 3057 uint32_t tid; 3058 uint32_t queue_ptr_lo; 3059 uint32_t queue_ptr_hi; 3060 uint32_t queue_no; 3061 uint32_t ba_window_size_valid; 3062 uint32_t ba_window_size; 3063 } __packed; 3064 3065 struct wmi_peer_reorder_queue_remove_cmd { 3066 uint32_t tlv_header; 3067 uint32_t vdev_id; 3068 struct wmi_mac_addr peer_macaddr; 3069 uint32_t tid_mask; 3070 } __packed; 3071 3072 struct gpio_config_params { 3073 uint32_t gpio_num; 3074 uint32_t input; 3075 uint32_t pull_type; 3076 uint32_t intr_mode; 3077 }; 3078 3079 enum wmi_gpio_type { 3080 WMI_GPIO_PULL_NONE, 3081 WMI_GPIO_PULL_UP, 3082 WMI_GPIO_PULL_DOWN 3083 }; 3084 3085 enum wmi_gpio_intr_type { 3086 WMI_GPIO_INTTYPE_DISABLE, 3087 WMI_GPIO_INTTYPE_RISING_EDGE, 3088 WMI_GPIO_INTTYPE_FALLING_EDGE, 3089 WMI_GPIO_INTTYPE_BOTH_EDGE, 3090 WMI_GPIO_INTTYPE_LEVEL_LOW, 3091 WMI_GPIO_INTTYPE_LEVEL_HIGH 3092 }; 3093 3094 enum wmi_bss_chan_info_req_type { 3095 WMI_BSS_SURVEY_REQ_TYPE_READ = 1, 3096 WMI_BSS_SURVEY_REQ_TYPE_READ_CLEAR, 3097 }; 3098 3099 struct wmi_gpio_config_cmd_param { 3100 uint32_t tlv_header; 3101 uint32_t gpio_num; 3102 uint32_t input; 3103 uint32_t pull_type; 3104 uint32_t intr_mode; 3105 }; 3106 3107 struct gpio_output_params { 3108 uint32_t gpio_num; 3109 uint32_t set; 3110 }; 3111 3112 struct wmi_gpio_output_cmd_param { 3113 uint32_t tlv_header; 3114 uint32_t gpio_num; 3115 uint32_t set; 3116 }; 3117 3118 struct set_fwtest_params { 3119 uint32_t arg; 3120 uint32_t value; 3121 }; 3122 3123 struct wmi_fwtest_set_param_cmd_param { 3124 uint32_t tlv_header; 3125 uint32_t param_id; 3126 uint32_t param_value; 3127 }; 3128 3129 struct wmi_pdev_set_param_cmd { 3130 uint32_t tlv_header; 3131 uint32_t pdev_id; 3132 uint32_t param_id; 3133 uint32_t param_value; 3134 } __packed; 3135 3136 struct wmi_pdev_set_ps_mode_cmd { 3137 uint32_t tlv_header; 3138 uint32_t vdev_id; 3139 uint32_t sta_ps_mode; 3140 } __packed; 3141 3142 struct wmi_pdev_suspend_cmd { 3143 uint32_t tlv_header; 3144 uint32_t pdev_id; 3145 uint32_t suspend_opt; 3146 } __packed; 3147 3148 struct wmi_pdev_resume_cmd { 3149 uint32_t tlv_header; 3150 uint32_t pdev_id; 3151 } __packed; 3152 3153 struct wmi_pdev_bss_chan_info_req_cmd { 3154 uint32_t tlv_header; 3155 /* ref wmi_bss_chan_info_req_type */ 3156 uint32_t req_type; 3157 uint32_t pdev_id; 3158 } __packed; 3159 3160 struct wmi_ap_ps_peer_cmd { 3161 uint32_t tlv_header; 3162 uint32_t vdev_id; 3163 struct wmi_mac_addr peer_macaddr; 3164 uint32_t param; 3165 uint32_t value; 3166 } __packed; 3167 3168 struct wmi_sta_powersave_param_cmd { 3169 uint32_t tlv_header; 3170 uint32_t vdev_id; 3171 uint32_t param; 3172 uint32_t value; 3173 } __packed; 3174 3175 struct wmi_pdev_set_regdomain_cmd { 3176 uint32_t tlv_header; 3177 uint32_t pdev_id; 3178 uint32_t reg_domain; 3179 uint32_t reg_domain_2g; 3180 uint32_t reg_domain_5g; 3181 uint32_t conformance_test_limit_2g; 3182 uint32_t conformance_test_limit_5g; 3183 uint32_t dfs_domain; 3184 } __packed; 3185 3186 struct wmi_peer_set_param_cmd { 3187 uint32_t tlv_header; 3188 uint32_t vdev_id; 3189 struct wmi_mac_addr peer_macaddr; 3190 uint32_t param_id; 3191 uint32_t param_value; 3192 } __packed; 3193 3194 struct wmi_peer_flush_tids_cmd { 3195 uint32_t tlv_header; 3196 uint32_t vdev_id; 3197 struct wmi_mac_addr peer_macaddr; 3198 uint32_t peer_tid_bitmap; 3199 } __packed; 3200 3201 struct wmi_dfs_phyerr_offload_cmd { 3202 uint32_t tlv_header; 3203 uint32_t pdev_id; 3204 } __packed; 3205 3206 struct wmi_bcn_offload_ctrl_cmd { 3207 uint32_t tlv_header; 3208 uint32_t vdev_id; 3209 uint32_t bcn_ctrl_op; 3210 } __packed; 3211 3212 enum scan_dwelltime_adaptive_mode { 3213 SCAN_DWELL_MODE_DEFAULT = 0, 3214 SCAN_DWELL_MODE_CONSERVATIVE = 1, 3215 SCAN_DWELL_MODE_MODERATE = 2, 3216 SCAN_DWELL_MODE_AGGRESSIVE = 3, 3217 SCAN_DWELL_MODE_STATIC = 4 3218 }; 3219 3220 #define WLAN_SSID_MAX_LEN 32 3221 3222 struct element_info { 3223 uint32_t len; 3224 uint8_t *ptr; 3225 }; 3226 3227 struct wlan_ssid { 3228 uint8_t length; 3229 uint8_t ssid[WLAN_SSID_MAX_LEN]; 3230 }; 3231 3232 #define WMI_IE_BITMAP_SIZE 8 3233 3234 /* prefix used by scan requestor ids on the host */ 3235 #define WMI_HOST_SCAN_REQUESTOR_ID_PREFIX 0xA000 3236 3237 /* prefix used by scan request ids generated on the host */ 3238 /* host cycles through the lower 12 bits to generate ids */ 3239 #define WMI_HOST_SCAN_REQ_ID_PREFIX 0xA000 3240 3241 /* Values lower than this may be refused by some firmware revisions with a scan 3242 * completion with a timedout reason. 3243 */ 3244 #define WMI_SCAN_CHAN_MIN_TIME_MSEC 40 3245 3246 /* Scan priority numbers must be sequential, starting with 0 */ 3247 enum wmi_scan_priority { 3248 WMI_SCAN_PRIORITY_VERY_LOW = 0, 3249 WMI_SCAN_PRIORITY_LOW, 3250 WMI_SCAN_PRIORITY_MEDIUM, 3251 WMI_SCAN_PRIORITY_HIGH, 3252 WMI_SCAN_PRIORITY_VERY_HIGH, 3253 WMI_SCAN_PRIORITY_COUNT /* number of priorities supported */ 3254 }; 3255 3256 enum wmi_scan_event_type { 3257 WMI_SCAN_EVENT_STARTED = BIT(0), 3258 WMI_SCAN_EVENT_COMPLETED = BIT(1), 3259 WMI_SCAN_EVENT_BSS_CHANNEL = BIT(2), 3260 WMI_SCAN_EVENT_FOREIGN_CHAN = BIT(3), 3261 WMI_SCAN_EVENT_DEQUEUED = BIT(4), 3262 /* possibly by high-prio scan */ 3263 WMI_SCAN_EVENT_PREEMPTED = BIT(5), 3264 WMI_SCAN_EVENT_START_FAILED = BIT(6), 3265 WMI_SCAN_EVENT_RESTARTED = BIT(7), 3266 WMI_SCAN_EVENT_FOREIGN_CHAN_EXIT = BIT(8), 3267 WMI_SCAN_EVENT_SUSPENDED = BIT(9), 3268 WMI_SCAN_EVENT_RESUMED = BIT(10), 3269 WMI_SCAN_EVENT_MAX = BIT(15), 3270 }; 3271 3272 enum wmi_scan_completion_reason { 3273 WMI_SCAN_REASON_COMPLETED, 3274 WMI_SCAN_REASON_CANCELLED, 3275 WMI_SCAN_REASON_PREEMPTED, 3276 WMI_SCAN_REASON_TIMEDOUT, 3277 WMI_SCAN_REASON_INTERNAL_FAILURE, 3278 WMI_SCAN_REASON_MAX, 3279 }; 3280 3281 struct wmi_start_scan_cmd { 3282 uint32_t tlv_header; 3283 uint32_t scan_id; 3284 uint32_t scan_req_id; 3285 uint32_t vdev_id; 3286 uint32_t scan_priority; 3287 uint32_t notify_scan_events; 3288 uint32_t dwell_time_active; 3289 uint32_t dwell_time_passive; 3290 uint32_t min_rest_time; 3291 uint32_t max_rest_time; 3292 uint32_t repeat_probe_time; 3293 uint32_t probe_spacing_time; 3294 uint32_t idle_time; 3295 uint32_t max_scan_time; 3296 uint32_t probe_delay; 3297 uint32_t scan_ctrl_flags; 3298 uint32_t burst_duration; 3299 uint32_t num_chan; 3300 uint32_t num_bssid; 3301 uint32_t num_ssids; 3302 uint32_t ie_len; 3303 uint32_t n_probes; 3304 struct wmi_mac_addr mac_addr; 3305 struct wmi_mac_addr mac_mask; 3306 uint32_t ie_bitmap[WMI_IE_BITMAP_SIZE]; 3307 uint32_t num_vendor_oui; 3308 uint32_t scan_ctrl_flags_ext; 3309 uint32_t dwell_time_active_2g; 3310 uint32_t dwell_time_active_6g; 3311 uint32_t dwell_time_passive_6g; 3312 uint32_t scan_start_offset; 3313 } __packed; 3314 3315 #define WMI_SCAN_FLAG_PASSIVE 0x1 3316 #define WMI_SCAN_ADD_BCAST_PROBE_REQ 0x2 3317 #define WMI_SCAN_ADD_CCK_RATES 0x4 3318 #define WMI_SCAN_ADD_OFDM_RATES 0x8 3319 #define WMI_SCAN_CHAN_STAT_EVENT 0x10 3320 #define WMI_SCAN_FILTER_PROBE_REQ 0x20 3321 #define WMI_SCAN_BYPASS_DFS_CHN 0x40 3322 #define WMI_SCAN_CONTINUE_ON_ERROR 0x80 3323 #define WMI_SCAN_FILTER_PROMISCUOS 0x100 3324 #define WMI_SCAN_FLAG_FORCE_ACTIVE_ON_DFS 0x200 3325 #define WMI_SCAN_ADD_TPC_IE_IN_PROBE_REQ 0x400 3326 #define WMI_SCAN_ADD_DS_IE_IN_PROBE_REQ 0x800 3327 #define WMI_SCAN_ADD_SPOOF_MAC_IN_PROBE_REQ 0x1000 3328 #define WMI_SCAN_OFFCHAN_MGMT_TX 0x2000 3329 #define WMI_SCAN_OFFCHAN_DATA_TX 0x4000 3330 #define WMI_SCAN_CAPTURE_PHY_ERROR 0x8000 3331 #define WMI_SCAN_FLAG_STRICT_PASSIVE_ON_PCHN 0x10000 3332 #define WMI_SCAN_FLAG_HALF_RATE_SUPPORT 0x20000 3333 #define WMI_SCAN_FLAG_QUARTER_RATE_SUPPORT 0x40000 3334 #define WMI_SCAN_RANDOM_SEQ_NO_IN_PROBE_REQ 0x80000 3335 #define WMI_SCAN_ENABLE_IE_WHTELIST_IN_PROBE_REQ 0x100000 3336 3337 #define WMI_SCAN_DWELL_MODE_MASK 0x00E00000 3338 #define WMI_SCAN_DWELL_MODE_SHIFT 21 3339 #define WMI_SCAN_FLAG_EXT_PASSIVE_SCAN_START_TIME_ENHANCE 0x00000800 3340 3341 #define WMI_SCAN_CONFIG_PER_CHANNEL_MASK GENMASK(19, 0) 3342 #define WMI_SCAN_CH_FLAG_SCAN_ONLY_IF_RNR_FOUND BIT(20) 3343 3344 enum { 3345 WMI_SCAN_DWELL_MODE_DEFAULT = 0, 3346 WMI_SCAN_DWELL_MODE_CONSERVATIVE = 1, 3347 WMI_SCAN_DWELL_MODE_MODERATE = 2, 3348 WMI_SCAN_DWELL_MODE_AGGRESSIVE = 3, 3349 WMI_SCAN_DWELL_MODE_STATIC = 4, 3350 }; 3351 3352 #define WMI_SCAN_SET_DWELL_MODE(flag, mode) \ 3353 ((flag) |= (((mode) << WMI_SCAN_DWELL_MODE_SHIFT) & \ 3354 WMI_SCAN_DWELL_MODE_MASK)) 3355 3356 struct hint_short_ssid { 3357 uint32_t freq_flags; 3358 uint32_t short_ssid; 3359 }; 3360 3361 struct hint_bssid { 3362 uint32_t freq_flags; 3363 struct wmi_mac_addr bssid; 3364 }; 3365 3366 struct scan_req_params { 3367 uint32_t scan_id; 3368 uint32_t scan_req_id; 3369 uint32_t vdev_id; 3370 uint32_t pdev_id; 3371 enum wmi_scan_priority scan_priority; 3372 union { 3373 struct { 3374 uint32_t scan_ev_started:1, 3375 scan_ev_completed:1, 3376 scan_ev_bss_chan:1, 3377 scan_ev_foreign_chan:1, 3378 scan_ev_dequeued:1, 3379 scan_ev_preempted:1, 3380 scan_ev_start_failed:1, 3381 scan_ev_restarted:1, 3382 scan_ev_foreign_chn_exit:1, 3383 scan_ev_invalid:1, 3384 scan_ev_gpio_timeout:1, 3385 scan_ev_suspended:1, 3386 scan_ev_resumed:1; 3387 }; 3388 uint32_t scan_events; 3389 }; 3390 uint32_t scan_ctrl_flags_ext; 3391 uint32_t dwell_time_active; 3392 uint32_t dwell_time_active_2g; 3393 uint32_t dwell_time_passive; 3394 uint32_t dwell_time_active_6g; 3395 uint32_t dwell_time_passive_6g; 3396 uint32_t min_rest_time; 3397 uint32_t max_rest_time; 3398 uint32_t repeat_probe_time; 3399 uint32_t probe_spacing_time; 3400 uint32_t idle_time; 3401 uint32_t max_scan_time; 3402 uint32_t probe_delay; 3403 union { 3404 struct { 3405 uint32_t scan_f_passive:1, 3406 scan_f_bcast_probe:1, 3407 scan_f_cck_rates:1, 3408 scan_f_ofdm_rates:1, 3409 scan_f_chan_stat_evnt:1, 3410 scan_f_filter_prb_req:1, 3411 scan_f_bypass_dfs_chn:1, 3412 scan_f_continue_on_err:1, 3413 scan_f_offchan_mgmt_tx:1, 3414 scan_f_offchan_data_tx:1, 3415 scan_f_promisc_mode:1, 3416 scan_f_capture_phy_err:1, 3417 scan_f_strict_passive_pch:1, 3418 scan_f_half_rate:1, 3419 scan_f_quarter_rate:1, 3420 scan_f_force_active_dfs_chn:1, 3421 scan_f_add_tpc_ie_in_probe:1, 3422 scan_f_add_ds_ie_in_probe:1, 3423 scan_f_add_spoofed_mac_in_probe:1, 3424 scan_f_add_rand_seq_in_probe:1, 3425 scan_f_en_ie_whitelist_in_probe:1, 3426 scan_f_forced:1, 3427 scan_f_2ghz:1, 3428 scan_f_5ghz:1, 3429 scan_f_80mhz:1; 3430 }; 3431 uint32_t scan_flags; 3432 }; 3433 enum scan_dwelltime_adaptive_mode adaptive_dwell_time_mode; 3434 uint32_t burst_duration; 3435 uint32_t num_chan; 3436 uint32_t num_bssid; 3437 uint32_t num_ssids; 3438 uint32_t n_probes; 3439 uint32_t *chan_list; 3440 uint32_t notify_scan_events; 3441 struct wlan_ssid ssid[WLAN_SCAN_PARAMS_MAX_SSID]; 3442 struct wmi_mac_addr bssid_list[WLAN_SCAN_PARAMS_MAX_BSSID]; 3443 struct element_info extraie; 3444 struct element_info htcap; 3445 struct element_info vhtcap; 3446 uint32_t num_hint_s_ssid; 3447 uint32_t num_hint_bssid; 3448 struct hint_short_ssid hint_s_ssid[WLAN_SCAN_MAX_HINT_S_SSID]; 3449 struct hint_bssid hint_bssid[WLAN_SCAN_MAX_HINT_BSSID]; 3450 struct wmi_mac_addr mac_addr; 3451 struct wmi_mac_addr mac_mask; 3452 }; 3453 3454 struct wmi_ssid_arg { 3455 int len; 3456 const uint8_t *ssid; 3457 }; 3458 3459 struct wmi_bssid_arg { 3460 const uint8_t *bssid; 3461 }; 3462 3463 struct wmi_start_scan_arg { 3464 uint32_t scan_id; 3465 uint32_t scan_req_id; 3466 uint32_t vdev_id; 3467 uint32_t scan_priority; 3468 uint32_t notify_scan_events; 3469 uint32_t dwell_time_active; 3470 uint32_t dwell_time_passive; 3471 uint32_t min_rest_time; 3472 uint32_t max_rest_time; 3473 uint32_t repeat_probe_time; 3474 uint32_t probe_spacing_time; 3475 uint32_t idle_time; 3476 uint32_t max_scan_time; 3477 uint32_t probe_delay; 3478 uint32_t scan_ctrl_flags; 3479 3480 uint32_t ie_len; 3481 uint32_t n_channels; 3482 uint32_t n_ssids; 3483 uint32_t n_bssids; 3484 3485 uint8_t ie[WLAN_SCAN_PARAMS_MAX_IE_LEN]; 3486 uint32_t channels[64]; 3487 struct wmi_ssid_arg ssids[WLAN_SCAN_PARAMS_MAX_SSID]; 3488 struct wmi_bssid_arg bssids[WLAN_SCAN_PARAMS_MAX_BSSID]; 3489 }; 3490 3491 #define WMI_SCAN_STOP_ONE 0x00000000 3492 #define WMI_SCN_STOP_VAP_ALL 0x01000000 3493 #define WMI_SCAN_STOP_ALL 0x04000000 3494 3495 /* Prefix 0xA000 indicates that the scan request 3496 * is trigger by HOST 3497 */ 3498 #define ATH11K_SCAN_ID 0xA000 3499 3500 enum scan_cancel_req_type { 3501 WLAN_SCAN_CANCEL_SINGLE = 1, 3502 WLAN_SCAN_CANCEL_VDEV_ALL, 3503 WLAN_SCAN_CANCEL_PDEV_ALL, 3504 }; 3505 3506 struct scan_cancel_param { 3507 uint32_t requester; 3508 uint32_t scan_id; 3509 enum scan_cancel_req_type req_type; 3510 uint32_t vdev_id; 3511 uint32_t pdev_id; 3512 }; 3513 3514 struct wmi_bcn_send_from_host_cmd { 3515 uint32_t tlv_header; 3516 uint32_t vdev_id; 3517 uint32_t data_len; 3518 union { 3519 uint32_t frag_ptr; 3520 uint32_t frag_ptr_lo; 3521 }; 3522 uint32_t frame_ctrl; 3523 uint32_t dtim_flag; 3524 uint32_t bcn_antenna; 3525 uint32_t frag_ptr_hi; 3526 }; 3527 3528 #define WMI_CHAN_INFO_MODE GENMASK(5, 0) 3529 #define WMI_CHAN_INFO_HT40_PLUS BIT(6) 3530 #define WMI_CHAN_INFO_PASSIVE BIT(7) 3531 #define WMI_CHAN_INFO_ADHOC_ALLOWED BIT(8) 3532 #define WMI_CHAN_INFO_AP_DISABLED BIT(9) 3533 #define WMI_CHAN_INFO_DFS BIT(10) 3534 #define WMI_CHAN_INFO_ALLOW_HT BIT(11) 3535 #define WMI_CHAN_INFO_ALLOW_VHT BIT(12) 3536 #define WMI_CHAN_INFO_CHAN_CHANGE_CAUSE_CSA BIT(13) 3537 #define WMI_CHAN_INFO_HALF_RATE BIT(14) 3538 #define WMI_CHAN_INFO_QUARTER_RATE BIT(15) 3539 #define WMI_CHAN_INFO_DFS_FREQ2 BIT(16) 3540 #define WMI_CHAN_INFO_ALLOW_HE BIT(17) 3541 #define WMI_CHAN_INFO_PSC BIT(18) 3542 3543 #define WMI_CHAN_REG_INFO1_MIN_PWR GENMASK(7, 0) 3544 #define WMI_CHAN_REG_INFO1_MAX_PWR GENMASK(15, 8) 3545 #define WMI_CHAN_REG_INFO1_MAX_REG_PWR GENMASK(23, 16) 3546 #define WMI_CHAN_REG_INFO1_REG_CLS GENMASK(31, 24) 3547 3548 #define WMI_CHAN_REG_INFO2_ANT_MAX GENMASK(7, 0) 3549 #define WMI_CHAN_REG_INFO2_MAX_TX_PWR GENMASK(15, 8) 3550 3551 struct wmi_channel { 3552 uint32_t tlv_header; 3553 uint32_t mhz; 3554 uint32_t band_center_freq1; 3555 uint32_t band_center_freq2; 3556 uint32_t info; 3557 uint32_t reg_info_1; 3558 uint32_t reg_info_2; 3559 } __packed; 3560 3561 struct wmi_mgmt_params { 3562 void *tx_frame; 3563 uint16_t frm_len; 3564 uint8_t vdev_id; 3565 uint16_t chanfreq; 3566 void *pdata; 3567 uint16_t desc_id; 3568 uint8_t *macaddr; 3569 }; 3570 3571 enum wmi_sta_ps_mode { 3572 WMI_STA_PS_MODE_DISABLED = 0, 3573 WMI_STA_PS_MODE_ENABLED = 1, 3574 }; 3575 3576 #define WMI_SMPS_MASK_LOWER_16BITS 0xFF 3577 #define WMI_SMPS_MASK_UPPER_3BITS 0x7 3578 #define WMI_SMPS_PARAM_VALUE_SHIFT 29 3579 3580 #define ATH11K_WMI_FW_HANG_ASSERT_TYPE 1 3581 #define ATH11K_WMI_FW_HANG_DELAY 0 3582 3583 /* type, 0:unused 1: ASSERT 2: not respond detect command 3584 * delay_time_ms, the simulate will delay time 3585 */ 3586 3587 struct wmi_force_fw_hang_cmd { 3588 uint32_t tlv_header; 3589 uint32_t type; 3590 uint32_t delay_time_ms; 3591 }; 3592 3593 struct wmi_vdev_set_param_cmd { 3594 uint32_t tlv_header; 3595 uint32_t vdev_id; 3596 uint32_t param_id; 3597 uint32_t param_value; 3598 } __packed; 3599 3600 enum wmi_stats_id { 3601 WMI_REQUEST_PEER_STAT = BIT(0), 3602 WMI_REQUEST_AP_STAT = BIT(1), 3603 WMI_REQUEST_PDEV_STAT = BIT(2), 3604 WMI_REQUEST_VDEV_STAT = BIT(3), 3605 WMI_REQUEST_BCNFLT_STAT = BIT(4), 3606 WMI_REQUEST_VDEV_RATE_STAT = BIT(5), 3607 WMI_REQUEST_INST_STAT = BIT(6), 3608 WMI_REQUEST_MIB_STAT = BIT(7), 3609 WMI_REQUEST_RSSI_PER_CHAIN_STAT = BIT(8), 3610 WMI_REQUEST_CONGESTION_STAT = BIT(9), 3611 WMI_REQUEST_PEER_EXTD_STAT = BIT(10), 3612 WMI_REQUEST_BCN_STAT = BIT(11), 3613 WMI_REQUEST_BCN_STAT_RESET = BIT(12), 3614 WMI_REQUEST_PEER_EXTD2_STAT = BIT(13), 3615 }; 3616 3617 struct wmi_request_stats_cmd { 3618 uint32_t tlv_header; 3619 enum wmi_stats_id stats_id; 3620 uint32_t vdev_id; 3621 struct wmi_mac_addr peer_macaddr; 3622 uint32_t pdev_id; 3623 } __packed; 3624 3625 struct wmi_get_pdev_temperature_cmd { 3626 uint32_t tlv_header; 3627 uint32_t param; 3628 uint32_t pdev_id; 3629 } __packed; 3630 3631 struct wmi_ftm_seg_hdr { 3632 uint32_t len; 3633 uint32_t msgref; 3634 uint32_t segmentinfo; 3635 uint32_t pdev_id; 3636 } __packed; 3637 3638 struct wmi_ftm_cmd { 3639 uint32_t tlv_header; 3640 struct wmi_ftm_seg_hdr seg_hdr; 3641 uint8_t data[]; 3642 } __packed; 3643 3644 struct wmi_ftm_event_msg { 3645 struct wmi_ftm_seg_hdr seg_hdr; 3646 uint8_t data[]; 3647 } __packed; 3648 3649 #define WMI_BEACON_TX_BUFFER_SIZE 512 3650 3651 #define WMI_EMA_TMPL_IDX_SHIFT 8 3652 #define WMI_EMA_FIRST_TMPL_SHIFT 16 3653 #define WMI_EMA_LAST_TMPL_SHIFT 24 3654 3655 struct wmi_bcn_tmpl_cmd { 3656 uint32_t tlv_header; 3657 uint32_t vdev_id; 3658 uint32_t tim_ie_offset; 3659 uint32_t buf_len; 3660 uint32_t csa_switch_count_offset; 3661 uint32_t ext_csa_switch_count_offset; 3662 uint32_t csa_event_bitmap; 3663 uint32_t mbssid_ie_offset; 3664 uint32_t esp_ie_offset; 3665 uint32_t csc_switch_count_offset; 3666 uint32_t csc_event_bitmap; 3667 uint32_t mu_edca_ie_offset; 3668 uint32_t feature_enable_bitmap; 3669 uint32_t ema_params; 3670 } __packed; 3671 3672 struct wmi_key_seq_counter { 3673 uint32_t key_seq_counter_l; 3674 uint32_t key_seq_counter_h; 3675 } __packed; 3676 3677 struct wmi_vdev_install_key_cmd { 3678 uint32_t tlv_header; 3679 uint32_t vdev_id; 3680 struct wmi_mac_addr peer_macaddr; 3681 uint32_t key_idx; 3682 uint32_t key_flags; 3683 uint32_t key_cipher; 3684 struct wmi_key_seq_counter key_rsc_counter; 3685 struct wmi_key_seq_counter key_global_rsc_counter; 3686 struct wmi_key_seq_counter key_tsc_counter; 3687 uint8_t wpi_key_rsc_counter[16]; 3688 uint8_t wpi_key_tsc_counter[16]; 3689 uint32_t key_len; 3690 uint32_t key_txmic_len; 3691 uint32_t key_rxmic_len; 3692 uint32_t is_group_key_id_valid; 3693 uint32_t group_key_id; 3694 3695 /* Followed by key_data containing key followed by 3696 * tx mic and then rx mic 3697 */ 3698 } __packed; 3699 3700 struct wmi_vdev_install_key_arg { 3701 uint32_t vdev_id; 3702 const uint8_t *macaddr; 3703 uint32_t key_idx; 3704 uint32_t key_flags; 3705 uint32_t key_cipher; 3706 uint32_t key_len; 3707 uint32_t key_txmic_len; 3708 uint32_t key_rxmic_len; 3709 uint64_t key_rsc_counter; 3710 const void *key_data; 3711 }; 3712 3713 #define WMI_MAX_SUPPORTED_RATES 128 3714 #define WMI_HOST_MAX_HECAP_PHY_SIZE 3 3715 #define WMI_HOST_MAX_HE_RATE_SET 3 3716 #define WMI_HECAP_TXRX_MCS_NSS_IDX_80 0 3717 #define WMI_HECAP_TXRX_MCS_NSS_IDX_160 1 3718 #define WMI_HECAP_TXRX_MCS_NSS_IDX_80_80 2 3719 3720 struct wmi_rate_set_arg { 3721 uint32_t num_rates; 3722 uint8_t rates[WMI_MAX_SUPPORTED_RATES]; 3723 }; 3724 3725 struct peer_assoc_params { 3726 struct wmi_mac_addr peer_macaddr; 3727 uint32_t vdev_id; 3728 uint32_t peer_new_assoc; 3729 uint32_t peer_associd; 3730 uint32_t peer_flags; 3731 uint32_t peer_caps; 3732 uint32_t peer_listen_intval; 3733 uint32_t peer_ht_caps; 3734 uint32_t peer_max_mpdu; 3735 uint32_t peer_mpdu_density; 3736 uint32_t peer_rate_caps; 3737 uint32_t peer_nss; 3738 uint32_t peer_vht_caps; 3739 uint32_t peer_phymode; 3740 uint32_t peer_ht_info[2]; 3741 struct wmi_rate_set_arg peer_legacy_rates; 3742 struct wmi_rate_set_arg peer_ht_rates; 3743 uint32_t rx_max_rate; 3744 uint32_t rx_mcs_set; 3745 uint32_t tx_max_rate; 3746 uint32_t tx_mcs_set; 3747 uint8_t vht_capable; 3748 uint8_t min_data_rate; 3749 uint32_t tx_max_mcs_nss; 3750 uint32_t peer_bw_rxnss_override; 3751 bool is_pmf_enabled; 3752 bool is_wme_set; 3753 bool qos_flag; 3754 bool apsd_flag; 3755 bool ht_flag; 3756 bool bw_40; 3757 bool bw_80; 3758 bool bw_160; 3759 bool stbc_flag; 3760 bool ldpc_flag; 3761 bool static_mimops_flag; 3762 bool dynamic_mimops_flag; 3763 bool spatial_mux_flag; 3764 bool vht_flag; 3765 bool vht_ng_flag; 3766 bool need_ptk_4_way; 3767 bool need_gtk_2_way; 3768 bool auth_flag; 3769 bool safe_mode_enabled; 3770 bool amsdu_disable; 3771 /* Use common structure */ 3772 uint8_t peer_mac[IEEE80211_ADDR_LEN]; 3773 3774 bool he_flag; 3775 uint32_t peer_he_cap_macinfo[2]; 3776 uint32_t peer_he_cap_macinfo_internal; 3777 uint32_t peer_he_caps_6ghz; 3778 uint32_t peer_he_ops; 3779 uint32_t peer_he_cap_phyinfo[WMI_HOST_MAX_HECAP_PHY_SIZE]; 3780 uint32_t peer_he_mcs_count; 3781 uint32_t peer_he_rx_mcs_set[WMI_HOST_MAX_HE_RATE_SET]; 3782 uint32_t peer_he_tx_mcs_set[WMI_HOST_MAX_HE_RATE_SET]; 3783 bool twt_responder; 3784 bool twt_requester; 3785 bool is_assoc; 3786 struct ath11k_ppe_threshold peer_ppet; 3787 }; 3788 3789 struct wmi_peer_assoc_complete_cmd { 3790 uint32_t tlv_header; 3791 struct wmi_mac_addr peer_macaddr; 3792 uint32_t vdev_id; 3793 uint32_t peer_new_assoc; 3794 uint32_t peer_associd; 3795 uint32_t peer_flags; 3796 uint32_t peer_caps; 3797 uint32_t peer_listen_intval; 3798 uint32_t peer_ht_caps; 3799 uint32_t peer_max_mpdu; 3800 uint32_t peer_mpdu_density; 3801 uint32_t peer_rate_caps; 3802 uint32_t peer_nss; 3803 uint32_t peer_vht_caps; 3804 uint32_t peer_phymode; 3805 uint32_t peer_ht_info[2]; 3806 uint32_t num_peer_legacy_rates; 3807 uint32_t num_peer_ht_rates; 3808 uint32_t peer_bw_rxnss_override; 3809 struct wmi_ppe_threshold peer_ppet; 3810 uint32_t peer_he_cap_info; 3811 uint32_t peer_he_ops; 3812 uint32_t peer_he_cap_phy[WMI_MAX_HECAP_PHY_SIZE]; 3813 uint32_t peer_he_mcs; 3814 uint32_t peer_he_cap_info_ext; 3815 uint32_t peer_he_cap_info_internal; 3816 uint32_t min_data_rate; 3817 uint32_t peer_he_caps_6ghz; 3818 } __packed; 3819 3820 struct wmi_stop_scan_cmd { 3821 uint32_t tlv_header; 3822 uint32_t requestor; 3823 uint32_t scan_id; 3824 uint32_t req_type; 3825 uint32_t vdev_id; 3826 uint32_t pdev_id; 3827 }; 3828 3829 struct scan_chan_list_params { 3830 uint32_t pdev_id; 3831 uint16_t nallchans; 3832 struct channel_param ch_param[]; 3833 }; 3834 3835 struct wmi_scan_chan_list_cmd { 3836 uint32_t tlv_header; 3837 uint32_t num_scan_chans; 3838 uint32_t flags; 3839 uint32_t pdev_id; 3840 } __packed; 3841 3842 struct wmi_scan_prob_req_oui_cmd { 3843 uint32_t tlv_header; 3844 uint32_t prob_req_oui; 3845 } __packed; 3846 3847 #define WMI_MGMT_SEND_DOWNLD_LEN 64 3848 3849 #define WMI_TX_PARAMS_DWORD0_POWER GENMASK(7, 0) 3850 #define WMI_TX_PARAMS_DWORD0_MCS_MASK GENMASK(19, 8) 3851 #define WMI_TX_PARAMS_DWORD0_NSS_MASK GENMASK(27, 20) 3852 #define WMI_TX_PARAMS_DWORD0_RETRY_LIMIT GENMASK(31, 28) 3853 3854 #define WMI_TX_PARAMS_DWORD1_CHAIN_MASK GENMASK(7, 0) 3855 #define WMI_TX_PARAMS_DWORD1_BW_MASK GENMASK(14, 8) 3856 #define WMI_TX_PARAMS_DWORD1_PREAMBLE_TYPE GENMASK(19, 15) 3857 #define WMI_TX_PARAMS_DWORD1_FRAME_TYPE BIT(20) 3858 #define WMI_TX_PARAMS_DWORD1_RSVD GENMASK(31, 21) 3859 3860 struct wmi_mgmt_send_params { 3861 uint32_t tlv_header; 3862 uint32_t tx_params_dword0; 3863 uint32_t tx_params_dword1; 3864 }; 3865 3866 struct wmi_mgmt_send_cmd { 3867 uint32_t tlv_header; 3868 uint32_t vdev_id; 3869 uint32_t desc_id; 3870 uint32_t chanfreq; 3871 uint32_t paddr_lo; 3872 uint32_t paddr_hi; 3873 uint32_t frame_len; 3874 uint32_t buf_len; 3875 uint32_t tx_params_valid; 3876 3877 /* This TLV is followed by struct wmi_mgmt_frame */ 3878 3879 /* Followed by struct wmi_mgmt_send_params */ 3880 } __packed; 3881 3882 struct wmi_sta_powersave_mode_cmd { 3883 uint32_t tlv_header; 3884 uint32_t vdev_id; 3885 uint32_t sta_ps_mode; 3886 }; 3887 3888 struct wmi_sta_smps_force_mode_cmd { 3889 uint32_t tlv_header; 3890 uint32_t vdev_id; 3891 uint32_t forced_mode; 3892 }; 3893 3894 struct wmi_sta_smps_param_cmd { 3895 uint32_t tlv_header; 3896 uint32_t vdev_id; 3897 uint32_t param; 3898 uint32_t value; 3899 }; 3900 3901 struct wmi_bcn_prb_info { 3902 uint32_t tlv_header; 3903 uint32_t caps; 3904 uint32_t erp; 3905 } __packed; 3906 3907 enum { 3908 WMI_PDEV_SUSPEND, 3909 WMI_PDEV_SUSPEND_AND_DISABLE_INTR, 3910 }; 3911 3912 struct green_ap_ps_params { 3913 uint32_t value; 3914 }; 3915 3916 struct wmi_pdev_green_ap_ps_enable_cmd_param { 3917 uint32_t tlv_header; 3918 uint32_t pdev_id; 3919 uint32_t enable; 3920 }; 3921 3922 struct ap_ps_params { 3923 uint32_t vdev_id; 3924 uint32_t param; 3925 uint32_t value; 3926 }; 3927 3928 struct vdev_set_params { 3929 uint32_t if_id; 3930 uint32_t param_id; 3931 uint32_t param_value; 3932 }; 3933 3934 struct stats_request_params { 3935 uint32_t stats_id; 3936 uint32_t vdev_id; 3937 uint32_t pdev_id; 3938 }; 3939 3940 struct wmi_set_current_country_params { 3941 uint8_t alpha2[3]; 3942 }; 3943 3944 struct wmi_set_current_country_cmd { 3945 uint32_t tlv_header; 3946 uint32_t pdev_id; 3947 uint32_t new_alpha2; 3948 } __packed; 3949 3950 enum set_init_cc_type { 3951 WMI_COUNTRY_INFO_TYPE_ALPHA, 3952 WMI_COUNTRY_INFO_TYPE_COUNTRY_CODE, 3953 WMI_COUNTRY_INFO_TYPE_REGDOMAIN, 3954 }; 3955 3956 enum set_init_cc_flags { 3957 INVALID_CC, 3958 CC_IS_SET, 3959 REGDMN_IS_SET, 3960 ALPHA_IS_SET, 3961 }; 3962 3963 struct wmi_init_country_params { 3964 union { 3965 uint16_t country_code; 3966 uint16_t regdom_id; 3967 uint8_t alpha2[3]; 3968 } cc_info; 3969 enum set_init_cc_flags flags; 3970 }; 3971 3972 struct wmi_init_country_cmd { 3973 uint32_t tlv_header; 3974 uint32_t pdev_id; 3975 uint32_t init_cc_type; 3976 union { 3977 uint32_t country_code; 3978 uint32_t regdom_id; 3979 uint32_t alpha2; 3980 } cc_info; 3981 } __packed; 3982 3983 struct wmi_11d_scan_start_params { 3984 uint32_t vdev_id; 3985 uint32_t scan_period_msec; 3986 uint32_t start_interval_msec; 3987 }; 3988 3989 struct wmi_11d_scan_start_cmd { 3990 uint32_t tlv_header; 3991 uint32_t vdev_id; 3992 uint32_t scan_period_msec; 3993 uint32_t start_interval_msec; 3994 } __packed; 3995 3996 struct wmi_11d_scan_stop_cmd { 3997 uint32_t tlv_header; 3998 uint32_t vdev_id; 3999 } __packed; 4000 4001 struct wmi_11d_new_cc_ev { 4002 uint32_t new_alpha2; 4003 } __packed; 4004 4005 #define THERMAL_LEVELS 1 4006 struct tt_level_config { 4007 uint32_t tmplwm; 4008 uint32_t tmphwm; 4009 uint32_t dcoffpercent; 4010 uint32_t priority; 4011 }; 4012 4013 struct thermal_mitigation_params { 4014 uint32_t pdev_id; 4015 uint32_t enable; 4016 uint32_t dc; 4017 uint32_t dc_per_event; 4018 struct tt_level_config levelconf[THERMAL_LEVELS]; 4019 }; 4020 4021 struct wmi_therm_throt_config_request_cmd { 4022 uint32_t tlv_header; 4023 uint32_t pdev_id; 4024 uint32_t enable; 4025 uint32_t dc; 4026 uint32_t dc_per_event; 4027 uint32_t therm_throt_levels; 4028 } __packed; 4029 4030 struct wmi_therm_throt_level_config_info { 4031 uint32_t tlv_header; 4032 uint32_t temp_lwm; 4033 uint32_t temp_hwm; 4034 uint32_t dc_off_percent; 4035 uint32_t prio; 4036 } __packed; 4037 4038 struct wmi_delba_send_cmd { 4039 uint32_t tlv_header; 4040 uint32_t vdev_id; 4041 struct wmi_mac_addr peer_macaddr; 4042 uint32_t tid; 4043 uint32_t initiator; 4044 uint32_t reasoncode; 4045 } __packed; 4046 4047 struct wmi_addba_setresponse_cmd { 4048 uint32_t tlv_header; 4049 uint32_t vdev_id; 4050 struct wmi_mac_addr peer_macaddr; 4051 uint32_t tid; 4052 uint32_t statuscode; 4053 } __packed; 4054 4055 struct wmi_addba_send_cmd { 4056 uint32_t tlv_header; 4057 uint32_t vdev_id; 4058 struct wmi_mac_addr peer_macaddr; 4059 uint32_t tid; 4060 uint32_t buffersize; 4061 } __packed; 4062 4063 struct wmi_addba_clear_resp_cmd { 4064 uint32_t tlv_header; 4065 uint32_t vdev_id; 4066 struct wmi_mac_addr peer_macaddr; 4067 } __packed; 4068 4069 struct wmi_pdev_pktlog_filter_info { 4070 uint32_t tlv_header; 4071 struct wmi_mac_addr peer_macaddr; 4072 } __packed; 4073 4074 struct wmi_pdev_pktlog_filter_cmd { 4075 uint32_t tlv_header; 4076 uint32_t pdev_id; 4077 uint32_t enable; 4078 uint32_t filter_type; 4079 uint32_t num_mac; 4080 } __packed; 4081 4082 enum ath11k_wmi_pktlog_enable { 4083 ATH11K_WMI_PKTLOG_ENABLE_AUTO = 0, 4084 ATH11K_WMI_PKTLOG_ENABLE_FORCE = 1, 4085 }; 4086 4087 struct wmi_pktlog_enable_cmd { 4088 uint32_t tlv_header; 4089 uint32_t pdev_id; 4090 uint32_t evlist; /* WMI_PKTLOG_EVENT */ 4091 uint32_t enable; 4092 } __packed; 4093 4094 struct wmi_pktlog_disable_cmd { 4095 uint32_t tlv_header; 4096 uint32_t pdev_id; 4097 } __packed; 4098 4099 #define DFS_PHYERR_UNIT_TEST_CMD 0 4100 #define DFS_UNIT_TEST_MODULE 0x2b 4101 #define DFS_UNIT_TEST_TOKEN 0xAA 4102 4103 enum dfs_test_args_idx { 4104 DFS_TEST_CMDID = 0, 4105 DFS_TEST_PDEV_ID, 4106 DFS_TEST_RADAR_PARAM, 4107 DFS_MAX_TEST_ARGS, 4108 }; 4109 4110 struct wmi_dfs_unit_test_arg { 4111 uint32_t cmd_id; 4112 uint32_t pdev_id; 4113 uint32_t radar_param; 4114 }; 4115 4116 struct wmi_unit_test_cmd { 4117 uint32_t tlv_header; 4118 uint32_t vdev_id; 4119 uint32_t module_id; 4120 uint32_t num_args; 4121 uint32_t diag_token; 4122 /* Followed by test args*/ 4123 } __packed; 4124 4125 #define MAX_SUPPORTED_RATES 128 4126 4127 #define WMI_PEER_AUTH 0x00000001 4128 #define WMI_PEER_QOS 0x00000002 4129 #define WMI_PEER_NEED_PTK_4_WAY 0x00000004 4130 #define WMI_PEER_NEED_GTK_2_WAY 0x00000010 4131 #define WMI_PEER_HE 0x00000400 4132 #define WMI_PEER_APSD 0x00000800 4133 #define WMI_PEER_HT 0x00001000 4134 #define WMI_PEER_40MHZ 0x00002000 4135 #define WMI_PEER_STBC 0x00008000 4136 #define WMI_PEER_LDPC 0x00010000 4137 #define WMI_PEER_DYN_MIMOPS 0x00020000 4138 #define WMI_PEER_STATIC_MIMOPS 0x00040000 4139 #define WMI_PEER_SPATIAL_MUX 0x00200000 4140 #define WMI_PEER_TWT_REQ 0x00400000 4141 #define WMI_PEER_TWT_RESP 0x00800000 4142 #define WMI_PEER_VHT 0x02000000 4143 #define WMI_PEER_80MHZ 0x04000000 4144 #define WMI_PEER_PMF 0x08000000 4145 /* TODO: Place holder for WLAN_PEER_F_PS_PRESEND_REQUIRED = 0x10000000. 4146 * Need to be cleaned up 4147 */ 4148 #define WMI_PEER_IS_P2P_CAPABLE 0x20000000 4149 #define WMI_PEER_160MHZ 0x40000000 4150 #define WMI_PEER_SAFEMODE_EN 0x80000000 4151 4152 struct beacon_tmpl_params { 4153 uint8_t vdev_id; 4154 uint32_t tim_ie_offset; 4155 uint32_t tmpl_len; 4156 uint32_t tmpl_len_aligned; 4157 uint32_t csa_switch_count_offset; 4158 uint32_t ext_csa_switch_count_offset; 4159 uint8_t *frm; 4160 }; 4161 4162 struct wmi_rate_set { 4163 uint32_t num_rates; 4164 uint32_t rates[(MAX_SUPPORTED_RATES / 4) + 1]; 4165 }; 4166 4167 struct wmi_vht_rate_set { 4168 uint32_t tlv_header; 4169 uint32_t rx_max_rate; 4170 uint32_t rx_mcs_set; 4171 uint32_t tx_max_rate; 4172 uint32_t tx_mcs_set; 4173 uint32_t tx_max_mcs_nss; 4174 } __packed; 4175 4176 struct wmi_he_rate_set { 4177 uint32_t tlv_header; 4178 4179 /* MCS at which the peer can receive */ 4180 uint32_t rx_mcs_set; 4181 4182 /* MCS at which the peer can transmit */ 4183 uint32_t tx_mcs_set; 4184 } __packed; 4185 4186 #define MAX_REG_RULES 10 4187 #define REG_ALPHA2_LEN 2 4188 #define MAX_6GHZ_REG_RULES 5 4189 4190 enum wmi_start_event_param { 4191 WMI_VDEV_START_RESP_EVENT = 0, 4192 WMI_VDEV_RESTART_RESP_EVENT, 4193 }; 4194 4195 struct wmi_vdev_start_resp_event { 4196 uint32_t vdev_id; 4197 uint32_t requestor_id; 4198 enum wmi_start_event_param resp_type; 4199 uint32_t status; 4200 uint32_t chain_mask; 4201 uint32_t smps_mode; 4202 union { 4203 uint32_t mac_id; 4204 uint32_t pdev_id; 4205 }; 4206 uint32_t cfgd_tx_streams; 4207 uint32_t cfgd_rx_streams; 4208 } __packed; 4209 4210 /* VDEV start response status codes */ 4211 enum wmi_vdev_start_resp_status_code { 4212 WMI_VDEV_START_RESPONSE_STATUS_SUCCESS = 0, 4213 WMI_VDEV_START_RESPONSE_INVALID_VDEVID = 1, 4214 WMI_VDEV_START_RESPONSE_NOT_SUPPORTED = 2, 4215 WMI_VDEV_START_RESPONSE_DFS_VIOLATION = 3, 4216 WMI_VDEV_START_RESPONSE_INVALID_REGDOMAIN = 4, 4217 }; 4218 4219 /* Regaulatory Rule Flags Passed by FW */ 4220 #define REGULATORY_CHAN_DISABLED BIT(0) 4221 #define REGULATORY_CHAN_NO_IR BIT(1) 4222 #define REGULATORY_CHAN_RADAR BIT(3) 4223 #define REGULATORY_CHAN_NO_OFDM BIT(6) 4224 #define REGULATORY_CHAN_INDOOR_ONLY BIT(9) 4225 4226 #define REGULATORY_CHAN_NO_HT40 BIT(4) 4227 #define REGULATORY_CHAN_NO_80MHZ BIT(7) 4228 #define REGULATORY_CHAN_NO_160MHZ BIT(8) 4229 #define REGULATORY_CHAN_NO_20MHZ BIT(11) 4230 #define REGULATORY_CHAN_NO_10MHZ BIT(12) 4231 4232 enum wmi_reg_chan_list_cmd_type { 4233 WMI_REG_CHAN_LIST_CC_ID = 0, 4234 WMI_REG_CHAN_LIST_CC_EXT_ID = 1, 4235 }; 4236 4237 enum wmi_reg_cc_setting_code { 4238 WMI_REG_SET_CC_STATUS_PASS = 0, 4239 WMI_REG_CURRENT_ALPHA2_NOT_FOUND = 1, 4240 WMI_REG_INIT_ALPHA2_NOT_FOUND = 2, 4241 WMI_REG_SET_CC_CHANGE_NOT_ALLOWED = 3, 4242 WMI_REG_SET_CC_STATUS_NO_MEMORY = 4, 4243 WMI_REG_SET_CC_STATUS_FAIL = 5, 4244 4245 /* add new setting code above, update in 4246 * @enum cc_setting_code as well. 4247 * Also handle it in ath11k_wmi_cc_setting_code_to_reg() 4248 */ 4249 }; 4250 4251 enum cc_setting_code { 4252 REG_SET_CC_STATUS_PASS = 0, 4253 REG_CURRENT_ALPHA2_NOT_FOUND = 1, 4254 REG_INIT_ALPHA2_NOT_FOUND = 2, 4255 REG_SET_CC_CHANGE_NOT_ALLOWED = 3, 4256 REG_SET_CC_STATUS_NO_MEMORY = 4, 4257 REG_SET_CC_STATUS_FAIL = 5, 4258 4259 /* add new setting code above, update in 4260 * @enum wmi_reg_cc_setting_code as well. 4261 * Also handle it in ath11k_cc_status_to_str() 4262 */ 4263 }; 4264 4265 static inline enum cc_setting_code 4266 qwx_wmi_cc_setting_code_to_reg(enum wmi_reg_cc_setting_code status_code) 4267 { 4268 switch (status_code) { 4269 case WMI_REG_SET_CC_STATUS_PASS: 4270 return REG_SET_CC_STATUS_PASS; 4271 case WMI_REG_CURRENT_ALPHA2_NOT_FOUND: 4272 return REG_CURRENT_ALPHA2_NOT_FOUND; 4273 case WMI_REG_INIT_ALPHA2_NOT_FOUND: 4274 return REG_INIT_ALPHA2_NOT_FOUND; 4275 case WMI_REG_SET_CC_CHANGE_NOT_ALLOWED: 4276 return REG_SET_CC_CHANGE_NOT_ALLOWED; 4277 case WMI_REG_SET_CC_STATUS_NO_MEMORY: 4278 return REG_SET_CC_STATUS_NO_MEMORY; 4279 case WMI_REG_SET_CC_STATUS_FAIL: 4280 return REG_SET_CC_STATUS_FAIL; 4281 } 4282 4283 return REG_SET_CC_STATUS_FAIL; 4284 } 4285 4286 static inline const char * 4287 qwx_cc_status_to_str(enum cc_setting_code code) 4288 { 4289 switch (code) { 4290 case REG_SET_CC_STATUS_PASS: 4291 return "REG_SET_CC_STATUS_PASS"; 4292 case REG_CURRENT_ALPHA2_NOT_FOUND: 4293 return "REG_CURRENT_ALPHA2_NOT_FOUND"; 4294 case REG_INIT_ALPHA2_NOT_FOUND: 4295 return "REG_INIT_ALPHA2_NOT_FOUND"; 4296 case REG_SET_CC_CHANGE_NOT_ALLOWED: 4297 return "REG_SET_CC_CHANGE_NOT_ALLOWED"; 4298 case REG_SET_CC_STATUS_NO_MEMORY: 4299 return "REG_SET_CC_STATUS_NO_MEMORY"; 4300 case REG_SET_CC_STATUS_FAIL: 4301 return "REG_SET_CC_STATUS_FAIL"; 4302 } 4303 4304 return "Unknown CC status"; 4305 } 4306 4307 enum wmi_reg_6ghz_ap_type { 4308 WMI_REG_INDOOR_AP = 0, 4309 WMI_REG_STANDARD_POWER_AP = 1, 4310 WMI_REG_VERY_LOW_POWER_AP = 2, 4311 4312 /* add AP type above, handle in ath11k_6ghz_ap_type_to_str() 4313 */ 4314 WMI_REG_CURRENT_MAX_AP_TYPE, 4315 WMI_REG_MAX_AP_TYPE = 7, 4316 }; 4317 4318 static inline const char * 4319 qwx_6ghz_ap_type_to_str(enum wmi_reg_6ghz_ap_type type) 4320 { 4321 switch (type) { 4322 case WMI_REG_INDOOR_AP: 4323 return "INDOOR AP"; 4324 case WMI_REG_STANDARD_POWER_AP: 4325 return "STANDARD POWER AP"; 4326 case WMI_REG_VERY_LOW_POWER_AP: 4327 return "VERY LOW POWER AP"; 4328 case WMI_REG_CURRENT_MAX_AP_TYPE: 4329 return "CURRENT_MAX_AP_TYPE"; 4330 case WMI_REG_MAX_AP_TYPE: 4331 return "MAX_AP_TYPE"; 4332 } 4333 4334 return "unknown 6 GHz AP type"; 4335 } 4336 4337 enum wmi_reg_6ghz_client_type { 4338 WMI_REG_DEFAULT_CLIENT = 0, 4339 WMI_REG_SUBORDINATE_CLIENT = 1, 4340 WMI_REG_MAX_CLIENT_TYPE = 2, 4341 4342 /* add client type above, handle it in 4343 * ath11k_6ghz_client_type_to_str() 4344 */ 4345 }; 4346 4347 static inline const char * 4348 qwx_6ghz_client_type_to_str(enum wmi_reg_6ghz_client_type type) 4349 { 4350 switch (type) { 4351 case WMI_REG_DEFAULT_CLIENT: 4352 return "DEFAULT CLIENT"; 4353 case WMI_REG_SUBORDINATE_CLIENT: 4354 return "SUBORDINATE CLIENT"; 4355 case WMI_REG_MAX_CLIENT_TYPE: 4356 return "MAX_CLIENT_TYPE"; 4357 } 4358 4359 return "unknown 6 GHz client type"; 4360 } 4361 4362 enum reg_subdomains_6ghz { 4363 EMPTY_6GHZ = 0x0, 4364 FCC1_CLIENT_LPI_REGULAR_6GHZ = 0x01, 4365 FCC1_CLIENT_SP_6GHZ = 0x02, 4366 FCC1_AP_LPI_6GHZ = 0x03, 4367 FCC1_CLIENT_LPI_SUBORDINATE = FCC1_AP_LPI_6GHZ, 4368 FCC1_AP_SP_6GHZ = 0x04, 4369 ETSI1_LPI_6GHZ = 0x10, 4370 ETSI1_VLP_6GHZ = 0x11, 4371 ETSI2_LPI_6GHZ = 0x12, 4372 ETSI2_VLP_6GHZ = 0x13, 4373 APL1_LPI_6GHZ = 0x20, 4374 APL1_VLP_6GHZ = 0x21, 4375 4376 /* add sub-domain above, handle it in 4377 * ath11k_sub_reg_6ghz_to_str() 4378 */ 4379 }; 4380 4381 static inline const char * 4382 qwx_sub_reg_6ghz_to_str(enum reg_subdomains_6ghz sub_id) 4383 { 4384 switch (sub_id) { 4385 case EMPTY_6GHZ: 4386 return "N/A"; 4387 case FCC1_CLIENT_LPI_REGULAR_6GHZ: 4388 return "FCC1_CLIENT_LPI_REGULAR_6GHZ"; 4389 case FCC1_CLIENT_SP_6GHZ: 4390 return "FCC1_CLIENT_SP_6GHZ"; 4391 case FCC1_AP_LPI_6GHZ: 4392 return "FCC1_AP_LPI_6GHZ/FCC1_CLIENT_LPI_SUBORDINATE"; 4393 case FCC1_AP_SP_6GHZ: 4394 return "FCC1_AP_SP_6GHZ"; 4395 case ETSI1_LPI_6GHZ: 4396 return "ETSI1_LPI_6GHZ"; 4397 case ETSI1_VLP_6GHZ: 4398 return "ETSI1_VLP_6GHZ"; 4399 case ETSI2_LPI_6GHZ: 4400 return "ETSI2_LPI_6GHZ"; 4401 case ETSI2_VLP_6GHZ: 4402 return "ETSI2_VLP_6GHZ"; 4403 case APL1_LPI_6GHZ: 4404 return "APL1_LPI_6GHZ"; 4405 case APL1_VLP_6GHZ: 4406 return "APL1_VLP_6GHZ"; 4407 } 4408 4409 return "unknown sub reg id"; 4410 } 4411 4412 enum reg_super_domain_6ghz { 4413 FCC1_6GHZ = 0x01, 4414 ETSI1_6GHZ = 0x02, 4415 ETSI2_6GHZ = 0x03, 4416 APL1_6GHZ = 0x04, 4417 FCC1_6GHZ_CL = 0x05, 4418 4419 /* add super domain above, handle it in 4420 * ath11k_super_reg_6ghz_to_str() 4421 */ 4422 }; 4423 4424 static inline const char * 4425 qwx_super_reg_6ghz_to_str(enum reg_super_domain_6ghz domain_id) 4426 { 4427 switch (domain_id) { 4428 case FCC1_6GHZ: 4429 return "FCC1_6GHZ"; 4430 case ETSI1_6GHZ: 4431 return "ETSI1_6GHZ"; 4432 case ETSI2_6GHZ: 4433 return "ETSI2_6GHZ"; 4434 case APL1_6GHZ: 4435 return "APL1_6GHZ"; 4436 case FCC1_6GHZ_CL: 4437 return "FCC1_6GHZ_CL"; 4438 } 4439 4440 return "unknown domain id"; 4441 } 4442 4443 struct cur_reg_rule { 4444 uint16_t start_freq; 4445 uint16_t end_freq; 4446 uint16_t max_bw; 4447 uint8_t reg_power; 4448 uint8_t ant_gain; 4449 uint16_t flags; 4450 bool psd_flag; 4451 int8_t psd_eirp; 4452 }; 4453 4454 struct cur_regulatory_info { 4455 enum cc_setting_code status_code; 4456 uint8_t num_phy; 4457 uint8_t phy_id; 4458 uint16_t reg_dmn_pair; 4459 uint16_t ctry_code; 4460 uint8_t alpha2[REG_ALPHA2_LEN + 1]; 4461 uint32_t dfs_region; 4462 uint32_t phybitmap; 4463 uint32_t min_bw_2ghz; 4464 uint32_t max_bw_2ghz; 4465 uint32_t min_bw_5ghz; 4466 uint32_t max_bw_5ghz; 4467 uint32_t num_2ghz_reg_rules; 4468 uint32_t num_5ghz_reg_rules; 4469 struct cur_reg_rule *reg_rules_2ghz_ptr; 4470 struct cur_reg_rule *reg_rules_5ghz_ptr; 4471 bool is_ext_reg_event; 4472 enum wmi_reg_6ghz_client_type client_type; 4473 bool rnr_tpe_usable; 4474 bool unspecified_ap_usable; 4475 uint8_t domain_code_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 4476 uint8_t domain_code_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4477 uint32_t domain_code_6ghz_super_id; 4478 uint32_t min_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 4479 uint32_t max_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 4480 uint32_t min_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4481 uint32_t max_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4482 uint32_t num_6ghz_rules_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 4483 uint32_t num_6ghz_rules_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4484 struct cur_reg_rule *reg_rules_6ghz_ap_ptr[WMI_REG_CURRENT_MAX_AP_TYPE]; 4485 struct cur_reg_rule *reg_rules_6ghz_client_ptr 4486 [WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4487 }; 4488 4489 struct wmi_reg_chan_list_cc_event { 4490 uint32_t status_code; 4491 uint32_t phy_id; 4492 uint32_t alpha2; 4493 uint32_t num_phy; 4494 uint32_t country_id; 4495 uint32_t domain_code; 4496 uint32_t dfs_region; 4497 uint32_t phybitmap; 4498 uint32_t min_bw_2ghz; 4499 uint32_t max_bw_2ghz; 4500 uint32_t min_bw_5ghz; 4501 uint32_t max_bw_5ghz; 4502 uint32_t num_2ghz_reg_rules; 4503 uint32_t num_5ghz_reg_rules; 4504 } __packed; 4505 4506 struct wmi_regulatory_rule_struct { 4507 uint32_t tlv_header; 4508 uint32_t freq_info; 4509 uint32_t bw_pwr_info; 4510 uint32_t flag_info; 4511 }; 4512 4513 #define WMI_REG_CLIENT_MAX 4 4514 4515 struct wmi_reg_chan_list_cc_ext_event { 4516 uint32_t status_code; 4517 uint32_t phy_id; 4518 uint32_t alpha2; 4519 uint32_t num_phy; 4520 uint32_t country_id; 4521 uint32_t domain_code; 4522 uint32_t dfs_region; 4523 uint32_t phybitmap; 4524 uint32_t min_bw_2ghz; 4525 uint32_t max_bw_2ghz; 4526 uint32_t min_bw_5ghz; 4527 uint32_t max_bw_5ghz; 4528 uint32_t num_2ghz_reg_rules; 4529 uint32_t num_5ghz_reg_rules; 4530 uint32_t client_type; 4531 uint32_t rnr_tpe_usable; 4532 uint32_t unspecified_ap_usable; 4533 uint32_t domain_code_6ghz_ap_lpi; 4534 uint32_t domain_code_6ghz_ap_sp; 4535 uint32_t domain_code_6ghz_ap_vlp; 4536 uint32_t domain_code_6ghz_client_lpi[WMI_REG_CLIENT_MAX]; 4537 uint32_t domain_code_6ghz_client_sp[WMI_REG_CLIENT_MAX]; 4538 uint32_t domain_code_6ghz_client_vlp[WMI_REG_CLIENT_MAX]; 4539 uint32_t domain_code_6ghz_super_id; 4540 uint32_t min_bw_6ghz_ap_sp; 4541 uint32_t max_bw_6ghz_ap_sp; 4542 uint32_t min_bw_6ghz_ap_lpi; 4543 uint32_t max_bw_6ghz_ap_lpi; 4544 uint32_t min_bw_6ghz_ap_vlp; 4545 uint32_t max_bw_6ghz_ap_vlp; 4546 uint32_t min_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX]; 4547 uint32_t max_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX]; 4548 uint32_t min_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX]; 4549 uint32_t max_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX]; 4550 uint32_t min_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX]; 4551 uint32_t max_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX]; 4552 uint32_t num_6ghz_reg_rules_ap_sp; 4553 uint32_t num_6ghz_reg_rules_ap_lpi; 4554 uint32_t num_6ghz_reg_rules_ap_vlp; 4555 uint32_t num_6ghz_reg_rules_client_sp[WMI_REG_CLIENT_MAX]; 4556 uint32_t num_6ghz_reg_rules_client_lpi[WMI_REG_CLIENT_MAX]; 4557 uint32_t num_6ghz_reg_rules_client_vlp[WMI_REG_CLIENT_MAX]; 4558 } __packed; 4559 4560 struct wmi_regulatory_ext_rule { 4561 uint32_t tlv_header; 4562 uint32_t freq_info; 4563 uint32_t bw_pwr_info; 4564 uint32_t flag_info; 4565 uint32_t psd_power_info; 4566 } __packed; 4567 4568 struct wmi_vdev_delete_resp_event { 4569 uint32_t vdev_id; 4570 } __packed; 4571 4572 struct wmi_peer_delete_resp_event { 4573 uint32_t vdev_id; 4574 struct wmi_mac_addr peer_macaddr; 4575 } __packed; 4576 4577 struct wmi_bcn_tx_status_event { 4578 uint32_t vdev_id; 4579 uint32_t tx_status; 4580 } __packed; 4581 4582 struct wmi_vdev_stopped_event { 4583 uint32_t vdev_id; 4584 } __packed; 4585 4586 struct wmi_pdev_bss_chan_info_event { 4587 uint32_t freq; /* Units in MHz */ 4588 uint32_t noise_floor; /* units are dBm */ 4589 /* rx clear - how often the channel was unused */ 4590 uint32_t rx_clear_count_low; 4591 uint32_t rx_clear_count_high; 4592 /* cycle count - elapsed time during measured period, in clock ticks */ 4593 uint32_t cycle_count_low; 4594 uint32_t cycle_count_high; 4595 /* tx cycle count - elapsed time spent in tx, in clock ticks */ 4596 uint32_t tx_cycle_count_low; 4597 uint32_t tx_cycle_count_high; 4598 /* rx cycle count - elapsed time spent in rx, in clock ticks */ 4599 uint32_t rx_cycle_count_low; 4600 uint32_t rx_cycle_count_high; 4601 /*rx_cycle cnt for my bss in 64bits format */ 4602 uint32_t rx_bss_cycle_count_low; 4603 uint32_t rx_bss_cycle_count_high; 4604 uint32_t pdev_id; 4605 } __packed; 4606 4607 #define WMI_VDEV_INSTALL_KEY_COMPL_STATUS_SUCCESS 0 4608 4609 struct wmi_vdev_install_key_compl_event { 4610 uint32_t vdev_id; 4611 struct wmi_mac_addr peer_macaddr; 4612 uint32_t key_idx; 4613 uint32_t key_flags; 4614 uint32_t status; 4615 } __packed; 4616 4617 struct wmi_vdev_install_key_complete_arg { 4618 uint32_t vdev_id; 4619 const uint8_t *macaddr; 4620 uint32_t key_idx; 4621 uint32_t key_flags; 4622 uint32_t status; 4623 }; 4624 4625 struct wmi_peer_assoc_conf_event { 4626 uint32_t vdev_id; 4627 struct wmi_mac_addr peer_macaddr; 4628 } __packed; 4629 4630 struct wmi_peer_assoc_conf_arg { 4631 uint32_t vdev_id; 4632 const uint8_t *macaddr; 4633 }; 4634 4635 struct wmi_fils_discovery_event { 4636 uint32_t vdev_id; 4637 uint32_t fils_tt; 4638 uint32_t tbtt; 4639 } __packed; 4640 4641 struct wmi_probe_resp_tx_status_event { 4642 uint32_t vdev_id; 4643 uint32_t tx_status; 4644 } __packed; 4645 4646 /* 4647 * PDEV statistics 4648 */ 4649 struct wmi_pdev_stats_base { 4650 int32_t chan_nf; 4651 uint32_t tx_frame_count; /* Cycles spent transmitting frames */ 4652 uint32_t rx_frame_count; /* Cycles spent receiving frames */ 4653 uint32_t rx_clear_count; /* Total channel busy time, evidently */ 4654 uint32_t cycle_count; /* Total on-channel time */ 4655 uint32_t phy_err_count; 4656 uint32_t chan_tx_pwr; 4657 } __packed; 4658 4659 struct wmi_pdev_stats_extra { 4660 uint32_t ack_rx_bad; 4661 uint32_t rts_bad; 4662 uint32_t rts_good; 4663 uint32_t fcs_bad; 4664 uint32_t no_beacons; 4665 uint32_t mib_int_count; 4666 } __packed; 4667 4668 struct wmi_pdev_stats_tx { 4669 /* Num HTT cookies queued to dispatch list */ 4670 int32_t comp_queued; 4671 4672 /* Num HTT cookies dispatched */ 4673 int32_t comp_delivered; 4674 4675 /* Num MSDU queued to WAL */ 4676 int32_t msdu_enqued; 4677 4678 /* Num MPDU queue to WAL */ 4679 int32_t mpdu_enqued; 4680 4681 /* Num MSDUs dropped by WMM limit */ 4682 int32_t wmm_drop; 4683 4684 /* Num Local frames queued */ 4685 int32_t local_enqued; 4686 4687 /* Num Local frames done */ 4688 int32_t local_freed; 4689 4690 /* Num queued to HW */ 4691 int32_t hw_queued; 4692 4693 /* Num PPDU reaped from HW */ 4694 int32_t hw_reaped; 4695 4696 /* Num underruns */ 4697 int32_t underrun; 4698 4699 /* Num hw paused */ 4700 uint32_t hw_paused; 4701 4702 /* Num PPDUs cleaned up in TX abort */ 4703 int32_t tx_abort; 4704 4705 /* Num MPDUs requeued by SW */ 4706 int32_t mpdus_requeued; 4707 4708 /* excessive retries */ 4709 uint32_t tx_ko; 4710 4711 uint32_t tx_xretry; 4712 4713 /* data hw rate code */ 4714 uint32_t data_rc; 4715 4716 /* Scheduler self triggers */ 4717 uint32_t self_triggers; 4718 4719 /* frames dropped due to excessive sw retries */ 4720 uint32_t sw_retry_failure; 4721 4722 /* illegal rate phy errors */ 4723 uint32_t illgl_rate_phy_err; 4724 4725 /* wal pdev continuous xretry */ 4726 uint32_t pdev_cont_xretry; 4727 4728 /* wal pdev tx timeouts */ 4729 uint32_t pdev_tx_timeout; 4730 4731 /* wal pdev resets */ 4732 uint32_t pdev_resets; 4733 4734 /* frames dropped due to non-availability of stateless TIDs */ 4735 uint32_t stateless_tid_alloc_failure; 4736 4737 /* PhY/BB underrun */ 4738 uint32_t phy_underrun; 4739 4740 /* MPDU is more than txop limit */ 4741 uint32_t txop_ovf; 4742 4743 /* Num sequences posted */ 4744 uint32_t seq_posted; 4745 4746 /* Num sequences failed in queueing */ 4747 uint32_t seq_failed_queueing; 4748 4749 /* Num sequences completed */ 4750 uint32_t seq_completed; 4751 4752 /* Num sequences restarted */ 4753 uint32_t seq_restarted; 4754 4755 /* Num of MU sequences posted */ 4756 uint32_t mu_seq_posted; 4757 4758 /* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT 4759 * (Reset,channel change) 4760 */ 4761 int32_t mpdus_sw_flush; 4762 4763 /* Num MPDUs filtered by HW, all filter condition (TTL expired) */ 4764 int32_t mpdus_hw_filter; 4765 4766 /* Num MPDUs truncated by PDG (TXOP, TBTT, 4767 * PPDU_duration based on rate, dyn_bw) 4768 */ 4769 int32_t mpdus_truncated; 4770 4771 /* Num MPDUs that was tried but didn't receive ACK or BA */ 4772 int32_t mpdus_ack_failed; 4773 4774 /* Num MPDUs that was dropped du to expiry. */ 4775 int32_t mpdus_expired; 4776 } __packed; 4777 4778 struct wmi_pdev_stats_rx { 4779 /* Cnts any change in ring routing mid-ppdu */ 4780 int32_t mid_ppdu_route_change; 4781 4782 /* Total number of statuses processed */ 4783 int32_t status_rcvd; 4784 4785 /* Extra frags on rings 0-3 */ 4786 int32_t r0_frags; 4787 int32_t r1_frags; 4788 int32_t r2_frags; 4789 int32_t r3_frags; 4790 4791 /* MSDUs / MPDUs delivered to HTT */ 4792 int32_t htt_msdus; 4793 int32_t htt_mpdus; 4794 4795 /* MSDUs / MPDUs delivered to local stack */ 4796 int32_t loc_msdus; 4797 int32_t loc_mpdus; 4798 4799 /* AMSDUs that have more MSDUs than the status ring size */ 4800 int32_t oversize_amsdu; 4801 4802 /* Number of PHY errors */ 4803 int32_t phy_errs; 4804 4805 /* Number of PHY errors drops */ 4806 int32_t phy_err_drop; 4807 4808 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 4809 int32_t mpdu_errs; 4810 4811 /* Num overflow errors */ 4812 int32_t rx_ovfl_errs; 4813 } __packed; 4814 4815 struct wmi_pdev_stats { 4816 struct wmi_pdev_stats_base base; 4817 struct wmi_pdev_stats_tx tx; 4818 struct wmi_pdev_stats_rx rx; 4819 } __packed; 4820 4821 #define WLAN_MAX_AC 4 4822 #define MAX_TX_RATE_VALUES 10 4823 #define MAX_TX_RATE_VALUES 10 4824 4825 struct wmi_vdev_stats { 4826 uint32_t vdev_id; 4827 uint32_t beacon_snr; 4828 uint32_t data_snr; 4829 uint32_t num_tx_frames[WLAN_MAX_AC]; 4830 uint32_t num_rx_frames; 4831 uint32_t num_tx_frames_retries[WLAN_MAX_AC]; 4832 uint32_t num_tx_frames_failures[WLAN_MAX_AC]; 4833 uint32_t num_rts_fail; 4834 uint32_t num_rts_success; 4835 uint32_t num_rx_err; 4836 uint32_t num_rx_discard; 4837 uint32_t num_tx_not_acked; 4838 uint32_t tx_rate_history[MAX_TX_RATE_VALUES]; 4839 uint32_t beacon_rssi_history[MAX_TX_RATE_VALUES]; 4840 } __packed; 4841 4842 struct wmi_bcn_stats { 4843 uint32_t vdev_id; 4844 uint32_t tx_bcn_succ_cnt; 4845 uint32_t tx_bcn_outage_cnt; 4846 } __packed; 4847 4848 struct wmi_stats_event { 4849 uint32_t stats_id; 4850 uint32_t num_pdev_stats; 4851 uint32_t num_vdev_stats; 4852 uint32_t num_peer_stats; 4853 uint32_t num_bcnflt_stats; 4854 uint32_t num_chan_stats; 4855 uint32_t num_mib_stats; 4856 uint32_t pdev_id; 4857 uint32_t num_bcn_stats; 4858 uint32_t num_peer_extd_stats; 4859 uint32_t num_peer_extd2_stats; 4860 } __packed; 4861 4862 struct wmi_rssi_stats { 4863 uint32_t vdev_id; 4864 uint32_t rssi_avg_beacon[WMI_MAX_CHAINS]; 4865 uint32_t rssi_avg_data[WMI_MAX_CHAINS]; 4866 struct wmi_mac_addr peer_macaddr; 4867 } __packed; 4868 4869 struct wmi_per_chain_rssi_stats { 4870 uint32_t num_per_chain_rssi_stats; 4871 } __packed; 4872 4873 struct wmi_pdev_ctl_failsafe_chk_event { 4874 uint32_t pdev_id; 4875 uint32_t ctl_failsafe_status; 4876 } __packed; 4877 4878 struct wmi_pdev_csa_switch_ev { 4879 uint32_t pdev_id; 4880 uint32_t current_switch_count; 4881 uint32_t num_vdevs; 4882 } __packed; 4883 4884 struct wmi_pdev_radar_ev { 4885 uint32_t pdev_id; 4886 uint32_t detection_mode; 4887 uint32_t chan_freq; 4888 uint32_t chan_width; 4889 uint32_t detector_id; 4890 uint32_t segment_id; 4891 uint32_t timestamp; 4892 uint32_t is_chirp; 4893 int32_t freq_offset; 4894 int32_t sidx; 4895 } __packed; 4896 4897 struct wmi_pdev_temperature_event { 4898 /* temperature value in Celsius degree */ 4899 int32_t temp; 4900 uint32_t pdev_id; 4901 } __packed; 4902 4903 #define WMI_RX_STATUS_OK 0x00 4904 #define WMI_RX_STATUS_ERR_CRC 0x01 4905 #define WMI_RX_STATUS_ERR_DECRYPT 0x08 4906 #define WMI_RX_STATUS_ERR_MIC 0x10 4907 #define WMI_RX_STATUS_ERR_KEY_CACHE_MISS 0x20 4908 4909 #define WLAN_MGMT_TXRX_HOST_MAX_ANTENNA 4 4910 4911 struct mgmt_rx_event_params { 4912 uint32_t chan_freq; 4913 uint32_t channel; 4914 uint32_t snr; 4915 uint8_t rssi_ctl[WLAN_MGMT_TXRX_HOST_MAX_ANTENNA]; 4916 uint32_t rate; 4917 enum wmi_phy_mode phy_mode; 4918 uint32_t buf_len; 4919 int status; 4920 uint32_t flags; 4921 int rssi; 4922 uint32_t tsf_delta; 4923 uint8_t pdev_id; 4924 }; 4925 4926 #define ATH_MAX_ANTENNA 4 4927 4928 struct wmi_mgmt_rx_hdr { 4929 uint32_t channel; 4930 uint32_t snr; 4931 uint32_t rate; 4932 uint32_t phy_mode; 4933 uint32_t buf_len; 4934 uint32_t status; 4935 uint32_t rssi_ctl[ATH_MAX_ANTENNA]; 4936 uint32_t flags; 4937 int rssi; 4938 uint32_t tsf_delta; 4939 uint32_t rx_tsf_l32; 4940 uint32_t rx_tsf_u32; 4941 uint32_t pdev_id; 4942 uint32_t chan_freq; 4943 } __packed; 4944 4945 #define MAX_ANTENNA_EIGHT 8 4946 4947 struct wmi_rssi_ctl_ext { 4948 uint32_t tlv_header; 4949 uint32_t rssi_ctl_ext[MAX_ANTENNA_EIGHT - ATH_MAX_ANTENNA]; 4950 }; 4951 4952 struct wmi_mgmt_tx_compl_event { 4953 uint32_t desc_id; 4954 uint32_t status; 4955 uint32_t pdev_id; 4956 uint32_t ppdu_id; 4957 uint32_t ack_rssi; 4958 } __packed; 4959 4960 struct wmi_scan_event { 4961 uint32_t event_type; /* %WMI_SCAN_EVENT_ */ 4962 uint32_t reason; /* %WMI_SCAN_REASON_ */ 4963 uint32_t channel_freq; /* only valid for WMI_SCAN_EVENT_FOREIGN_CHANNEL */ 4964 uint32_t scan_req_id; 4965 uint32_t scan_id; 4966 uint32_t vdev_id; 4967 /* TSF Timestamp when the scan event (%WMI_SCAN_EVENT_) is completed 4968 * In case of AP it is TSF of the AP vdev 4969 * In case of STA connected state, this is the TSF of the AP 4970 * In case of STA not connected, it will be the free running HW timer 4971 */ 4972 uint32_t tsf_timestamp; 4973 } __packed; 4974 4975 struct wmi_peer_sta_kickout_arg { 4976 const uint8_t *mac_addr; 4977 }; 4978 4979 struct wmi_peer_sta_kickout_event { 4980 struct wmi_mac_addr peer_macaddr; 4981 } __packed; 4982 4983 enum wmi_roam_reason { 4984 WMI_ROAM_REASON_BETTER_AP = 1, 4985 WMI_ROAM_REASON_BEACON_MISS = 2, 4986 WMI_ROAM_REASON_LOW_RSSI = 3, 4987 WMI_ROAM_REASON_SUITABLE_AP_FOUND = 4, 4988 WMI_ROAM_REASON_HO_FAILED = 5, 4989 4990 /* keep last */ 4991 WMI_ROAM_REASON_MAX, 4992 }; 4993 4994 struct wmi_roam_event { 4995 uint32_t vdev_id; 4996 uint32_t reason; 4997 uint32_t rssi; 4998 } __packed; 4999 5000 #define WMI_CHAN_INFO_START_RESP 0 5001 #define WMI_CHAN_INFO_END_RESP 1 5002 5003 struct wmi_chan_info_event { 5004 uint32_t err_code; 5005 uint32_t freq; 5006 uint32_t cmd_flags; 5007 uint32_t noise_floor; 5008 uint32_t rx_clear_count; 5009 uint32_t cycle_count; 5010 uint32_t chan_tx_pwr_range; 5011 uint32_t chan_tx_pwr_tp; 5012 uint32_t rx_frame_count; 5013 uint32_t my_bss_rx_cycle_count; 5014 uint32_t rx_11b_mode_data_duration; 5015 uint32_t tx_frame_cnt; 5016 uint32_t mac_clk_mhz; 5017 uint32_t vdev_id; 5018 } __packed; 5019 5020 struct ath11k_targ_cap { 5021 uint32_t phy_capability; 5022 uint32_t max_frag_entry; 5023 uint32_t num_rf_chains; 5024 uint32_t ht_cap_info; 5025 uint32_t vht_cap_info; 5026 uint32_t vht_supp_mcs; 5027 uint32_t hw_min_tx_power; 5028 uint32_t hw_max_tx_power; 5029 uint32_t sys_cap_info; 5030 uint32_t min_pkt_size_enable; 5031 uint32_t max_bcn_ie_size; 5032 uint32_t max_num_scan_channels; 5033 uint32_t max_supported_macs; 5034 uint32_t wmi_fw_sub_feat_caps; 5035 uint32_t txrx_chainmask; 5036 uint32_t default_dbs_hw_mode_index; 5037 uint32_t num_msdu_desc; 5038 }; 5039 5040 enum wmi_vdev_type { 5041 WMI_VDEV_TYPE_AP = 1, 5042 WMI_VDEV_TYPE_STA = 2, 5043 WMI_VDEV_TYPE_IBSS = 3, 5044 WMI_VDEV_TYPE_MONITOR = 4, 5045 }; 5046 5047 enum wmi_vdev_subtype { 5048 WMI_VDEV_SUBTYPE_NONE, 5049 WMI_VDEV_SUBTYPE_P2P_DEVICE, 5050 WMI_VDEV_SUBTYPE_P2P_CLIENT, 5051 WMI_VDEV_SUBTYPE_P2P_GO, 5052 WMI_VDEV_SUBTYPE_PROXY_STA, 5053 WMI_VDEV_SUBTYPE_MESH_NON_11S, 5054 WMI_VDEV_SUBTYPE_MESH_11S, 5055 }; 5056 5057 enum wmi_sta_powersave_param { 5058 WMI_STA_PS_PARAM_RX_WAKE_POLICY = 0, 5059 WMI_STA_PS_PARAM_TX_WAKE_THRESHOLD = 1, 5060 WMI_STA_PS_PARAM_PSPOLL_COUNT = 2, 5061 WMI_STA_PS_PARAM_INACTIVITY_TIME = 3, 5062 WMI_STA_PS_PARAM_UAPSD = 4, 5063 }; 5064 5065 #define WMI_UAPSD_AC_TYPE_DELI 0 5066 #define WMI_UAPSD_AC_TYPE_TRIG 1 5067 5068 #define WMI_UAPSD_AC_BIT_MASK(ac, type) \ 5069 ((type == WMI_UAPSD_AC_TYPE_DELI) ? \ 5070 (1 << (ac << 1)) : (1 << ((ac << 1) + 1))) 5071 5072 enum wmi_sta_ps_param_uapsd { 5073 WMI_STA_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0), 5074 WMI_STA_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1), 5075 WMI_STA_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2), 5076 WMI_STA_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3), 5077 WMI_STA_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4), 5078 WMI_STA_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5), 5079 WMI_STA_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6), 5080 WMI_STA_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7), 5081 }; 5082 5083 #define WMI_STA_UAPSD_MAX_INTERVAL_MSEC UINT_MAX 5084 5085 struct wmi_sta_uapsd_auto_trig_param { 5086 uint32_t wmm_ac; 5087 uint32_t user_priority; 5088 uint32_t service_interval; 5089 uint32_t suspend_interval; 5090 uint32_t delay_interval; 5091 }; 5092 5093 struct wmi_sta_uapsd_auto_trig_cmd_fixed_param { 5094 uint32_t vdev_id; 5095 struct wmi_mac_addr peer_macaddr; 5096 uint32_t num_ac; 5097 }; 5098 5099 struct wmi_sta_uapsd_auto_trig_arg { 5100 uint32_t wmm_ac; 5101 uint32_t user_priority; 5102 uint32_t service_interval; 5103 uint32_t suspend_interval; 5104 uint32_t delay_interval; 5105 }; 5106 5107 enum wmi_sta_ps_param_tx_wake_threshold { 5108 WMI_STA_PS_TX_WAKE_THRESHOLD_NEVER = 0, 5109 WMI_STA_PS_TX_WAKE_THRESHOLD_ALWAYS = 1, 5110 5111 /* Values greater than one indicate that many TX attempts per beacon 5112 * interval before the STA will wake up 5113 */ 5114 }; 5115 5116 /* The maximum number of PS-Poll frames the FW will send in response to 5117 * traffic advertised in TIM before waking up (by sending a null frame with PS 5118 * = 0). Value 0 has a special meaning: there is no maximum count and the FW 5119 * will send as many PS-Poll as are necessary to retrieve buffered BU. This 5120 * parameter is used when the RX wake policy is 5121 * WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD and ignored when the RX wake 5122 * policy is WMI_STA_PS_RX_WAKE_POLICY_WAKE. 5123 */ 5124 enum wmi_sta_ps_param_pspoll_count { 5125 WMI_STA_PS_PSPOLL_COUNT_NO_MAX = 0, 5126 /* Values greater than 0 indicate the maximum number of PS-Poll frames 5127 * FW will send before waking up. 5128 */ 5129 }; 5130 5131 /* U-APSD configuration of peer station from (re)assoc request and TSPECs */ 5132 enum wmi_ap_ps_param_uapsd { 5133 WMI_AP_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0), 5134 WMI_AP_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1), 5135 WMI_AP_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2), 5136 WMI_AP_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3), 5137 WMI_AP_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4), 5138 WMI_AP_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5), 5139 WMI_AP_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6), 5140 WMI_AP_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7), 5141 }; 5142 5143 /* U-APSD maximum service period of peer station */ 5144 enum wmi_ap_ps_peer_param_max_sp { 5145 WMI_AP_PS_PEER_PARAM_MAX_SP_UNLIMITED = 0, 5146 WMI_AP_PS_PEER_PARAM_MAX_SP_2 = 1, 5147 WMI_AP_PS_PEER_PARAM_MAX_SP_4 = 2, 5148 WMI_AP_PS_PEER_PARAM_MAX_SP_6 = 3, 5149 MAX_WMI_AP_PS_PEER_PARAM_MAX_SP, 5150 }; 5151 5152 enum wmi_ap_ps_peer_param { 5153 /** Set uapsd configuration for a given peer. 5154 * 5155 * This include the delivery and trigger enabled state for each AC. 5156 * The host MLME needs to set this based on AP capability and stations 5157 * request Set in the association request received from the station. 5158 * 5159 * Lower 8 bits of the value specify the UAPSD configuration. 5160 * 5161 * (see enum wmi_ap_ps_param_uapsd) 5162 * The default value is 0. 5163 */ 5164 WMI_AP_PS_PEER_PARAM_UAPSD = 0, 5165 5166 /** 5167 * Set the service period for a UAPSD capable station 5168 * 5169 * The service period from wme ie in the (re)assoc request frame. 5170 * 5171 * (see enum wmi_ap_ps_peer_param_max_sp) 5172 */ 5173 WMI_AP_PS_PEER_PARAM_MAX_SP = 1, 5174 5175 /** Time in seconds for aging out buffered frames 5176 * for STA in power save 5177 */ 5178 WMI_AP_PS_PEER_PARAM_AGEOUT_TIME = 2, 5179 5180 /** Specify frame types that are considered SIFS 5181 * RESP trigger frame 5182 */ 5183 WMI_AP_PS_PEER_PARAM_SIFS_RESP_FRMTYPE = 3, 5184 5185 /** Specifies the trigger state of TID. 5186 * Valid only for UAPSD frame type 5187 */ 5188 WMI_AP_PS_PEER_PARAM_SIFS_RESP_UAPSD = 4, 5189 5190 /* Specifies the WNM sleep state of a STA */ 5191 WMI_AP_PS_PEER_PARAM_WNM_SLEEP = 5, 5192 }; 5193 5194 #define DISABLE_SIFS_RESPONSE_TRIGGER 0 5195 5196 #define WMI_MAX_KEY_INDEX 3 5197 #define WMI_MAX_KEY_LEN 32 5198 5199 #define WMI_KEY_PAIRWISE 0x00 5200 #define WMI_KEY_GROUP 0x01 5201 5202 #define WMI_CIPHER_NONE 0x0 /* clear key */ 5203 #define WMI_CIPHER_WEP 0x1 5204 #define WMI_CIPHER_TKIP 0x2 5205 #define WMI_CIPHER_AES_OCB 0x3 5206 #define WMI_CIPHER_AES_CCM 0x4 5207 #define WMI_CIPHER_WAPI 0x5 5208 #define WMI_CIPHER_CKIP 0x6 5209 #define WMI_CIPHER_AES_CMAC 0x7 5210 #define WMI_CIPHER_ANY 0x8 5211 #define WMI_CIPHER_AES_GCM 0x9 5212 #define WMI_CIPHER_AES_GMAC 0xa 5213 5214 /* Value to disable fixed rate setting */ 5215 #define WMI_FIXED_RATE_NONE (0xffff) 5216 5217 #define ATH11K_RC_VERSION_OFFSET 28 5218 #define ATH11K_RC_PREAMBLE_OFFSET 8 5219 #define ATH11K_RC_NSS_OFFSET 5 5220 5221 #define ATH11K_HW_RATE_CODE(rate, nss, preamble) \ 5222 ((1 << ATH11K_RC_VERSION_OFFSET) | \ 5223 ((nss) << ATH11K_RC_NSS_OFFSET) | \ 5224 ((preamble) << ATH11K_RC_PREAMBLE_OFFSET) | \ 5225 (rate)) 5226 5227 /* Preamble types to be used with VDEV fixed rate configuration */ 5228 enum wmi_rate_preamble { 5229 WMI_RATE_PREAMBLE_OFDM, 5230 WMI_RATE_PREAMBLE_CCK, 5231 WMI_RATE_PREAMBLE_HT, 5232 WMI_RATE_PREAMBLE_VHT, 5233 WMI_RATE_PREAMBLE_HE, 5234 }; 5235 5236 /** 5237 * enum wmi_rtscts_prot_mode - Enable/Disable RTS/CTS and CTS2Self Protection. 5238 * @WMI_RTS_CTS_DISABLED: RTS/CTS protection is disabled. 5239 * @WMI_USE_RTS_CTS: RTS/CTS Enabled. 5240 * @WMI_USE_CTS2SELF: CTS to self protection Enabled. 5241 */ 5242 enum wmi_rtscts_prot_mode { 5243 WMI_RTS_CTS_DISABLED = 0, 5244 WMI_USE_RTS_CTS = 1, 5245 WMI_USE_CTS2SELF = 2, 5246 }; 5247 5248 /** 5249 * enum wmi_rtscts_profile - Selection of RTS CTS profile along with enabling 5250 * protection mode. 5251 * @WMI_RTSCTS_FOR_NO_RATESERIES: Neither of rate-series should use RTS-CTS 5252 * @WMI_RTSCTS_FOR_SECOND_RATESERIES: Only second rate-series will use RTS-CTS 5253 * @WMI_RTSCTS_ACROSS_SW_RETRIES: Only the second rate-series will use RTS-CTS, 5254 * but if there's a sw retry, both the rate 5255 * series will use RTS-CTS. 5256 * @WMI_RTSCTS_ERP: RTS/CTS used for ERP protection for every PPDU. 5257 * @WMI_RTSCTS_FOR_ALL_RATESERIES: Enable RTS-CTS for all rate series. 5258 */ 5259 enum wmi_rtscts_profile { 5260 WMI_RTSCTS_FOR_NO_RATESERIES = 0, 5261 WMI_RTSCTS_FOR_SECOND_RATESERIES = 1, 5262 WMI_RTSCTS_ACROSS_SW_RETRIES = 2, 5263 WMI_RTSCTS_ERP = 3, 5264 WMI_RTSCTS_FOR_ALL_RATESERIES = 4, 5265 }; 5266 5267 struct ath11k_hal_reg_cap { 5268 uint32_t eeprom_rd; 5269 uint32_t eeprom_rd_ext; 5270 uint32_t regcap1; 5271 uint32_t regcap2; 5272 uint32_t wireless_modes; 5273 uint32_t low_2ghz_chan; 5274 uint32_t high_2ghz_chan; 5275 uint32_t low_5ghz_chan; 5276 uint32_t high_5ghz_chan; 5277 }; 5278 5279 struct ath11k_mem_chunk { 5280 void *vaddr; 5281 bus_addr_t paddr; 5282 uint32_t len; 5283 uint32_t req_id; 5284 }; 5285 5286 enum wmi_sta_ps_param_rx_wake_policy { 5287 WMI_STA_PS_RX_WAKE_POLICY_WAKE = 0, 5288 WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD = 1, 5289 }; 5290 5291 /* Do not change existing values! Used by ath11k_frame_mode parameter 5292 * module parameter. 5293 */ 5294 enum ath11k_hw_txrx_mode { 5295 ATH11K_HW_TXRX_RAW = 0, 5296 ATH11K_HW_TXRX_NATIVE_WIFI = 1, 5297 ATH11K_HW_TXRX_ETHERNET = 2, 5298 }; 5299 5300 struct wmi_wmm_params { 5301 uint32_t tlv_header; 5302 uint32_t cwmin; 5303 uint32_t cwmax; 5304 uint32_t aifs; 5305 uint32_t txoplimit; 5306 uint32_t acm; 5307 uint32_t no_ack; 5308 } __packed; 5309 5310 struct wmi_wmm_params_arg { 5311 uint8_t acm; 5312 uint8_t aifs; 5313 uint16_t cwmin; 5314 uint16_t cwmax; 5315 uint16_t txop; 5316 uint8_t no_ack; 5317 }; 5318 5319 struct wmi_vdev_set_wmm_params_cmd { 5320 uint32_t tlv_header; 5321 uint32_t vdev_id; 5322 struct wmi_wmm_params wmm_params[4]; 5323 uint32_t wmm_param_type; 5324 } __packed; 5325 5326 struct wmi_wmm_params_all_arg { 5327 struct wmi_wmm_params_arg ac_be; 5328 struct wmi_wmm_params_arg ac_bk; 5329 struct wmi_wmm_params_arg ac_vi; 5330 struct wmi_wmm_params_arg ac_vo; 5331 }; 5332 5333 #define ATH11K_TWT_DEF_STA_CONG_TIMER_MS 5000 5334 #define ATH11K_TWT_DEF_DEFAULT_SLOT_SIZE 10 5335 #define ATH11K_TWT_DEF_CONGESTION_THRESH_SETUP 50 5336 #define ATH11K_TWT_DEF_CONGESTION_THRESH_TEARDOWN 20 5337 #define ATH11K_TWT_DEF_CONGESTION_THRESH_CRITICAL 100 5338 #define ATH11K_TWT_DEF_INTERFERENCE_THRESH_TEARDOWN 80 5339 #define ATH11K_TWT_DEF_INTERFERENCE_THRESH_SETUP 50 5340 #define ATH11K_TWT_DEF_MIN_NO_STA_SETUP 10 5341 #define ATH11K_TWT_DEF_MIN_NO_STA_TEARDOWN 2 5342 #define ATH11K_TWT_DEF_NO_OF_BCAST_MCAST_SLOTS 2 5343 #define ATH11K_TWT_DEF_MIN_NO_TWT_SLOTS 2 5344 #define ATH11K_TWT_DEF_MAX_NO_STA_TWT 500 5345 #define ATH11K_TWT_DEF_MODE_CHECK_INTERVAL 10000 5346 #define ATH11K_TWT_DEF_ADD_STA_SLOT_INTERVAL 1000 5347 #define ATH11K_TWT_DEF_REMOVE_STA_SLOT_INTERVAL 5000 5348 5349 struct wmi_twt_enable_params { 5350 uint32_t sta_cong_timer_ms; 5351 uint32_t mbss_support; 5352 uint32_t default_slot_size; 5353 uint32_t congestion_thresh_setup; 5354 uint32_t congestion_thresh_teardown; 5355 uint32_t congestion_thresh_critical; 5356 uint32_t interference_thresh_teardown; 5357 uint32_t interference_thresh_setup; 5358 uint32_t min_no_sta_setup; 5359 uint32_t min_no_sta_teardown; 5360 uint32_t no_of_bcast_mcast_slots; 5361 uint32_t min_no_twt_slots; 5362 uint32_t max_no_sta_twt; 5363 uint32_t mode_check_interval; 5364 uint32_t add_sta_slot_interval; 5365 uint32_t remove_sta_slot_interval; 5366 }; 5367 5368 struct wmi_twt_enable_params_cmd { 5369 uint32_t tlv_header; 5370 uint32_t pdev_id; 5371 uint32_t sta_cong_timer_ms; 5372 uint32_t mbss_support; 5373 uint32_t default_slot_size; 5374 uint32_t congestion_thresh_setup; 5375 uint32_t congestion_thresh_teardown; 5376 uint32_t congestion_thresh_critical; 5377 uint32_t interference_thresh_teardown; 5378 uint32_t interference_thresh_setup; 5379 uint32_t min_no_sta_setup; 5380 uint32_t min_no_sta_teardown; 5381 uint32_t no_of_bcast_mcast_slots; 5382 uint32_t min_no_twt_slots; 5383 uint32_t max_no_sta_twt; 5384 uint32_t mode_check_interval; 5385 uint32_t add_sta_slot_interval; 5386 uint32_t remove_sta_slot_interval; 5387 } __packed; 5388 5389 struct wmi_twt_disable_params_cmd { 5390 uint32_t tlv_header; 5391 uint32_t pdev_id; 5392 } __packed; 5393 5394 enum WMI_HOST_TWT_COMMAND { 5395 WMI_HOST_TWT_COMMAND_REQUEST_TWT = 0, 5396 WMI_HOST_TWT_COMMAND_SUGGEST_TWT, 5397 WMI_HOST_TWT_COMMAND_DEMAND_TWT, 5398 WMI_HOST_TWT_COMMAND_TWT_GROUPING, 5399 WMI_HOST_TWT_COMMAND_ACCEPT_TWT, 5400 WMI_HOST_TWT_COMMAND_ALTERNATE_TWT, 5401 WMI_HOST_TWT_COMMAND_DICTATE_TWT, 5402 WMI_HOST_TWT_COMMAND_REJECT_TWT, 5403 }; 5404 5405 #define WMI_TWT_ADD_DIALOG_FLAG_BCAST BIT(8) 5406 #define WMI_TWT_ADD_DIALOG_FLAG_TRIGGER BIT(9) 5407 #define WMI_TWT_ADD_DIALOG_FLAG_FLOW_TYPE BIT(10) 5408 #define WMI_TWT_ADD_DIALOG_FLAG_PROTECTION BIT(11) 5409 5410 struct wmi_twt_add_dialog_params_cmd { 5411 uint32_t tlv_header; 5412 uint32_t vdev_id; 5413 struct wmi_mac_addr peer_macaddr; 5414 uint32_t dialog_id; 5415 uint32_t wake_intvl_us; 5416 uint32_t wake_intvl_mantis; 5417 uint32_t wake_dura_us; 5418 uint32_t sp_offset_us; 5419 uint32_t flags; 5420 } __packed; 5421 5422 struct wmi_twt_add_dialog_params { 5423 uint32_t vdev_id; 5424 uint8_t peer_macaddr[IEEE80211_ADDR_LEN]; 5425 uint32_t dialog_id; 5426 uint32_t wake_intvl_us; 5427 uint32_t wake_intvl_mantis; 5428 uint32_t wake_dura_us; 5429 uint32_t sp_offset_us; 5430 uint8_t twt_cmd; 5431 uint8_t flag_bcast; 5432 uint8_t flag_trigger; 5433 uint8_t flag_flow_type; 5434 uint8_t flag_protection; 5435 } __packed; 5436 5437 enum wmi_twt_add_dialog_status { 5438 WMI_ADD_TWT_STATUS_OK, 5439 WMI_ADD_TWT_STATUS_TWT_NOT_ENABLED, 5440 WMI_ADD_TWT_STATUS_USED_DIALOG_ID, 5441 WMI_ADD_TWT_STATUS_INVALID_PARAM, 5442 WMI_ADD_TWT_STATUS_NOT_READY, 5443 WMI_ADD_TWT_STATUS_NO_RESOURCE, 5444 WMI_ADD_TWT_STATUS_NO_ACK, 5445 WMI_ADD_TWT_STATUS_NO_RESPONSE, 5446 WMI_ADD_TWT_STATUS_DENIED, 5447 WMI_ADD_TWT_STATUS_UNKNOWN_ERROR, 5448 }; 5449 5450 struct wmi_twt_add_dialog_event { 5451 uint32_t vdev_id; 5452 struct wmi_mac_addr peer_macaddr; 5453 uint32_t dialog_id; 5454 uint32_t status; 5455 } __packed; 5456 5457 struct wmi_twt_del_dialog_params { 5458 uint32_t vdev_id; 5459 uint8_t peer_macaddr[IEEE80211_ADDR_LEN]; 5460 uint32_t dialog_id; 5461 } __packed; 5462 5463 struct wmi_twt_del_dialog_params_cmd { 5464 uint32_t tlv_header; 5465 uint32_t vdev_id; 5466 struct wmi_mac_addr peer_macaddr; 5467 uint32_t dialog_id; 5468 } __packed; 5469 5470 struct wmi_twt_pause_dialog_params { 5471 uint32_t vdev_id; 5472 uint8_t peer_macaddr[IEEE80211_ADDR_LEN]; 5473 uint32_t dialog_id; 5474 } __packed; 5475 5476 struct wmi_twt_pause_dialog_params_cmd { 5477 uint32_t tlv_header; 5478 uint32_t vdev_id; 5479 struct wmi_mac_addr peer_macaddr; 5480 uint32_t dialog_id; 5481 } __packed; 5482 5483 struct wmi_twt_resume_dialog_params { 5484 uint32_t vdev_id; 5485 uint8_t peer_macaddr[IEEE80211_ADDR_LEN]; 5486 uint32_t dialog_id; 5487 uint32_t sp_offset_us; 5488 uint32_t next_twt_size; 5489 } __packed; 5490 5491 struct wmi_twt_resume_dialog_params_cmd { 5492 uint32_t tlv_header; 5493 uint32_t vdev_id; 5494 struct wmi_mac_addr peer_macaddr; 5495 uint32_t dialog_id; 5496 uint32_t sp_offset_us; 5497 uint32_t next_twt_size; 5498 } __packed; 5499 5500 struct wmi_obss_spatial_reuse_params_cmd { 5501 uint32_t tlv_header; 5502 uint32_t pdev_id; 5503 uint32_t enable; 5504 int32_t obss_min; 5505 int32_t obss_max; 5506 uint32_t vdev_id; 5507 } __packed; 5508 5509 struct wmi_pdev_obss_pd_bitmap_cmd { 5510 uint32_t tlv_header; 5511 uint32_t pdev_id; 5512 uint32_t bitmap[2]; 5513 } __packed; 5514 5515 #define ATH11K_BSS_COLOR_COLLISION_SCAN_PERIOD_MS 200 5516 #define ATH11K_OBSS_COLOR_COLLISION_DETECTION_DISABLE 0 5517 #define ATH11K_OBSS_COLOR_COLLISION_DETECTION 1 5518 5519 #define ATH11K_BSS_COLOR_COLLISION_DETECTION_STA_PERIOD_MS 10000 5520 #define ATH11K_BSS_COLOR_COLLISION_DETECTION_AP_PERIOD_MS 5000 5521 5522 enum wmi_bss_color_collision { 5523 WMI_BSS_COLOR_COLLISION_DISABLE = 0, 5524 WMI_BSS_COLOR_COLLISION_DETECTION, 5525 WMI_BSS_COLOR_FREE_SLOT_TIMER_EXPIRY, 5526 WMI_BSS_COLOR_FREE_SLOT_AVAILABLE, 5527 }; 5528 5529 struct wmi_obss_color_collision_cfg_params_cmd { 5530 uint32_t tlv_header; 5531 uint32_t vdev_id; 5532 uint32_t flags; 5533 uint32_t evt_type; 5534 uint32_t current_bss_color; 5535 uint32_t detection_period_ms; 5536 uint32_t scan_period_ms; 5537 uint32_t free_slot_expiry_time_ms; 5538 } __packed; 5539 5540 struct wmi_bss_color_change_enable_params_cmd { 5541 uint32_t tlv_header; 5542 uint32_t vdev_id; 5543 uint32_t enable; 5544 } __packed; 5545 5546 struct wmi_obss_color_collision_event { 5547 uint32_t vdev_id; 5548 uint32_t evt_type; 5549 uint64_t obss_color_bitmap; 5550 } __packed; 5551 5552 #define ATH11K_IPV4_TH_SEED_SIZE 5 5553 #define ATH11K_IPV6_TH_SEED_SIZE 11 5554 5555 struct ath11k_wmi_pdev_lro_config_cmd { 5556 uint32_t tlv_header; 5557 uint32_t lro_enable; 5558 uint32_t res; 5559 uint32_t th_4[ATH11K_IPV4_TH_SEED_SIZE]; 5560 uint32_t th_6[ATH11K_IPV6_TH_SEED_SIZE]; 5561 uint32_t pdev_id; 5562 } __packed; 5563 5564 #define ATH11K_WMI_SPECTRAL_COUNT_DEFAULT 0 5565 #define ATH11K_WMI_SPECTRAL_PERIOD_DEFAULT 224 5566 #define ATH11K_WMI_SPECTRAL_PRIORITY_DEFAULT 1 5567 #define ATH11K_WMI_SPECTRAL_FFT_SIZE_DEFAULT 7 5568 #define ATH11K_WMI_SPECTRAL_GC_ENA_DEFAULT 1 5569 #define ATH11K_WMI_SPECTRAL_RESTART_ENA_DEFAULT 0 5570 #define ATH11K_WMI_SPECTRAL_NOISE_FLOOR_REF_DEFAULT -96 5571 #define ATH11K_WMI_SPECTRAL_INIT_DELAY_DEFAULT 80 5572 #define ATH11K_WMI_SPECTRAL_NB_TONE_THR_DEFAULT 12 5573 #define ATH11K_WMI_SPECTRAL_STR_BIN_THR_DEFAULT 8 5574 #define ATH11K_WMI_SPECTRAL_WB_RPT_MODE_DEFAULT 0 5575 #define ATH11K_WMI_SPECTRAL_RSSI_RPT_MODE_DEFAULT 0 5576 #define ATH11K_WMI_SPECTRAL_RSSI_THR_DEFAULT 0xf0 5577 #define ATH11K_WMI_SPECTRAL_PWR_FORMAT_DEFAULT 0 5578 #define ATH11K_WMI_SPECTRAL_RPT_MODE_DEFAULT 2 5579 #define ATH11K_WMI_SPECTRAL_BIN_SCALE_DEFAULT 1 5580 #define ATH11K_WMI_SPECTRAL_DBM_ADJ_DEFAULT 1 5581 #define ATH11K_WMI_SPECTRAL_CHN_MASK_DEFAULT 1 5582 5583 struct ath11k_wmi_vdev_spectral_conf_param { 5584 uint32_t vdev_id; 5585 uint32_t scan_count; 5586 uint32_t scan_period; 5587 uint32_t scan_priority; 5588 uint32_t scan_fft_size; 5589 uint32_t scan_gc_ena; 5590 uint32_t scan_restart_ena; 5591 uint32_t scan_noise_floor_ref; 5592 uint32_t scan_init_delay; 5593 uint32_t scan_nb_tone_thr; 5594 uint32_t scan_str_bin_thr; 5595 uint32_t scan_wb_rpt_mode; 5596 uint32_t scan_rssi_rpt_mode; 5597 uint32_t scan_rssi_thr; 5598 uint32_t scan_pwr_format; 5599 uint32_t scan_rpt_mode; 5600 uint32_t scan_bin_scale; 5601 uint32_t scan_dbm_adj; 5602 uint32_t scan_chn_mask; 5603 } __packed; 5604 5605 struct ath11k_wmi_vdev_spectral_conf_cmd { 5606 uint32_t tlv_header; 5607 struct ath11k_wmi_vdev_spectral_conf_param param; 5608 } __packed; 5609 5610 #define ATH11K_WMI_SPECTRAL_TRIGGER_CMD_TRIGGER 1 5611 #define ATH11K_WMI_SPECTRAL_TRIGGER_CMD_CLEAR 2 5612 #define ATH11K_WMI_SPECTRAL_ENABLE_CMD_ENABLE 1 5613 #define ATH11K_WMI_SPECTRAL_ENABLE_CMD_DISABLE 2 5614 5615 struct ath11k_wmi_vdev_spectral_enable_cmd { 5616 uint32_t tlv_header; 5617 uint32_t vdev_id; 5618 uint32_t trigger_cmd; 5619 uint32_t enable_cmd; 5620 } __packed; 5621 5622 struct ath11k_wmi_pdev_dma_ring_cfg_req_cmd { 5623 uint32_t tlv_header; 5624 uint32_t pdev_id; 5625 uint32_t module_id; /* see enum wmi_direct_buffer_module */ 5626 uint32_t base_paddr_lo; 5627 uint32_t base_paddr_hi; 5628 uint32_t head_idx_paddr_lo; 5629 uint32_t head_idx_paddr_hi; 5630 uint32_t tail_idx_paddr_lo; 5631 uint32_t tail_idx_paddr_hi; 5632 uint32_t num_elems; /* Number of elems in the ring */ 5633 uint32_t buf_size; /* size of allocated buffer in bytes */ 5634 5635 /* Number of wmi_dma_buf_release_entry packed together */ 5636 uint32_t num_resp_per_event; 5637 5638 /* Target should timeout and send whatever resp 5639 * it has if this time expires, units in milliseconds 5640 */ 5641 uint32_t event_timeout_ms; 5642 } __packed; 5643 5644 struct ath11k_wmi_dma_buf_release_fixed_param { 5645 uint32_t pdev_id; 5646 uint32_t module_id; 5647 uint32_t num_buf_release_entry; 5648 uint32_t num_meta_data_entry; 5649 } __packed; 5650 5651 struct wmi_dma_buf_release_entry { 5652 uint32_t tlv_header; 5653 uint32_t paddr_lo; 5654 5655 /* Bits 11:0: address of data 5656 * Bits 31:12: host context data 5657 */ 5658 uint32_t paddr_hi; 5659 } __packed; 5660 5661 #define WMI_SPECTRAL_META_INFO1_FREQ1 GENMASK(15, 0) 5662 #define WMI_SPECTRAL_META_INFO1_FREQ2 GENMASK(31, 16) 5663 5664 #define WMI_SPECTRAL_META_INFO2_CHN_WIDTH GENMASK(7, 0) 5665 5666 struct wmi_dma_buf_release_meta_data { 5667 uint32_t tlv_header; 5668 int32_t noise_floor[WMI_MAX_CHAINS]; 5669 uint32_t reset_delay; 5670 uint32_t freq1; 5671 uint32_t freq2; 5672 uint32_t ch_width; 5673 } __packed; 5674 5675 enum wmi_fils_discovery_cmd_type { 5676 WMI_FILS_DISCOVERY_CMD, 5677 WMI_UNSOL_BCAST_PROBE_RESP, 5678 }; 5679 5680 struct wmi_fils_discovery_cmd { 5681 uint32_t tlv_header; 5682 uint32_t vdev_id; 5683 uint32_t interval; 5684 uint32_t config; /* enum wmi_fils_discovery_cmd_type */ 5685 } __packed; 5686 5687 struct wmi_fils_discovery_tmpl_cmd { 5688 uint32_t tlv_header; 5689 uint32_t vdev_id; 5690 uint32_t buf_len; 5691 } __packed; 5692 5693 struct wmi_probe_tmpl_cmd { 5694 uint32_t tlv_header; 5695 uint32_t vdev_id; 5696 uint32_t buf_len; 5697 } __packed; 5698 5699 struct target_resource_config { 5700 uint32_t num_vdevs; 5701 uint32_t num_peers; 5702 uint32_t num_active_peers; 5703 uint32_t num_offload_peers; 5704 uint32_t num_offload_reorder_buffs; 5705 uint32_t num_peer_keys; 5706 uint32_t num_tids; 5707 uint32_t ast_skid_limit; 5708 uint32_t tx_chain_mask; 5709 uint32_t rx_chain_mask; 5710 uint32_t rx_timeout_pri[4]; 5711 uint32_t rx_decap_mode; 5712 uint32_t scan_max_pending_req; 5713 uint32_t bmiss_offload_max_vdev; 5714 uint32_t roam_offload_max_vdev; 5715 uint32_t roam_offload_max_ap_profiles; 5716 uint32_t num_mcast_groups; 5717 uint32_t num_mcast_table_elems; 5718 uint32_t mcast2ucast_mode; 5719 uint32_t tx_dbg_log_size; 5720 uint32_t num_wds_entries; 5721 uint32_t dma_burst_size; 5722 uint32_t mac_aggr_delim; 5723 uint32_t rx_skip_defrag_timeout_dup_detection_check; 5724 uint32_t vow_config; 5725 uint32_t gtk_offload_max_vdev; 5726 uint32_t num_msdu_desc; 5727 uint32_t max_frag_entries; 5728 uint32_t max_peer_ext_stats; 5729 uint32_t smart_ant_cap; 5730 uint32_t bk_minfree; 5731 uint32_t be_minfree; 5732 uint32_t vi_minfree; 5733 uint32_t vo_minfree; 5734 uint32_t rx_batchmode; 5735 uint32_t tt_support; 5736 uint32_t flag1; 5737 uint32_t iphdr_pad_config; 5738 uint32_t qwrap_config:16, 5739 alloc_frag_desc_for_data_pkt:16; 5740 uint32_t num_tdls_vdevs; 5741 uint32_t num_tdls_conn_table_entries; 5742 uint32_t beacon_tx_offload_max_vdev; 5743 uint32_t num_multicast_filter_entries; 5744 uint32_t num_wow_filters; 5745 uint32_t num_keep_alive_pattern; 5746 uint32_t keep_alive_pattern_size; 5747 uint32_t max_tdls_concurrent_sleep_sta; 5748 uint32_t max_tdls_concurrent_buffer_sta; 5749 uint32_t wmi_send_separate; 5750 uint32_t num_ocb_vdevs; 5751 uint32_t num_ocb_channels; 5752 uint32_t num_ocb_schedules; 5753 uint32_t num_ns_ext_tuples_cfg; 5754 uint32_t bpf_instruction_size; 5755 uint32_t max_bssid_rx_filters; 5756 uint32_t use_pdev_id; 5757 uint32_t peer_map_unmap_v2_support; 5758 uint32_t sched_params; 5759 uint32_t twt_ap_pdev_count; 5760 uint32_t twt_ap_sta_count; 5761 uint8_t is_reg_cc_ext_event_supported; 5762 uint32_t ema_max_vap_cnt; 5763 uint32_t ema_max_profile_period; 5764 }; 5765 5766 enum wmi_debug_log_param { 5767 WMI_DEBUG_LOG_PARAM_LOG_LEVEL = 0x1, 5768 WMI_DEBUG_LOG_PARAM_VDEV_ENABLE, 5769 WMI_DEBUG_LOG_PARAM_VDEV_DISABLE, 5770 WMI_DEBUG_LOG_PARAM_VDEV_ENABLE_BITMAP, 5771 WMI_DEBUG_LOG_PARAM_MOD_ENABLE_BITMAP, 5772 WMI_DEBUG_LOG_PARAM_WOW_MOD_ENABLE_BITMAP, 5773 }; 5774 5775 struct wmi_debug_log_config_cmd_fixed_param { 5776 uint32_t tlv_header; 5777 uint32_t dbg_log_param; 5778 uint32_t value; 5779 } __packed; 5780 5781 #define WMI_MAX_MEM_REQS 32 5782 5783 #define MAX_RADIOS 3 5784 5785 #define WMI_SERVICE_READY_TIMEOUT_HZ (5 * HZ) 5786 #define WMI_SEND_TIMEOUT_HZ (3 * HZ) 5787 5788 enum ath11k_wmi_peer_ps_state { 5789 WMI_PEER_PS_STATE_OFF, 5790 WMI_PEER_PS_STATE_ON, 5791 WMI_PEER_PS_STATE_DISABLED, 5792 }; 5793 5794 enum wmi_peer_ps_supported_bitmap { 5795 /* Used to indicate that power save state change is valid */ 5796 WMI_PEER_PS_VALID = 0x1, 5797 WMI_PEER_PS_STATE_TIMESTAMP = 0x2, 5798 }; 5799 5800 struct wmi_peer_sta_ps_state_chg_event { 5801 struct wmi_mac_addr peer_macaddr; 5802 uint32_t peer_ps_state; 5803 uint32_t ps_supported_bitmap; 5804 uint32_t peer_ps_valid; 5805 uint32_t peer_ps_timestamp; 5806 } __packed; 5807 5808 /* Definition of HW data filtering */ 5809 enum hw_data_filter_type { 5810 WMI_HW_DATA_FILTER_DROP_NON_ARP_BC = BIT(0), 5811 WMI_HW_DATA_FILTER_DROP_NON_ICMPV6_MC = BIT(1), 5812 }; 5813 5814 struct wmi_hw_data_filter_cmd { 5815 uint32_t tlv_header; 5816 uint32_t vdev_id; 5817 uint32_t enable; 5818 uint32_t hw_filter_bitmap; 5819 } __packed; 5820 5821 /* WOW structures */ 5822 enum wmi_wow_wakeup_event { 5823 WOW_BMISS_EVENT = 0, 5824 WOW_BETTER_AP_EVENT, 5825 WOW_DEAUTH_RECVD_EVENT, 5826 WOW_MAGIC_PKT_RECVD_EVENT, 5827 WOW_GTK_ERR_EVENT, 5828 WOW_FOURWAY_HSHAKE_EVENT, 5829 WOW_EAPOL_RECVD_EVENT, 5830 WOW_NLO_DETECTED_EVENT, 5831 WOW_DISASSOC_RECVD_EVENT, 5832 WOW_PATTERN_MATCH_EVENT, 5833 WOW_CSA_IE_EVENT, 5834 WOW_PROBE_REQ_WPS_IE_EVENT, 5835 WOW_AUTH_REQ_EVENT, 5836 WOW_ASSOC_REQ_EVENT, 5837 WOW_HTT_EVENT, 5838 WOW_RA_MATCH_EVENT, 5839 WOW_HOST_AUTO_SHUTDOWN_EVENT, 5840 WOW_IOAC_MAGIC_EVENT, 5841 WOW_IOAC_SHORT_EVENT, 5842 WOW_IOAC_EXTEND_EVENT, 5843 WOW_IOAC_TIMER_EVENT, 5844 WOW_DFS_PHYERR_RADAR_EVENT, 5845 WOW_BEACON_EVENT, 5846 WOW_CLIENT_KICKOUT_EVENT, 5847 WOW_EVENT_MAX, 5848 }; 5849 5850 enum wmi_wow_interface_cfg { 5851 WOW_IFACE_PAUSE_ENABLED, 5852 WOW_IFACE_PAUSE_DISABLED 5853 }; 5854 5855 #define C2S(x) case x: return #x 5856 5857 static inline const char *wow_wakeup_event(enum wmi_wow_wakeup_event ev) 5858 { 5859 switch (ev) { 5860 C2S(WOW_BMISS_EVENT); 5861 C2S(WOW_BETTER_AP_EVENT); 5862 C2S(WOW_DEAUTH_RECVD_EVENT); 5863 C2S(WOW_MAGIC_PKT_RECVD_EVENT); 5864 C2S(WOW_GTK_ERR_EVENT); 5865 C2S(WOW_FOURWAY_HSHAKE_EVENT); 5866 C2S(WOW_EAPOL_RECVD_EVENT); 5867 C2S(WOW_NLO_DETECTED_EVENT); 5868 C2S(WOW_DISASSOC_RECVD_EVENT); 5869 C2S(WOW_PATTERN_MATCH_EVENT); 5870 C2S(WOW_CSA_IE_EVENT); 5871 C2S(WOW_PROBE_REQ_WPS_IE_EVENT); 5872 C2S(WOW_AUTH_REQ_EVENT); 5873 C2S(WOW_ASSOC_REQ_EVENT); 5874 C2S(WOW_HTT_EVENT); 5875 C2S(WOW_RA_MATCH_EVENT); 5876 C2S(WOW_HOST_AUTO_SHUTDOWN_EVENT); 5877 C2S(WOW_IOAC_MAGIC_EVENT); 5878 C2S(WOW_IOAC_SHORT_EVENT); 5879 C2S(WOW_IOAC_EXTEND_EVENT); 5880 C2S(WOW_IOAC_TIMER_EVENT); 5881 C2S(WOW_DFS_PHYERR_RADAR_EVENT); 5882 C2S(WOW_BEACON_EVENT); 5883 C2S(WOW_CLIENT_KICKOUT_EVENT); 5884 C2S(WOW_EVENT_MAX); 5885 default: 5886 return NULL; 5887 } 5888 } 5889 5890 enum wmi_wow_wake_reason { 5891 WOW_REASON_UNSPECIFIED = -1, 5892 WOW_REASON_NLOD = 0, 5893 WOW_REASON_AP_ASSOC_LOST, 5894 WOW_REASON_LOW_RSSI, 5895 WOW_REASON_DEAUTH_RECVD, 5896 WOW_REASON_DISASSOC_RECVD, 5897 WOW_REASON_GTK_HS_ERR, 5898 WOW_REASON_EAP_REQ, 5899 WOW_REASON_FOURWAY_HS_RECV, 5900 WOW_REASON_TIMER_INTR_RECV, 5901 WOW_REASON_PATTERN_MATCH_FOUND, 5902 WOW_REASON_RECV_MAGIC_PATTERN, 5903 WOW_REASON_P2P_DISC, 5904 WOW_REASON_WLAN_HB, 5905 WOW_REASON_CSA_EVENT, 5906 WOW_REASON_PROBE_REQ_WPS_IE_RECV, 5907 WOW_REASON_AUTH_REQ_RECV, 5908 WOW_REASON_ASSOC_REQ_RECV, 5909 WOW_REASON_HTT_EVENT, 5910 WOW_REASON_RA_MATCH, 5911 WOW_REASON_HOST_AUTO_SHUTDOWN, 5912 WOW_REASON_IOAC_MAGIC_EVENT, 5913 WOW_REASON_IOAC_SHORT_EVENT, 5914 WOW_REASON_IOAC_EXTEND_EVENT, 5915 WOW_REASON_IOAC_TIMER_EVENT, 5916 WOW_REASON_ROAM_HO, 5917 WOW_REASON_DFS_PHYERR_RADADR_EVENT, 5918 WOW_REASON_BEACON_RECV, 5919 WOW_REASON_CLIENT_KICKOUT_EVENT, 5920 WOW_REASON_PAGE_FAULT = 0x3a, 5921 WOW_REASON_DEBUG_TEST = 0xFF, 5922 }; 5923 5924 static inline const char *wow_reason(enum wmi_wow_wake_reason reason) 5925 { 5926 switch (reason) { 5927 C2S(WOW_REASON_UNSPECIFIED); 5928 C2S(WOW_REASON_NLOD); 5929 C2S(WOW_REASON_AP_ASSOC_LOST); 5930 C2S(WOW_REASON_LOW_RSSI); 5931 C2S(WOW_REASON_DEAUTH_RECVD); 5932 C2S(WOW_REASON_DISASSOC_RECVD); 5933 C2S(WOW_REASON_GTK_HS_ERR); 5934 C2S(WOW_REASON_EAP_REQ); 5935 C2S(WOW_REASON_FOURWAY_HS_RECV); 5936 C2S(WOW_REASON_TIMER_INTR_RECV); 5937 C2S(WOW_REASON_PATTERN_MATCH_FOUND); 5938 C2S(WOW_REASON_RECV_MAGIC_PATTERN); 5939 C2S(WOW_REASON_P2P_DISC); 5940 C2S(WOW_REASON_WLAN_HB); 5941 C2S(WOW_REASON_CSA_EVENT); 5942 C2S(WOW_REASON_PROBE_REQ_WPS_IE_RECV); 5943 C2S(WOW_REASON_AUTH_REQ_RECV); 5944 C2S(WOW_REASON_ASSOC_REQ_RECV); 5945 C2S(WOW_REASON_HTT_EVENT); 5946 C2S(WOW_REASON_RA_MATCH); 5947 C2S(WOW_REASON_HOST_AUTO_SHUTDOWN); 5948 C2S(WOW_REASON_IOAC_MAGIC_EVENT); 5949 C2S(WOW_REASON_IOAC_SHORT_EVENT); 5950 C2S(WOW_REASON_IOAC_EXTEND_EVENT); 5951 C2S(WOW_REASON_IOAC_TIMER_EVENT); 5952 C2S(WOW_REASON_ROAM_HO); 5953 C2S(WOW_REASON_DFS_PHYERR_RADADR_EVENT); 5954 C2S(WOW_REASON_BEACON_RECV); 5955 C2S(WOW_REASON_CLIENT_KICKOUT_EVENT); 5956 C2S(WOW_REASON_PAGE_FAULT); 5957 C2S(WOW_REASON_DEBUG_TEST); 5958 default: 5959 return NULL; 5960 } 5961 } 5962 5963 #undef C2S 5964 5965 struct wmi_wow_ev_arg { 5966 uint32_t vdev_id; 5967 uint32_t flag; 5968 enum wmi_wow_wake_reason wake_reason; 5969 uint32_t data_len; 5970 }; 5971 5972 enum wmi_tlv_pattern_type { 5973 WOW_PATTERN_MIN = 0, 5974 WOW_BITMAP_PATTERN = WOW_PATTERN_MIN, 5975 WOW_IPV4_SYNC_PATTERN, 5976 WOW_IPV6_SYNC_PATTERN, 5977 WOW_WILD_CARD_PATTERN, 5978 WOW_TIMER_PATTERN, 5979 WOW_MAGIC_PATTERN, 5980 WOW_IPV6_RA_PATTERN, 5981 WOW_IOAC_PKT_PATTERN, 5982 WOW_IOAC_TMR_PATTERN, 5983 WOW_PATTERN_MAX 5984 }; 5985 5986 #define WOW_DEFAULT_BITMAP_PATTERN_SIZE 148 5987 #define WOW_DEFAULT_BITMASK_SIZE 148 5988 5989 #define WOW_MIN_PATTERN_SIZE 1 5990 #define WOW_MAX_PATTERN_SIZE 148 5991 #define WOW_MAX_PKT_OFFSET 128 5992 #define WOW_HDR_LEN (sizeof(struct ieee80211_hdr_3addr) + \ 5993 sizeof(struct rfc1042_hdr)) 5994 #define WOW_MAX_REDUCE (WOW_HDR_LEN - sizeof(struct ethhdr) - \ 5995 offsetof(struct ieee80211_hdr_3addr, addr1)) 5996 5997 struct wmi_wow_add_del_event_cmd { 5998 uint32_t tlv_header; 5999 uint32_t vdev_id; 6000 uint32_t is_add; 6001 uint32_t event_bitmap; 6002 } __packed; 6003 6004 struct wmi_wow_enable_cmd { 6005 uint32_t tlv_header; 6006 uint32_t enable; 6007 uint32_t pause_iface_config; 6008 uint32_t flags; 6009 } __packed; 6010 6011 struct wmi_wow_host_wakeup_ind { 6012 uint32_t tlv_header; 6013 uint32_t reserved; 6014 } __packed; 6015 6016 struct wmi_tlv_wow_event_info { 6017 uint32_t vdev_id; 6018 uint32_t flag; 6019 uint32_t wake_reason; 6020 uint32_t data_len; 6021 } __packed; 6022 6023 struct wmi_wow_bitmap_pattern { 6024 uint32_t tlv_header; 6025 uint8_t patternbuf[WOW_DEFAULT_BITMAP_PATTERN_SIZE]; 6026 uint8_t bitmaskbuf[WOW_DEFAULT_BITMASK_SIZE]; 6027 uint32_t pattern_offset; 6028 uint32_t pattern_len; 6029 uint32_t bitmask_len; 6030 uint32_t pattern_id; 6031 } __packed; 6032 6033 struct wmi_wow_add_pattern_cmd { 6034 uint32_t tlv_header; 6035 uint32_t vdev_id; 6036 uint32_t pattern_id; 6037 uint32_t pattern_type; 6038 } __packed; 6039 6040 struct wmi_wow_del_pattern_cmd { 6041 uint32_t tlv_header; 6042 uint32_t vdev_id; 6043 uint32_t pattern_id; 6044 uint32_t pattern_type; 6045 } __packed; 6046 6047 #define WMI_PNO_MAX_SCHED_SCAN_PLANS 2 6048 #define WMI_PNO_MAX_SCHED_SCAN_PLAN_INT 7200 6049 #define WMI_PNO_MAX_SCHED_SCAN_PLAN_ITRNS 100 6050 #define WMI_PNO_MAX_NETW_CHANNELS 26 6051 #define WMI_PNO_MAX_NETW_CHANNELS_EX 60 6052 #define WMI_PNO_MAX_SUPP_NETWORKS WLAN_SCAN_PARAMS_MAX_SSID 6053 #define WMI_PNO_MAX_IE_LENGTH WLAN_SCAN_PARAMS_MAX_IE_LEN 6054 6055 /* size based of dot11 declaration without extra IEs as we will not carry those for PNO */ 6056 #define WMI_PNO_MAX_PB_REQ_SIZE 450 6057 6058 #define WMI_PNO_24G_DEFAULT_CH 1 6059 #define WMI_PNO_5G_DEFAULT_CH 36 6060 6061 #define WMI_ACTIVE_MAX_CHANNEL_TIME 40 6062 #define WMI_PASSIVE_MAX_CHANNEL_TIME 110 6063 6064 /* SSID broadcast type */ 6065 enum wmi_ssid_bcast_type { 6066 BCAST_UNKNOWN = 0, 6067 BCAST_NORMAL = 1, 6068 BCAST_HIDDEN = 2, 6069 }; 6070 6071 #define WMI_NLO_MAX_SSIDS 16 6072 #define WMI_NLO_MAX_CHAN 48 6073 6074 #define WMI_NLO_CONFIG_STOP BIT(0) 6075 #define WMI_NLO_CONFIG_START BIT(1) 6076 #define WMI_NLO_CONFIG_RESET BIT(2) 6077 #define WMI_NLO_CONFIG_SLOW_SCAN BIT(4) 6078 #define WMI_NLO_CONFIG_FAST_SCAN BIT(5) 6079 #define WMI_NLO_CONFIG_SSID_HIDE_EN BIT(6) 6080 6081 /* This bit is used to indicate if EPNO or supplicant PNO is enabled. 6082 * Only one of them can be enabled at a given time 6083 */ 6084 #define WMI_NLO_CONFIG_ENLO BIT(7) 6085 #define WMI_NLO_CONFIG_SCAN_PASSIVE BIT(8) 6086 #define WMI_NLO_CONFIG_ENLO_RESET BIT(9) 6087 #define WMI_NLO_CONFIG_SPOOFED_MAC_IN_PROBE_REQ BIT(10) 6088 #define WMI_NLO_CONFIG_RANDOM_SEQ_NO_IN_PROBE_REQ BIT(11) 6089 #define WMI_NLO_CONFIG_ENABLE_IE_WHITELIST_IN_PROBE_REQ BIT(12) 6090 #define WMI_NLO_CONFIG_ENABLE_CNLO_RSSI_CONFIG BIT(13) 6091 6092 struct wmi_nlo_ssid_param { 6093 uint32_t valid; 6094 struct wmi_ssid ssid; 6095 } __packed; 6096 6097 struct wmi_nlo_enc_param { 6098 uint32_t valid; 6099 uint32_t enc_type; 6100 } __packed; 6101 6102 struct wmi_nlo_auth_param { 6103 uint32_t valid; 6104 uint32_t auth_type; 6105 } __packed; 6106 6107 struct wmi_nlo_bcast_nw_param { 6108 uint32_t valid; 6109 uint32_t bcast_nw_type; 6110 } __packed; 6111 6112 struct wmi_nlo_rssi_param { 6113 uint32_t valid; 6114 int32_t rssi; 6115 } __packed; 6116 6117 struct nlo_configured_parameters { 6118 /* TLV tag and len;*/ 6119 uint32_t tlv_header; 6120 struct wmi_nlo_ssid_param ssid; 6121 struct wmi_nlo_enc_param enc_type; 6122 struct wmi_nlo_auth_param auth_type; 6123 struct wmi_nlo_rssi_param rssi_cond; 6124 6125 /* indicates if the SSID is hidden or not */ 6126 struct wmi_nlo_bcast_nw_param bcast_nw_type; 6127 } __packed; 6128 6129 struct wmi_network_type { 6130 struct wmi_ssid ssid; 6131 uint32_t authentication; 6132 uint32_t encryption; 6133 uint32_t bcast_nw_type; 6134 uint8_t channel_count; 6135 uint16_t channels[WMI_PNO_MAX_NETW_CHANNELS_EX]; 6136 int32_t rssi_threshold; 6137 }; 6138 6139 struct wmi_pno_scan_req { 6140 uint8_t enable; 6141 uint8_t vdev_id; 6142 uint8_t uc_networks_count; 6143 struct wmi_network_type a_networks[WMI_PNO_MAX_SUPP_NETWORKS]; 6144 uint32_t fast_scan_period; 6145 uint32_t slow_scan_period; 6146 uint8_t fast_scan_max_cycles; 6147 6148 bool do_passive_scan; 6149 6150 uint32_t delay_start_time; 6151 uint32_t active_min_time; 6152 uint32_t active_max_time; 6153 uint32_t passive_min_time; 6154 uint32_t passive_max_time; 6155 6156 /* mac address randomization attributes */ 6157 uint32_t enable_pno_scan_randomization; 6158 uint8_t mac_addr[IEEE80211_ADDR_LEN]; 6159 uint8_t mac_addr_mask[IEEE80211_ADDR_LEN]; 6160 }; 6161 6162 struct wmi_wow_nlo_config_cmd { 6163 uint32_t tlv_header; 6164 uint32_t flags; 6165 uint32_t vdev_id; 6166 uint32_t fast_scan_max_cycles; 6167 uint32_t active_dwell_time; 6168 uint32_t passive_dwell_time; 6169 uint32_t probe_bundle_size; 6170 6171 /* ART = IRT */ 6172 uint32_t rest_time; 6173 6174 /* Max value that can be reached after SBM */ 6175 uint32_t max_rest_time; 6176 6177 /* SBM */ 6178 uint32_t scan_backoff_multiplier; 6179 6180 /* SCBM */ 6181 uint32_t fast_scan_period; 6182 6183 /* specific to windows */ 6184 uint32_t slow_scan_period; 6185 6186 uint32_t no_of_ssids; 6187 6188 uint32_t num_of_channels; 6189 6190 /* NLO scan start delay time in milliseconds */ 6191 uint32_t delay_start_time; 6192 6193 /* MAC Address to use in Probe Req as SA */ 6194 struct wmi_mac_addr mac_addr; 6195 6196 /* Mask on which MAC has to be randomized */ 6197 struct wmi_mac_addr mac_mask; 6198 6199 /* IE bitmap to use in Probe Req */ 6200 uint32_t ie_bitmap[8]; 6201 6202 /* Number of vendor OUIs. In the TLV vendor_oui[] */ 6203 uint32_t num_vendor_oui; 6204 6205 /* Number of connected NLO band preferences */ 6206 uint32_t num_cnlo_band_pref; 6207 6208 /* The TLVs will follow. 6209 * nlo_configured_parameters nlo_list[]; 6210 * uint32_t channel_list[num_of_channels]; 6211 */ 6212 } __packed; 6213 6214 #define WMI_MAX_NS_OFFLOADS 2 6215 #define WMI_MAX_ARP_OFFLOADS 2 6216 6217 #define WMI_ARPOL_FLAGS_VALID BIT(0) 6218 #define WMI_ARPOL_FLAGS_MAC_VALID BIT(1) 6219 #define WMI_ARPOL_FLAGS_REMOTE_IP_VALID BIT(2) 6220 6221 struct wmi_arp_offload_tuple { 6222 uint32_t tlv_header; 6223 uint32_t flags; 6224 uint8_t target_ipaddr[4]; 6225 uint8_t remote_ipaddr[4]; 6226 struct wmi_mac_addr target_mac; 6227 } __packed; 6228 6229 #define WMI_NSOL_FLAGS_VALID BIT(0) 6230 #define WMI_NSOL_FLAGS_MAC_VALID BIT(1) 6231 #define WMI_NSOL_FLAGS_REMOTE_IP_VALID BIT(2) 6232 #define WMI_NSOL_FLAGS_IS_IPV6_ANYCAST BIT(3) 6233 6234 #define WMI_NSOL_MAX_TARGET_IPS 2 6235 6236 struct wmi_ns_offload_tuple { 6237 uint32_t tlv_header; 6238 uint32_t flags; 6239 uint8_t target_ipaddr[WMI_NSOL_MAX_TARGET_IPS][16]; 6240 uint8_t solicitation_ipaddr[16]; 6241 uint8_t remote_ipaddr[16]; 6242 struct wmi_mac_addr target_mac; 6243 } __packed; 6244 6245 struct wmi_set_arp_ns_offload_cmd { 6246 uint32_t tlv_header; 6247 uint32_t flags; 6248 uint32_t vdev_id; 6249 uint32_t num_ns_ext_tuples; 6250 /* The TLVs follow: 6251 * wmi_ns_offload_tuple ns_tuples[WMI_MAX_NS_OFFLOADS]; 6252 * wmi_arp_offload_tuple arp_tuples[WMI_MAX_ARP_OFFLOADS]; 6253 * wmi_ns_offload_tuple ns_ext_tuples[num_ns_ext_tuples]; 6254 */ 6255 } __packed; 6256 6257 #define GTK_OFFLOAD_OPCODE_MASK 0xFF000000 6258 #define GTK_OFFLOAD_ENABLE_OPCODE 0x01000000 6259 #define GTK_OFFLOAD_DISABLE_OPCODE 0x02000000 6260 #define GTK_OFFLOAD_REQUEST_STATUS_OPCODE 0x04000000 6261 6262 #define GTK_OFFLOAD_KEK_BYTES 16 6263 #define GTK_OFFLOAD_KCK_BYTES 16 6264 #define GTK_REPLAY_COUNTER_BYTES 8 6265 #define WMI_MAX_KEY_LEN 32 6266 #define IGTK_PN_SIZE 6 6267 6268 struct wmi_replayc_cnt { 6269 union { 6270 uint8_t counter[GTK_REPLAY_COUNTER_BYTES]; 6271 struct { 6272 uint32_t word0; 6273 uint32_t word1; 6274 } __packed; 6275 } __packed; 6276 } __packed; 6277 6278 struct wmi_gtk_offload_status_event { 6279 uint32_t vdev_id; 6280 uint32_t flags; 6281 uint32_t refresh_cnt; 6282 struct wmi_replayc_cnt replay_ctr; 6283 uint8_t igtk_key_index; 6284 uint8_t igtk_key_length; 6285 uint8_t igtk_key_rsc[IGTK_PN_SIZE]; 6286 uint8_t igtk_key[WMI_MAX_KEY_LEN]; 6287 uint8_t gtk_key_index; 6288 uint8_t gtk_key_length; 6289 uint8_t gtk_key_rsc[GTK_REPLAY_COUNTER_BYTES]; 6290 uint8_t gtk_key[WMI_MAX_KEY_LEN]; 6291 } __packed; 6292 6293 struct wmi_gtk_rekey_offload_cmd { 6294 uint32_t tlv_header; 6295 uint32_t vdev_id; 6296 uint32_t flags; 6297 uint8_t kek[GTK_OFFLOAD_KEK_BYTES]; 6298 uint8_t kck[GTK_OFFLOAD_KCK_BYTES]; 6299 uint8_t replay_ctr[GTK_REPLAY_COUNTER_BYTES]; 6300 } __packed; 6301 6302 #define BIOS_SAR_TABLE_LEN (22) 6303 #define BIOS_SAR_RSVD1_LEN (6) 6304 #define BIOS_SAR_RSVD2_LEN (18) 6305 6306 struct wmi_pdev_set_sar_table_cmd { 6307 uint32_t tlv_header; 6308 uint32_t pdev_id; 6309 uint32_t sar_len; 6310 uint32_t rsvd_len; 6311 } __packed; 6312 6313 struct wmi_pdev_set_geo_table_cmd { 6314 uint32_t tlv_header; 6315 uint32_t pdev_id; 6316 uint32_t rsvd_len; 6317 } __packed; 6318 6319 struct wmi_sta_keepalive_cmd { 6320 uint32_t tlv_header; 6321 uint32_t vdev_id; 6322 uint32_t enabled; 6323 6324 /* WMI_STA_KEEPALIVE_METHOD_ */ 6325 uint32_t method; 6326 6327 /* in seconds */ 6328 uint32_t interval; 6329 6330 /* following this structure is the TLV for struct 6331 * wmi_sta_keepalive_arp_resp 6332 */ 6333 } __packed; 6334 6335 struct wmi_sta_keepalive_arp_resp { 6336 uint32_t tlv_header; 6337 uint32_t src_ip4_addr; 6338 uint32_t dest_ip4_addr; 6339 struct wmi_mac_addr dest_mac_addr; 6340 } __packed; 6341 6342 struct wmi_sta_keepalive_arg { 6343 uint32_t vdev_id; 6344 uint32_t enabled; 6345 uint32_t method; 6346 uint32_t interval; 6347 uint32_t src_ip4_addr; 6348 uint32_t dest_ip4_addr; 6349 const uint8_t dest_mac_addr[IEEE80211_ADDR_LEN]; 6350 }; 6351 6352 enum wmi_sta_keepalive_method { 6353 WMI_STA_KEEPALIVE_METHOD_NULL_FRAME = 1, 6354 WMI_STA_KEEPALIVE_METHOD_UNSOLICITED_ARP_RESPONSE = 2, 6355 WMI_STA_KEEPALIVE_METHOD_ETHERNET_LOOPBACK = 3, 6356 WMI_STA_KEEPALIVE_METHOD_GRATUITOUS_ARP_REQUEST = 4, 6357 WMI_STA_KEEPALIVE_METHOD_MGMT_VENDOR_ACTION = 5, 6358 }; 6359 6360 #define WMI_STA_KEEPALIVE_INTERVAL_DEFAULT 30 6361 #define WMI_STA_KEEPALIVE_INTERVAL_DISABLE 0 6362 6363 6364 /* 6365 * qrtr.h 6366 */ 6367 6368 #define QRTR_PROTO_VER_1 1 6369 #define QRTR_PROTO_VER_2 3 /* (sic!) */ 6370 6371 struct qrtr_hdr_v1 { 6372 uint32_t version; 6373 uint32_t type; 6374 uint32_t src_node_id; 6375 uint32_t src_port_id; 6376 uint32_t confirm_rx; 6377 uint32_t size; 6378 uint32_t dst_node_id; 6379 uint32_t dst_port_id; 6380 } __packed; 6381 6382 struct qrtr_hdr_v2 { 6383 uint8_t version; 6384 uint8_t type; 6385 uint8_t flags; 6386 uint8_t optlen; 6387 uint32_t size; 6388 uint16_t src_node_id; 6389 uint16_t src_port_id; 6390 uint16_t dst_node_id; 6391 uint16_t dst_port_id; 6392 }; 6393 6394 struct qrtr_ctrl_pkt { 6395 uint32_t cmd; 6396 6397 union { 6398 struct { 6399 uint32_t service; 6400 uint32_t instance; 6401 uint32_t node; 6402 uint32_t port; 6403 } server; 6404 struct { 6405 uint32_t node; 6406 uint32_t port; 6407 } client; 6408 }; 6409 } __packed; 6410 6411 #define QRTR_TYPE_DATA 1 6412 #define QRTR_TYPE_HELLO 2 6413 #define QRTR_TYPE_BYE 3 6414 #define QRTR_TYPE_NEW_SERVER 4 6415 #define QRTR_TYPE_DEL_SERVER 5 6416 #define QRTR_TYPE_DEL_CLIENT 6 6417 #define QRTR_TYPE_RESUME_TX 7 6418 #define QRTR_TYPE_EXIT 8 6419 #define QRTR_TYPE_PING 9 6420 #define QRTR_TYPE_NEW_LOOKUP 10 6421 #define QRTR_TYPE_DEL_LOOKUP 11 6422 6423 #define QRTR_FLAGS_CONFIRM_RX (1 << 0) 6424 6425 #define QRTR_NODE_BCAST 0xffffffffU 6426 #define QRTR_PORT_CTRL 0xfffffffeU 6427 6428 /* 6429 * qmi.h 6430 */ 6431 6432 #define QMI_REQUEST 0 6433 #define QMI_RESPONSE 2 6434 #define QMI_INDICATION 4 6435 6436 struct qmi_header { 6437 uint8_t type; 6438 uint16_t txn_id; 6439 uint16_t msg_id; 6440 uint16_t msg_len; 6441 } __packed; 6442 6443 #define QMI_COMMON_TLV_TYPE 0 6444 6445 enum qmi_elem_type { 6446 QMI_EOTI, 6447 QMI_OPT_FLAG, 6448 QMI_DATA_LEN, 6449 QMI_UNSIGNED_1_BYTE, 6450 QMI_UNSIGNED_2_BYTE, 6451 QMI_UNSIGNED_4_BYTE, 6452 QMI_UNSIGNED_8_BYTE, 6453 QMI_SIGNED_2_BYTE_ENUM, 6454 QMI_SIGNED_4_BYTE_ENUM, 6455 QMI_STRUCT, 6456 QMI_STRING, 6457 QMI_NUM_DATA_TYPES 6458 }; 6459 6460 enum qmi_array_type { 6461 NO_ARRAY, 6462 STATIC_ARRAY, 6463 VAR_LEN_ARRAY, 6464 }; 6465 6466 struct qmi_elem_info { 6467 enum qmi_elem_type data_type; 6468 uint32_t elem_len; 6469 uint32_t elem_size; 6470 enum qmi_array_type array_type; 6471 uint8_t tlv_type; 6472 uint32_t offset; 6473 const struct qmi_elem_info *ei_array; 6474 }; 6475 6476 #define QMI_RESULT_SUCCESS_V01 0 6477 #define QMI_RESULT_FAILURE_V01 1 6478 6479 #define QMI_ERR_NONE_V01 0 6480 #define QMI_ERR_MALFORMED_MSG_V01 1 6481 #define QMI_ERR_NO_MEMORY_V01 2 6482 #define QMI_ERR_INTERNAL_V01 3 6483 #define QMI_ERR_CLIENT_IDS_EXHAUSTED_V01 5 6484 #define QMI_ERR_INVALID_ID_V01 41 6485 #define QMI_ERR_ENCODING_V01 58 6486 #define QMI_ERR_DISABLED_V01 69 6487 #define QMI_ERR_INCOMPATIBLE_STATE_V01 90 6488 #define QMI_ERR_NOT_SUPPORTED_V01 94 6489 6490 struct qmi_response_type_v01 { 6491 uint16_t result; 6492 uint16_t error; 6493 }; 6494 6495 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN 54 6496 #define QMI_WLANFW_IND_REGISTER_REQ_V01 0x0020 6497 #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN 18 6498 #define QMI_WLANFW_IND_REGISTER_RESP_V01 0x0020 6499 #define QMI_WLANFW_CLIENT_ID 0x4b4e454c 6500 6501 struct qmi_wlanfw_ind_register_req_msg_v01 { 6502 uint8_t fw_ready_enable_valid; 6503 uint8_t fw_ready_enable; 6504 uint8_t initiate_cal_download_enable_valid; 6505 uint8_t initiate_cal_download_enable; 6506 uint8_t initiate_cal_update_enable_valid; 6507 uint8_t initiate_cal_update_enable; 6508 uint8_t msa_ready_enable_valid; 6509 uint8_t msa_ready_enable; 6510 uint8_t pin_connect_result_enable_valid; 6511 uint8_t pin_connect_result_enable; 6512 uint8_t client_id_valid; 6513 uint32_t client_id; 6514 uint8_t request_mem_enable_valid; 6515 uint8_t request_mem_enable; 6516 uint8_t fw_mem_ready_enable_valid; 6517 uint8_t fw_mem_ready_enable; 6518 uint8_t fw_init_done_enable_valid; 6519 uint8_t fw_init_done_enable; 6520 uint8_t rejuvenate_enable_valid; 6521 uint32_t rejuvenate_enable; 6522 uint8_t xo_cal_enable_valid; 6523 uint8_t xo_cal_enable; 6524 uint8_t cal_done_enable_valid; 6525 uint8_t cal_done_enable; 6526 }; 6527 6528 struct qmi_wlanfw_ind_register_resp_msg_v01 { 6529 struct qmi_response_type_v01 resp; 6530 uint8_t fw_status_valid; 6531 uint64_t fw_status; 6532 }; 6533 6534 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN 261 6535 #define QMI_WLANFW_HOST_CAP_REQ_V01 0x0034 6536 #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN 7 6537 #define QMI_WLFW_HOST_CAP_RESP_V01 0x0034 6538 #define QMI_WLFW_MAX_NUM_GPIO_V01 32 6539 #define QMI_IPQ8074_FW_MEM_MODE 0xFF 6540 #define HOST_DDR_REGION_TYPE 0x1 6541 #define BDF_MEM_REGION_TYPE 0x2 6542 #define M3_DUMP_REGION_TYPE 0x3 6543 #define CALDB_MEM_REGION_TYPE 0x4 6544 6545 struct qmi_wlanfw_host_cap_req_msg_v01 { 6546 uint8_t num_clients_valid; 6547 uint32_t num_clients; 6548 uint8_t wake_msi_valid; 6549 uint32_t wake_msi; 6550 uint8_t gpios_valid; 6551 uint32_t gpios_len; 6552 uint32_t gpios[QMI_WLFW_MAX_NUM_GPIO_V01]; 6553 uint8_t nm_modem_valid; 6554 uint8_t nm_modem; 6555 uint8_t bdf_support_valid; 6556 uint8_t bdf_support; 6557 uint8_t bdf_cache_support_valid; 6558 uint8_t bdf_cache_support; 6559 uint8_t m3_support_valid; 6560 uint8_t m3_support; 6561 uint8_t m3_cache_support_valid; 6562 uint8_t m3_cache_support; 6563 uint8_t cal_filesys_support_valid; 6564 uint8_t cal_filesys_support; 6565 uint8_t cal_cache_support_valid; 6566 uint8_t cal_cache_support; 6567 uint8_t cal_done_valid; 6568 uint8_t cal_done; 6569 uint8_t mem_bucket_valid; 6570 uint32_t mem_bucket; 6571 uint8_t mem_cfg_mode_valid; 6572 uint8_t mem_cfg_mode; 6573 }; 6574 6575 struct qmi_wlanfw_host_cap_resp_msg_v01 { 6576 struct qmi_response_type_v01 resp; 6577 }; 6578 6579 #define ATH11K_HOST_VERSION_STRING "WIN" 6580 #define ATH11K_QMI_WLANFW_TIMEOUT_MS 10000 6581 #define ATH11K_QMI_MAX_BDF_FILE_NAME_SIZE 64 6582 #define ATH11K_QMI_CALDB_ADDRESS 0x4BA00000 6583 #define ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 128 6584 #define ATH11K_QMI_WLFW_SERVICE_ID_V01 0x45 6585 #define ATH11K_QMI_WLFW_SERVICE_VERS_V01 0x01 6586 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01 0x02 6587 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390 0x01 6588 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074 0x02 6589 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074 0x07 6590 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750 0x03 6591 #define ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32 6592 6593 #define ATH11K_QMI_RESP_LEN_MAX 8192 6594 #define ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52 6595 #define ATH11K_QMI_CALDB_SIZE 0x480000 6596 #define ATH11K_QMI_BDF_EXT_STR_LENGTH 0x20 6597 #define ATH11K_QMI_FW_MEM_REQ_SEGMENT_CNT 5 6598 6599 #define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035 6600 #define QMI_WLFW_RESPOND_MEM_RESP_V01 0x0036 6601 #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037 6602 #define QMI_WLFW_COLD_BOOT_CAL_DONE_IND_V01 0x003E 6603 #define QMI_WLFW_FW_READY_IND_V01 0x0021 6604 #define QMI_WLFW_FW_INIT_DONE_IND_V01 0x0038 6605 6606 #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144 6607 #define ATH11K_FIRMWARE_MODE_OFF 4 6608 #define ATH11K_COLD_BOOT_FW_RESET_DELAY (40 * HZ) 6609 6610 #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN 1824 6611 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN 888 6612 #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN 7 6613 #define QMI_WLANFW_REQUEST_MEM_IND_V01 0x0035 6614 #define QMI_WLANFW_RESPOND_MEM_REQ_V01 0x0036 6615 #define QMI_WLANFW_RESPOND_MEM_RESP_V01 0x0036 6616 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01 2 6617 6618 struct qmi_wlanfw_mem_cfg_s_v01 { 6619 uint64_t offset; 6620 uint32_t size; 6621 uint8_t secure_flag; 6622 }; 6623 6624 enum qmi_wlanfw_mem_type_enum_v01 { 6625 WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 6626 QMI_WLANFW_MEM_TYPE_MSA_V01 = 0, 6627 QMI_WLANFW_MEM_TYPE_DDR_V01 = 1, 6628 QMI_WLANFW_MEM_BDF_V01 = 2, 6629 QMI_WLANFW_MEM_M3_V01 = 3, 6630 QMI_WLANFW_MEM_CAL_V01 = 4, 6631 QMI_WLANFW_MEM_DPD_V01 = 5, 6632 WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 6633 }; 6634 6635 struct qmi_wlanfw_mem_seg_s_v01 { 6636 uint32_t size; 6637 enum qmi_wlanfw_mem_type_enum_v01 type; 6638 uint32_t mem_cfg_len; 6639 struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01]; 6640 }; 6641 6642 struct qmi_wlanfw_request_mem_ind_msg_v01 { 6643 uint32_t mem_seg_len; 6644 struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 6645 }; 6646 6647 struct qmi_wlanfw_mem_seg_resp_s_v01 { 6648 uint64_t addr; 6649 uint32_t size; 6650 enum qmi_wlanfw_mem_type_enum_v01 type; 6651 uint8_t restore; 6652 }; 6653 6654 struct qmi_wlanfw_respond_mem_req_msg_v01 { 6655 uint32_t mem_seg_len; 6656 struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 6657 }; 6658 6659 struct qmi_wlanfw_respond_mem_resp_msg_v01 { 6660 struct qmi_response_type_v01 resp; 6661 }; 6662 6663 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 { 6664 char placeholder; 6665 }; 6666 6667 struct qmi_wlanfw_fw_ready_ind_msg_v01 { 6668 char placeholder; 6669 }; 6670 6671 struct qmi_wlanfw_fw_cold_cal_done_ind_msg_v01 { 6672 char placeholder; 6673 }; 6674 6675 struct qmi_wlfw_fw_init_done_ind_msg_v01 { 6676 char placeholder; 6677 }; 6678 6679 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0 6680 #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN 235 6681 #define QMI_WLANFW_CAP_REQ_V01 0x0024 6682 #define QMI_WLANFW_CAP_RESP_V01 0x0024 6683 #define QMI_WLANFW_DEVICE_INFO_REQ_V01 0x004C 6684 #define QMI_WLANFW_DEVICE_INFO_REQ_MSG_V01_MAX_LEN 0 6685 6686 enum qmi_wlanfw_pipedir_enum_v01 { 6687 QMI_WLFW_PIPEDIR_NONE_V01 = 0, 6688 QMI_WLFW_PIPEDIR_IN_V01 = 1, 6689 QMI_WLFW_PIPEDIR_OUT_V01 = 2, 6690 QMI_WLFW_PIPEDIR_INOUT_V01 = 3, 6691 }; 6692 6693 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 { 6694 uint32_t pipe_num; 6695 uint32_t pipe_dir; 6696 uint32_t nentries; 6697 uint32_t nbytes_max; 6698 uint32_t flags; 6699 }; 6700 6701 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 { 6702 uint32_t service_id; 6703 uint32_t pipe_dir; 6704 uint32_t pipe_num; 6705 }; 6706 6707 struct qmi_wlanfw_shadow_reg_cfg_s_v01 { 6708 uint16_t id; 6709 uint16_t offset; 6710 }; 6711 6712 struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01 { 6713 uint32_t addr; 6714 }; 6715 6716 struct qmi_wlanfw_memory_region_info_s_v01 { 6717 uint64_t region_addr; 6718 uint32_t size; 6719 uint8_t secure_flag; 6720 }; 6721 6722 struct qmi_wlanfw_rf_chip_info_s_v01 { 6723 uint32_t chip_id; 6724 uint32_t chip_family; 6725 }; 6726 6727 struct qmi_wlanfw_rf_board_info_s_v01 { 6728 uint32_t board_id; 6729 }; 6730 6731 struct qmi_wlanfw_soc_info_s_v01 { 6732 uint32_t soc_id; 6733 }; 6734 6735 struct qmi_wlanfw_fw_version_info_s_v01 { 6736 uint32_t fw_version; 6737 char fw_build_timestamp[ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 6738 }; 6739 6740 enum qmi_wlanfw_cal_temp_id_enum_v01 { 6741 QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0, 6742 QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1, 6743 QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2, 6744 QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3, 6745 QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4, 6746 QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF, 6747 }; 6748 6749 struct qmi_wlanfw_cap_resp_msg_v01 { 6750 struct qmi_response_type_v01 resp; 6751 uint8_t chip_info_valid; 6752 struct qmi_wlanfw_rf_chip_info_s_v01 chip_info; 6753 uint8_t board_info_valid; 6754 struct qmi_wlanfw_rf_board_info_s_v01 board_info; 6755 uint8_t soc_info_valid; 6756 struct qmi_wlanfw_soc_info_s_v01 soc_info; 6757 uint8_t fw_version_info_valid; 6758 struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info; 6759 uint8_t fw_build_id_valid; 6760 char fw_build_id[ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 6761 uint8_t num_macs_valid; 6762 uint8_t num_macs; 6763 uint8_t voltage_mv_valid; 6764 uint32_t voltage_mv; 6765 uint8_t time_freq_hz_valid; 6766 uint32_t time_freq_hz; 6767 uint8_t otp_version_valid; 6768 uint32_t otp_version; 6769 uint8_t eeprom_read_timeout_valid; 6770 uint32_t eeprom_read_timeout; 6771 }; 6772 6773 struct qmi_wlanfw_cap_req_msg_v01 { 6774 char placeholder; 6775 }; 6776 6777 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6182 6778 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN 7 6779 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01 0x0025 6780 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01 0x0025 6781 /* TODO: Need to check with MCL and FW team that data can be pointer and 6782 * can be last element in structure 6783 */ 6784 struct qmi_wlanfw_bdf_download_req_msg_v01 { 6785 uint8_t valid; 6786 uint8_t file_id_valid; 6787 enum qmi_wlanfw_cal_temp_id_enum_v01 file_id; 6788 uint8_t total_size_valid; 6789 uint32_t total_size; 6790 uint8_t seg_id_valid; 6791 uint32_t seg_id; 6792 uint8_t data_valid; 6793 uint32_t data_len; 6794 uint8_t data[QMI_WLANFW_MAX_DATA_SIZE_V01]; 6795 uint8_t end_valid; 6796 uint8_t end; 6797 uint8_t bdf_type_valid; 6798 uint8_t bdf_type; 6799 }; 6800 6801 struct qmi_wlanfw_bdf_download_resp_msg_v01 { 6802 struct qmi_response_type_v01 resp; 6803 }; 6804 6805 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 6806 #define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 6807 #define QMI_WLANFW_M3_INFO_RESP_V01 0x003c 6808 #define QMI_WLANFW_M3_INFO_REQ_V01 0x003c 6809 6810 struct qmi_wlanfw_m3_info_req_msg_v01 { 6811 uint64_t addr; 6812 uint32_t size; 6813 }; 6814 6815 struct qmi_wlanfw_m3_info_resp_msg_v01 { 6816 struct qmi_response_type_v01 resp; 6817 }; 6818 6819 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN 11 6820 #define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN 7 6821 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN 803 6822 #define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN 7 6823 #define QMI_WLANFW_WLAN_INI_REQ_MSG_V01_MAX_LEN 4 6824 #define QMI_WLANFW_WLAN_MODE_REQ_V01 0x0022 6825 #define QMI_WLANFW_WLAN_MODE_RESP_V01 0x0022 6826 #define QMI_WLANFW_WLAN_CFG_REQ_V01 0x0023 6827 #define QMI_WLANFW_WLAN_CFG_RESP_V01 0x0023 6828 #define QMI_WLANFW_WLAN_INI_REQ_V01 0x002f 6829 #define QMI_WLANFW_WLAN_INI_RESP_V01 0x002f 6830 #define QMI_WLANFW_MAX_STR_LEN_V01 16 6831 #define QMI_WLANFW_MAX_NUM_CE_V01 12 6832 #define QMI_WLANFW_MAX_NUM_SVC_V01 24 6833 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01 24 6834 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01 36 6835 6836 struct qmi_wlanfw_wlan_mode_req_msg_v01 { 6837 uint32_t mode; 6838 uint8_t hw_debug_valid; 6839 uint8_t hw_debug; 6840 }; 6841 6842 struct qmi_wlanfw_wlan_mode_resp_msg_v01 { 6843 struct qmi_response_type_v01 resp; 6844 }; 6845 6846 struct qmi_wlanfw_wlan_cfg_req_msg_v01 { 6847 uint8_t host_version_valid; 6848 char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1]; 6849 uint8_t tgt_cfg_valid; 6850 uint32_t tgt_cfg_len; 6851 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 6852 tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01]; 6853 uint8_t svc_cfg_valid; 6854 uint32_t svc_cfg_len; 6855 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 6856 svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01]; 6857 uint8_t shadow_reg_valid; 6858 uint32_t shadow_reg_len; 6859 struct qmi_wlanfw_shadow_reg_cfg_s_v01 6860 shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01]; 6861 uint8_t shadow_reg_v2_valid; 6862 uint32_t shadow_reg_v2_len; 6863 struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01 6864 shadow_reg_v2[QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01]; 6865 }; 6866 6867 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 { 6868 struct qmi_response_type_v01 resp; 6869 }; 6870 6871 struct qmi_wlanfw_wlan_ini_req_msg_v01 { 6872 /* Must be set to true if enablefwlog is being passed */ 6873 uint8_t enablefwlog_valid; 6874 uint8_t enablefwlog; 6875 }; 6876 6877 struct qmi_wlanfw_wlan_ini_resp_msg_v01 { 6878 struct qmi_response_type_v01 resp; 6879 }; 6880 6881 enum ath11k_qmi_file_type { 6882 ATH11K_QMI_FILE_TYPE_BDF_GOLDEN, 6883 ATH11K_QMI_FILE_TYPE_CALDATA = 2, 6884 ATH11K_QMI_FILE_TYPE_EEPROM, 6885 ATH11K_QMI_MAX_FILE_TYPE, 6886 }; 6887 6888 enum ath11k_qmi_bdf_type { 6889 ATH11K_QMI_BDF_TYPE_BIN = 0, 6890 ATH11K_QMI_BDF_TYPE_ELF = 1, 6891 ATH11K_QMI_BDF_TYPE_REGDB = 4, 6892 }; 6893 6894 #define HAL_LINK_DESC_SIZE (32 << 2) 6895 #define HAL_LINK_DESC_ALIGN 128 6896 #define HAL_NUM_MPDUS_PER_LINK_DESC 6 6897 #define HAL_NUM_TX_MSDUS_PER_LINK_DESC 7 6898 #define HAL_NUM_RX_MSDUS_PER_LINK_DESC 6 6899 #define HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC 12 6900 #define HAL_MAX_AVAIL_BLK_RES 3 6901 6902 #define HAL_RING_BASE_ALIGN 8 6903 6904 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX 32704 6905 /* TODO: Check with hw team on the supported scatter buf size */ 6906 #define HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE 8 6907 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE (HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX - \ 6908 HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE) 6909 6910 #define HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX 48 6911 #define HAL_DSCP_TID_TBL_SIZE 24 6912 6913 /* calculate the register address from bar0 of shadow register x */ 6914 #define HAL_SHADOW_BASE_ADDR(sc) \ 6915 (sc->hw_params.regs->hal_shadow_base_addr) 6916 #define HAL_SHADOW_NUM_REGS 36 6917 #define HAL_HP_OFFSET_IN_REG_START 1 6918 #define HAL_OFFSET_FROM_HP_TO_TP 4 6919 6920 #define HAL_SHADOW_REG(sc, x) (HAL_SHADOW_BASE_ADDR(sc) + (4 * (x))) 6921 6922 /* SRNG registers are split into two groups R0 and R2 */ 6923 #define HAL_SRNG_REG_GRP_R0 0 6924 #define HAL_SRNG_REG_GRP_R2 1 6925 #define HAL_SRNG_NUM_REG_GRP 2 6926 6927 enum hal_srng_ring_id { 6928 HAL_SRNG_RING_ID_REO2SW1 = 0, 6929 HAL_SRNG_RING_ID_REO2SW2, 6930 HAL_SRNG_RING_ID_REO2SW3, 6931 HAL_SRNG_RING_ID_REO2SW4, 6932 HAL_SRNG_RING_ID_REO2TCL, 6933 HAL_SRNG_RING_ID_SW2REO, 6934 6935 HAL_SRNG_RING_ID_REO_CMD = 8, 6936 HAL_SRNG_RING_ID_REO_STATUS, 6937 6938 HAL_SRNG_RING_ID_SW2TCL1 = 16, 6939 HAL_SRNG_RING_ID_SW2TCL2, 6940 HAL_SRNG_RING_ID_SW2TCL3, 6941 HAL_SRNG_RING_ID_SW2TCL4, 6942 6943 HAL_SRNG_RING_ID_SW2TCL_CMD = 24, 6944 HAL_SRNG_RING_ID_TCL_STATUS, 6945 6946 HAL_SRNG_RING_ID_CE0_SRC = 32, 6947 HAL_SRNG_RING_ID_CE1_SRC, 6948 HAL_SRNG_RING_ID_CE2_SRC, 6949 HAL_SRNG_RING_ID_CE3_SRC, 6950 HAL_SRNG_RING_ID_CE4_SRC, 6951 HAL_SRNG_RING_ID_CE5_SRC, 6952 HAL_SRNG_RING_ID_CE6_SRC, 6953 HAL_SRNG_RING_ID_CE7_SRC, 6954 HAL_SRNG_RING_ID_CE8_SRC, 6955 HAL_SRNG_RING_ID_CE9_SRC, 6956 HAL_SRNG_RING_ID_CE10_SRC, 6957 HAL_SRNG_RING_ID_CE11_SRC, 6958 6959 HAL_SRNG_RING_ID_CE0_DST = 56, 6960 HAL_SRNG_RING_ID_CE1_DST, 6961 HAL_SRNG_RING_ID_CE2_DST, 6962 HAL_SRNG_RING_ID_CE3_DST, 6963 HAL_SRNG_RING_ID_CE4_DST, 6964 HAL_SRNG_RING_ID_CE5_DST, 6965 HAL_SRNG_RING_ID_CE6_DST, 6966 HAL_SRNG_RING_ID_CE7_DST, 6967 HAL_SRNG_RING_ID_CE8_DST, 6968 HAL_SRNG_RING_ID_CE9_DST, 6969 HAL_SRNG_RING_ID_CE10_DST, 6970 HAL_SRNG_RING_ID_CE11_DST, 6971 6972 HAL_SRNG_RING_ID_CE0_DST_STATUS = 80, 6973 HAL_SRNG_RING_ID_CE1_DST_STATUS, 6974 HAL_SRNG_RING_ID_CE2_DST_STATUS, 6975 HAL_SRNG_RING_ID_CE3_DST_STATUS, 6976 HAL_SRNG_RING_ID_CE4_DST_STATUS, 6977 HAL_SRNG_RING_ID_CE5_DST_STATUS, 6978 HAL_SRNG_RING_ID_CE6_DST_STATUS, 6979 HAL_SRNG_RING_ID_CE7_DST_STATUS, 6980 HAL_SRNG_RING_ID_CE8_DST_STATUS, 6981 HAL_SRNG_RING_ID_CE9_DST_STATUS, 6982 HAL_SRNG_RING_ID_CE10_DST_STATUS, 6983 HAL_SRNG_RING_ID_CE11_DST_STATUS, 6984 6985 HAL_SRNG_RING_ID_WBM_IDLE_LINK = 104, 6986 HAL_SRNG_RING_ID_WBM_SW_RELEASE, 6987 HAL_SRNG_RING_ID_WBM2SW0_RELEASE, 6988 HAL_SRNG_RING_ID_WBM2SW1_RELEASE, 6989 HAL_SRNG_RING_ID_WBM2SW2_RELEASE, 6990 HAL_SRNG_RING_ID_WBM2SW3_RELEASE, 6991 HAL_SRNG_RING_ID_WBM2SW4_RELEASE, 6992 6993 HAL_SRNG_RING_ID_UMAC_ID_END = 127, 6994 HAL_SRNG_RING_ID_LMAC1_ID_START, 6995 6996 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF = HAL_SRNG_RING_ID_LMAC1_ID_START, 6997 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF, 6998 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA2_BUF, 6999 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_STATBUF, 7000 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_STATBUF, 7001 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0, 7002 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1, 7003 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_DESC, 7004 HAL_SRNG_RING_ID_RXDMA_DIR_BUF, 7005 7006 HAL_SRNG_RING_ID_LMAC1_ID_END = 143 7007 }; 7008 7009 /* SRNG registers are split into two groups R0 and R2 */ 7010 #define HAL_SRNG_REG_GRP_R0 0 7011 #define HAL_SRNG_REG_GRP_R2 1 7012 #define HAL_SRNG_NUM_REG_GRP 2 7013 7014 #define HAL_SRNG_NUM_LMACS 3 7015 #define HAL_SRNG_REO_EXCEPTION HAL_SRNG_RING_ID_REO2SW1 7016 #define HAL_SRNG_RINGS_PER_LMAC (HAL_SRNG_RING_ID_LMAC1_ID_END - \ 7017 HAL_SRNG_RING_ID_LMAC1_ID_START) 7018 #define HAL_SRNG_NUM_LMAC_RINGS (HAL_SRNG_NUM_LMACS * HAL_SRNG_RINGS_PER_LMAC) 7019 #define HAL_SRNG_RING_ID_MAX (HAL_SRNG_RING_ID_UMAC_ID_END + \ 7020 HAL_SRNG_NUM_LMAC_RINGS) 7021 7022 #define HAL_RX_MAX_BA_WINDOW 256 7023 7024 #define HAL_DEFAULT_REO_TIMEOUT_USEC (40 * 1000) 7025 7026 /** 7027 * enum hal_reo_cmd_type: Enum for REO command type 7028 * @HAL_REO_CMD_GET_QUEUE_STATS: Get REO queue status/stats 7029 * @HAL_REO_CMD_FLUSH_QUEUE: Flush all frames in REO queue 7030 * @HAL_REO_CMD_FLUSH_CACHE: Flush descriptor entries in the cache 7031 * @HAL_REO_CMD_UNBLOCK_CACHE: Unblock a descriptor's address that was blocked 7032 * earlier with a 'REO_FLUSH_CACHE' command 7033 * @HAL_REO_CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list 7034 * @HAL_REO_CMD_UPDATE_RX_QUEUE: Update REO queue settings 7035 */ 7036 enum hal_reo_cmd_type { 7037 HAL_REO_CMD_GET_QUEUE_STATS = 0, 7038 HAL_REO_CMD_FLUSH_QUEUE = 1, 7039 HAL_REO_CMD_FLUSH_CACHE = 2, 7040 HAL_REO_CMD_UNBLOCK_CACHE = 3, 7041 HAL_REO_CMD_FLUSH_TIMEOUT_LIST = 4, 7042 HAL_REO_CMD_UPDATE_RX_QUEUE = 5, 7043 }; 7044 7045 /** 7046 * enum hal_reo_cmd_status: Enum for execution status of REO command 7047 * @HAL_REO_CMD_SUCCESS: Command has successfully executed 7048 * @HAL_REO_CMD_BLOCKED: Command could not be executed as the queue 7049 * or cache was blocked 7050 * @HAL_REO_CMD_FAILED: Command execution failed, could be due to 7051 * invalid queue desc 7052 * @HAL_REO_CMD_RESOURCE_BLOCKED: 7053 * @HAL_REO_CMD_DRAIN: 7054 */ 7055 enum hal_reo_cmd_status { 7056 HAL_REO_CMD_SUCCESS = 0, 7057 HAL_REO_CMD_BLOCKED = 1, 7058 HAL_REO_CMD_FAILED = 2, 7059 HAL_REO_CMD_RESOURCE_BLOCKED = 3, 7060 HAL_REO_CMD_DRAIN = 0xff, 7061 }; 7062 7063 /* Interrupt mitigation - Batch threshold in terms of number of frames */ 7064 #define HAL_SRNG_INT_BATCH_THRESHOLD_TX 256 7065 #define HAL_SRNG_INT_BATCH_THRESHOLD_RX 128 7066 #define HAL_SRNG_INT_BATCH_THRESHOLD_OTHER 1 7067 7068 /* Interrupt mitigation - timer threshold in us */ 7069 #define HAL_SRNG_INT_TIMER_THRESHOLD_TX 1000 7070 #define HAL_SRNG_INT_TIMER_THRESHOLD_RX 500 7071 #define HAL_SRNG_INT_TIMER_THRESHOLD_OTHER 256 7072 7073 /* WCSS Relative address */ 7074 #define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000 7075 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000 7076 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000 7077 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(sc) \ 7078 (sc->hw_params.regs->hal_seq_wcss_umac_ce0_src_reg) 7079 #define HAL_SEQ_WCSS_UMAC_CE0_DST_REG(sc) \ 7080 (sc->hw_params.regs->hal_seq_wcss_umac_ce0_dst_reg) 7081 #define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(sc) \ 7082 (sc->hw_params.regs->hal_seq_wcss_umac_ce1_src_reg) 7083 #define HAL_SEQ_WCSS_UMAC_CE1_DST_REG(sc) \ 7084 (sc->hw_params.regs->hal_seq_wcss_umac_ce1_dst_reg) 7085 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000 7086 7087 #define HAL_CE_WFSS_CE_REG_BASE 0x01b80000 7088 #define HAL_WLAON_REG_BASE 0x01f80000 7089 7090 /* SW2TCL(x) R0 ring configuration address */ 7091 #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000014 7092 #define HAL_TCL1_RING_DSCP_TID_MAP 0x0000002c 7093 #define HAL_TCL1_RING_BASE_LSB(sc) \ 7094 (sc->hw_params.regs->hal_tcl1_ring_base_lsb) 7095 #define HAL_TCL1_RING_BASE_MSB(sc) \ 7096 (sc->hw_params.regs->hal_tcl1_ring_base_msb) 7097 #define HAL_TCL1_RING_ID(sc) \ 7098 (sc->hw_params.regs->hal_tcl1_ring_id) 7099 #define HAL_TCL1_RING_MISC(sc) \ 7100 (sc->hw_params.regs->hal_tcl1_ring_misc) 7101 #define HAL_TCL1_RING_TP_ADDR_LSB(sc) \ 7102 (sc->hw_params.regs->hal_tcl1_ring_tp_addr_lsb) 7103 #define HAL_TCL1_RING_TP_ADDR_MSB(sc) \ 7104 (sc->hw_params.regs->hal_tcl1_ring_tp_addr_msb) 7105 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(sc) \ 7106 (sc->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix0) 7107 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(sc) \ 7108 (sc->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix1) 7109 #define HAL_TCL1_RING_MSI1_BASE_LSB(sc) \ 7110 (sc->hw_params.regs->hal_tcl1_ring_msi1_base_lsb) 7111 #define HAL_TCL1_RING_MSI1_BASE_MSB(sc) \ 7112 (sc->hw_params.regs->hal_tcl1_ring_msi1_base_msb) 7113 #define HAL_TCL1_RING_MSI1_DATA(sc) \ 7114 (sc->hw_params.regs->hal_tcl1_ring_msi1_data) 7115 #define HAL_TCL2_RING_BASE_LSB(sc) \ 7116 (sc->hw_params.regs->hal_tcl2_ring_base_lsb) 7117 #define HAL_TCL_RING_BASE_LSB(sc) \ 7118 (sc->hw_params.regs->hal_tcl_ring_base_lsb) 7119 7120 #define HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(sc) \ 7121 (HAL_TCL1_RING_MSI1_BASE_LSB(sc) - HAL_TCL1_RING_BASE_LSB(sc)) 7122 #define HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET(sc) \ 7123 (HAL_TCL1_RING_MSI1_BASE_MSB(sc) - HAL_TCL1_RING_BASE_LSB(sc)) 7124 #define HAL_TCL1_RING_MSI1_DATA_OFFSET(sc) \ 7125 (HAL_TCL1_RING_MSI1_DATA(sc) - HAL_TCL1_RING_BASE_LSB(sc)) 7126 #define HAL_TCL1_RING_BASE_MSB_OFFSET(sc) \ 7127 (HAL_TCL1_RING_BASE_MSB(sc) - HAL_TCL1_RING_BASE_LSB(sc)) 7128 #define HAL_TCL1_RING_ID_OFFSET(sc) \ 7129 (HAL_TCL1_RING_ID(sc) - HAL_TCL1_RING_BASE_LSB(sc)) 7130 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(sc) \ 7131 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(sc) - HAL_TCL1_RING_BASE_LSB(sc)) 7132 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(sc) \ 7133 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(sc) - \ 7134 HAL_TCL1_RING_BASE_LSB(sc)) 7135 #define HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(sc) \ 7136 (HAL_TCL1_RING_TP_ADDR_LSB(sc) - HAL_TCL1_RING_BASE_LSB(sc)) 7137 #define HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(sc) \ 7138 (HAL_TCL1_RING_TP_ADDR_MSB(sc) - HAL_TCL1_RING_BASE_LSB(sc)) 7139 #define HAL_TCL1_RING_MISC_OFFSET(sc) \ 7140 (HAL_TCL1_RING_MISC(sc) - HAL_TCL1_RING_BASE_LSB(sc)) 7141 7142 /* SW2TCL(x) R2 ring pointers (head/tail) address */ 7143 #define HAL_TCL1_RING_HP 0x00002000 7144 #define HAL_TCL1_RING_TP 0x00002004 7145 #define HAL_TCL2_RING_HP 0x00002008 7146 #define HAL_TCL_RING_HP 0x00002018 7147 7148 #define HAL_TCL1_RING_TP_OFFSET \ 7149 (HAL_TCL1_RING_TP - HAL_TCL1_RING_HP) 7150 7151 /* TCL STATUS ring address */ 7152 #define HAL_TCL_STATUS_RING_BASE_LSB(sc) \ 7153 (sc->hw_params.regs->hal_tcl_status_ring_base_lsb) 7154 #define HAL_TCL_STATUS_RING_HP 0x00002030 7155 7156 /* REO2SW(x) R0 ring configuration address */ 7157 #define HAL_REO1_GEN_ENABLE 0x00000000 7158 #define HAL_REO1_DEST_RING_CTRL_IX_0 0x00000004 7159 #define HAL_REO1_DEST_RING_CTRL_IX_1 0x00000008 7160 #define HAL_REO1_DEST_RING_CTRL_IX_2 0x0000000c 7161 #define HAL_REO1_DEST_RING_CTRL_IX_3 0x00000010 7162 #define HAL_REO1_MISC_CTL(sc) \ 7163 (sc->hw_params.regs->hal_reo1_misc_ctl) 7164 #define HAL_REO1_RING_BASE_LSB(sc) \ 7165 (sc->hw_params.regs->hal_reo1_ring_base_lsb) 7166 #define HAL_REO1_RING_BASE_MSB(sc) \ 7167 (sc->hw_params.regs->hal_reo1_ring_base_msb) 7168 #define HAL_REO1_RING_ID(sc) \ 7169 (sc->hw_params.regs->hal_reo1_ring_id) 7170 #define HAL_REO1_RING_MISC(sc) \ 7171 (sc->hw_params.regs->hal_reo1_ring_misc) 7172 #define HAL_REO1_RING_HP_ADDR_LSB(sc) \ 7173 (sc->hw_params.regs->hal_reo1_ring_hp_addr_lsb) 7174 #define HAL_REO1_RING_HP_ADDR_MSB(sc) \ 7175 (sc->hw_params.regs->hal_reo1_ring_hp_addr_msb) 7176 #define HAL_REO1_RING_PRODUCER_INT_SETUP(sc) \ 7177 (sc->hw_params.regs->hal_reo1_ring_producer_int_setup) 7178 #define HAL_REO1_RING_MSI1_BASE_LSB(sc) \ 7179 (sc->hw_params.regs->hal_reo1_ring_msi1_base_lsb) 7180 #define HAL_REO1_RING_MSI1_BASE_MSB(sc) \ 7181 (sc->hw_params.regs->hal_reo1_ring_msi1_base_msb) 7182 #define HAL_REO1_RING_MSI1_DATA(sc) \ 7183 (sc->hw_params.regs->hal_reo1_ring_msi1_data) 7184 #define HAL_REO2_RING_BASE_LSB(sc) \ 7185 (sc->hw_params.regs->hal_reo2_ring_base_lsb) 7186 #define HAL_REO1_AGING_THRESH_IX_0(sc) \ 7187 (sc->hw_params.regs->hal_reo1_aging_thresh_ix_0) 7188 #define HAL_REO1_AGING_THRESH_IX_1(sc) \ 7189 (sc->hw_params.regs->hal_reo1_aging_thresh_ix_1) 7190 #define HAL_REO1_AGING_THRESH_IX_2(sc) \ 7191 (sc->hw_params.regs->hal_reo1_aging_thresh_ix_2) 7192 #define HAL_REO1_AGING_THRESH_IX_3(sc) \ 7193 (sc->hw_params.regs->hal_reo1_aging_thresh_ix_3) 7194 7195 #define HAL_REO1_RING_MSI1_BASE_LSB_OFFSET(sc) \ 7196 (HAL_REO1_RING_MSI1_BASE_LSB(sc) - HAL_REO1_RING_BASE_LSB(sc)) 7197 #define HAL_REO1_RING_MSI1_BASE_MSB_OFFSET(sc) \ 7198 (HAL_REO1_RING_MSI1_BASE_MSB(sc) - HAL_REO1_RING_BASE_LSB(sc)) 7199 #define HAL_REO1_RING_MSI1_DATA_OFFSET(sc) \ 7200 (HAL_REO1_RING_MSI1_DATA(sc) - HAL_REO1_RING_BASE_LSB(sc)) 7201 #define HAL_REO1_RING_BASE_MSB_OFFSET(sc) \ 7202 (HAL_REO1_RING_BASE_MSB(sc) - HAL_REO1_RING_BASE_LSB(sc)) 7203 #define HAL_REO1_RING_ID_OFFSET(sc) (HAL_REO1_RING_ID(sc) - \ 7204 HAL_REO1_RING_BASE_LSB(sc)) 7205 #define HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET(sc) \ 7206 (HAL_REO1_RING_PRODUCER_INT_SETUP(sc) - \ 7207 HAL_REO1_RING_BASE_LSB(sc)) 7208 #define HAL_REO1_RING_HP_ADDR_LSB_OFFSET(sc) \ 7209 (HAL_REO1_RING_HP_ADDR_LSB(sc) - HAL_REO1_RING_BASE_LSB(sc)) 7210 #define HAL_REO1_RING_HP_ADDR_MSB_OFFSET(sc) \ 7211 (HAL_REO1_RING_HP_ADDR_MSB(sc) - HAL_REO1_RING_BASE_LSB(sc)) 7212 #define HAL_REO1_RING_MISC_OFFSET(sc) \ 7213 (HAL_REO1_RING_MISC(sc) - HAL_REO1_RING_BASE_LSB(sc)) 7214 7215 /* REO2SW(x) R2 ring pointers (head/tail) address */ 7216 #define HAL_REO1_RING_HP(sc) \ 7217 (sc->hw_params.regs->hal_reo1_ring_hp) 7218 #define HAL_REO1_RING_TP(sc) \ 7219 (sc->hw_params.regs->hal_reo1_ring_tp) 7220 #define HAL_REO2_RING_HP(sc) \ 7221 (sc->hw_params.regs->hal_reo2_ring_hp) 7222 7223 #define HAL_REO1_RING_TP_OFFSET(sc) \ 7224 (HAL_REO1_RING_TP(sc) - HAL_REO1_RING_HP(sc)) 7225 7226 /* REO2TCL R0 ring configuration address */ 7227 #define HAL_REO_TCL_RING_BASE_LSB(sc) \ 7228 (sc->hw_params.regs->hal_reo_tcl_ring_base_lsb) 7229 7230 /* REO2TCL R2 ring pointer (head/tail) address */ 7231 #define HAL_REO_TCL_RING_HP(sc) \ 7232 (sc->hw_params.regs->hal_reo_tcl_ring_hp) 7233 7234 /* REO CMD R0 address */ 7235 #define HAL_REO_CMD_RING_BASE_LSB(sc) \ 7236 (sc->hw_params.regs->hal_reo_cmd_ring_base_lsb) 7237 7238 /* REO CMD R2 address */ 7239 #define HAL_REO_CMD_HP(sc) \ 7240 (sc->hw_params.regs->hal_reo_cmd_ring_hp) 7241 7242 /* SW2REO R0 address */ 7243 #define HAL_SW2REO_RING_BASE_LSB(sc) \ 7244 (sc->hw_params.regs->hal_sw2reo_ring_base_lsb) 7245 7246 /* SW2REO R2 address */ 7247 #define HAL_SW2REO_RING_HP(sc) \ 7248 (sc->hw_params.regs->hal_sw2reo_ring_hp) 7249 7250 /* CE ring R0 address */ 7251 #define HAL_CE_DST_RING_BASE_LSB 0x00000000 7252 #define HAL_CE_DST_STATUS_RING_BASE_LSB 0x00000058 7253 #define HAL_CE_DST_RING_CTRL 0x000000b0 7254 7255 /* CE ring R2 address */ 7256 #define HAL_CE_DST_RING_HP 0x00000400 7257 #define HAL_CE_DST_STATUS_RING_HP 0x00000408 7258 7259 /* REO status address */ 7260 #define HAL_REO_STATUS_RING_BASE_LSB(sc) \ 7261 (sc->hw_params.regs->hal_reo_status_ring_base_lsb) 7262 #define HAL_REO_STATUS_HP(sc) \ 7263 (sc->hw_params.regs->hal_reo_status_hp) 7264 7265 /* WBM Idle R0 address */ 7266 #define HAL_WBM_IDLE_LINK_RING_BASE_LSB(x) \ 7267 (sc->hw_params.regs->hal_wbm_idle_link_ring_base_lsb) 7268 #define HAL_WBM_IDLE_LINK_RING_MISC_ADDR(x) \ 7269 (sc->hw_params.regs->hal_wbm_idle_link_ring_misc) 7270 #define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR 0x00000048 7271 #define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR 0x0000004c 7272 #define HAL_WBM_SCATTERED_RING_BASE_LSB 0x00000058 7273 #define HAL_WBM_SCATTERED_RING_BASE_MSB 0x0000005c 7274 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0 0x00000068 7275 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1 0x0000006c 7276 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0 0x00000078 7277 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1 0x0000007c 7278 #define HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR 0x00000084 7279 7280 /* WBM Idle R2 address */ 7281 #define HAL_WBM_IDLE_LINK_RING_HP 0x000030b0 7282 7283 /* SW2WBM R0 release address */ 7284 #define HAL_WBM_RELEASE_RING_BASE_LSB(x) \ 7285 (sc->hw_params.regs->hal_wbm_release_ring_base_lsb) 7286 7287 /* SW2WBM R2 release address */ 7288 #define HAL_WBM_RELEASE_RING_HP 0x00003018 7289 7290 /* WBM2SW R0 release address */ 7291 #define HAL_WBM0_RELEASE_RING_BASE_LSB(x) \ 7292 (sc->hw_params.regs->hal_wbm0_release_ring_base_lsb) 7293 #define HAL_WBM1_RELEASE_RING_BASE_LSB(x) \ 7294 (sc->hw_params.regs->hal_wbm1_release_ring_base_lsb) 7295 7296 /* WBM2SW R2 release address */ 7297 #define HAL_WBM0_RELEASE_RING_HP 0x000030c0 7298 #define HAL_WBM1_RELEASE_RING_HP 0x000030c8 7299 7300 /* TCL ring field mask and offset */ 7301 #define HAL_TCL1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 7302 #define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 7303 #define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 7304 #define HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE BIT(1) 7305 #define HAL_TCL1_RING_MISC_MSI_SWAP BIT(3) 7306 #define HAL_TCL1_RING_MISC_HOST_FW_SWAP BIT(4) 7307 #define HAL_TCL1_RING_MISC_DATA_TLV_SWAP BIT(5) 7308 #define HAL_TCL1_RING_MISC_SRNG_ENABLE BIT(6) 7309 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD GENMASK(31, 16) 7310 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0) 7311 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD GENMASK(15, 0) 7312 #define HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 7313 #define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 7314 #define HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN BIT(17) 7315 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP GENMASK(31, 0) 7316 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0 GENMASK(2, 0) 7317 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1 GENMASK(5, 3) 7318 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2 GENMASK(8, 6) 7319 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3 GENMASK(11, 9) 7320 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4 GENMASK(14, 12) 7321 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5 GENMASK(17, 15) 7322 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6 GENMASK(20, 18) 7323 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7 GENMASK(23, 21) 7324 7325 /* REO ring field mask and offset */ 7326 #define HAL_REO1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 7327 #define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 7328 #define HAL_REO1_RING_ID_RING_ID GENMASK(15, 8) 7329 #define HAL_REO1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 7330 #define HAL_REO1_RING_MISC_MSI_SWAP BIT(3) 7331 #define HAL_REO1_RING_MISC_HOST_FW_SWAP BIT(4) 7332 #define HAL_REO1_RING_MISC_DATA_TLV_SWAP BIT(5) 7333 #define HAL_REO1_RING_MISC_SRNG_ENABLE BIT(6) 7334 #define HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD GENMASK(31, 16) 7335 #define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0) 7336 #define HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 7337 #define HAL_REO1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 7338 #define HAL_REO1_GEN_ENABLE_FRAG_DST_RING GENMASK(25, 23) 7339 #define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE BIT(2) 7340 #define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE BIT(3) 7341 #define HAL_REO1_MISC_CTL_FRAGMENT_DST_RING GENMASK(20, 17) 7342 7343 /* CE ring bit field mask and shift */ 7344 #define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0) 7345 7346 #define HAL_ADDR_LSB_REG_MASK 0xffffffff 7347 7348 #define HAL_ADDR_MSB_REG_SHIFT 32 7349 7350 /* WBM ring bit field mask and shift */ 7351 #define HAL_WBM_LINK_DESC_IDLE_LIST_MODE BIT(1) 7352 #define HAL_WBM_SCATTER_BUFFER_SIZE GENMASK(10, 2) 7353 #define HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST GENMASK(31, 16) 7354 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32 GENMASK(7, 0) 7355 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG GENMASK(31, 8) 7356 7357 #define HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1 GENMASK(20, 8) 7358 #define HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1 GENMASK(20, 8) 7359 7360 #define BASE_ADDR_MATCH_TAG_VAL 0x5 7361 7362 #define HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE 0x000fffff 7363 #define HAL_REO_REO2TCL_RING_BASE_MSB_RING_SIZE 0x000fffff 7364 #define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE 0x0000ffff 7365 #define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE 0x0000ffff 7366 #define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 7367 #define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE 0x000fffff 7368 #define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE 0x000fffff 7369 #define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 7370 #define HAL_CE_SRC_RING_BASE_MSB_RING_SIZE 0x0000ffff 7371 #define HAL_CE_DST_RING_BASE_MSB_RING_SIZE 0x0000ffff 7372 #define HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 7373 #define HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE 0x0000ffff 7374 #define HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE 0x0000ffff 7375 #define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff 7376 #define HAL_RXDMA_RING_MAX_SIZE 0x0000ffff 7377 7378 /* IPQ5018 ce registers */ 7379 #define HAL_IPQ5018_CE_WFSS_REG_BASE 0x08400000 7380 #define HAL_IPQ5018_CE_SIZE 0x200000 7381 7382 #define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0) 7383 7384 #define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0) 7385 #define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(10, 8) 7386 #define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 11) 7387 7388 struct ath11k_buffer_addr { 7389 uint32_t info0; 7390 uint32_t info1; 7391 } __packed; 7392 7393 /* ath11k_buffer_addr 7394 * 7395 * info0 7396 * Address (lower 32 bits) of the msdu buffer or msdu extension 7397 * descriptor or Link descriptor 7398 * 7399 * addr 7400 * Address (upper 8 bits) of the msdu buffer or msdu extension 7401 * descriptor or Link descriptor 7402 * 7403 * return_buffer_manager (RBM) 7404 * Consumer: WBM 7405 * Producer: SW/FW 7406 * Indicates to which buffer manager the buffer or MSDU_EXTENSION 7407 * descriptor or link descriptor that is being pointed to shall be 7408 * returned after the frame has been processed. It is used by WBM 7409 * for routing purposes. 7410 * 7411 * Values are defined in enum %HAL_RX_BUF_RBM_ 7412 * 7413 * sw_buffer_cookie 7414 * Cookie field exclusively used by SW. HW ignores the contents, 7415 * accept that it passes the programmed value on to other 7416 * descriptors together with the physical address. 7417 * 7418 * Field can be used by SW to for example associate the buffers 7419 * physical address with the virtual address. 7420 */ 7421 7422 enum hal_tlv_tag { 7423 HAL_MACTX_CBF_START = 0 /* 0x0 */, 7424 HAL_PHYRX_DATA = 1 /* 0x1 */, 7425 HAL_PHYRX_CBF_DATA_RESP = 2 /* 0x2 */, 7426 HAL_PHYRX_ABORT_REQUEST = 3 /* 0x3 */, 7427 HAL_PHYRX_USER_ABORT_NOTIFICATION = 4 /* 0x4 */, 7428 HAL_MACTX_DATA_RESP = 5 /* 0x5 */, 7429 HAL_MACTX_CBF_DATA = 6 /* 0x6 */, 7430 HAL_MACTX_CBF_DONE = 7 /* 0x7 */, 7431 HAL_MACRX_CBF_READ_REQUEST = 8 /* 0x8 */, 7432 HAL_MACRX_CBF_DATA_REQUEST = 9 /* 0x9 */, 7433 HAL_MACRX_EXPECT_NDP_RECEPTION = 10 /* 0xa */, 7434 HAL_MACRX_FREEZE_CAPTURE_CHANNEL = 11 /* 0xb */, 7435 HAL_MACRX_NDP_TIMEOUT = 12 /* 0xc */, 7436 HAL_MACRX_ABORT_ACK = 13 /* 0xd */, 7437 HAL_MACRX_REQ_IMPLICIT_FB = 14 /* 0xe */, 7438 HAL_MACRX_CHAIN_MASK = 15 /* 0xf */, 7439 HAL_MACRX_NAP_USER = 16 /* 0x10 */, 7440 HAL_MACRX_ABORT_REQUEST = 17 /* 0x11 */, 7441 HAL_PHYTX_OTHER_TRANSMIT_INFO16 = 18 /* 0x12 */, 7442 HAL_PHYTX_ABORT_ACK = 19 /* 0x13 */, 7443 HAL_PHYTX_ABORT_REQUEST = 20 /* 0x14 */, 7444 HAL_PHYTX_PKT_END = 21 /* 0x15 */, 7445 HAL_PHYTX_PPDU_HEADER_INFO_REQUEST = 22 /* 0x16 */, 7446 HAL_PHYTX_REQUEST_CTRL_INFO = 23 /* 0x17 */, 7447 HAL_PHYTX_DATA_REQUEST = 24 /* 0x18 */, 7448 HAL_PHYTX_BF_CV_LOADING_DONE = 25 /* 0x19 */, 7449 HAL_PHYTX_NAP_ACK = 26 /* 0x1a */, 7450 HAL_PHYTX_NAP_DONE = 27 /* 0x1b */, 7451 HAL_PHYTX_OFF_ACK = 28 /* 0x1c */, 7452 HAL_PHYTX_ON_ACK = 29 /* 0x1d */, 7453 HAL_PHYTX_SYNTH_OFF_ACK = 30 /* 0x1e */, 7454 HAL_PHYTX_DEBUG16 = 31 /* 0x1f */, 7455 HAL_MACTX_ABORT_REQUEST = 32 /* 0x20 */, 7456 HAL_MACTX_ABORT_ACK = 33 /* 0x21 */, 7457 HAL_MACTX_PKT_END = 34 /* 0x22 */, 7458 HAL_MACTX_PRE_PHY_DESC = 35 /* 0x23 */, 7459 HAL_MACTX_BF_PARAMS_COMMON = 36 /* 0x24 */, 7460 HAL_MACTX_BF_PARAMS_PER_USER = 37 /* 0x25 */, 7461 HAL_MACTX_PREFETCH_CV = 38 /* 0x26 */, 7462 HAL_MACTX_USER_DESC_COMMON = 39 /* 0x27 */, 7463 HAL_MACTX_USER_DESC_PER_USER = 40 /* 0x28 */, 7464 HAL_EXAMPLE_USER_TLV_16 = 41 /* 0x29 */, 7465 HAL_EXAMPLE_TLV_16 = 42 /* 0x2a */, 7466 HAL_MACTX_PHY_OFF = 43 /* 0x2b */, 7467 HAL_MACTX_PHY_ON = 44 /* 0x2c */, 7468 HAL_MACTX_SYNTH_OFF = 45 /* 0x2d */, 7469 HAL_MACTX_EXPECT_CBF_COMMON = 46 /* 0x2e */, 7470 HAL_MACTX_EXPECT_CBF_PER_USER = 47 /* 0x2f */, 7471 HAL_MACTX_PHY_DESC = 48 /* 0x30 */, 7472 HAL_MACTX_L_SIG_A = 49 /* 0x31 */, 7473 HAL_MACTX_L_SIG_B = 50 /* 0x32 */, 7474 HAL_MACTX_HT_SIG = 51 /* 0x33 */, 7475 HAL_MACTX_VHT_SIG_A = 52 /* 0x34 */, 7476 HAL_MACTX_VHT_SIG_B_SU20 = 53 /* 0x35 */, 7477 HAL_MACTX_VHT_SIG_B_SU40 = 54 /* 0x36 */, 7478 HAL_MACTX_VHT_SIG_B_SU80 = 55 /* 0x37 */, 7479 HAL_MACTX_VHT_SIG_B_SU160 = 56 /* 0x38 */, 7480 HAL_MACTX_VHT_SIG_B_MU20 = 57 /* 0x39 */, 7481 HAL_MACTX_VHT_SIG_B_MU40 = 58 /* 0x3a */, 7482 HAL_MACTX_VHT_SIG_B_MU80 = 59 /* 0x3b */, 7483 HAL_MACTX_VHT_SIG_B_MU160 = 60 /* 0x3c */, 7484 HAL_MACTX_SERVICE = 61 /* 0x3d */, 7485 HAL_MACTX_HE_SIG_A_SU = 62 /* 0x3e */, 7486 HAL_MACTX_HE_SIG_A_MU_DL = 63 /* 0x3f */, 7487 HAL_MACTX_HE_SIG_A_MU_UL = 64 /* 0x40 */, 7488 HAL_MACTX_HE_SIG_B1_MU = 65 /* 0x41 */, 7489 HAL_MACTX_HE_SIG_B2_MU = 66 /* 0x42 */, 7490 HAL_MACTX_HE_SIG_B2_OFDMA = 67 /* 0x43 */, 7491 HAL_MACTX_DELETE_CV = 68 /* 0x44 */, 7492 HAL_MACTX_MU_UPLINK_COMMON = 69 /* 0x45 */, 7493 HAL_MACTX_MU_UPLINK_USER_SETUP = 70 /* 0x46 */, 7494 HAL_MACTX_OTHER_TRANSMIT_INFO = 71 /* 0x47 */, 7495 HAL_MACTX_PHY_NAP = 72 /* 0x48 */, 7496 HAL_MACTX_DEBUG = 73 /* 0x49 */, 7497 HAL_PHYRX_ABORT_ACK = 74 /* 0x4a */, 7498 HAL_PHYRX_GENERATED_CBF_DETAILS = 75 /* 0x4b */, 7499 HAL_PHYRX_RSSI_LEGACY = 76 /* 0x4c */, 7500 HAL_PHYRX_RSSI_HT = 77 /* 0x4d */, 7501 HAL_PHYRX_USER_INFO = 78 /* 0x4e */, 7502 HAL_PHYRX_PKT_END = 79 /* 0x4f */, 7503 HAL_PHYRX_DEBUG = 80 /* 0x50 */, 7504 HAL_PHYRX_CBF_TRANSFER_DONE = 81 /* 0x51 */, 7505 HAL_PHYRX_CBF_TRANSFER_ABORT = 82 /* 0x52 */, 7506 HAL_PHYRX_L_SIG_A = 83 /* 0x53 */, 7507 HAL_PHYRX_L_SIG_B = 84 /* 0x54 */, 7508 HAL_PHYRX_HT_SIG = 85 /* 0x55 */, 7509 HAL_PHYRX_VHT_SIG_A = 86 /* 0x56 */, 7510 HAL_PHYRX_VHT_SIG_B_SU20 = 87 /* 0x57 */, 7511 HAL_PHYRX_VHT_SIG_B_SU40 = 88 /* 0x58 */, 7512 HAL_PHYRX_VHT_SIG_B_SU80 = 89 /* 0x59 */, 7513 HAL_PHYRX_VHT_SIG_B_SU160 = 90 /* 0x5a */, 7514 HAL_PHYRX_VHT_SIG_B_MU20 = 91 /* 0x5b */, 7515 HAL_PHYRX_VHT_SIG_B_MU40 = 92 /* 0x5c */, 7516 HAL_PHYRX_VHT_SIG_B_MU80 = 93 /* 0x5d */, 7517 HAL_PHYRX_VHT_SIG_B_MU160 = 94 /* 0x5e */, 7518 HAL_PHYRX_HE_SIG_A_SU = 95 /* 0x5f */, 7519 HAL_PHYRX_HE_SIG_A_MU_DL = 96 /* 0x60 */, 7520 HAL_PHYRX_HE_SIG_A_MU_UL = 97 /* 0x61 */, 7521 HAL_PHYRX_HE_SIG_B1_MU = 98 /* 0x62 */, 7522 HAL_PHYRX_HE_SIG_B2_MU = 99 /* 0x63 */, 7523 HAL_PHYRX_HE_SIG_B2_OFDMA = 100 /* 0x64 */, 7524 HAL_PHYRX_OTHER_RECEIVE_INFO = 101 /* 0x65 */, 7525 HAL_PHYRX_COMMON_USER_INFO = 102 /* 0x66 */, 7526 HAL_PHYRX_DATA_DONE = 103 /* 0x67 */, 7527 HAL_RECEIVE_RSSI_INFO = 104 /* 0x68 */, 7528 HAL_RECEIVE_USER_INFO = 105 /* 0x69 */, 7529 HAL_MIMO_CONTROL_INFO = 106 /* 0x6a */, 7530 HAL_RX_LOCATION_INFO = 107 /* 0x6b */, 7531 HAL_COEX_TX_REQ = 108 /* 0x6c */, 7532 HAL_DUMMY = 109 /* 0x6d */, 7533 HAL_RX_TIMING_OFFSET_INFO = 110 /* 0x6e */, 7534 HAL_EXAMPLE_TLV_32_NAME = 111 /* 0x6f */, 7535 HAL_MPDU_LIMIT = 112 /* 0x70 */, 7536 HAL_NA_LENGTH_END = 113 /* 0x71 */, 7537 HAL_OLE_BUF_STATUS = 114 /* 0x72 */, 7538 HAL_PCU_PPDU_SETUP_DONE = 115 /* 0x73 */, 7539 HAL_PCU_PPDU_SETUP_END = 116 /* 0x74 */, 7540 HAL_PCU_PPDU_SETUP_INIT = 117 /* 0x75 */, 7541 HAL_PCU_PPDU_SETUP_START = 118 /* 0x76 */, 7542 HAL_PDG_FES_SETUP = 119 /* 0x77 */, 7543 HAL_PDG_RESPONSE = 120 /* 0x78 */, 7544 HAL_PDG_TX_REQ = 121 /* 0x79 */, 7545 HAL_SCH_WAIT_INSTR = 122 /* 0x7a */, 7546 HAL_SCHEDULER_TLV = 123 /* 0x7b */, 7547 HAL_TQM_FLOW_EMPTY_STATUS = 124 /* 0x7c */, 7548 HAL_TQM_FLOW_NOT_EMPTY_STATUS = 125 /* 0x7d */, 7549 HAL_TQM_GEN_MPDU_LENGTH_LIST = 126 /* 0x7e */, 7550 HAL_TQM_GEN_MPDU_LENGTH_LIST_STATUS = 127 /* 0x7f */, 7551 HAL_TQM_GEN_MPDUS = 128 /* 0x80 */, 7552 HAL_TQM_GEN_MPDUS_STATUS = 129 /* 0x81 */, 7553 HAL_TQM_REMOVE_MPDU = 130 /* 0x82 */, 7554 HAL_TQM_REMOVE_MPDU_STATUS = 131 /* 0x83 */, 7555 HAL_TQM_REMOVE_MSDU = 132 /* 0x84 */, 7556 HAL_TQM_REMOVE_MSDU_STATUS = 133 /* 0x85 */, 7557 HAL_TQM_UPDATE_TX_MPDU_COUNT = 134 /* 0x86 */, 7558 HAL_TQM_WRITE_CMD = 135 /* 0x87 */, 7559 HAL_OFDMA_TRIGGER_DETAILS = 136 /* 0x88 */, 7560 HAL_TX_DATA = 137 /* 0x89 */, 7561 HAL_TX_FES_SETUP = 138 /* 0x8a */, 7562 HAL_RX_PACKET = 139 /* 0x8b */, 7563 HAL_EXPECTED_RESPONSE = 140 /* 0x8c */, 7564 HAL_TX_MPDU_END = 141 /* 0x8d */, 7565 HAL_TX_MPDU_START = 142 /* 0x8e */, 7566 HAL_TX_MSDU_END = 143 /* 0x8f */, 7567 HAL_TX_MSDU_START = 144 /* 0x90 */, 7568 HAL_TX_SW_MODE_SETUP = 145 /* 0x91 */, 7569 HAL_TXPCU_BUFFER_STATUS = 146 /* 0x92 */, 7570 HAL_TXPCU_USER_BUFFER_STATUS = 147 /* 0x93 */, 7571 HAL_DATA_TO_TIME_CONFIG = 148 /* 0x94 */, 7572 HAL_EXAMPLE_USER_TLV_32 = 149 /* 0x95 */, 7573 HAL_MPDU_INFO = 150 /* 0x96 */, 7574 HAL_PDG_USER_SETUP = 151 /* 0x97 */, 7575 HAL_TX_11AH_SETUP = 152 /* 0x98 */, 7576 HAL_REO_UPDATE_RX_REO_QUEUE_STATUS = 153 /* 0x99 */, 7577 HAL_TX_PEER_ENTRY = 154 /* 0x9a */, 7578 HAL_TX_RAW_OR_NATIVE_FRAME_SETUP = 155 /* 0x9b */, 7579 HAL_EXAMPLE_STRUCT_NAME = 156 /* 0x9c */, 7580 HAL_PCU_PPDU_SETUP_END_INFO = 157 /* 0x9d */, 7581 HAL_PPDU_RATE_SETTING = 158 /* 0x9e */, 7582 HAL_PROT_RATE_SETTING = 159 /* 0x9f */, 7583 HAL_RX_MPDU_DETAILS = 160 /* 0xa0 */, 7584 HAL_EXAMPLE_USER_TLV_42 = 161 /* 0xa1 */, 7585 HAL_RX_MSDU_LINK = 162 /* 0xa2 */, 7586 HAL_RX_REO_QUEUE = 163 /* 0xa3 */, 7587 HAL_ADDR_SEARCH_ENTRY = 164 /* 0xa4 */, 7588 HAL_SCHEDULER_CMD = 165 /* 0xa5 */, 7589 HAL_TX_FLUSH = 166 /* 0xa6 */, 7590 HAL_TQM_ENTRANCE_RING = 167 /* 0xa7 */, 7591 HAL_TX_DATA_WORD = 168 /* 0xa8 */, 7592 HAL_TX_MPDU_DETAILS = 169 /* 0xa9 */, 7593 HAL_TX_MPDU_LINK = 170 /* 0xaa */, 7594 HAL_TX_MPDU_LINK_PTR = 171 /* 0xab */, 7595 HAL_TX_MPDU_QUEUE_HEAD = 172 /* 0xac */, 7596 HAL_TX_MPDU_QUEUE_EXT = 173 /* 0xad */, 7597 HAL_TX_MPDU_QUEUE_EXT_PTR = 174 /* 0xae */, 7598 HAL_TX_MSDU_DETAILS = 175 /* 0xaf */, 7599 HAL_TX_MSDU_EXTENSION = 176 /* 0xb0 */, 7600 HAL_TX_MSDU_FLOW = 177 /* 0xb1 */, 7601 HAL_TX_MSDU_LINK = 178 /* 0xb2 */, 7602 HAL_TX_MSDU_LINK_ENTRY_PTR = 179 /* 0xb3 */, 7603 HAL_RESPONSE_RATE_SETTING = 180 /* 0xb4 */, 7604 HAL_TXPCU_BUFFER_BASICS = 181 /* 0xb5 */, 7605 HAL_UNIFORM_DESCRIPTOR_HEADER = 182 /* 0xb6 */, 7606 HAL_UNIFORM_TQM_CMD_HEADER = 183 /* 0xb7 */, 7607 HAL_UNIFORM_TQM_STATUS_HEADER = 184 /* 0xb8 */, 7608 HAL_USER_RATE_SETTING = 185 /* 0xb9 */, 7609 HAL_WBM_BUFFER_RING = 186 /* 0xba */, 7610 HAL_WBM_LINK_DESCRIPTOR_RING = 187 /* 0xbb */, 7611 HAL_WBM_RELEASE_RING = 188 /* 0xbc */, 7612 HAL_TX_FLUSH_REQ = 189 /* 0xbd */, 7613 HAL_RX_MSDU_DETAILS = 190 /* 0xbe */, 7614 HAL_TQM_WRITE_CMD_STATUS = 191 /* 0xbf */, 7615 HAL_TQM_GET_MPDU_QUEUE_STATS = 192 /* 0xc0 */, 7616 HAL_TQM_GET_MSDU_FLOW_STATS = 193 /* 0xc1 */, 7617 HAL_EXAMPLE_USER_CTLV_32 = 194 /* 0xc2 */, 7618 HAL_TX_FES_STATUS_START = 195 /* 0xc3 */, 7619 HAL_TX_FES_STATUS_USER_PPDU = 196 /* 0xc4 */, 7620 HAL_TX_FES_STATUS_USER_RESPONSE = 197 /* 0xc5 */, 7621 HAL_TX_FES_STATUS_END = 198 /* 0xc6 */, 7622 HAL_RX_TRIG_INFO = 199 /* 0xc7 */, 7623 HAL_RXPCU_TX_SETUP_CLEAR = 200 /* 0xc8 */, 7624 HAL_RX_FRAME_BITMAP_REQ = 201 /* 0xc9 */, 7625 HAL_RX_FRAME_BITMAP_ACK = 202 /* 0xca */, 7626 HAL_COEX_RX_STATUS = 203 /* 0xcb */, 7627 HAL_RX_START_PARAM = 204 /* 0xcc */, 7628 HAL_RX_PPDU_START = 205 /* 0xcd */, 7629 HAL_RX_PPDU_END = 206 /* 0xce */, 7630 HAL_RX_MPDU_START = 207 /* 0xcf */, 7631 HAL_RX_MPDU_END = 208 /* 0xd0 */, 7632 HAL_RX_MSDU_START = 209 /* 0xd1 */, 7633 HAL_RX_MSDU_END = 210 /* 0xd2 */, 7634 HAL_RX_ATTENTION = 211 /* 0xd3 */, 7635 HAL_RECEIVED_RESPONSE_INFO = 212 /* 0xd4 */, 7636 HAL_RX_PHY_SLEEP = 213 /* 0xd5 */, 7637 HAL_RX_HEADER = 214 /* 0xd6 */, 7638 HAL_RX_PEER_ENTRY = 215 /* 0xd7 */, 7639 HAL_RX_FLUSH = 216 /* 0xd8 */, 7640 HAL_RX_RESPONSE_REQUIRED_INFO = 217 /* 0xd9 */, 7641 HAL_RX_FRAMELESS_BAR_DETAILS = 218 /* 0xda */, 7642 HAL_TQM_GET_MPDU_QUEUE_STATS_STATUS = 219 /* 0xdb */, 7643 HAL_TQM_GET_MSDU_FLOW_STATS_STATUS = 220 /* 0xdc */, 7644 HAL_TX_CBF_INFO = 221 /* 0xdd */, 7645 HAL_PCU_PPDU_SETUP_USER = 222 /* 0xde */, 7646 HAL_RX_MPDU_PCU_START = 223 /* 0xdf */, 7647 HAL_RX_PM_INFO = 224 /* 0xe0 */, 7648 HAL_RX_USER_PPDU_END = 225 /* 0xe1 */, 7649 HAL_RX_PRE_PPDU_START = 226 /* 0xe2 */, 7650 HAL_RX_PREAMBLE = 227 /* 0xe3 */, 7651 HAL_TX_FES_SETUP_COMPLETE = 228 /* 0xe4 */, 7652 HAL_TX_LAST_MPDU_FETCHED = 229 /* 0xe5 */, 7653 HAL_TXDMA_STOP_REQUEST = 230 /* 0xe6 */, 7654 HAL_RXPCU_SETUP = 231 /* 0xe7 */, 7655 HAL_RXPCU_USER_SETUP = 232 /* 0xe8 */, 7656 HAL_TX_FES_STATUS_ACK_OR_BA = 233 /* 0xe9 */, 7657 HAL_TQM_ACKED_MPDU = 234 /* 0xea */, 7658 HAL_COEX_TX_RESP = 235 /* 0xeb */, 7659 HAL_COEX_TX_STATUS = 236 /* 0xec */, 7660 HAL_MACTX_COEX_PHY_CTRL = 237 /* 0xed */, 7661 HAL_COEX_STATUS_BROADCAST = 238 /* 0xee */, 7662 HAL_RESPONSE_START_STATUS = 239 /* 0xef */, 7663 HAL_RESPONSE_END_STATUS = 240 /* 0xf0 */, 7664 HAL_CRYPTO_STATUS = 241 /* 0xf1 */, 7665 HAL_RECEIVED_TRIGGER_INFO = 242 /* 0xf2 */, 7666 HAL_REO_ENTRANCE_RING = 243 /* 0xf3 */, 7667 HAL_RX_MPDU_LINK = 244 /* 0xf4 */, 7668 HAL_COEX_TX_STOP_CTRL = 245 /* 0xf5 */, 7669 HAL_RX_PPDU_ACK_REPORT = 246 /* 0xf6 */, 7670 HAL_RX_PPDU_NO_ACK_REPORT = 247 /* 0xf7 */, 7671 HAL_SCH_COEX_STATUS = 248 /* 0xf8 */, 7672 HAL_SCHEDULER_COMMAND_STATUS = 249 /* 0xf9 */, 7673 HAL_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS = 250 /* 0xfa */, 7674 HAL_TX_FES_STATUS_PROT = 251 /* 0xfb */, 7675 HAL_TX_FES_STATUS_START_PPDU = 252 /* 0xfc */, 7676 HAL_TX_FES_STATUS_START_PROT = 253 /* 0xfd */, 7677 HAL_TXPCU_PHYTX_DEBUG32 = 254 /* 0xfe */, 7678 HAL_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 = 255 /* 0xff */, 7679 HAL_TX_MPDU_COUNT_TRANSFER_END = 256 /* 0x100 */, 7680 HAL_WHO_ANCHOR_OFFSET = 257 /* 0x101 */, 7681 HAL_WHO_ANCHOR_VALUE = 258 /* 0x102 */, 7682 HAL_WHO_CCE_INFO = 259 /* 0x103 */, 7683 HAL_WHO_COMMIT = 260 /* 0x104 */, 7684 HAL_WHO_COMMIT_DONE = 261 /* 0x105 */, 7685 HAL_WHO_FLUSH = 262 /* 0x106 */, 7686 HAL_WHO_L2_LLC = 263 /* 0x107 */, 7687 HAL_WHO_L2_PAYLOAD = 264 /* 0x108 */, 7688 HAL_WHO_L3_CHECKSUM = 265 /* 0x109 */, 7689 HAL_WHO_L3_INFO = 266 /* 0x10a */, 7690 HAL_WHO_L4_CHECKSUM = 267 /* 0x10b */, 7691 HAL_WHO_L4_INFO = 268 /* 0x10c */, 7692 HAL_WHO_MSDU = 269 /* 0x10d */, 7693 HAL_WHO_MSDU_MISC = 270 /* 0x10e */, 7694 HAL_WHO_PACKET_DATA = 271 /* 0x10f */, 7695 HAL_WHO_PACKET_HDR = 272 /* 0x110 */, 7696 HAL_WHO_PPDU_END = 273 /* 0x111 */, 7697 HAL_WHO_PPDU_START = 274 /* 0x112 */, 7698 HAL_WHO_TSO = 275 /* 0x113 */, 7699 HAL_WHO_WMAC_HEADER_PV0 = 276 /* 0x114 */, 7700 HAL_WHO_WMAC_HEADER_PV1 = 277 /* 0x115 */, 7701 HAL_WHO_WMAC_IV = 278 /* 0x116 */, 7702 HAL_MPDU_INFO_END = 279 /* 0x117 */, 7703 HAL_MPDU_INFO_BITMAP = 280 /* 0x118 */, 7704 HAL_TX_QUEUE_EXTENSION = 281 /* 0x119 */, 7705 HAL_RX_PEER_ENTRY_DETAILS = 282 /* 0x11a */, 7706 HAL_RX_REO_QUEUE_REFERENCE = 283 /* 0x11b */, 7707 HAL_RX_REO_QUEUE_EXT = 284 /* 0x11c */, 7708 HAL_SCHEDULER_SELFGEN_RESPONSE_STATUS = 285 /* 0x11d */, 7709 HAL_TQM_UPDATE_TX_MPDU_COUNT_STATUS = 286 /* 0x11e */, 7710 HAL_TQM_ACKED_MPDU_STATUS = 287 /* 0x11f */, 7711 HAL_TQM_ADD_MSDU_STATUS = 288 /* 0x120 */, 7712 HAL_RX_MPDU_LINK_PTR = 289 /* 0x121 */, 7713 HAL_REO_DESTINATION_RING = 290 /* 0x122 */, 7714 HAL_TQM_LIST_GEN_DONE = 291 /* 0x123 */, 7715 HAL_WHO_TERMINATE = 292 /* 0x124 */, 7716 HAL_TX_LAST_MPDU_END = 293 /* 0x125 */, 7717 HAL_TX_CV_DATA = 294 /* 0x126 */, 7718 HAL_TCL_ENTRANCE_FROM_PPE_RING = 295 /* 0x127 */, 7719 HAL_PPDU_TX_END = 296 /* 0x128 */, 7720 HAL_PROT_TX_END = 297 /* 0x129 */, 7721 HAL_PDG_RESPONSE_RATE_SETTING = 298 /* 0x12a */, 7722 HAL_MPDU_INFO_GLOBAL_END = 299 /* 0x12b */, 7723 HAL_TQM_SCH_INSTR_GLOBAL_END = 300 /* 0x12c */, 7724 HAL_RX_PPDU_END_USER_STATS = 301 /* 0x12d */, 7725 HAL_RX_PPDU_END_USER_STATS_EXT = 302 /* 0x12e */, 7726 HAL_NO_ACK_REPORT = 303 /* 0x12f */, 7727 HAL_ACK_REPORT = 304 /* 0x130 */, 7728 HAL_UNIFORM_REO_CMD_HEADER = 305 /* 0x131 */, 7729 HAL_REO_GET_QUEUE_STATS = 306 /* 0x132 */, 7730 HAL_REO_FLUSH_QUEUE = 307 /* 0x133 */, 7731 HAL_REO_FLUSH_CACHE = 308 /* 0x134 */, 7732 HAL_REO_UNBLOCK_CACHE = 309 /* 0x135 */, 7733 HAL_UNIFORM_REO_STATUS_HEADER = 310 /* 0x136 */, 7734 HAL_REO_GET_QUEUE_STATS_STATUS = 311 /* 0x137 */, 7735 HAL_REO_FLUSH_QUEUE_STATUS = 312 /* 0x138 */, 7736 HAL_REO_FLUSH_CACHE_STATUS = 313 /* 0x139 */, 7737 HAL_REO_UNBLOCK_CACHE_STATUS = 314 /* 0x13a */, 7738 HAL_TQM_FLUSH_CACHE = 315 /* 0x13b */, 7739 HAL_TQM_UNBLOCK_CACHE = 316 /* 0x13c */, 7740 HAL_TQM_FLUSH_CACHE_STATUS = 317 /* 0x13d */, 7741 HAL_TQM_UNBLOCK_CACHE_STATUS = 318 /* 0x13e */, 7742 HAL_RX_PPDU_END_STATUS_DONE = 319 /* 0x13f */, 7743 HAL_RX_STATUS_BUFFER_DONE = 320 /* 0x140 */, 7744 HAL_BUFFER_ADDR_INFO = 321 /* 0x141 */, 7745 HAL_RX_MSDU_DESC_INFO = 322 /* 0x142 */, 7746 HAL_RX_MPDU_DESC_INFO = 323 /* 0x143 */, 7747 HAL_TCL_DATA_CMD = 324 /* 0x144 */, 7748 HAL_TCL_GSE_CMD = 325 /* 0x145 */, 7749 HAL_TCL_EXIT_BASE = 326 /* 0x146 */, 7750 HAL_TCL_COMPACT_EXIT_RING = 327 /* 0x147 */, 7751 HAL_TCL_REGULAR_EXIT_RING = 328 /* 0x148 */, 7752 HAL_TCL_EXTENDED_EXIT_RING = 329 /* 0x149 */, 7753 HAL_UPLINK_COMMON_INFO = 330 /* 0x14a */, 7754 HAL_UPLINK_USER_SETUP_INFO = 331 /* 0x14b */, 7755 HAL_TX_DATA_SYNC = 332 /* 0x14c */, 7756 HAL_PHYRX_CBF_READ_REQUEST_ACK = 333 /* 0x14d */, 7757 HAL_TCL_STATUS_RING = 334 /* 0x14e */, 7758 HAL_TQM_GET_MPDU_HEAD_INFO = 335 /* 0x14f */, 7759 HAL_TQM_SYNC_CMD = 336 /* 0x150 */, 7760 HAL_TQM_GET_MPDU_HEAD_INFO_STATUS = 337 /* 0x151 */, 7761 HAL_TQM_SYNC_CMD_STATUS = 338 /* 0x152 */, 7762 HAL_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS = 339 /* 0x153 */, 7763 HAL_TQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 340 /* 0x154 */, 7764 HAL_REO_FLUSH_TIMEOUT_LIST = 341 /* 0x155 */, 7765 HAL_REO_FLUSH_TIMEOUT_LIST_STATUS = 342 /* 0x156 */, 7766 HAL_REO_TO_PPE_RING = 343 /* 0x157 */, 7767 HAL_RX_MPDU_INFO = 344 /* 0x158 */, 7768 HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 345 /* 0x159 */, 7769 HAL_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS = 346 /* 0x15a */, 7770 HAL_EXAMPLE_USER_TLV_32_NAME = 347 /* 0x15b */, 7771 HAL_RX_PPDU_START_USER_INFO = 348 /* 0x15c */, 7772 HAL_RX_RXPCU_CLASSIFICATION_OVERVIEW = 349 /* 0x15d */, 7773 HAL_RX_RING_MASK = 350 /* 0x15e */, 7774 HAL_WHO_CLASSIFY_INFO = 351 /* 0x15f */, 7775 HAL_TXPT_CLASSIFY_INFO = 352 /* 0x160 */, 7776 HAL_RXPT_CLASSIFY_INFO = 353 /* 0x161 */, 7777 HAL_TX_FLOW_SEARCH_ENTRY = 354 /* 0x162 */, 7778 HAL_RX_FLOW_SEARCH_ENTRY = 355 /* 0x163 */, 7779 HAL_RECEIVED_TRIGGER_INFO_DETAILS = 356 /* 0x164 */, 7780 HAL_COEX_MAC_NAP = 357 /* 0x165 */, 7781 HAL_MACRX_ABORT_REQUEST_INFO = 358 /* 0x166 */, 7782 HAL_MACTX_ABORT_REQUEST_INFO = 359 /* 0x167 */, 7783 HAL_PHYRX_ABORT_REQUEST_INFO = 360 /* 0x168 */, 7784 HAL_PHYTX_ABORT_REQUEST_INFO = 361 /* 0x169 */, 7785 HAL_RXPCU_PPDU_END_INFO = 362 /* 0x16a */, 7786 HAL_WHO_MESH_CONTROL = 363 /* 0x16b */, 7787 HAL_L_SIG_A_INFO = 364 /* 0x16c */, 7788 HAL_L_SIG_B_INFO = 365 /* 0x16d */, 7789 HAL_HT_SIG_INFO = 366 /* 0x16e */, 7790 HAL_VHT_SIG_A_INFO = 367 /* 0x16f */, 7791 HAL_VHT_SIG_B_SU20_INFO = 368 /* 0x170 */, 7792 HAL_VHT_SIG_B_SU40_INFO = 369 /* 0x171 */, 7793 HAL_VHT_SIG_B_SU80_INFO = 370 /* 0x172 */, 7794 HAL_VHT_SIG_B_SU160_INFO = 371 /* 0x173 */, 7795 HAL_VHT_SIG_B_MU20_INFO = 372 /* 0x174 */, 7796 HAL_VHT_SIG_B_MU40_INFO = 373 /* 0x175 */, 7797 HAL_VHT_SIG_B_MU80_INFO = 374 /* 0x176 */, 7798 HAL_VHT_SIG_B_MU160_INFO = 375 /* 0x177 */, 7799 HAL_SERVICE_INFO = 376 /* 0x178 */, 7800 HAL_HE_SIG_A_SU_INFO = 377 /* 0x179 */, 7801 HAL_HE_SIG_A_MU_DL_INFO = 378 /* 0x17a */, 7802 HAL_HE_SIG_A_MU_UL_INFO = 379 /* 0x17b */, 7803 HAL_HE_SIG_B1_MU_INFO = 380 /* 0x17c */, 7804 HAL_HE_SIG_B2_MU_INFO = 381 /* 0x17d */, 7805 HAL_HE_SIG_B2_OFDMA_INFO = 382 /* 0x17e */, 7806 HAL_PDG_SW_MODE_BW_START = 383 /* 0x17f */, 7807 HAL_PDG_SW_MODE_BW_END = 384 /* 0x180 */, 7808 HAL_PDG_WAIT_FOR_MAC_REQUEST = 385 /* 0x181 */, 7809 HAL_PDG_WAIT_FOR_PHY_REQUEST = 386 /* 0x182 */, 7810 HAL_SCHEDULER_END = 387 /* 0x183 */, 7811 HAL_PEER_TABLE_ENTRY = 388 /* 0x184 */, 7812 HAL_SW_PEER_INFO = 389 /* 0x185 */, 7813 HAL_RXOLE_CCE_CLASSIFY_INFO = 390 /* 0x186 */, 7814 HAL_TCL_CCE_CLASSIFY_INFO = 391 /* 0x187 */, 7815 HAL_RXOLE_CCE_INFO = 392 /* 0x188 */, 7816 HAL_TCL_CCE_INFO = 393 /* 0x189 */, 7817 HAL_TCL_CCE_SUPERRULE = 394 /* 0x18a */, 7818 HAL_CCE_RULE = 395 /* 0x18b */, 7819 HAL_RX_PPDU_START_DROPPED = 396 /* 0x18c */, 7820 HAL_RX_PPDU_END_DROPPED = 397 /* 0x18d */, 7821 HAL_RX_PPDU_END_STATUS_DONE_DROPPED = 398 /* 0x18e */, 7822 HAL_RX_MPDU_START_DROPPED = 399 /* 0x18f */, 7823 HAL_RX_MSDU_START_DROPPED = 400 /* 0x190 */, 7824 HAL_RX_MSDU_END_DROPPED = 401 /* 0x191 */, 7825 HAL_RX_MPDU_END_DROPPED = 402 /* 0x192 */, 7826 HAL_RX_ATTENTION_DROPPED = 403 /* 0x193 */, 7827 HAL_TXPCU_USER_SETUP = 404 /* 0x194 */, 7828 HAL_RXPCU_USER_SETUP_EXT = 405 /* 0x195 */, 7829 HAL_CE_SRC_DESC = 406 /* 0x196 */, 7830 HAL_CE_STAT_DESC = 407 /* 0x197 */, 7831 HAL_RXOLE_CCE_SUPERRULE = 408 /* 0x198 */, 7832 HAL_TX_RATE_STATS_INFO = 409 /* 0x199 */, 7833 HAL_CMD_PART_0_END = 410 /* 0x19a */, 7834 HAL_MACTX_SYNTH_ON = 411 /* 0x19b */, 7835 HAL_SCH_CRITICAL_TLV_REFERENCE = 412 /* 0x19c */, 7836 HAL_TQM_MPDU_GLOBAL_START = 413 /* 0x19d */, 7837 HAL_EXAMPLE_TLV_32 = 414 /* 0x19e */, 7838 HAL_TQM_UPDATE_TX_MSDU_FLOW = 415 /* 0x19f */, 7839 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD = 416 /* 0x1a0 */, 7840 HAL_TQM_UPDATE_TX_MSDU_FLOW_STATUS = 417 /* 0x1a1 */, 7841 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS = 418 /* 0x1a2 */, 7842 HAL_REO_UPDATE_RX_REO_QUEUE = 419 /* 0x1a3 */, 7843 HAL_CE_DST_DESC = 420 /* 0x1a4 */, 7844 HAL_TLV_BASE = 511 /* 0x1ff */, 7845 }; 7846 7847 #define HAL_TLV_HDR_TAG GENMASK(9, 1) 7848 #define HAL_TLV_HDR_LEN GENMASK(25, 10) 7849 #define HAL_TLV_USR_ID GENMASK(31, 26) 7850 7851 #define HAL_TLV_ALIGN 4 7852 7853 struct hal_tlv_hdr { 7854 uint32_t tl; 7855 uint8_t value[]; 7856 } __packed; 7857 7858 #define RX_MPDU_DESC_INFO0_MSDU_COUNT 0xff 7859 #define RX_MPDU_DESC_INFO0_SEQ_NUM 0xfff00 7860 #define RX_MPDU_DESC_INFO0_FRAG_FLAG (1 << 20) 7861 #define RX_MPDU_DESC_INFO0_MPDU_RETRY (1 << 21) 7862 #define RX_MPDU_DESC_INFO0_AMPDU_FLAG (1 << 22) 7863 #define RX_MPDU_DESC_INFO0_BAR_FRAME (1 << 23) 7864 #define RX_MPDU_DESC_INFO0_VALID_PN (1 << 24) 7865 #define RX_MPDU_DESC_INFO0_VALID_SA (1 << 25) 7866 #define RX_MPDU_DESC_INFO0_SA_IDX_TIMEOUT (1 << 26) 7867 #define RX_MPDU_DESC_INFO0_VALID_DA (1 << 27) 7868 #define RX_MPDU_DESC_INFO0_DA_MCBC (1 << 28) 7869 #define RX_MPDU_DESC_INFO0_DA_IDX_TIMEOUT (1 << 29) 7870 #define RX_MPDU_DESC_INFO0_RAW_MPDU (1 << 30) 7871 7872 #define RX_MPDU_DESC_META_DATA_PEER_ID 0xffff 7873 7874 struct rx_mpdu_desc { 7875 uint32_t info0; /* %RX_MPDU_DESC_INFO */ 7876 uint32_t meta_data; 7877 } __packed; 7878 7879 /* rx_mpdu_desc 7880 * Producer: RXDMA 7881 * Consumer: REO/SW/FW 7882 * 7883 * msdu_count 7884 * The number of MSDUs within the MPDU 7885 * 7886 * mpdu_sequence_number 7887 * The field can have two different meanings based on the setting 7888 * of field 'bar_frame'. If 'bar_frame' is set, it means the MPDU 7889 * start sequence number from the BAR frame otherwise it means 7890 * the MPDU sequence number of the received frame. 7891 * 7892 * fragment_flag 7893 * When set, this MPDU is a fragment and REO should forward this 7894 * fragment MPDU to the REO destination ring without any reorder 7895 * checks, pn checks or bitmap update. This implies that REO is 7896 * forwarding the pointer to the MSDU link descriptor. 7897 * 7898 * mpdu_retry_bit 7899 * The retry bit setting from the MPDU header of the received frame 7900 * 7901 * ampdu_flag 7902 * Indicates the MPDU was received as part of an A-MPDU. 7903 * 7904 * bar_frame 7905 * Indicates the received frame is a BAR frame. After processing, 7906 * this frame shall be pushed to SW or deleted. 7907 * 7908 * valid_pn 7909 * When not set, REO will not perform a PN sequence number check. 7910 * 7911 * valid_sa 7912 * Indicates OLE found a valid SA entry for all MSDUs in this MPDU. 7913 * 7914 * sa_idx_timeout 7915 * Indicates, at least 1 MSDU within the MPDU has an unsuccessful 7916 * MAC source address search due to the expiration of search timer. 7917 * 7918 * valid_da 7919 * When set, OLE found a valid DA entry for all MSDUs in this MPDU. 7920 * 7921 * da_mcbc 7922 * Field Only valid if valid_da is set. Indicates at least one of 7923 * the DA addresses is a Multicast or Broadcast address. 7924 * 7925 * da_idx_timeout 7926 * Indicates, at least 1 MSDU within the MPDU has an unsuccessful 7927 * MAC destination address search due to the expiration of search 7928 * timer. 7929 * 7930 * raw_mpdu 7931 * Field only valid when first_msdu_in_mpdu_flag is set. Indicates 7932 * the contents in the MSDU buffer contains a 'RAW' MPDU. 7933 */ 7934 7935 enum hal_rx_msdu_desc_reo_dest_ind { 7936 HAL_RX_MSDU_DESC_REO_DEST_IND_TCL, 7937 HAL_RX_MSDU_DESC_REO_DEST_IND_SW1, 7938 HAL_RX_MSDU_DESC_REO_DEST_IND_SW2, 7939 HAL_RX_MSDU_DESC_REO_DEST_IND_SW3, 7940 HAL_RX_MSDU_DESC_REO_DEST_IND_SW4, 7941 HAL_RX_MSDU_DESC_REO_DEST_IND_RELEASE, 7942 HAL_RX_MSDU_DESC_REO_DEST_IND_FW, 7943 }; 7944 7945 #define RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU (1 << 0) 7946 #define RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU (1 << 1) 7947 #define RX_MSDU_DESC_INFO0_MSDU_CONTINUATION (1 << 2) 7948 #define RX_MSDU_DESC_INFO0_MSDU_LENGTH GENMASK(16, 3) 7949 #define RX_MSDU_DESC_INFO0_REO_DEST_IND GENMASK(21, 17) 7950 #define RX_MSDU_DESC_INFO0_MSDU_DROP (1 << 22) 7951 #define RX_MSDU_DESC_INFO0_VALID_SA (1 << 23) 7952 #define RX_MSDU_DESC_INFO0_SA_IDX_TIMEOUT (1 << 24) 7953 #define RX_MSDU_DESC_INFO0_VALID_DA (1 << 25) 7954 #define RX_MSDU_DESC_INFO0_DA_MCBC (1 << 26) 7955 #define RX_MSDU_DESC_INFO0_DA_IDX_TIMEOUT (1 << 27) 7956 7957 #define HAL_RX_MSDU_PKT_LENGTH_GET(val) \ 7958 (FIELD_GET(RX_MSDU_DESC_INFO0_MSDU_LENGTH, (val))) 7959 7960 struct rx_msdu_desc { 7961 uint32_t info0; 7962 uint32_t rsvd0; 7963 } __packed; 7964 7965 /* rx_msdu_desc 7966 * 7967 * first_msdu_in_mpdu 7968 * Indicates first msdu in mpdu. 7969 * 7970 * last_msdu_in_mpdu 7971 * Indicates last msdu in mpdu. This flag can be true only when 7972 * 'Msdu_continuation' set to 0. This implies that when an msdu 7973 * is spread out over multiple buffers and thus msdu_continuation 7974 * is set, only for the very last buffer of the msdu, can the 7975 * 'last_msdu_in_mpdu' be set. 7976 * 7977 * When both first_msdu_in_mpdu and last_msdu_in_mpdu are set, 7978 * the MPDU that this MSDU belongs to only contains a single MSDU. 7979 * 7980 * msdu_continuation 7981 * When set, this MSDU buffer was not able to hold the entire MSDU. 7982 * The next buffer will therefore contain additional information 7983 * related to this MSDU. 7984 * 7985 * msdu_length 7986 * Field is only valid in combination with the 'first_msdu_in_mpdu' 7987 * being set. Full MSDU length in bytes after decapsulation. This 7988 * field is still valid for MPDU frames without A-MSDU. It still 7989 * represents MSDU length after decapsulation Or in case of RAW 7990 * MPDUs, it indicates the length of the entire MPDU (without FCS 7991 * field). 7992 * 7993 * reo_destination_indication 7994 * The id of the reo exit ring where the msdu frame shall push 7995 * after (MPDU level) reordering has finished. Values are defined 7996 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. 7997 * 7998 * msdu_drop 7999 * Indicates that REO shall drop this MSDU and not forward it to 8000 * any other ring. 8001 * 8002 * valid_sa 8003 * Indicates OLE found a valid SA entry for this MSDU. 8004 * 8005 * sa_idx_timeout 8006 * Indicates, an unsuccessful MAC source address search due to 8007 * the expiration of search timer for this MSDU. 8008 * 8009 * valid_da 8010 * When set, OLE found a valid DA entry for this MSDU. 8011 * 8012 * da_mcbc 8013 * Field Only valid if valid_da is set. Indicates the DA address 8014 * is a Multicast or Broadcast address for this MSDU. 8015 * 8016 * da_idx_timeout 8017 * Indicates, an unsuccessful MAC destination address search due 8018 * to the expiration of search timer for this MSDU. 8019 */ 8020 8021 enum hal_reo_dest_ring_buffer_type { 8022 HAL_REO_DEST_RING_BUFFER_TYPE_MSDU, 8023 HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC, 8024 }; 8025 8026 enum hal_reo_dest_ring_push_reason { 8027 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED, 8028 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION, 8029 }; 8030 8031 enum hal_reo_dest_ring_error_code { 8032 HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO, 8033 HAL_REO_DEST_RING_ERROR_CODE_DESC_INVALID, 8034 HAL_REO_DEST_RING_ERROR_CODE_AMPDU_IN_NON_BA, 8035 HAL_REO_DEST_RING_ERROR_CODE_NON_BA_DUPLICATE, 8036 HAL_REO_DEST_RING_ERROR_CODE_BA_DUPLICATE, 8037 HAL_REO_DEST_RING_ERROR_CODE_FRAME_2K_JUMP, 8038 HAL_REO_DEST_RING_ERROR_CODE_BAR_2K_JUMP, 8039 HAL_REO_DEST_RING_ERROR_CODE_FRAME_OOR, 8040 HAL_REO_DEST_RING_ERROR_CODE_BAR_OOR, 8041 HAL_REO_DEST_RING_ERROR_CODE_NO_BA_SESSION, 8042 HAL_REO_DEST_RING_ERROR_CODE_FRAME_SN_EQUALS_SSN, 8043 HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED, 8044 HAL_REO_DEST_RING_ERROR_CODE_2K_ERR_FLAG_SET, 8045 HAL_REO_DEST_RING_ERROR_CODE_PN_ERR_FLAG_SET, 8046 HAL_REO_DEST_RING_ERROR_CODE_DESC_BLOCKED, 8047 HAL_REO_DEST_RING_ERROR_CODE_MAX, 8048 }; 8049 8050 #define HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 8051 #define HAL_REO_DEST_RING_INFO0_BUFFER_TYPE (1 << 8) 8052 #define HAL_REO_DEST_RING_INFO0_PUSH_REASON GENMASK(10, 9) 8053 #define HAL_REO_DEST_RING_INFO0_ERROR_CODE GENMASK(15, 11) 8054 #define HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM GENMASK(31, 16) 8055 8056 #define HAL_REO_DEST_RING_INFO1_REORDER_INFO_VALID (1 << 0) 8057 #define HAL_REO_DEST_RING_INFO1_REORDER_OPCODE GENMASK(4, 1) 8058 #define HAL_REO_DEST_RING_INFO1_REORDER_SLOT_IDX GENMASK(12, 5) 8059 8060 #define HAL_REO_DEST_RING_INFO2_RING_ID GENMASK(27, 20) 8061 #define HAL_REO_DEST_RING_INFO2_LOOPING_COUNT GENMASK(31, 28) 8062 8063 struct hal_reo_dest_ring { 8064 struct ath11k_buffer_addr buf_addr_info; 8065 struct rx_mpdu_desc rx_mpdu_info; 8066 struct rx_msdu_desc rx_msdu_info; 8067 uint32_t queue_addr_lo; 8068 uint32_t info0; /* %HAL_REO_DEST_RING_INFO0_ */ 8069 uint32_t info1; /* %HAL_REO_DEST_RING_INFO1_ */ 8070 uint32_t rsvd0; 8071 uint32_t rsvd1; 8072 uint32_t rsvd2; 8073 uint32_t rsvd3; 8074 uint32_t rsvd4; 8075 uint32_t rsvd5; 8076 uint32_t info2; /* %HAL_REO_DEST_RING_INFO2_ */ 8077 } __packed; 8078 8079 /* hal_reo_dest_ring 8080 * 8081 * Producer: RXDMA 8082 * Consumer: REO/SW/FW 8083 * 8084 * buf_addr_info 8085 * Details of the physical address of a buffer or MSDU 8086 * link descriptor. 8087 * 8088 * rx_mpdu_info 8089 * General information related to the MPDU that is passed 8090 * on from REO entrance ring to the REO destination ring. 8091 * 8092 * rx_msdu_info 8093 * General information related to the MSDU that is passed 8094 * on from RXDMA all the way to the REO destination ring. 8095 * 8096 * queue_addr_lo 8097 * Address (lower 32 bits) of the REO queue descriptor. 8098 * 8099 * queue_addr_hi 8100 * Address (upper 8 bits) of the REO queue descriptor. 8101 * 8102 * buffer_type 8103 * Indicates the type of address provided in the buf_addr_info. 8104 * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_. 8105 * 8106 * push_reason 8107 * Reason for pushing this frame to this exit ring. Values are 8108 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 8109 * 8110 * error_code 8111 * Valid only when 'push_reason' is set. All error codes are 8112 * defined in enum %HAL_REO_DEST_RING_ERROR_CODE_. 8113 * 8114 * rx_queue_num 8115 * Indicates the REO MPDU reorder queue id from which this frame 8116 * originated. 8117 * 8118 * reorder_info_valid 8119 * When set, REO has been instructed to not perform the actual 8120 * re-ordering of frames for this queue, but just to insert 8121 * the reorder opcodes. 8122 * 8123 * reorder_opcode 8124 * Field is valid when 'reorder_info_valid' is set. This field is 8125 * always valid for debug purpose as well. 8126 * 8127 * reorder_slot_idx 8128 * Valid only when 'reorder_info_valid' is set. 8129 * 8130 * ring_id 8131 * The buffer pointer ring id. 8132 * 0 - Idle ring 8133 * 1 - N refers to other rings. 8134 * 8135 * looping_count 8136 * Indicates the number of times the producer of entries into 8137 * this ring has looped around the ring. 8138 */ 8139 8140 enum hal_reo_entr_rxdma_ecode { 8141 HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR, 8142 HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR, 8143 HAL_REO_ENTR_RING_RXDMA_ECODE_FCS_ERR, 8144 HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR, 8145 HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR, 8146 HAL_REO_ENTR_RING_RXDMA_ECODE_UNECRYPTED_ERR, 8147 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LEN_ERR, 8148 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LIMIT_ERR, 8149 HAL_REO_ENTR_RING_RXDMA_ECODE_WIFI_PARSE_ERR, 8150 HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_PARSE_ERR, 8151 HAL_REO_ENTR_RING_RXDMA_ECODE_SA_TIMEOUT_ERR, 8152 HAL_REO_ENTR_RING_RXDMA_ECODE_DA_TIMEOUT_ERR, 8153 HAL_REO_ENTR_RING_RXDMA_ECODE_FLOW_TIMEOUT_ERR, 8154 HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR, 8155 HAL_REO_ENTR_RING_RXDMA_ECODE_MAX, 8156 }; 8157 8158 #define HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 8159 #define HAL_REO_ENTR_RING_INFO0_MPDU_BYTE_COUNT GENMASK(21, 8) 8160 #define HAL_REO_ENTR_RING_INFO0_DEST_IND GENMASK(26, 22) 8161 #define HAL_REO_ENTR_RING_INFO0_FRAMELESS_BAR BIT(27) 8162 8163 #define HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON GENMASK(1, 0) 8164 #define HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE GENMASK(6, 2) 8165 8166 struct hal_reo_entrance_ring { 8167 struct ath11k_buffer_addr buf_addr_info; 8168 struct rx_mpdu_desc rx_mpdu_info; 8169 uint32_t queue_addr_lo; 8170 uint32_t info0; /* %HAL_REO_ENTR_RING_INFO0_ */ 8171 uint32_t info1; /* %HAL_REO_ENTR_RING_INFO1_ */ 8172 uint32_t info2; /* %HAL_REO_DEST_RING_INFO2_ */ 8173 8174 } __packed; 8175 8176 /* hal_reo_entrance_ring 8177 * 8178 * Producer: RXDMA 8179 * Consumer: REO 8180 * 8181 * buf_addr_info 8182 * Details of the physical address of a buffer or MSDU 8183 * link descriptor. 8184 * 8185 * rx_mpdu_info 8186 * General information related to the MPDU that is passed 8187 * on from REO entrance ring to the REO destination ring. 8188 * 8189 * queue_addr_lo 8190 * Address (lower 32 bits) of the REO queue descriptor. 8191 * 8192 * queue_addr_hi 8193 * Address (upper 8 bits) of the REO queue descriptor. 8194 * 8195 * mpdu_byte_count 8196 * An approximation of the number of bytes received in this MPDU. 8197 * Used to keeps stats on the amount of data flowing 8198 * through a queue. 8199 * 8200 * reo_destination_indication 8201 * The id of the reo exit ring where the msdu frame shall push 8202 * after (MPDU level) reordering has finished. Values are defined 8203 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. 8204 * 8205 * frameless_bar 8206 * Indicates that this REO entrance ring struct contains BAR info 8207 * from a multi TID BAR frame. The original multi TID BAR frame 8208 * itself contained all the REO info for the first TID, but all 8209 * the subsequent TID info and their linkage to the REO descriptors 8210 * is passed down as 'frameless' BAR info. 8211 * 8212 * The only fields valid in this descriptor when this bit is set 8213 * are queue_addr_lo, queue_addr_hi, mpdu_sequence_number, 8214 * bar_frame and peer_meta_data. 8215 * 8216 * rxdma_push_reason 8217 * Reason for pushing this frame to this exit ring. Values are 8218 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 8219 * 8220 * rxdma_error_code 8221 * Valid only when 'push_reason' is set. All error codes are 8222 * defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_. 8223 * 8224 * ring_id 8225 * The buffer pointer ring id. 8226 * 0 - Idle ring 8227 * 1 - N refers to other rings. 8228 * 8229 * looping_count 8230 * Indicates the number of times the producer of entries into 8231 * this ring has looped around the ring. 8232 */ 8233 8234 #define HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON GENMASK(1, 0) 8235 #define HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE GENMASK(6, 2) 8236 #define HAL_SW_MON_RING_INFO0_MPDU_FRAG_NUMBER GENMASK(10, 7) 8237 #define HAL_SW_MON_RING_INFO0_FRAMELESS_BAR BIT(11) 8238 #define HAL_SW_MON_RING_INFO0_STATUS_BUF_CNT GENMASK(15, 12) 8239 #define HAL_SW_MON_RING_INFO0_END_OF_PPDU BIT(16) 8240 8241 #define HAL_SW_MON_RING_INFO1_PHY_PPDU_ID GENMASK(15, 0) 8242 #define HAL_SW_MON_RING_INFO1_RING_ID GENMASK(27, 20) 8243 #define HAL_SW_MON_RING_INFO1_LOOPING_COUNT GENMASK(31, 28) 8244 8245 struct hal_sw_monitor_ring { 8246 struct ath11k_buffer_addr buf_addr_info; 8247 struct rx_mpdu_desc rx_mpdu_info; 8248 struct ath11k_buffer_addr status_buf_addr_info; 8249 uint32_t info0; 8250 uint32_t info1; 8251 } __packed; 8252 8253 #define HAL_REO_CMD_HDR_INFO0_CMD_NUMBER GENMASK(15, 0) 8254 #define HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED BIT(16) 8255 8256 struct hal_reo_cmd_hdr { 8257 uint32_t info0; 8258 } __packed; 8259 8260 8261 #define HAL_SRNG_DESC_LOOP_CNT 0xf0000000 8262 8263 #define HAL_REO_CMD_FLG_NEED_STATUS BIT(0) 8264 #define HAL_REO_CMD_FLG_STATS_CLEAR BIT(1) 8265 #define HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER BIT(2) 8266 #define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING BIT(3) 8267 #define HAL_REO_CMD_FLG_FLUSH_NO_INVAL BIT(4) 8268 #define HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS BIT(5) 8269 #define HAL_REO_CMD_FLG_FLUSH_ALL BIT(6) 8270 #define HAL_REO_CMD_FLG_UNBLK_RESOURCE BIT(7) 8271 #define HAL_REO_CMD_FLG_UNBLK_CACHE BIT(8) 8272 8273 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO0_UPD_* feilds */ 8274 #define HAL_REO_CMD_UPD0_RX_QUEUE_NUM BIT(8) 8275 #define HAL_REO_CMD_UPD0_VLD BIT(9) 8276 #define HAL_REO_CMD_UPD0_ALDC BIT(10) 8277 #define HAL_REO_CMD_UPD0_DIS_DUP_DETECTION BIT(11) 8278 #define HAL_REO_CMD_UPD0_SOFT_REORDER_EN BIT(12) 8279 #define HAL_REO_CMD_UPD0_AC BIT(13) 8280 #define HAL_REO_CMD_UPD0_BAR BIT(14) 8281 #define HAL_REO_CMD_UPD0_RETRY BIT(15) 8282 #define HAL_REO_CMD_UPD0_CHECK_2K_MODE BIT(16) 8283 #define HAL_REO_CMD_UPD0_OOR_MODE BIT(17) 8284 #define HAL_REO_CMD_UPD0_BA_WINDOW_SIZE BIT(18) 8285 #define HAL_REO_CMD_UPD0_PN_CHECK BIT(19) 8286 #define HAL_REO_CMD_UPD0_EVEN_PN BIT(20) 8287 #define HAL_REO_CMD_UPD0_UNEVEN_PN BIT(21) 8288 #define HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE BIT(22) 8289 #define HAL_REO_CMD_UPD0_PN_SIZE BIT(23) 8290 #define HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG BIT(24) 8291 #define HAL_REO_CMD_UPD0_SVLD BIT(25) 8292 #define HAL_REO_CMD_UPD0_SSN BIT(26) 8293 #define HAL_REO_CMD_UPD0_SEQ_2K_ERR BIT(27) 8294 #define HAL_REO_CMD_UPD0_PN_ERR BIT(28) 8295 #define HAL_REO_CMD_UPD0_PN_VALID BIT(29) 8296 #define HAL_REO_CMD_UPD0_PN BIT(30) 8297 8298 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO1_* feilds */ 8299 #define HAL_REO_CMD_UPD1_VLD BIT(16) 8300 #define HAL_REO_CMD_UPD1_ALDC GENMASK(18, 17) 8301 #define HAL_REO_CMD_UPD1_DIS_DUP_DETECTION BIT(19) 8302 #define HAL_REO_CMD_UPD1_SOFT_REORDER_EN BIT(20) 8303 #define HAL_REO_CMD_UPD1_AC GENMASK(22, 21) 8304 #define HAL_REO_CMD_UPD1_BAR BIT(23) 8305 #define HAL_REO_CMD_UPD1_RETRY BIT(24) 8306 #define HAL_REO_CMD_UPD1_CHECK_2K_MODE BIT(25) 8307 #define HAL_REO_CMD_UPD1_OOR_MODE BIT(26) 8308 #define HAL_REO_CMD_UPD1_PN_CHECK BIT(27) 8309 #define HAL_REO_CMD_UPD1_EVEN_PN BIT(28) 8310 #define HAL_REO_CMD_UPD1_UNEVEN_PN BIT(29) 8311 #define HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE BIT(30) 8312 #define HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG BIT(31) 8313 8314 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO2_* feilds */ 8315 #define HAL_REO_CMD_UPD2_SVLD BIT(10) 8316 #define HAL_REO_CMD_UPD2_SSN GENMASK(22, 11) 8317 #define HAL_REO_CMD_UPD2_SEQ_2K_ERR BIT(23) 8318 #define HAL_REO_CMD_UPD2_PN_ERR BIT(24) 8319 8320 #define HAL_REO_DEST_RING_CTRL_HASH_RING_MAP GENMASK(31, 8) 8321 8322 struct ath11k_hal_reo_cmd { 8323 uint32_t addr_lo; 8324 uint32_t flag; 8325 uint32_t upd0; 8326 uint32_t upd1; 8327 uint32_t upd2; 8328 uint32_t pn[4]; 8329 uint16_t rx_queue_num; 8330 uint16_t min_rel; 8331 uint16_t min_fwd; 8332 uint8_t addr_hi; 8333 uint8_t ac_list; 8334 uint8_t blocking_idx; 8335 uint16_t ba_window_size; 8336 uint8_t pn_size; 8337 }; 8338 8339 #define HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 8340 #define HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS BIT(8) 8341 8342 struct hal_reo_get_queue_stats { 8343 struct hal_reo_cmd_hdr cmd; 8344 uint32_t queue_addr_lo; 8345 uint32_t info0; 8346 uint32_t rsvd0[6]; 8347 } __packed; 8348 8349 /* hal_reo_get_queue_stats 8350 * Producer: SW 8351 * Consumer: REO 8352 * 8353 * cmd 8354 * Details for command execution tracking purposes. 8355 * 8356 * queue_addr_lo 8357 * Address (lower 32 bits) of the REO queue descriptor. 8358 * 8359 * queue_addr_hi 8360 * Address (upper 8 bits) of the REO queue descriptor. 8361 * 8362 * clear_stats 8363 * Clear stats settings. When set, Clear the stats after 8364 * generating the status. 8365 * 8366 * Following stats will be cleared. 8367 * Timeout_count 8368 * Forward_due_to_bar_count 8369 * Duplicate_count 8370 * Frames_in_order_count 8371 * BAR_received_count 8372 * MPDU_Frames_processed_count 8373 * MSDU_Frames_processed_count 8374 * Total_processed_byte_count 8375 * Late_receive_MPDU_count 8376 * window_jump_2k 8377 * Hole_count 8378 */ 8379 8380 #define HAL_REO_FLUSH_QUEUE_INFO0_DESC_ADDR_HI GENMASK(7, 0) 8381 #define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_DESC_ADDR BIT(8) 8382 #define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_RESRC_IDX GENMASK(10, 9) 8383 8384 struct hal_reo_flush_queue { 8385 struct hal_reo_cmd_hdr cmd; 8386 uint32_t desc_addr_lo; 8387 uint32_t info0; 8388 uint32_t rsvd0[6]; 8389 } __packed; 8390 8391 #define HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI GENMASK(7, 0) 8392 #define HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS BIT(8) 8393 #define HAL_REO_FLUSH_CACHE_INFO0_RELEASE_BLOCK_IDX BIT(9) 8394 #define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX GENMASK(11, 10) 8395 #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE BIT(12) 8396 #define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE BIT(13) 8397 #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL BIT(14) 8398 8399 struct hal_reo_flush_cache { 8400 struct hal_reo_cmd_hdr cmd; 8401 uint32_t cache_addr_lo; 8402 uint32_t info0; 8403 uint32_t rsvd0[6]; 8404 } __packed; 8405 8406 #define HAL_TCL_DATA_CMD_INFO0_DESC_TYPE BIT(0) 8407 #define HAL_TCL_DATA_CMD_INFO0_EPD BIT(1) 8408 #define HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE GENMASK(3, 2) 8409 #define HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE GENMASK(7, 4) 8410 #define HAL_TCL_DATA_CMD_INFO0_SRC_BUF_SWAP BIT(8) 8411 #define HAL_TCL_DATA_CMD_INFO0_LNK_META_SWAP BIT(9) 8412 #define HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE GENMASK(13, 12) 8413 #define HAL_TCL_DATA_CMD_INFO0_ADDR_EN GENMASK(15, 14) 8414 #define HAL_TCL_DATA_CMD_INFO0_CMD_NUM GENMASK(31, 16) 8415 8416 #define HAL_TCL_DATA_CMD_INFO1_DATA_LEN GENMASK(15, 0) 8417 #define HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN BIT(16) 8418 #define HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN BIT(17) 8419 #define HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN BIT(18) 8420 #define HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN BIT(19) 8421 #define HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN BIT(20) 8422 #define HAL_TCL_DATA_CMD_INFO1_TO_FW BIT(21) 8423 #define HAL_TCL_DATA_CMD_INFO1_PKT_OFFSET GENMASK(31, 23) 8424 8425 #define HAL_TCL_DATA_CMD_INFO2_BUF_TIMESTAMP GENMASK(18, 0) 8426 #define HAL_TCL_DATA_CMD_INFO2_BUF_T_VALID BIT(19) 8427 #define HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE BIT(20) 8428 #define HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE BIT(21) 8429 #define HAL_TCL_DATA_CMD_INFO2_TID GENMASK(25, 22) 8430 #define HAL_TCL_DATA_CMD_INFO2_LMAC_ID GENMASK(27, 26) 8431 8432 #define HAL_TCL_DATA_CMD_INFO3_DSCP_TID_TABLE_IDX GENMASK(5, 0) 8433 #define HAL_TCL_DATA_CMD_INFO3_SEARCH_INDEX GENMASK(25, 6) 8434 #define HAL_TCL_DATA_CMD_INFO3_CACHE_SET_NUM GENMASK(29, 26) 8435 #define HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE GENMASK(31, 30) 8436 8437 #define HAL_TCL_DATA_CMD_INFO4_RING_ID GENMASK(27, 20) 8438 #define HAL_TCL_DATA_CMD_INFO4_LOOPING_COUNT GENMASK(31, 28) 8439 8440 enum hal_encrypt_type { 8441 HAL_ENCRYPT_TYPE_WEP_40, 8442 HAL_ENCRYPT_TYPE_WEP_104, 8443 HAL_ENCRYPT_TYPE_TKIP_NO_MIC, 8444 HAL_ENCRYPT_TYPE_WEP_128, 8445 HAL_ENCRYPT_TYPE_TKIP_MIC, 8446 HAL_ENCRYPT_TYPE_WAPI, 8447 HAL_ENCRYPT_TYPE_CCMP_128, 8448 HAL_ENCRYPT_TYPE_OPEN, 8449 HAL_ENCRYPT_TYPE_CCMP_256, 8450 HAL_ENCRYPT_TYPE_GCMP_128, 8451 HAL_ENCRYPT_TYPE_AES_GCMP_256, 8452 HAL_ENCRYPT_TYPE_WAPI_GCM_SM4, 8453 }; 8454 8455 enum hal_tcl_encap_type { 8456 HAL_TCL_ENCAP_TYPE_RAW, 8457 HAL_TCL_ENCAP_TYPE_NATIVE_WIFI, 8458 HAL_TCL_ENCAP_TYPE_ETHERNET, 8459 HAL_TCL_ENCAP_TYPE_802_3 = 3, 8460 }; 8461 8462 enum hal_tcl_desc_type { 8463 HAL_TCL_DESC_TYPE_BUFFER, 8464 HAL_TCL_DESC_TYPE_EXT_DESC, 8465 }; 8466 8467 enum hal_wbm_htt_tx_comp_status { 8468 HAL_WBM_REL_HTT_TX_COMP_STATUS_OK, 8469 HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP, 8470 HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL, 8471 HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ, 8472 HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT, 8473 HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY, 8474 }; 8475 8476 struct hal_tcl_data_cmd { 8477 struct ath11k_buffer_addr buf_addr_info; 8478 uint32_t info0; 8479 uint32_t info1; 8480 uint32_t info2; 8481 uint32_t info3; 8482 uint32_t info4; 8483 } __packed; 8484 8485 /* hal_tcl_data_cmd 8486 * 8487 * buf_addr_info 8488 * Details of the physical address of a buffer or MSDU 8489 * link descriptor. 8490 * 8491 * desc_type 8492 * Indicates the type of address provided in the buf_addr_info. 8493 * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_. 8494 * 8495 * epd 8496 * When this bit is set then input packet is an EPD type. 8497 * 8498 * encap_type 8499 * Indicates the encapsulation that HW will perform. Values are 8500 * defined in enum %HAL_TCL_ENCAP_TYPE_. 8501 * 8502 * encrypt_type 8503 * Field only valid for encap_type: RAW 8504 * Values are defined in enum %HAL_ENCRYPT_TYPE_. 8505 * 8506 * src_buffer_swap 8507 * Treats source memory (packet buffer) organization as big-endian. 8508 * 1'b0: Source memory is little endian 8509 * 1'b1: Source memory is big endian 8510 * 8511 * link_meta_swap 8512 * Treats link descriptor and Metadata as big-endian. 8513 * 1'b0: memory is little endian 8514 * 1'b1: memory is big endian 8515 * 8516 * search_type 8517 * Search type select 8518 * 0 - Normal search, 1 - Index based address search, 8519 * 2 - Index based flow search 8520 * 8521 * addrx_en 8522 * addry_en 8523 * Address X/Y search enable in ASE correspondingly. 8524 * 1'b0: Search disable 8525 * 1'b1: Search Enable 8526 * 8527 * cmd_num 8528 * This number can be used to match against status. 8529 * 8530 * data_length 8531 * MSDU length in case of direct descriptor. Length of link 8532 * extension descriptor in case of Link extension descriptor. 8533 * 8534 * *_checksum_en 8535 * Enable checksum replacement for ipv4, udp_over_ipv4, ipv6, 8536 * udp_over_ipv6, tcp_over_ipv4 and tcp_over_ipv6. 8537 * 8538 * to_fw 8539 * Forward packet to FW along with classification result. The 8540 * packet will not be forward to TQM when this bit is set. 8541 * 1'b0: Use classification result to forward the packet. 8542 * 1'b1: Override classification result & forward packet only to fw 8543 * 8544 * packet_offset 8545 * Packet offset from Metadata in case of direct buffer descriptor. 8546 * 8547 * buffer_timestamp 8548 * buffer_timestamp_valid 8549 * Frame system entrance timestamp. It shall be filled by first 8550 * module (SW, TCL or TQM) that sees the frames first. 8551 * 8552 * mesh_enable 8553 * For raw WiFi frames, this indicates transmission to a mesh STA, 8554 * enabling the interpretation of the 'Mesh Control Present' bit 8555 * (bit 8) of QoS Control. 8556 * For native WiFi frames, this indicates that a 'Mesh Control' 8557 * field is present between the header and the LLC. 8558 * 8559 * hlos_tid_overwrite 8560 * 8561 * When set, TCL shall ignore the IP DSCP and VLAN PCP 8562 * fields and use HLOS_TID as the final TID. Otherwise TCL 8563 * shall consider the DSCP and PCP fields as well as HLOS_TID 8564 * and choose a final TID based on the configured priority 8565 * 8566 * hlos_tid 8567 * HLOS MSDU priority 8568 * Field is used when HLOS_TID_overwrite is set. 8569 * 8570 * lmac_id 8571 * TCL uses this LMAC_ID in address search, i.e, while 8572 * finding matching entry for the packet in AST corresponding 8573 * to given LMAC_ID 8574 * 8575 * If LMAC ID is all 1s (=> value 3), it indicates wildcard 8576 * match for any MAC 8577 * 8578 * dscp_tid_table_num 8579 * DSCP to TID mapping table number that need to be used 8580 * for the MSDU. 8581 * 8582 * search_index 8583 * The index that will be used for index based address or 8584 * flow search. The field is valid when 'search_type' is 1 or 2. 8585 * 8586 * cache_set_num 8587 * 8588 * Cache set number that should be used to cache the index 8589 * based search results, for address and flow search. This 8590 * value should be equal to LSB four bits of the hash value of 8591 * match data, in case of search index points to an entry which 8592 * may be used in content based search also. The value can be 8593 * anything when the entry pointed by search index will not be 8594 * used for content based search. 8595 * 8596 * ring_id 8597 * The buffer pointer ring ID. 8598 * 0 refers to the IDLE ring 8599 * 1 - N refers to other rings 8600 * 8601 * looping_count 8602 * 8603 * A count value that indicates the number of times the 8604 * producer of entries into the Ring has looped around the 8605 * ring. 8606 * 8607 * At initialization time, this value is set to 0. On the 8608 * first loop, this value is set to 1. After the max value is 8609 * reached allowed by the number of bits for this field, the 8610 * count value continues with 0 again. 8611 * 8612 * In case SW is the consumer of the ring entries, it can 8613 * use this field to figure out up to where the producer of 8614 * entries has created new entries. This eliminates the need to 8615 * check where the head pointer' of the ring is located once 8616 * the SW starts processing an interrupt indicating that new 8617 * entries have been put into this ring... 8618 * 8619 * Also note that SW if it wants only needs to look at the 8620 * LSB bit of this count value. 8621 */ 8622 8623 #define HAL_TCL_DESC_LEN sizeof(struct hal_tcl_data_cmd) 8624 8625 enum hal_tcl_gse_ctrl { 8626 HAL_TCL_GSE_CTRL_RD_STAT, 8627 HAL_TCL_GSE_CTRL_SRCH_DIS, 8628 HAL_TCL_GSE_CTRL_WR_BK_SINGLE, 8629 HAL_TCL_GSE_CTRL_WR_BK_ALL, 8630 HAL_TCL_GSE_CTRL_INVAL_SINGLE, 8631 HAL_TCL_GSE_CTRL_INVAL_ALL, 8632 HAL_TCL_GSE_CTRL_WR_BK_INVAL_SINGLE, 8633 HAL_TCL_GSE_CTRL_WR_BK_INVAL_ALL, 8634 HAL_TCL_GSE_CTRL_CLR_STAT_SINGLE, 8635 }; 8636 8637 /* hal_tcl_gse_ctrl 8638 * 8639 * rd_stat 8640 * Report or Read statistics 8641 * srch_dis 8642 * Search disable. Report only Hash. 8643 * wr_bk_single 8644 * Write Back single entry 8645 * wr_bk_all 8646 * Write Back entire cache entry 8647 * inval_single 8648 * Invalidate single cache entry 8649 * inval_all 8650 * Invalidate entire cache 8651 * wr_bk_inval_single 8652 * Write back and invalidate single entry in cache 8653 * wr_bk_inval_all 8654 * Write back and invalidate entire cache 8655 * clr_stat_single 8656 * Clear statistics for single entry 8657 */ 8658 8659 #define HAL_TCL_GSE_CMD_INFO0_CTRL_BUF_ADDR_HI GENMASK(7, 0) 8660 #define HAL_TCL_GSE_CMD_INFO0_GSE_CTRL GENMASK(11, 8) 8661 #define HAL_TCL_GSE_CMD_INFO0_GSE_SEL BIT(12) 8662 #define HAL_TCL_GSE_CMD_INFO0_STATUS_DEST_RING_ID BIT(13) 8663 #define HAL_TCL_GSE_CMD_INFO0_SWAP BIT(14) 8664 8665 #define HAL_TCL_GSE_CMD_INFO1_RING_ID GENMASK(27, 20) 8666 #define HAL_TCL_GSE_CMD_INFO1_LOOPING_COUNT GENMASK(31, 28) 8667 8668 struct hal_tcl_gse_cmd { 8669 uint32_t ctrl_buf_addr_lo; 8670 uint32_t info0; 8671 uint32_t meta_data[2]; 8672 uint32_t rsvd0[2]; 8673 uint32_t info1; 8674 } __packed; 8675 8676 /* hal_tcl_gse_cmd 8677 * 8678 * ctrl_buf_addr_lo, ctrl_buf_addr_hi 8679 * Address of a control buffer containing additional info needed 8680 * for this command execution. 8681 * 8682 * gse_ctrl 8683 * GSE control operations. This includes cache operations and table 8684 * entry statistics read/clear operation. Values are defined in 8685 * enum %HAL_TCL_GSE_CTRL. 8686 * 8687 * gse_sel 8688 * To select the ASE/FSE to do the operation mention by GSE_ctrl. 8689 * 0: FSE select 1: ASE select 8690 * 8691 * status_destination_ring_id 8692 * TCL status ring to which the GSE status needs to be send. 8693 * 8694 * swap 8695 * Bit to enable byte swapping of contents of buffer. 8696 * 8697 * meta_data 8698 * Meta data to be returned in the status descriptor 8699 */ 8700 8701 enum hal_tcl_cache_op_res { 8702 HAL_TCL_CACHE_OP_RES_DONE, 8703 HAL_TCL_CACHE_OP_RES_NOT_FOUND, 8704 HAL_TCL_CACHE_OP_RES_TIMEOUT, 8705 }; 8706 8707 #define HAL_TCL_STATUS_RING_INFO0_GSE_CTRL GENMASK(3, 0) 8708 #define HAL_TCL_STATUS_RING_INFO0_GSE_SEL BIT(4) 8709 #define HAL_TCL_STATUS_RING_INFO0_CACHE_OP_RES GENMASK(6, 5) 8710 #define HAL_TCL_STATUS_RING_INFO0_MSDU_CNT GENMASK(31, 8) 8711 8712 #define HAL_TCL_STATUS_RING_INFO1_HASH_IDX GENMASK(19, 0) 8713 8714 #define HAL_TCL_STATUS_RING_INFO2_RING_ID GENMASK(27, 20) 8715 #define HAL_TCL_STATUS_RING_INFO2_LOOPING_COUNT GENMASK(31, 28) 8716 8717 struct hal_tcl_status_ring { 8718 uint32_t info0; 8719 uint32_t msdu_byte_count; 8720 uint32_t msdu_timestamp; 8721 uint32_t meta_data[2]; 8722 uint32_t info1; 8723 uint32_t rsvd0; 8724 uint32_t info2; 8725 } __packed; 8726 8727 /* hal_tcl_status_ring 8728 * 8729 * gse_ctrl 8730 * GSE control operations. This includes cache operations and table 8731 * entry statistics read/clear operation. Values are defined in 8732 * enum %HAL_TCL_GSE_CTRL. 8733 * 8734 * gse_sel 8735 * To select the ASE/FSE to do the operation mention by GSE_ctrl. 8736 * 0: FSE select 1: ASE select 8737 * 8738 * cache_op_res 8739 * Cache operation result. Values are defined in enum 8740 * %HAL_TCL_CACHE_OP_RES_. 8741 * 8742 * msdu_cnt 8743 * msdu_byte_count 8744 * MSDU count of Entry and MSDU byte count for entry 1. 8745 * 8746 * hash_indx 8747 * Hash value of the entry in case of search failed or disabled. 8748 */ 8749 8750 #define HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0) 8751 #define HAL_CE_SRC_DESC_ADDR_INFO_HASH_EN BIT(8) 8752 #define HAL_CE_SRC_DESC_ADDR_INFO_BYTE_SWAP BIT(9) 8753 #define HAL_CE_SRC_DESC_ADDR_INFO_DEST_SWAP BIT(10) 8754 #define HAL_CE_SRC_DESC_ADDR_INFO_GATHER BIT(11) 8755 #define HAL_CE_SRC_DESC_ADDR_INFO_LEN GENMASK(31, 16) 8756 8757 #define HAL_CE_SRC_DESC_META_INFO_DATA GENMASK(15, 0) 8758 8759 #define HAL_CE_SRC_DESC_FLAGS_RING_ID GENMASK(27, 20) 8760 #define HAL_CE_SRC_DESC_FLAGS_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 8761 8762 struct hal_ce_srng_src_desc { 8763 uint32_t buffer_addr_low; 8764 uint32_t buffer_addr_info; /* %HAL_CE_SRC_DESC_ADDR_INFO_ */ 8765 uint32_t meta_info; /* %HAL_CE_SRC_DESC_META_INFO_ */ 8766 uint32_t flags; /* %HAL_CE_SRC_DESC_FLAGS_ */ 8767 } __packed; 8768 8769 /* 8770 * hal_ce_srng_src_desc 8771 * 8772 * buffer_addr_lo 8773 * LSB 32 bits of the 40 Bit Pointer to the source buffer 8774 * 8775 * buffer_addr_hi 8776 * MSB 8 bits of the 40 Bit Pointer to the source buffer 8777 * 8778 * toeplitz_en 8779 * Enable generation of 32-bit Toeplitz-LFSR hash for 8780 * data transfer. In case of gather field in first source 8781 * ring entry of the gather copy cycle in taken into account. 8782 * 8783 * src_swap 8784 * Treats source memory organization as big-endian. For 8785 * each dword read (4 bytes), the byte 0 is swapped with byte 3 8786 * and byte 1 is swapped with byte 2. 8787 * In case of gather field in first source ring entry of 8788 * the gather copy cycle in taken into account. 8789 * 8790 * dest_swap 8791 * Treats destination memory organization as big-endian. 8792 * For each dword write (4 bytes), the byte 0 is swapped with 8793 * byte 3 and byte 1 is swapped with byte 2. 8794 * In case of gather field in first source ring entry of 8795 * the gather copy cycle in taken into account. 8796 * 8797 * gather 8798 * Enables gather of multiple copy engine source 8799 * descriptors to one destination. 8800 * 8801 * ce_res_0 8802 * Reserved 8803 * 8804 * 8805 * length 8806 * Length of the buffer in units of octets of the current 8807 * descriptor 8808 * 8809 * fw_metadata 8810 * Meta data used by FW. 8811 * In case of gather field in first source ring entry of 8812 * the gather copy cycle in taken into account. 8813 * 8814 * ce_res_1 8815 * Reserved 8816 * 8817 * ce_res_2 8818 * Reserved 8819 * 8820 * ring_id 8821 * The buffer pointer ring ID. 8822 * 0 refers to the IDLE ring 8823 * 1 - N refers to other rings 8824 * Helps with debugging when dumping ring contents. 8825 * 8826 * looping_count 8827 * A count value that indicates the number of times the 8828 * producer of entries into the Ring has looped around the 8829 * ring. 8830 * 8831 * At initialization time, this value is set to 0. On the 8832 * first loop, this value is set to 1. After the max value is 8833 * reached allowed by the number of bits for this field, the 8834 * count value continues with 0 again. 8835 * 8836 * In case SW is the consumer of the ring entries, it can 8837 * use this field to figure out up to where the producer of 8838 * entries has created new entries. This eliminates the need to 8839 * check where the head pointer' of the ring is located once 8840 * the SW starts processing an interrupt indicating that new 8841 * entries have been put into this ring... 8842 * 8843 * Also note that SW if it wants only needs to look at the 8844 * LSB bit of this count value. 8845 */ 8846 8847 #define HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0) 8848 #define HAL_CE_DEST_DESC_ADDR_INFO_RING_ID GENMASK(27, 20) 8849 #define HAL_CE_DEST_DESC_ADDR_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 8850 8851 struct hal_ce_srng_dest_desc { 8852 uint32_t buffer_addr_low; 8853 uint32_t buffer_addr_info; /* %HAL_CE_DEST_DESC_ADDR_INFO_ */ 8854 } __packed; 8855 8856 /* hal_ce_srng_dest_desc 8857 * 8858 * dst_buffer_low 8859 * LSB 32 bits of the 40 Bit Pointer to the Destination 8860 * buffer 8861 * 8862 * dst_buffer_high 8863 * MSB 8 bits of the 40 Bit Pointer to the Destination 8864 * buffer 8865 * 8866 * ce_res_4 8867 * Reserved 8868 * 8869 * ring_id 8870 * The buffer pointer ring ID. 8871 * 0 refers to the IDLE ring 8872 * 1 - N refers to other rings 8873 * Helps with debugging when dumping ring contents. 8874 * 8875 * looping_count 8876 * A count value that indicates the number of times the 8877 * producer of entries into the Ring has looped around the 8878 * ring. 8879 * 8880 * At initialization time, this value is set to 0. On the 8881 * first loop, this value is set to 1. After the max value is 8882 * reached allowed by the number of bits for this field, the 8883 * count value continues with 0 again. 8884 * 8885 * In case SW is the consumer of the ring entries, it can 8886 * use this field to figure out up to where the producer of 8887 * entries has created new entries. This eliminates the need to 8888 * check where the head pointer' of the ring is located once 8889 * the SW starts processing an interrupt indicating that new 8890 * entries have been put into this ring... 8891 * 8892 * Also note that SW if it wants only needs to look at the 8893 * LSB bit of this count value. 8894 */ 8895 8896 #define HAL_CE_DST_STATUS_DESC_FLAGS_HASH_EN BIT(8) 8897 #define HAL_CE_DST_STATUS_DESC_FLAGS_BYTE_SWAP BIT(9) 8898 #define HAL_CE_DST_STATUS_DESC_FLAGS_DEST_SWAP BIT(10) 8899 #define HAL_CE_DST_STATUS_DESC_FLAGS_GATHER BIT(11) 8900 #define HAL_CE_DST_STATUS_DESC_FLAGS_LEN GENMASK(31, 16) 8901 8902 #define HAL_CE_DST_STATUS_DESC_META_INFO_DATA GENMASK(15, 0) 8903 #define HAL_CE_DST_STATUS_DESC_META_INFO_RING_ID GENMASK(27, 20) 8904 #define HAL_CE_DST_STATUS_DESC_META_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 8905 8906 struct hal_ce_srng_dst_status_desc { 8907 uint32_t flags; /* %HAL_CE_DST_STATUS_DESC_FLAGS_ */ 8908 uint32_t toeplitz_hash0; 8909 uint32_t toeplitz_hash1; 8910 uint32_t meta_info; /* HAL_CE_DST_STATUS_DESC_META_INFO_ */ 8911 } __packed; 8912 8913 /* hal_ce_srng_dst_status_desc 8914 * 8915 * ce_res_5 8916 * Reserved 8917 * 8918 * toeplitz_en 8919 * 8920 * src_swap 8921 * Source memory buffer swapped 8922 * 8923 * dest_swap 8924 * Destination memory buffer swapped 8925 * 8926 * gather 8927 * Gather of multiple copy engine source descriptors to one 8928 * destination enabled 8929 * 8930 * ce_res_6 8931 * Reserved 8932 * 8933 * length 8934 * Sum of all the Lengths of the source descriptor in the 8935 * gather chain 8936 * 8937 * toeplitz_hash_0 8938 * 32 LS bits of 64 bit Toeplitz LFSR hash result 8939 * 8940 * toeplitz_hash_1 8941 * 32 MS bits of 64 bit Toeplitz LFSR hash result 8942 * 8943 * fw_metadata 8944 * Meta data used by FW 8945 * In case of gather field in first source ring entry of 8946 * the gather copy cycle in taken into account. 8947 * 8948 * ce_res_7 8949 * Reserved 8950 * 8951 * ring_id 8952 * The buffer pointer ring ID. 8953 * 0 refers to the IDLE ring 8954 * 1 - N refers to other rings 8955 * Helps with debugging when dumping ring contents. 8956 * 8957 * looping_count 8958 * A count value that indicates the number of times the 8959 * producer of entries into the Ring has looped around the 8960 * ring. 8961 * 8962 * At initialization time, this value is set to 0. On the 8963 * first loop, this value is set to 1. After the max value is 8964 * reached allowed by the number of bits for this field, the 8965 * count value continues with 0 again. 8966 * 8967 * In case SW is the consumer of the ring entries, it can 8968 * use this field to figure out up to where the producer of 8969 * entries has created new entries. This eliminates the need to 8970 * check where the head pointer' of the ring is located once 8971 * the SW starts processing an interrupt indicating that new 8972 * entries have been put into this ring... 8973 * 8974 * Also note that SW if it wants only needs to look at the 8975 * LSB bit of this count value. 8976 */ 8977 8978 #define HAL_TX_RATE_STATS_INFO0_VALID BIT(0) 8979 #define HAL_TX_RATE_STATS_INFO0_BW GENMASK(2, 1) 8980 #define HAL_TX_RATE_STATS_INFO0_PKT_TYPE GENMASK(6, 3) 8981 #define HAL_TX_RATE_STATS_INFO0_STBC BIT(7) 8982 #define HAL_TX_RATE_STATS_INFO0_LDPC BIT(8) 8983 #define HAL_TX_RATE_STATS_INFO0_SGI GENMASK(10, 9) 8984 #define HAL_TX_RATE_STATS_INFO0_MCS GENMASK(14, 11) 8985 #define HAL_TX_RATE_STATS_INFO0_OFDMA_TX BIT(15) 8986 #define HAL_TX_RATE_STATS_INFO0_TONES_IN_RU GENMASK(27, 16) 8987 8988 enum hal_tx_rate_stats_bw { 8989 HAL_TX_RATE_STATS_BW_20, 8990 HAL_TX_RATE_STATS_BW_40, 8991 HAL_TX_RATE_STATS_BW_80, 8992 HAL_TX_RATE_STATS_BW_160, 8993 }; 8994 8995 enum hal_tx_rate_stats_pkt_type { 8996 HAL_TX_RATE_STATS_PKT_TYPE_11A, 8997 HAL_TX_RATE_STATS_PKT_TYPE_11B, 8998 HAL_TX_RATE_STATS_PKT_TYPE_11N, 8999 HAL_TX_RATE_STATS_PKT_TYPE_11AC, 9000 HAL_TX_RATE_STATS_PKT_TYPE_11AX, 9001 }; 9002 9003 enum hal_tx_rate_stats_sgi { 9004 HAL_TX_RATE_STATS_SGI_08US, 9005 HAL_TX_RATE_STATS_SGI_04US, 9006 HAL_TX_RATE_STATS_SGI_16US, 9007 HAL_TX_RATE_STATS_SGI_32US, 9008 }; 9009 9010 struct hal_tx_rate_stats { 9011 uint32_t info0; 9012 uint32_t tsf; 9013 } __packed; 9014 9015 struct hal_wbm_link_desc { 9016 struct ath11k_buffer_addr buf_addr_info; 9017 } __packed; 9018 9019 /* hal_wbm_link_desc 9020 * 9021 * Producer: WBM 9022 * Consumer: WBM 9023 * 9024 * buf_addr_info 9025 * Details of the physical address of a buffer or MSDU 9026 * link descriptor. 9027 */ 9028 9029 enum hal_wbm_rel_src_module { 9030 HAL_WBM_REL_SRC_MODULE_TQM, 9031 HAL_WBM_REL_SRC_MODULE_RXDMA, 9032 HAL_WBM_REL_SRC_MODULE_REO, 9033 HAL_WBM_REL_SRC_MODULE_FW, 9034 HAL_WBM_REL_SRC_MODULE_SW, 9035 }; 9036 9037 enum hal_wbm_rel_desc_type { 9038 HAL_WBM_REL_DESC_TYPE_REL_MSDU, 9039 HAL_WBM_REL_DESC_TYPE_MSDU_LINK, 9040 HAL_WBM_REL_DESC_TYPE_MPDU_LINK, 9041 HAL_WBM_REL_DESC_TYPE_MSDU_EXT, 9042 HAL_WBM_REL_DESC_TYPE_QUEUE_EXT, 9043 }; 9044 9045 /* hal_wbm_rel_desc_type 9046 * 9047 * msdu_buffer 9048 * The address points to an MSDU buffer 9049 * 9050 * msdu_link_descriptor 9051 * The address points to an Tx MSDU link descriptor 9052 * 9053 * mpdu_link_descriptor 9054 * The address points to an MPDU link descriptor 9055 * 9056 * msdu_ext_descriptor 9057 * The address points to an MSDU extension descriptor 9058 * 9059 * queue_ext_descriptor 9060 * The address points to an TQM queue extension descriptor. WBM should 9061 * treat this is the same way as a link descriptor. 9062 */ 9063 9064 enum hal_wbm_rel_bm_act { 9065 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE, 9066 HAL_WBM_REL_BM_ACT_REL_MSDU, 9067 }; 9068 9069 /* hal_wbm_rel_bm_act 9070 * 9071 * put_in_idle_list 9072 * Put the buffer or descriptor back in the idle list. In case of MSDU or 9073 * MDPU link descriptor, BM does not need to check to release any 9074 * individual MSDU buffers. 9075 * 9076 * release_msdu_list 9077 * This BM action can only be used in combination with desc_type being 9078 * msdu_link_descriptor. Field first_msdu_index points out which MSDU 9079 * pointer in the MSDU link descriptor is the first of an MPDU that is 9080 * released. BM shall release all the MSDU buffers linked to this first 9081 * MSDU buffer pointer. All related MSDU buffer pointer entries shall be 9082 * set to value 0, which represents the 'NULL' pointer. When all MSDU 9083 * buffer pointers in the MSDU link descriptor are 'NULL', the MSDU link 9084 * descriptor itself shall also be released. 9085 */ 9086 9087 #define HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE GENMASK(2, 0) 9088 #define HAL_WBM_RELEASE_INFO0_BM_ACTION GENMASK(5, 3) 9089 #define HAL_WBM_RELEASE_INFO0_DESC_TYPE GENMASK(8, 6) 9090 #define HAL_WBM_RELEASE_INFO0_FIRST_MSDU_IDX GENMASK(12, 9) 9091 #define HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON GENMASK(16, 13) 9092 #define HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17) 9093 #define HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19) 9094 #define HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON GENMASK(25, 24) 9095 #define HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE GENMASK(30, 26) 9096 #define HAL_WBM_RELEASE_INFO0_WBM_INTERNAL_ERROR BIT(31) 9097 9098 #define HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0) 9099 #define HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT GENMASK(30, 24) 9100 9101 #define HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI GENMASK(7, 0) 9102 #define HAL_WBM_RELEASE_INFO2_SW_REL_DETAILS_VALID BIT(8) 9103 #define HAL_WBM_RELEASE_INFO2_FIRST_MSDU BIT(9) 9104 #define HAL_WBM_RELEASE_INFO2_LAST_MSDU BIT(10) 9105 #define HAL_WBM_RELEASE_INFO2_MSDU_IN_AMSDU BIT(11) 9106 #define HAL_WBM_RELEASE_INFO2_FW_TX_NOTIF_FRAME BIT(12) 9107 #define HAL_WBM_RELEASE_INFO2_BUFFER_TIMESTAMP GENMASK(31, 13) 9108 9109 #define HAL_WBM_RELEASE_INFO3_PEER_ID GENMASK(15, 0) 9110 #define HAL_WBM_RELEASE_INFO3_TID GENMASK(19, 16) 9111 #define HAL_WBM_RELEASE_INFO3_RING_ID GENMASK(27, 20) 9112 #define HAL_WBM_RELEASE_INFO3_LOOPING_COUNT GENMASK(31, 28) 9113 9114 #define HAL_WBM_REL_HTT_TX_COMP_INFO0_STATUS GENMASK(12, 9) 9115 #define HAL_WBM_REL_HTT_TX_COMP_INFO0_REINJ_REASON GENMASK(16, 13) 9116 #define HAL_WBM_REL_HTT_TX_COMP_INFO0_EXP_FRAME BIT(17) 9117 9118 struct hal_wbm_release_ring { 9119 struct ath11k_buffer_addr buf_addr_info; 9120 uint32_t info0; 9121 uint32_t info1; 9122 uint32_t info2; 9123 struct hal_tx_rate_stats rate_stats; 9124 uint32_t info3; 9125 } __packed; 9126 9127 /* hal_wbm_release_ring 9128 * 9129 * Producer: SW/TQM/RXDMA/REO/SWITCH 9130 * Consumer: WBM/SW/FW 9131 * 9132 * HTT tx status is overlaid on wbm_release ring on 4-byte words 2, 3, 4 and 5 9133 * for software based completions. 9134 * 9135 * buf_addr_info 9136 * Details of the physical address of the buffer or link descriptor. 9137 * 9138 * release_source_module 9139 * Indicates which module initiated the release of this buffer/descriptor. 9140 * Values are defined in enum %HAL_WBM_REL_SRC_MODULE_. 9141 * 9142 * bm_action 9143 * Field only valid when the field return_buffer_manager in 9144 * Released_buff_or_desc_addr_info indicates: 9145 * WBM_IDLE_BUF_LIST / WBM_IDLE_DESC_LIST 9146 * Values are defined in enum %HAL_WBM_REL_BM_ACT_. 9147 * 9148 * buffer_or_desc_type 9149 * Field only valid when WBM is marked as the return_buffer_manager in 9150 * the Released_Buffer_address_info. Indicates that type of buffer or 9151 * descriptor is being released. Values are in enum %HAL_WBM_REL_DESC_TYPE. 9152 * 9153 * first_msdu_index 9154 * Field only valid for the bm_action release_msdu_list. The index of the 9155 * first MSDU in an MSDU link descriptor all belonging to the same MPDU. 9156 * 9157 * tqm_release_reason 9158 * Field only valid when Release_source_module is set to release_source_TQM 9159 * Release reasons are defined in enum %HAL_WBM_TQM_REL_REASON_. 9160 * 9161 * rxdma_push_reason 9162 * reo_push_reason 9163 * Indicates why rxdma/reo pushed the frame to this ring and values are 9164 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 9165 * 9166 * rxdma_error_code 9167 * Field only valid when 'rxdma_push_reason' set to 'error_detected'. 9168 * Values are defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_. 9169 * 9170 * reo_error_code 9171 * Field only valid when 'reo_push_reason' set to 'error_detected'. Values 9172 * are defined in enum %HAL_REO_DEST_RING_ERROR_CODE_. 9173 * 9174 * wbm_internal_error 9175 * Is set when WBM got a buffer pointer but the action was to push it to 9176 * the idle link descriptor ring or do link related activity OR 9177 * Is set when WBM got a link buffer pointer but the action was to push it 9178 * to the buffer descriptor ring. 9179 * 9180 * tqm_status_number 9181 * The value in this field is equal to tqm_cmd_number in TQM command. It is 9182 * used to correlate the statu with TQM commands. Only valid when 9183 * release_source_module is TQM. 9184 * 9185 * transmit_count 9186 * The number of times the frame has been transmitted, valid only when 9187 * release source in TQM. 9188 * 9189 * ack_frame_rssi 9190 * This field is only valid when the source is TQM. If this frame is 9191 * removed as the result of the reception of an ACK or BA, this field 9192 * indicates the RSSI of the received ACK or BA frame. 9193 * 9194 * sw_release_details_valid 9195 * This is set when WMB got a 'release_msdu_list' command from TQM and 9196 * return buffer manager is not WMB. WBM will then de-aggregate all MSDUs 9197 * and pass them one at a time on to the 'buffer owner'. 9198 * 9199 * first_msdu 9200 * Field only valid when SW_release_details_valid is set. 9201 * When set, this MSDU is the first MSDU pointed to in the 9202 * 'release_msdu_list' command. 9203 * 9204 * last_msdu 9205 * Field only valid when SW_release_details_valid is set. 9206 * When set, this MSDU is the last MSDU pointed to in the 9207 * 'release_msdu_list' command. 9208 * 9209 * msdu_part_of_amsdu 9210 * Field only valid when SW_release_details_valid is set. 9211 * When set, this MSDU was part of an A-MSDU in MPDU 9212 * 9213 * fw_tx_notify_frame 9214 * Field only valid when SW_release_details_valid is set. 9215 * 9216 * buffer_timestamp 9217 * Field only valid when SW_release_details_valid is set. 9218 * This is the Buffer_timestamp field from the 9219 * Timestamp in units of 1024 us 9220 * 9221 * struct hal_tx_rate_stats rate_stats 9222 * Details for command execution tracking purposes. 9223 * 9224 * sw_peer_id 9225 * tid 9226 * Field only valid when Release_source_module is set to 9227 * release_source_TQM 9228 * 9229 * 1) Release of msdu buffer due to drop_frame = 1. Flow is 9230 * not fetched and hence sw_peer_id and tid = 0 9231 * 9232 * buffer_or_desc_type = e_num 0 9233 * MSDU_rel_buffertqm_release_reason = e_num 1 9234 * tqm_rr_rem_cmd_rem 9235 * 9236 * 2) Release of msdu buffer due to Flow is not fetched and 9237 * hence sw_peer_id and tid = 0 9238 * 9239 * buffer_or_desc_type = e_num 0 9240 * MSDU_rel_buffertqm_release_reason = e_num 1 9241 * tqm_rr_rem_cmd_rem 9242 * 9243 * 3) Release of msdu link due to remove_mpdu or acked_mpdu 9244 * command. 9245 * 9246 * buffer_or_desc_type = e_num1 9247 * msdu_link_descriptortqm_release_reason can be:e_num 1 9248 * tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx 9249 * e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged 9250 * 9251 * This field represents the TID from the TX_MSDU_FLOW 9252 * descriptor or TX_MPDU_QUEUE descriptor 9253 * 9254 * rind_id 9255 * For debugging. 9256 * This field is filled in by the SRNG module. 9257 * It help to identify the ring that is being looked 9258 * 9259 * looping_count 9260 * A count value that indicates the number of times the 9261 * producer of entries into the Buffer Manager Ring has looped 9262 * around the ring. 9263 * 9264 * At initialization time, this value is set to 0. On the 9265 * first loop, this value is set to 1. After the max value is 9266 * reached allowed by the number of bits for this field, the 9267 * count value continues with 0 again. 9268 * 9269 * In case SW is the consumer of the ring entries, it can 9270 * use this field to figure out up to where the producer of 9271 * entries has created new entries. This eliminates the need to 9272 * check where the head pointer' of the ring is located once 9273 * the SW starts processing an interrupt indicating that new 9274 * entries have been put into this ring... 9275 * 9276 * Also note that SW if it wants only needs to look at the 9277 * LSB bit of this count value. 9278 */ 9279 9280 /** 9281 * enum hal_wbm_tqm_rel_reason - TQM release reason code 9282 * @HAL_WBM_TQM_REL_REASON_FRAME_ACKED: ACK or BACK received for the frame 9283 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU: Command remove_mpdus initiated by SW 9284 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX: Command remove transmitted_mpdus 9285 * initiated by sw. 9286 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX: Command remove untransmitted_mpdus 9287 * initiated by sw. 9288 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES: Command remove aged msdus or 9289 * mpdus. 9290 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1: Remove command initiated by 9291 * fw with fw_reason1. 9292 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2: Remove command initiated by 9293 * fw with fw_reason2. 9294 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3: Remove command initiated by 9295 * fw with fw_reason3. 9296 */ 9297 enum hal_wbm_tqm_rel_reason { 9298 HAL_WBM_TQM_REL_REASON_FRAME_ACKED, 9299 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU, 9300 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX, 9301 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX, 9302 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES, 9303 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1, 9304 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2, 9305 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3, 9306 }; 9307 9308 struct hal_wbm_buffer_ring { 9309 struct ath11k_buffer_addr buf_addr_info; 9310 }; 9311 9312 enum hal_desc_owner { 9313 HAL_DESC_OWNER_WBM, 9314 HAL_DESC_OWNER_SW, 9315 HAL_DESC_OWNER_TQM, 9316 HAL_DESC_OWNER_RXDMA, 9317 HAL_DESC_OWNER_REO, 9318 HAL_DESC_OWNER_SWITCH, 9319 }; 9320 9321 enum hal_desc_buf_type { 9322 HAL_DESC_BUF_TYPE_TX_MSDU_LINK, 9323 HAL_DESC_BUF_TYPE_TX_MPDU_LINK, 9324 HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_HEAD, 9325 HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_EXT, 9326 HAL_DESC_BUF_TYPE_TX_FLOW, 9327 HAL_DESC_BUF_TYPE_TX_BUFFER, 9328 HAL_DESC_BUF_TYPE_RX_MSDU_LINK, 9329 HAL_DESC_BUF_TYPE_RX_MPDU_LINK, 9330 HAL_DESC_BUF_TYPE_RX_REO_QUEUE, 9331 HAL_DESC_BUF_TYPE_RX_REO_QUEUE_EXT, 9332 HAL_DESC_BUF_TYPE_RX_BUFFER, 9333 HAL_DESC_BUF_TYPE_IDLE_LINK, 9334 }; 9335 9336 #define HAL_DESC_REO_OWNED 4 9337 #define HAL_DESC_REO_QUEUE_DESC 8 9338 #define HAL_DESC_REO_QUEUE_EXT_DESC 9 9339 #define HAL_DESC_REO_NON_QOS_TID 16 9340 9341 #define HAL_DESC_HDR_INFO0_OWNER GENMASK(3, 0) 9342 #define HAL_DESC_HDR_INFO0_BUF_TYPE GENMASK(7, 4) 9343 #define HAL_DESC_HDR_INFO0_DBG_RESERVED GENMASK(31, 8) 9344 9345 struct hal_desc_header { 9346 uint32_t info0; 9347 } __packed; 9348 9349 struct hal_rx_mpdu_link_ptr { 9350 struct ath11k_buffer_addr addr_info; 9351 } __packed; 9352 9353 struct hal_rx_msdu_details { 9354 struct ath11k_buffer_addr buf_addr_info; 9355 struct rx_msdu_desc rx_msdu_info; 9356 } __packed; 9357 9358 #define HAL_RX_MSDU_LNK_INFO0_RX_QUEUE_NUMBER GENMASK(15, 0) 9359 #define HAL_RX_MSDU_LNK_INFO0_FIRST_MSDU_LNK BIT(16) 9360 9361 struct hal_rx_msdu_link { 9362 struct hal_desc_header desc_hdr; 9363 struct ath11k_buffer_addr buf_addr_info; 9364 uint32_t info0; 9365 uint32_t pn[4]; 9366 struct hal_rx_msdu_details msdu_link[6]; 9367 } __packed; 9368 9369 struct hal_rx_reo_queue_ext { 9370 struct hal_desc_header desc_hdr; 9371 uint32_t rsvd; 9372 struct hal_rx_mpdu_link_ptr mpdu_link[15]; 9373 } __packed; 9374 9375 /* hal_rx_reo_queue_ext 9376 * Consumer: REO 9377 * Producer: REO 9378 * 9379 * descriptor_header 9380 * Details about which module owns this struct. 9381 * 9382 * mpdu_link 9383 * Pointer to the next MPDU_link descriptor in the MPDU queue. 9384 */ 9385 9386 enum hal_rx_reo_queue_pn_size { 9387 HAL_RX_REO_QUEUE_PN_SIZE_24, 9388 HAL_RX_REO_QUEUE_PN_SIZE_48, 9389 HAL_RX_REO_QUEUE_PN_SIZE_128, 9390 }; 9391 9392 #define HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER GENMASK(15, 0) 9393 9394 #define HAL_RX_REO_QUEUE_INFO0_VLD BIT(0) 9395 #define HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER GENMASK(2, 1) 9396 #define HAL_RX_REO_QUEUE_INFO0_DIS_DUP_DETECTION BIT(3) 9397 #define HAL_RX_REO_QUEUE_INFO0_SOFT_REORDER_EN BIT(4) 9398 #define HAL_RX_REO_QUEUE_INFO0_AC GENMASK(6, 5) 9399 #define HAL_RX_REO_QUEUE_INFO0_BAR BIT(7) 9400 #define HAL_RX_REO_QUEUE_INFO0_RETRY BIT(8) 9401 #define HAL_RX_REO_QUEUE_INFO0_CHECK_2K_MODE BIT(9) 9402 #define HAL_RX_REO_QUEUE_INFO0_OOR_MODE BIT(10) 9403 #define HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE GENMASK(18, 11) 9404 #define HAL_RX_REO_QUEUE_INFO0_PN_CHECK BIT(19) 9405 #define HAL_RX_REO_QUEUE_INFO0_EVEN_PN BIT(20) 9406 #define HAL_RX_REO_QUEUE_INFO0_UNEVEN_PN BIT(21) 9407 #define HAL_RX_REO_QUEUE_INFO0_PN_HANDLE_ENABLE BIT(22) 9408 #define HAL_RX_REO_QUEUE_INFO0_PN_SIZE GENMASK(24, 23) 9409 #define HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG BIT(25) 9410 9411 #define HAL_RX_REO_QUEUE_INFO1_SVLD BIT(0) 9412 #define HAL_RX_REO_QUEUE_INFO1_SSN GENMASK(12, 1) 9413 #define HAL_RX_REO_QUEUE_INFO1_CURRENT_IDX GENMASK(20, 13) 9414 #define HAL_RX_REO_QUEUE_INFO1_SEQ_2K_ERR BIT(21) 9415 #define HAL_RX_REO_QUEUE_INFO1_PN_ERR BIT(22) 9416 #define HAL_RX_REO_QUEUE_INFO1_PN_VALID BIT(31) 9417 9418 #define HAL_RX_REO_QUEUE_INFO2_MPDU_COUNT GENMASK(6, 0) 9419 #define HAL_RX_REO_QUEUE_INFO2_MSDU_COUNT (31, 7) 9420 9421 #define HAL_RX_REO_QUEUE_INFO3_TIMEOUT_COUNT GENMASK(9, 4) 9422 #define HAL_RX_REO_QUEUE_INFO3_FWD_DUE_TO_BAR_CNT GENMASK(15, 10) 9423 #define HAL_RX_REO_QUEUE_INFO3_DUPLICATE_COUNT GENMASK(31, 16) 9424 9425 #define HAL_RX_REO_QUEUE_INFO4_FRAME_IN_ORD_COUNT GENMASK(23, 0) 9426 #define HAL_RX_REO_QUEUE_INFO4_BAR_RECVD_COUNT GENMASK(31, 24) 9427 9428 #define HAL_RX_REO_QUEUE_INFO5_LATE_RX_MPDU_COUNT GENMASK(11, 0) 9429 #define HAL_RX_REO_QUEUE_INFO5_WINDOW_JUMP_2K GENMASK(15, 12) 9430 #define HAL_RX_REO_QUEUE_INFO5_HOLE_COUNT GENMASK(31, 16) 9431 9432 struct hal_rx_reo_queue { 9433 struct hal_desc_header desc_hdr; 9434 uint32_t rx_queue_num; 9435 uint32_t info0; 9436 uint32_t info1; 9437 uint32_t pn[4]; 9438 uint32_t last_rx_enqueue_timestamp; 9439 uint32_t last_rx_dequeue_timestamp; 9440 uint32_t next_aging_queue[2]; 9441 uint32_t prev_aging_queue[2]; 9442 uint32_t rx_bitmap[8]; 9443 uint32_t info2; 9444 uint32_t info3; 9445 uint32_t info4; 9446 uint32_t processed_mpdus; 9447 uint32_t processed_msdus; 9448 uint32_t processed_total_bytes; 9449 uint32_t info5; 9450 uint32_t rsvd[3]; 9451 struct hal_rx_reo_queue_ext ext_desc[]; 9452 } __packed; 9453 9454 /* hal_rx_reo_queue 9455 * 9456 * descriptor_header 9457 * Details about which module owns this struct. Note that sub field 9458 * Buffer_type shall be set to receive_reo_queue_descriptor. 9459 * 9460 * receive_queue_number 9461 * Indicates the MPDU queue ID to which this MPDU link descriptor belongs. 9462 * 9463 * vld 9464 * Valid bit indicating a session is established and the queue descriptor 9465 * is valid. 9466 * associated_link_descriptor_counter 9467 * Indicates which of the 3 link descriptor counters shall be incremented 9468 * or decremented when link descriptors are added or removed from this 9469 * flow queue. 9470 * disable_duplicate_detection 9471 * When set, do not perform any duplicate detection. 9472 * soft_reorder_enable 9473 * When set, REO has been instructed to not perform the actual re-ordering 9474 * of frames for this queue, but just to insert the reorder opcodes. 9475 * ac 9476 * Indicates the access category of the queue descriptor. 9477 * bar 9478 * Indicates if BAR has been received. 9479 * retry 9480 * Retry bit is checked if this bit is set. 9481 * chk_2k_mode 9482 * Indicates what type of operation is expected from Reo when the received 9483 * frame SN falls within the 2K window. 9484 * oor_mode 9485 * Indicates what type of operation is expected when the received frame 9486 * falls within the OOR window. 9487 * ba_window_size 9488 * Indicates the negotiated (window size + 1). Max of 256 bits. 9489 * 9490 * A value 255 means 256 bitmap, 63 means 64 bitmap, 0 (means non-BA 9491 * session, with window size of 0). The 3 values here are the main values 9492 * validated, but other values should work as well. 9493 * 9494 * A BA window size of 0 (=> one frame entry bitmat), means that there is 9495 * no additional rx_reo_queue_ext desc. following rx_reo_queue in memory. 9496 * A BA window size of 1 - 105, means that there is 1 rx_reo_queue_ext. 9497 * A BA window size of 106 - 210, means that there are 2 rx_reo_queue_ext. 9498 * A BA window size of 211 - 256, means that there are 3 rx_reo_queue_ext. 9499 * pn_check_needed, pn_shall_be_even, pn_shall_be_uneven, pn_handling_enable, 9500 * pn_size 9501 * REO shall perform the PN increment check, even number check, uneven 9502 * number check, PN error check and size of the PN field check. 9503 * ignore_ampdu_flag 9504 * REO shall ignore the ampdu_flag on entrance descriptor for this queue. 9505 * 9506 * svld 9507 * Sequence number in next field is valid one. 9508 * ssn 9509 * Starting Sequence number of the session. 9510 * current_index 9511 * Points to last forwarded packet 9512 * seq_2k_error_detected_flag 9513 * REO has detected a 2k error jump in the sequence number and from that 9514 * moment forward, all new frames are forwarded directly to FW, without 9515 * duplicate detect, reordering, etc. 9516 * pn_error_detected_flag 9517 * REO has detected a PN error. 9518 */ 9519 9520 #define HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 9521 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM BIT(8) 9522 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD BIT(9) 9523 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT BIT(10) 9524 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION BIT(11) 9525 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN BIT(12) 9526 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC BIT(13) 9527 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR BIT(14) 9528 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY BIT(15) 9529 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE BIT(16) 9530 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE BIT(17) 9531 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE BIT(18) 9532 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK BIT(19) 9533 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN BIT(20) 9534 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN BIT(21) 9535 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE BIT(22) 9536 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE BIT(23) 9537 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG BIT(24) 9538 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD BIT(25) 9539 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN BIT(26) 9540 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR BIT(27) 9541 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_ERR BIT(28) 9542 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID BIT(29) 9543 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN BIT(30) 9544 9545 #define HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER GENMASK(15, 0) 9546 #define HAL_REO_UPD_RX_QUEUE_INFO1_VLD BIT(16) 9547 #define HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER GENMASK(18, 17) 9548 #define HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION BIT(19) 9549 #define HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN BIT(20) 9550 #define HAL_REO_UPD_RX_QUEUE_INFO1_AC GENMASK(22, 21) 9551 #define HAL_REO_UPD_RX_QUEUE_INFO1_BAR BIT(23) 9552 #define HAL_REO_UPD_RX_QUEUE_INFO1_RETRY BIT(24) 9553 #define HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE BIT(25) 9554 #define HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE BIT(26) 9555 #define HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK BIT(27) 9556 #define HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN BIT(28) 9557 #define HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN BIT(29) 9558 #define HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE BIT(30) 9559 #define HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG BIT(31) 9560 9561 #define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE GENMASK(7, 0) 9562 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE GENMASK(9, 8) 9563 #define HAL_REO_UPD_RX_QUEUE_INFO2_SVLD BIT(10) 9564 #define HAL_REO_UPD_RX_QUEUE_INFO2_SSN GENMASK(22, 11) 9565 #define HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR BIT(23) 9566 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR BIT(24) 9567 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_VALID BIT(25) 9568 9569 struct hal_reo_update_rx_queue { 9570 struct hal_reo_cmd_hdr cmd; 9571 uint32_t queue_addr_lo; 9572 uint32_t info0; 9573 uint32_t info1; 9574 uint32_t info2; 9575 uint32_t pn[4]; 9576 } __packed; 9577 9578 #define HAL_REO_UNBLOCK_CACHE_INFO0_UNBLK_CACHE BIT(0) 9579 #define HAL_REO_UNBLOCK_CACHE_INFO0_RESOURCE_IDX GENMASK(2, 1) 9580 9581 struct hal_reo_unblock_cache { 9582 struct hal_reo_cmd_hdr cmd; 9583 uint32_t info0; 9584 uint32_t rsvd[7]; 9585 } __packed; 9586 9587 enum hal_reo_exec_status { 9588 HAL_REO_EXEC_STATUS_SUCCESS, 9589 HAL_REO_EXEC_STATUS_BLOCKED, 9590 HAL_REO_EXEC_STATUS_FAILED, 9591 HAL_REO_EXEC_STATUS_RESOURCE_BLOCKED, 9592 }; 9593 9594 #define HAL_REO_STATUS_HDR_INFO0_STATUS_NUM GENMASK(15, 0) 9595 #define HAL_REO_STATUS_HDR_INFO0_EXEC_TIME GENMASK(25, 16) 9596 #define HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS GENMASK(27, 26) 9597 9598 struct hal_reo_status_hdr { 9599 uint32_t info0; 9600 uint32_t timestamp; 9601 } __packed; 9602 9603 /* hal_reo_status_hdr 9604 * Producer: REO 9605 * Consumer: SW 9606 * 9607 * status_num 9608 * The value in this field is equal to value of the reo command 9609 * number. This field helps to correlate the statuses with the REO 9610 * commands. 9611 * 9612 * execution_time (in us) 9613 * The amount of time REO took to execute the command. Note that 9614 * this time does not include the duration of the command waiting 9615 * in the command ring, before the execution started. 9616 * 9617 * execution_status 9618 * Execution status of the command. Values are defined in 9619 * enum %HAL_REO_EXEC_STATUS_. 9620 */ 9621 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN GENMASK(11, 0) 9622 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX GENMASK(19, 12) 9623 9624 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT GENMASK(6, 0) 9625 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT GENMASK(31, 7) 9626 9627 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT GENMASK(9, 4) 9628 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT GENMASK(15, 10) 9629 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT GENMASK(31, 16) 9630 9631 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT GENMASK(23, 0) 9632 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT GENMASK(31, 24) 9633 9634 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU GENMASK(11, 0) 9635 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_WINDOW_JMP2K GENMASK(15, 12) 9636 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT GENMASK(31, 16) 9637 9638 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT GENMASK(31, 28) 9639 9640 struct hal_reo_get_queue_stats_status { 9641 struct hal_reo_status_hdr hdr; 9642 uint32_t info0; 9643 uint32_t pn[4]; 9644 uint32_t last_rx_enqueue_timestamp; 9645 uint32_t last_rx_dequeue_timestamp; 9646 uint32_t rx_bitmap[8]; 9647 uint32_t info1; 9648 uint32_t info2; 9649 uint32_t info3; 9650 uint32_t num_mpdu_frames; 9651 uint32_t num_msdu_frames; 9652 uint32_t total_bytes; 9653 uint32_t info4; 9654 uint32_t info5; 9655 } __packed; 9656 9657 /* hal_reo_get_queue_stats_status 9658 * Producer: REO 9659 * Consumer: SW 9660 * 9661 * status_hdr 9662 * Details that can link this status with the original command. It 9663 * also contains info on how long REO took to execute this command. 9664 * 9665 * ssn 9666 * Starting Sequence number of the session, this changes whenever 9667 * window moves (can be filled by SW then maintained by REO). 9668 * 9669 * current_index 9670 * Points to last forwarded packet. 9671 * 9672 * pn 9673 * Bits of the PN number. 9674 * 9675 * last_rx_enqueue_timestamp 9676 * last_rx_dequeue_timestamp 9677 * Timestamp of arrival of the last MPDU for this queue and 9678 * Timestamp of forwarding an MPDU accordingly. 9679 * 9680 * rx_bitmap 9681 * When a bit is set, the corresponding frame is currently held 9682 * in the re-order queue. The bitmap is Fully managed by HW. 9683 * 9684 * current_mpdu_count 9685 * current_msdu_count 9686 * The number of MPDUs and MSDUs in the queue. 9687 * 9688 * timeout_count 9689 * The number of times REO started forwarding frames even though 9690 * there is a hole in the bitmap. Forwarding reason is timeout. 9691 * 9692 * forward_due_to_bar_count 9693 * The number of times REO started forwarding frames even though 9694 * there is a hole in the bitmap. Fwd reason is reception of BAR. 9695 * 9696 * duplicate_count 9697 * The number of duplicate frames that have been detected. 9698 * 9699 * frames_in_order_count 9700 * The number of frames that have been received in order (without 9701 * a hole that prevented them from being forwarded immediately). 9702 * 9703 * bar_received_count 9704 * The number of times a BAR frame is received. 9705 * 9706 * mpdu_frames_processed_count 9707 * msdu_frames_processed_count 9708 * The total number of MPDU/MSDU frames that have been processed. 9709 * 9710 * total_bytes 9711 * An approximation of the number of bytes received for this queue. 9712 * 9713 * late_receive_mpdu_count 9714 * The number of MPDUs received after the window had already moved 9715 * on. The 'late' sequence window is defined as 9716 * (Window SSN - 256) - (Window SSN - 1). 9717 * 9718 * window_jump_2k 9719 * The number of times the window moved more than 2K 9720 * 9721 * hole_count 9722 * The number of times a hole was created in the receive bitmap. 9723 * 9724 * looping_count 9725 * A count value that indicates the number of times the producer of 9726 * entries into this Ring has looped around the ring. 9727 */ 9728 9729 #define HAL_REO_STATUS_LOOP_CNT GENMASK(31, 28) 9730 9731 #define HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED BIT(0) 9732 #define HAL_REO_FLUSH_QUEUE_INFO0_RSVD GENMASK(31, 1) 9733 #define HAL_REO_FLUSH_QUEUE_INFO1_RSVD GENMASK(27, 0) 9734 9735 struct hal_reo_flush_queue_status { 9736 struct hal_reo_status_hdr hdr; 9737 uint32_t info0; 9738 uint32_t rsvd0[21]; 9739 uint32_t info1; 9740 } __packed; 9741 9742 /* hal_reo_flush_queue_status 9743 * Producer: REO 9744 * Consumer: SW 9745 * 9746 * status_hdr 9747 * Details that can link this status with the original command. It 9748 * also contains info on how long REO took to execute this command. 9749 * 9750 * error_detected 9751 * Status of blocking resource 9752 * 9753 * 0 - No error has been detected while executing this command 9754 * 1 - Error detected. The resource to be used for blocking was 9755 * already in use. 9756 * 9757 * looping_count 9758 * A count value that indicates the number of times the producer of 9759 * entries into this Ring has looped around the ring. 9760 */ 9761 9762 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR BIT(0) 9763 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE GENMASK(2, 1) 9764 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT BIT(8) 9765 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE GENMASK(11, 9) 9766 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID GENMASK(15, 12) 9767 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR GENMASK(17, 16) 9768 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT GENMASK(25, 18) 9769 9770 struct hal_reo_flush_cache_status { 9771 struct hal_reo_status_hdr hdr; 9772 uint32_t info0; 9773 uint32_t rsvd0[21]; 9774 uint32_t info1; 9775 } __packed; 9776 9777 /* hal_reo_flush_cache_status 9778 * Producer: REO 9779 * Consumer: SW 9780 * 9781 * status_hdr 9782 * Details that can link this status with the original command. It 9783 * also contains info on how long REO took to execute this command. 9784 * 9785 * error_detected 9786 * Status for blocking resource handling 9787 * 9788 * 0 - No error has been detected while executing this command 9789 * 1 - An error in the blocking resource management was detected 9790 * 9791 * block_error_details 9792 * only valid when error_detected is set 9793 * 9794 * 0 - No blocking related errors found 9795 * 1 - Blocking resource is already in use 9796 * 2 - Resource requested to be unblocked, was not blocked 9797 * 9798 * cache_controller_flush_status_hit 9799 * The status that the cache controller returned on executing the 9800 * flush command. 9801 * 9802 * 0 - miss; 1 - hit 9803 * 9804 * cache_controller_flush_status_desc_type 9805 * Flush descriptor type 9806 * 9807 * cache_controller_flush_status_client_id 9808 * Module who made the flush request 9809 * 9810 * In REO, this is always 0 9811 * 9812 * cache_controller_flush_status_error 9813 * Error condition 9814 * 9815 * 0 - No error found 9816 * 1 - HW interface is still busy 9817 * 2 - Line currently locked. Used for one line flush command 9818 * 3 - At least one line is still locked. 9819 * Used for cache flush command. 9820 * 9821 * cache_controller_flush_count 9822 * The number of lines that were actually flushed out 9823 * 9824 * looping_count 9825 * A count value that indicates the number of times the producer of 9826 * entries into this Ring has looped around the ring. 9827 */ 9828 9829 #define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR BIT(0) 9830 #define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE BIT(1) 9831 9832 struct hal_reo_unblock_cache_status { 9833 struct hal_reo_status_hdr hdr; 9834 uint32_t info0; 9835 uint32_t rsvd0[21]; 9836 uint32_t info1; 9837 } __packed; 9838 9839 /* hal_reo_unblock_cache_status 9840 * Producer: REO 9841 * Consumer: SW 9842 * 9843 * status_hdr 9844 * Details that can link this status with the original command. It 9845 * also contains info on how long REO took to execute this command. 9846 * 9847 * error_detected 9848 * 0 - No error has been detected while executing this command 9849 * 1 - The blocking resource was not in use, and therefore it could 9850 * not be unblocked. 9851 * 9852 * unblock_type 9853 * Reference to the type of unblock command 9854 * 0 - Unblock a blocking resource 9855 * 1 - The entire cache usage is unblock 9856 * 9857 * looping_count 9858 * A count value that indicates the number of times the producer of 9859 * entries into this Ring has looped around the ring. 9860 */ 9861 9862 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR BIT(0) 9863 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY BIT(1) 9864 9865 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT GENMASK(15, 0) 9866 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT GENMASK(31, 16) 9867 9868 struct hal_reo_flush_timeout_list_status { 9869 struct hal_reo_status_hdr hdr; 9870 uint32_t info0; 9871 uint32_t info1; 9872 uint32_t rsvd0[20]; 9873 uint32_t info2; 9874 } __packed; 9875 9876 /* hal_reo_flush_timeout_list_status 9877 * Producer: REO 9878 * Consumer: SW 9879 * 9880 * status_hdr 9881 * Details that can link this status with the original command. It 9882 * also contains info on how long REO took to execute this command. 9883 * 9884 * error_detected 9885 * 0 - No error has been detected while executing this command 9886 * 1 - Command not properly executed and returned with error 9887 * 9888 * timeout_list_empty 9889 * When set, REO has depleted the timeout list and all entries are 9890 * gone. 9891 * 9892 * release_desc_count 9893 * Producer: SW; Consumer: REO 9894 * The number of link descriptor released 9895 * 9896 * forward_buf_count 9897 * Producer: SW; Consumer: REO 9898 * The number of buffers forwarded to the REO destination rings 9899 * 9900 * looping_count 9901 * A count value that indicates the number of times the producer of 9902 * entries into this Ring has looped around the ring. 9903 */ 9904 9905 #define HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX GENMASK(1, 0) 9906 #define HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0 GENMASK(23, 0) 9907 #define HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1 GENMASK(23, 0) 9908 #define HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2 GENMASK(23, 0) 9909 #define HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM GENMASK(25, 0) 9910 9911 struct hal_reo_desc_thresh_reached_status { 9912 struct hal_reo_status_hdr hdr; 9913 uint32_t info0; 9914 uint32_t info1; 9915 uint32_t info2; 9916 uint32_t info3; 9917 uint32_t info4; 9918 uint32_t rsvd0[17]; 9919 uint32_t info5; 9920 } __packed; 9921 9922 /* hal_reo_desc_thresh_reached_status 9923 * Producer: REO 9924 * Consumer: SW 9925 * 9926 * status_hdr 9927 * Details that can link this status with the original command. It 9928 * also contains info on how long REO took to execute this command. 9929 * 9930 * threshold_index 9931 * The index of the threshold register whose value got reached 9932 * 9933 * link_descriptor_counter0 9934 * link_descriptor_counter1 9935 * link_descriptor_counter2 9936 * link_descriptor_counter_sum 9937 * Value of the respective counters at generation of this message 9938 * 9939 * looping_count 9940 * A count value that indicates the number of times the producer of 9941 * entries into this Ring has looped around the ring. 9942 */ 9943 9944 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0 0xDDBEEF 9945 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1 0xADBEEF 9946 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2 0xBDBEEF 9947 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3 0xCDBEEF 9948 9949 #define HAL_TX_ADDRX_EN 1 9950 #define HAL_TX_ADDRY_EN 2 9951 9952 #define HAL_TX_ADDR_SEARCH_DEFAULT 0 9953 #define HAL_TX_ADDR_SEARCH_INDEX 1 9954 9955 /* 9956 * Copy Engine 9957 */ 9958 9959 #define CE_COUNT_MAX 12 9960 9961 /* Byte swap data words */ 9962 #define CE_ATTR_BYTE_SWAP_DATA 2 9963 9964 /* no interrupt on copy completion */ 9965 #define CE_ATTR_DIS_INTR 8 9966 9967 /* Host software's Copy Engine configuration. */ 9968 #ifdef __BIG_ENDIAN 9969 #define CE_ATTR_FLAGS CE_ATTR_BYTE_SWAP_DATA 9970 #else 9971 #define CE_ATTR_FLAGS 0 9972 #endif 9973 9974 /* Threshold to poll for tx completion in case of Interrupt disabled CE's */ 9975 #define ATH11K_CE_USAGE_THRESHOLD 32 9976 9977 /* 9978 * Directions for interconnect pipe configuration. 9979 * These definitions may be used during configuration and are shared 9980 * between Host and Target. 9981 * 9982 * Pipe Directions are relative to the Host, so PIPEDIR_IN means 9983 * "coming IN over air through Target to Host" as with a WiFi Rx operation. 9984 * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air" 9985 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man" 9986 * Target since things that are "PIPEDIR_OUT" are coming IN to the Target 9987 * over the interconnect. 9988 */ 9989 #define PIPEDIR_NONE 0 9990 #define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */ 9991 #define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */ 9992 #define PIPEDIR_INOUT 3 /* bidirectional */ 9993 #define PIPEDIR_INOUT_H2H 4 /* bidirectional, host to host */ 9994 9995 /* CE address/mask */ 9996 #define CE_HOST_IE_ADDRESS 0x00A1803C 9997 #define CE_HOST_IE_2_ADDRESS 0x00A18040 9998 #define CE_HOST_IE_3_ADDRESS CE_HOST_IE_ADDRESS 9999 10000 /* CE IE registers are different for IPQ5018 */ 10001 #define CE_HOST_IPQ5018_IE_ADDRESS 0x0841804C 10002 #define CE_HOST_IPQ5018_IE_2_ADDRESS 0x08418050 10003 #define CE_HOST_IPQ5018_IE_3_ADDRESS CE_HOST_IPQ5018_IE_ADDRESS 10004 10005 #define CE_HOST_IE_3_SHIFT 0xC 10006 10007 #define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask)) 10008 10009 /* 10010 * Establish a mapping between a service/direction and a pipe. 10011 * Configuration information for a Copy Engine pipe and services. 10012 * Passed from Host to Target through QMI message and must be in 10013 * little endian format. 10014 */ 10015 struct service_to_pipe { 10016 uint32_t service_id; 10017 uint32_t pipedir; 10018 uint32_t pipenum; 10019 }; 10020 10021 /* 10022 * Configuration information for a Copy Engine pipe. 10023 * Passed from Host to Target through QMI message during startup (one per CE). 10024 * 10025 * NOTE: Structure is shared between Host software and Target firmware! 10026 */ 10027 struct ce_pipe_config { 10028 uint32_t pipenum; 10029 uint32_t pipedir; 10030 uint32_t nentries; 10031 uint32_t nbytes_max; 10032 uint32_t flags; 10033 uint32_t reserved; 10034 }; 10035 10036 /* 10037 * HTC 10038 */ 10039 10040 #define HTC_HDR_ENDPOINTID GENMASK(7, 0) 10041 #define HTC_HDR_FLAGS GENMASK(15, 8) 10042 #define HTC_HDR_PAYLOADLEN GENMASK(31, 16) 10043 #define HTC_HDR_CONTROLBYTES0 GENMASK(7, 0) 10044 #define HTC_HDR_CONTROLBYTES1 GENMASK(15, 8) 10045 #define HTC_HDR_RESERVED GENMASK(31, 16) 10046 10047 #define HTC_SVC_MSG_SERVICE_ID GENMASK(31, 16) 10048 #define HTC_SVC_MSG_CONNECTIONFLAGS GENMASK(15, 0) 10049 #define HTC_SVC_MSG_SERVICEMETALENGTH GENMASK(23, 16) 10050 #define HTC_READY_MSG_CREDITCOUNT GENMASK(31, 16) 10051 #define HTC_READY_MSG_CREDITSIZE GENMASK(15, 0) 10052 #define HTC_READY_MSG_MAXENDPOINTS GENMASK(23, 16) 10053 10054 #define HTC_READY_EX_MSG_HTCVERSION GENMASK(7, 0) 10055 #define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE GENMASK(15, 8) 10056 10057 #define HTC_SVC_RESP_MSG_SERVICEID GENMASK(31, 16) 10058 #define HTC_SVC_RESP_MSG_STATUS GENMASK(7, 0) 10059 #define HTC_SVC_RESP_MSG_ENDPOINTID GENMASK(15, 8) 10060 #define HTC_SVC_RESP_MSG_MAXMSGSIZE GENMASK(31, 16) 10061 #define HTC_SVC_RESP_MSG_SERVICEMETALENGTH GENMASK(7, 0) 10062 10063 #define HTC_MSG_MESSAGEID GENMASK(15, 0) 10064 #define HTC_SETUP_COMPLETE_EX_MSG_SETUPFLAGS GENMASK(31, 0) 10065 #define HTC_SETUP_COMPLETE_EX_MSG_MAXMSGSPERBUNDLEDRECV GENMASK(7, 0) 10066 #define HTC_SETUP_COMPLETE_EX_MSG_RSVD0 GENMASK(15, 8) 10067 #define HTC_SETUP_COMPLETE_EX_MSG_RSVD1 GENMASK(23, 16) 10068 #define HTC_SETUP_COMPLETE_EX_MSG_RSVD2 GENMASK(31, 24) 10069 10070 enum ath11k_htc_tx_flags { 10071 ATH11K_HTC_FLAG_NEED_CREDIT_UPDATE = 0x01, 10072 ATH11K_HTC_FLAG_SEND_BUNDLE = 0x02 10073 }; 10074 10075 enum ath11k_htc_rx_flags { 10076 ATH11K_HTC_FLAG_TRAILER_PRESENT = 0x02, 10077 ATH11K_HTC_FLAG_BUNDLE_MASK = 0xF0 10078 }; 10079 10080 10081 struct ath11k_htc_hdr { 10082 uint32_t htc_info; 10083 uint32_t ctrl_info; 10084 } __packed __aligned(4); 10085 10086 enum ath11k_htc_msg_id { 10087 ATH11K_HTC_MSG_READY_ID = 1, 10088 ATH11K_HTC_MSG_CONNECT_SERVICE_ID = 2, 10089 ATH11K_HTC_MSG_CONNECT_SERVICE_RESP_ID = 3, 10090 ATH11K_HTC_MSG_SETUP_COMPLETE_ID = 4, 10091 ATH11K_HTC_MSG_SETUP_COMPLETE_EX_ID = 5, 10092 ATH11K_HTC_MSG_SEND_SUSPEND_COMPLETE = 6, 10093 ATH11K_HTC_MSG_NACK_SUSPEND = 7, 10094 ATH11K_HTC_MSG_WAKEUP_FROM_SUSPEND_ID = 8, 10095 }; 10096 10097 enum ath11k_htc_version { 10098 ATH11K_HTC_VERSION_2P0 = 0x00, /* 2.0 */ 10099 ATH11K_HTC_VERSION_2P1 = 0x01, /* 2.1 */ 10100 }; 10101 10102 #define ATH11K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_MASK GENMASK(1, 0) 10103 #define ATH11K_HTC_CONN_FLAGS_RECV_ALLOC GENMASK(15, 8) 10104 10105 enum ath11k_htc_conn_flags { 10106 ATH11K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH = 0x0, 10107 ATH11K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_ONE_HALF = 0x1, 10108 ATH11K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS = 0x2, 10109 ATH11K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_UNITY = 0x3, 10110 ATH11K_HTC_CONN_FLAGS_REDUCE_CREDIT_DRIBBLE = 0x4, 10111 ATH11K_HTC_CONN_FLAGS_DISABLE_CREDIT_FLOW_CTRL = 0x8, 10112 }; 10113 10114 enum ath11k_htc_conn_svc_status { 10115 ATH11K_HTC_CONN_SVC_STATUS_SUCCESS = 0, 10116 ATH11K_HTC_CONN_SVC_STATUS_NOT_FOUND = 1, 10117 ATH11K_HTC_CONN_SVC_STATUS_FAILED = 2, 10118 ATH11K_HTC_CONN_SVC_STATUS_NO_RESOURCES = 3, 10119 ATH11K_HTC_CONN_SVC_STATUS_NO_MORE_EP = 4 10120 }; 10121 10122 struct ath11k_htc_ready { 10123 uint32_t id_credit_count; 10124 uint32_t size_ep; 10125 } __packed; 10126 10127 struct ath11k_htc_ready_extended { 10128 struct ath11k_htc_ready base; 10129 uint32_t ver_bundle; 10130 } __packed; 10131 10132 struct ath11k_htc_conn_svc { 10133 uint32_t msg_svc_id; 10134 uint32_t flags_len; 10135 } __packed; 10136 10137 struct ath11k_htc_conn_svc_resp { 10138 uint32_t msg_svc_id; 10139 uint32_t flags_len; 10140 uint32_t svc_meta_pad; 10141 } __packed; 10142 10143 #define ATH11K_GLOBAL_DISABLE_CREDIT_FLOW BIT(1) 10144 10145 struct ath11k_htc_setup_complete_extended { 10146 uint32_t msg_id; 10147 uint32_t flags; 10148 uint32_t max_msgs_per_bundled_recv; 10149 } __packed; 10150 10151 struct ath11k_htc_msg { 10152 uint32_t msg_svc_id; 10153 uint32_t flags_len; 10154 } __packed __aligned(4); 10155 10156 enum ath11k_htc_record_id { 10157 ATH11K_HTC_RECORD_NULL = 0, 10158 ATH11K_HTC_RECORD_CREDITS = 1 10159 }; 10160 10161 struct ath11k_htc_record_hdr { 10162 uint8_t id; /* @enum ath11k_htc_record_id */ 10163 uint8_t len; 10164 uint8_t pad0; 10165 uint8_t pad1; 10166 } __packed; 10167 10168 struct ath11k_htc_credit_report { 10169 uint8_t eid; /* @enum ath11k_htc_ep_id */ 10170 uint8_t credits; 10171 uint8_t pad0; 10172 uint8_t pad1; 10173 } __packed; 10174 10175 struct ath11k_htc_record { 10176 struct ath11k_htc_record_hdr hdr; 10177 union { 10178 struct ath11k_htc_credit_report credit_report[0]; 10179 uint8_t payload[0]; 10180 }; 10181 } __packed __aligned(4); 10182 10183 /* note: the trailer offset is dynamic depending 10184 * on payload length. this is only a struct layout draft 10185 */ 10186 struct ath11k_htc_frame { 10187 struct ath11k_htc_hdr hdr; 10188 union { 10189 struct ath11k_htc_msg msg; 10190 uint8_t payload[0]; 10191 }; 10192 struct ath11k_htc_record trailer[0]; 10193 } __packed __aligned(4); 10194 10195 enum ath11k_htc_svc_gid { 10196 ATH11K_HTC_SVC_GRP_RSVD = 0, 10197 ATH11K_HTC_SVC_GRP_WMI = 1, 10198 ATH11K_HTC_SVC_GRP_NMI = 2, 10199 ATH11K_HTC_SVC_GRP_HTT = 3, 10200 ATH11K_HTC_SVC_GRP_CFG = 4, 10201 ATH11K_HTC_SVC_GRP_IPA = 5, 10202 ATH11K_HTC_SVC_GRP_PKTLOG = 6, 10203 10204 ATH11K_HTC_SVC_GRP_TEST = 254, 10205 ATH11K_HTC_SVC_GRP_LAST = 255, 10206 }; 10207 10208 #define SVC(group, idx) \ 10209 (int)(((int)(group) << 8) | (int)(idx)) 10210 10211 enum ath11k_htc_svc_id { 10212 /* NOTE: service ID of 0x0000 is reserved and should never be used */ 10213 ATH11K_HTC_SVC_ID_RESERVED = 0x0000, 10214 ATH11K_HTC_SVC_ID_UNUSED = ATH11K_HTC_SVC_ID_RESERVED, 10215 10216 ATH11K_HTC_SVC_ID_RSVD_CTRL = SVC(ATH11K_HTC_SVC_GRP_RSVD, 1), 10217 ATH11K_HTC_SVC_ID_WMI_CONTROL = SVC(ATH11K_HTC_SVC_GRP_WMI, 0), 10218 ATH11K_HTC_SVC_ID_WMI_DATA_BE = SVC(ATH11K_HTC_SVC_GRP_WMI, 1), 10219 ATH11K_HTC_SVC_ID_WMI_DATA_BK = SVC(ATH11K_HTC_SVC_GRP_WMI, 2), 10220 ATH11K_HTC_SVC_ID_WMI_DATA_VI = SVC(ATH11K_HTC_SVC_GRP_WMI, 3), 10221 ATH11K_HTC_SVC_ID_WMI_DATA_VO = SVC(ATH11K_HTC_SVC_GRP_WMI, 4), 10222 ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1 = SVC(ATH11K_HTC_SVC_GRP_WMI, 5), 10223 ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2 = SVC(ATH11K_HTC_SVC_GRP_WMI, 6), 10224 10225 ATH11K_HTC_SVC_ID_NMI_CONTROL = SVC(ATH11K_HTC_SVC_GRP_NMI, 0), 10226 ATH11K_HTC_SVC_ID_NMI_DATA = SVC(ATH11K_HTC_SVC_GRP_NMI, 1), 10227 10228 ATH11K_HTC_SVC_ID_HTT_DATA_MSG = SVC(ATH11K_HTC_SVC_GRP_HTT, 0), 10229 10230 /* raw stream service (i.e. flash, tcmd, calibration apps) */ 10231 ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS = SVC(ATH11K_HTC_SVC_GRP_TEST, 0), 10232 ATH11K_HTC_SVC_ID_IPA_TX = SVC(ATH11K_HTC_SVC_GRP_IPA, 0), 10233 ATH11K_HTC_SVC_ID_PKT_LOG = SVC(ATH11K_HTC_SVC_GRP_PKTLOG, 0), 10234 }; 10235 10236 #undef SVC 10237 10238 enum ath11k_htc_ep_id { 10239 ATH11K_HTC_EP_UNUSED = -1, 10240 ATH11K_HTC_EP_0 = 0, 10241 ATH11K_HTC_EP_1 = 1, 10242 ATH11K_HTC_EP_2, 10243 ATH11K_HTC_EP_3, 10244 ATH11K_HTC_EP_4, 10245 ATH11K_HTC_EP_5, 10246 ATH11K_HTC_EP_6, 10247 ATH11K_HTC_EP_7, 10248 ATH11K_HTC_EP_8, 10249 ATH11K_HTC_EP_COUNT, 10250 }; 10251 10252 /* 10253 * hw.h 10254 */ 10255 10256 /* Target configuration defines */ 10257 10258 /* Num VDEVS per radio */ 10259 #define TARGET_NUM_VDEVS(sc) (sc->hw_params.num_vdevs) 10260 10261 #define TARGET_NUM_PEERS_PDEV(sc) (sc->hw_params.num_peers + TARGET_NUM_VDEVS(sc)) 10262 10263 /* Num of peers for Single Radio mode */ 10264 #define TARGET_NUM_PEERS_SINGLE(sc) (TARGET_NUM_PEERS_PDEV(sc)) 10265 10266 /* Num of peers for DBS */ 10267 #define TARGET_NUM_PEERS_DBS(sc) (2 * TARGET_NUM_PEERS_PDEV(sc)) 10268 10269 /* Num of peers for DBS_SBS */ 10270 #define TARGET_NUM_PEERS_DBS_SBS(sc) (3 * TARGET_NUM_PEERS_PDEV(sc)) 10271 10272 /* Max num of stations (per radio) */ 10273 #define TARGET_NUM_STATIONS(sc) (sc->hw_params.num_peers) 10274 10275 #define TARGET_NUM_PEERS(sc, x) TARGET_NUM_PEERS_##x(sc) 10276 #define TARGET_NUM_PEER_KEYS 2 10277 #define TARGET_NUM_TIDS(sc, x) (2 * TARGET_NUM_PEERS(sc, x) + \ 10278 4 * TARGET_NUM_VDEVS(sc) + 8) 10279 10280 #define TARGET_AST_SKID_LIMIT 16 10281 #define TARGET_NUM_OFFLD_PEERS 4 10282 #define TARGET_NUM_OFFLD_REORDER_BUFFS 4 10283 10284 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4)) 10285 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4)) 10286 #define TARGET_RX_TIMEOUT_LO_PRI 100 10287 #define TARGET_RX_TIMEOUT_HI_PRI 40 10288 10289 #define TARGET_DECAP_MODE_RAW 0 10290 #define TARGET_DECAP_MODE_NATIVE_WIFI 1 10291 #define TARGET_DECAP_MODE_ETH 2 10292 10293 #define TARGET_SCAN_MAX_PENDING_REQS 4 10294 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 10295 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 10296 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 10297 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 10298 #define TARGET_NUM_MCAST_GROUPS 12 10299 #define TARGET_NUM_MCAST_TABLE_ELEMS 64 10300 #define TARGET_MCAST2UCAST_MODE 2 10301 #define TARGET_TX_DBG_LOG_SIZE 1024 10302 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 10303 #define TARGET_VOW_CONFIG 0 10304 #define TARGET_NUM_MSDU_DESC (2500) 10305 #define TARGET_MAX_FRAG_ENTRIES 6 10306 #define TARGET_MAX_BCN_OFFLD 16 10307 #define TARGET_NUM_WDS_ENTRIES 32 10308 #define TARGET_DMA_BURST_SIZE 1 10309 #define TARGET_RX_BATCHMODE 1 10310 #define TARGET_EMA_MAX_PROFILE_PERIOD 8 10311 10312 #define ATH11K_HW_MAX_QUEUES 4 10313 #define ATH11K_QUEUE_LEN 4096 10314 10315 #define ATH11k_HW_RATECODE_CCK_SHORT_PREAM_MASK 0x4 10316 10317 enum ath11k_hw_rate_cck { 10318 ATH11K_HW_RATE_CCK_LP_11M = 0, 10319 ATH11K_HW_RATE_CCK_LP_5_5M, 10320 ATH11K_HW_RATE_CCK_LP_2M, 10321 ATH11K_HW_RATE_CCK_LP_1M, 10322 ATH11K_HW_RATE_CCK_SP_11M, 10323 ATH11K_HW_RATE_CCK_SP_5_5M, 10324 ATH11K_HW_RATE_CCK_SP_2M, 10325 }; 10326 10327 enum ath11k_hw_rate_ofdm { 10328 ATH11K_HW_RATE_OFDM_48M = 0, 10329 ATH11K_HW_RATE_OFDM_24M, 10330 ATH11K_HW_RATE_OFDM_12M, 10331 ATH11K_HW_RATE_OFDM_6M, 10332 ATH11K_HW_RATE_OFDM_54M, 10333 ATH11K_HW_RATE_OFDM_36M, 10334 ATH11K_HW_RATE_OFDM_18M, 10335 ATH11K_HW_RATE_OFDM_9M, 10336 }; 10337 10338 enum ath11k_bus { 10339 ATH11K_BUS_AHB, 10340 ATH11K_BUS_PCI, 10341 }; 10342 10343 #define ATH11K_EXT_IRQ_GRP_NUM_MAX 11 10344 10345 /* 10346 * rx_desc.h 10347 */ 10348 10349 enum rx_desc_rxpcu_filter { 10350 RX_DESC_RXPCU_FILTER_PASS, 10351 RX_DESC_RXPCU_FILTER_MONITOR_CLIENT, 10352 RX_DESC_RXPCU_FILTER_MONITOR_OTHER, 10353 }; 10354 10355 /* rxpcu_filter_pass 10356 * This MPDU passed the normal frame filter programming of rxpcu. 10357 * 10358 * rxpcu_filter_monitor_client 10359 * This MPDU did not pass the regular frame filter and would 10360 * have been dropped, were it not for the frame fitting into the 10361 * 'monitor_client' category. 10362 * 10363 * rxpcu_filter_monitor_other 10364 * This MPDU did not pass the regular frame filter and also did 10365 * not pass the rxpcu_monitor_client filter. It would have been 10366 * dropped accept that it did pass the 'monitor_other' category. 10367 */ 10368 10369 #define RX_DESC_INFO0_RXPCU_MPDU_FITLER GENMASK(1, 0) 10370 #define RX_DESC_INFO0_SW_FRAME_GRP_ID GENMASK(8, 2) 10371 10372 enum rx_desc_sw_frame_grp_id { 10373 RX_DESC_SW_FRAME_GRP_ID_NDP_FRAME, 10374 RX_DESC_SW_FRAME_GRP_ID_MCAST_DATA, 10375 RX_DESC_SW_FRAME_GRP_ID_UCAST_DATA, 10376 RX_DESC_SW_FRAME_GRP_ID_NULL_DATA, 10377 RX_DESC_SW_FRAME_GRP_ID_MGMT_0000, 10378 RX_DESC_SW_FRAME_GRP_ID_MGMT_0001, 10379 RX_DESC_SW_FRAME_GRP_ID_MGMT_0010, 10380 RX_DESC_SW_FRAME_GRP_ID_MGMT_0011, 10381 RX_DESC_SW_FRAME_GRP_ID_MGMT_0100, 10382 RX_DESC_SW_FRAME_GRP_ID_MGMT_0101, 10383 RX_DESC_SW_FRAME_GRP_ID_MGMT_0110, 10384 RX_DESC_SW_FRAME_GRP_ID_MGMT_0111, 10385 RX_DESC_SW_FRAME_GRP_ID_MGMT_1000, 10386 RX_DESC_SW_FRAME_GRP_ID_MGMT_1001, 10387 RX_DESC_SW_FRAME_GRP_ID_MGMT_1010, 10388 RX_DESC_SW_FRAME_GRP_ID_MGMT_1011, 10389 RX_DESC_SW_FRAME_GRP_ID_MGMT_1100, 10390 RX_DESC_SW_FRAME_GRP_ID_MGMT_1101, 10391 RX_DESC_SW_FRAME_GRP_ID_MGMT_1110, 10392 RX_DESC_SW_FRAME_GRP_ID_MGMT_1111, 10393 RX_DESC_SW_FRAME_GRP_ID_CTRL_0000, 10394 RX_DESC_SW_FRAME_GRP_ID_CTRL_0001, 10395 RX_DESC_SW_FRAME_GRP_ID_CTRL_0010, 10396 RX_DESC_SW_FRAME_GRP_ID_CTRL_0011, 10397 RX_DESC_SW_FRAME_GRP_ID_CTRL_0100, 10398 RX_DESC_SW_FRAME_GRP_ID_CTRL_0101, 10399 RX_DESC_SW_FRAME_GRP_ID_CTRL_0110, 10400 RX_DESC_SW_FRAME_GRP_ID_CTRL_0111, 10401 RX_DESC_SW_FRAME_GRP_ID_CTRL_1000, 10402 RX_DESC_SW_FRAME_GRP_ID_CTRL_1001, 10403 RX_DESC_SW_FRAME_GRP_ID_CTRL_1010, 10404 RX_DESC_SW_FRAME_GRP_ID_CTRL_1011, 10405 RX_DESC_SW_FRAME_GRP_ID_CTRL_1100, 10406 RX_DESC_SW_FRAME_GRP_ID_CTRL_1101, 10407 RX_DESC_SW_FRAME_GRP_ID_CTRL_1110, 10408 RX_DESC_SW_FRAME_GRP_ID_CTRL_1111, 10409 RX_DESC_SW_FRAME_GRP_ID_UNSUPPORTED, 10410 RX_DESC_SW_FRAME_GRP_ID_PHY_ERR, 10411 }; 10412 10413 enum rx_desc_decap_type { 10414 RX_DESC_DECAP_TYPE_RAW, 10415 RX_DESC_DECAP_TYPE_NATIVE_WIFI, 10416 RX_DESC_DECAP_TYPE_ETHERNET2_DIX, 10417 RX_DESC_DECAP_TYPE_8023, 10418 }; 10419 10420 enum rx_desc_decrypt_status_code { 10421 RX_DESC_DECRYPT_STATUS_CODE_OK, 10422 RX_DESC_DECRYPT_STATUS_CODE_UNPROTECTED_FRAME, 10423 RX_DESC_DECRYPT_STATUS_CODE_DATA_ERR, 10424 RX_DESC_DECRYPT_STATUS_CODE_KEY_INVALID, 10425 RX_DESC_DECRYPT_STATUS_CODE_PEER_ENTRY_INVALID, 10426 RX_DESC_DECRYPT_STATUS_CODE_OTHER, 10427 }; 10428 10429 #define RX_ATTENTION_INFO1_FIRST_MPDU BIT(0) 10430 #define RX_ATTENTION_INFO1_RSVD_1A BIT(1) 10431 #define RX_ATTENTION_INFO1_MCAST_BCAST BIT(2) 10432 #define RX_ATTENTION_INFO1_AST_IDX_NOT_FOUND BIT(3) 10433 #define RX_ATTENTION_INFO1_AST_IDX_TIMEDOUT BIT(4) 10434 #define RX_ATTENTION_INFO1_POWER_MGMT BIT(5) 10435 #define RX_ATTENTION_INFO1_NON_QOS BIT(6) 10436 #define RX_ATTENTION_INFO1_NULL_DATA BIT(7) 10437 #define RX_ATTENTION_INFO1_MGMT_TYPE BIT(8) 10438 #define RX_ATTENTION_INFO1_CTRL_TYPE BIT(9) 10439 #define RX_ATTENTION_INFO1_MORE_DATA BIT(10) 10440 #define RX_ATTENTION_INFO1_EOSP BIT(11) 10441 #define RX_ATTENTION_INFO1_A_MSDU_ERROR BIT(12) 10442 #define RX_ATTENTION_INFO1_FRAGMENT BIT(13) 10443 #define RX_ATTENTION_INFO1_ORDER BIT(14) 10444 #define RX_ATTENTION_INFO1_CCE_MATCH BIT(15) 10445 #define RX_ATTENTION_INFO1_OVERFLOW_ERR BIT(16) 10446 #define RX_ATTENTION_INFO1_MSDU_LEN_ERR BIT(17) 10447 #define RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL BIT(18) 10448 #define RX_ATTENTION_INFO1_IP_CKSUM_FAIL BIT(19) 10449 #define RX_ATTENTION_INFO1_SA_IDX_INVALID BIT(20) 10450 #define RX_ATTENTION_INFO1_DA_IDX_INVALID BIT(21) 10451 #define RX_ATTENTION_INFO1_RSVD_1B BIT(22) 10452 #define RX_ATTENTION_INFO1_RX_IN_TX_DECRYPT_BYP BIT(23) 10453 #define RX_ATTENTION_INFO1_ENCRYPT_REQUIRED BIT(24) 10454 #define RX_ATTENTION_INFO1_DIRECTED BIT(25) 10455 #define RX_ATTENTION_INFO1_BUFFER_FRAGMENT BIT(26) 10456 #define RX_ATTENTION_INFO1_MPDU_LEN_ERR BIT(27) 10457 #define RX_ATTENTION_INFO1_TKIP_MIC_ERR BIT(28) 10458 #define RX_ATTENTION_INFO1_DECRYPT_ERR BIT(29) 10459 #define RX_ATTENTION_INFO1_UNDECRYPT_FRAME_ERR BIT(30) 10460 #define RX_ATTENTION_INFO1_FCS_ERR BIT(31) 10461 10462 #define RX_ATTENTION_INFO2_FLOW_IDX_TIMEOUT BIT(0) 10463 #define RX_ATTENTION_INFO2_FLOW_IDX_INVALID BIT(1) 10464 #define RX_ATTENTION_INFO2_WIFI_PARSER_ERR BIT(2) 10465 #define RX_ATTENTION_INFO2_AMSDU_PARSER_ERR BIT(3) 10466 #define RX_ATTENTION_INFO2_SA_IDX_TIMEOUT BIT(4) 10467 #define RX_ATTENTION_INFO2_DA_IDX_TIMEOUT BIT(5) 10468 #define RX_ATTENTION_INFO2_MSDU_LIMIT_ERR BIT(6) 10469 #define RX_ATTENTION_INFO2_DA_IS_VALID BIT(7) 10470 #define RX_ATTENTION_INFO2_DA_IS_MCBC BIT(8) 10471 #define RX_ATTENTION_INFO2_SA_IS_VALID BIT(9) 10472 #define RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE GENMASK(12, 10) 10473 #define RX_ATTENTION_INFO2_RX_BITMAP_NOT_UPDED BIT(13) 10474 #define RX_ATTENTION_INFO2_MSDU_DONE BIT(31) 10475 10476 struct rx_attention { 10477 uint16_t info0; 10478 uint16_t phy_ppdu_id; 10479 uint32_t info1; 10480 uint32_t info2; 10481 } __packed; 10482 10483 /* rx_attention 10484 * 10485 * rxpcu_mpdu_filter_in_category 10486 * Field indicates what the reason was that this mpdu frame 10487 * was allowed to come into the receive path by rxpcu. Values 10488 * are defined in enum %RX_DESC_RXPCU_FILTER_*. 10489 * 10490 * sw_frame_group_id 10491 * SW processes frames based on certain classifications. Values 10492 * are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*. 10493 * 10494 * phy_ppdu_id 10495 * A ppdu counter value that PHY increments for every PPDU 10496 * received. The counter value wraps around. 10497 * 10498 * first_mpdu 10499 * Indicates the first MSDU of the PPDU. If both first_mpdu 10500 * and last_mpdu are set in the MSDU then this is a not an 10501 * A-MPDU frame but a stand alone MPDU. Interior MPDU in an 10502 * A-MPDU shall have both first_mpdu and last_mpdu bits set to 10503 * 0. The PPDU start status will only be valid when this bit 10504 * is set. 10505 * 10506 * mcast_bcast 10507 * Multicast / broadcast indicator. Only set when the MAC 10508 * address 1 bit 0 is set indicating mcast/bcast and the BSSID 10509 * matches one of the 4 BSSID registers. Only set when 10510 * first_msdu is set. 10511 * 10512 * ast_index_not_found 10513 * Only valid when first_msdu is set. Indicates no AST matching 10514 * entries within the max search count. 10515 * 10516 * ast_index_timeout 10517 * Only valid when first_msdu is set. Indicates an unsuccessful 10518 * search in the address search table due to timeout. 10519 * 10520 * power_mgmt 10521 * Power management bit set in the 802.11 header. Only set 10522 * when first_msdu is set. 10523 * 10524 * non_qos 10525 * Set if packet is not a non-QoS data frame. Only set when 10526 * first_msdu is set. 10527 * 10528 * null_data 10529 * Set if frame type indicates either null data or QoS null 10530 * data format. Only set when first_msdu is set. 10531 * 10532 * mgmt_type 10533 * Set if packet is a management packet. Only set when 10534 * first_msdu is set. 10535 * 10536 * ctrl_type 10537 * Set if packet is a control packet. Only set when first_msdu 10538 * is set. 10539 * 10540 * more_data 10541 * Set if more bit in frame control is set. Only set when 10542 * first_msdu is set. 10543 * 10544 * eosp 10545 * Set if the EOSP (end of service period) bit in the QoS 10546 * control field is set. Only set when first_msdu is set. 10547 * 10548 * a_msdu_error 10549 * Set if number of MSDUs in A-MSDU is above a threshold or if the 10550 * size of the MSDU is invalid. This receive buffer will contain 10551 * all of the remainder of MSDUs in this MPDU w/o decapsulation. 10552 * 10553 * fragment 10554 * Indicates that this is an 802.11 fragment frame. This is 10555 * set when either the more_frag bit is set in the frame 10556 * control or the fragment number is not zero. Only set when 10557 * first_msdu is set. 10558 * 10559 * order 10560 * Set if the order bit in the frame control is set. Only set 10561 * when first_msdu is set. 10562 * 10563 * cce_match 10564 * Indicates that this status has a corresponding MSDU that 10565 * requires FW processing. The OLE will have classification 10566 * ring mask registers which will indicate the ring(s) for 10567 * packets and descriptors which need FW attention. 10568 * 10569 * overflow_err 10570 * PCU Receive FIFO does not have enough space to store the 10571 * full receive packet. Enough space is reserved in the 10572 * receive FIFO for the status is written. This MPDU remaining 10573 * packets in the PPDU will be filtered and no Ack response 10574 * will be transmitted. 10575 * 10576 * msdu_length_err 10577 * Indicates that the MSDU length from the 802.3 encapsulated 10578 * length field extends beyond the MPDU boundary. 10579 * 10580 * tcp_udp_chksum_fail 10581 * Indicates that the computed checksum (tcp_udp_chksum) did 10582 * not match the checksum in the TCP/UDP header. 10583 * 10584 * ip_chksum_fail 10585 * Indicates that the computed checksum did not match the 10586 * checksum in the IP header. 10587 * 10588 * sa_idx_invalid 10589 * Indicates no matching entry was found in the address search 10590 * table for the source MAC address. 10591 * 10592 * da_idx_invalid 10593 * Indicates no matching entry was found in the address search 10594 * table for the destination MAC address. 10595 * 10596 * rx_in_tx_decrypt_byp 10597 * Indicates that RX packet is not decrypted as Crypto is busy 10598 * with TX packet processing. 10599 * 10600 * encrypt_required 10601 * Indicates that this data type frame is not encrypted even if 10602 * the policy for this MPDU requires encryption as indicated in 10603 * the peer table key type. 10604 * 10605 * directed 10606 * MPDU is a directed packet which means that the RA matched 10607 * our STA addresses. In proxySTA it means that the TA matched 10608 * an entry in our address search table with the corresponding 10609 * 'no_ack' bit is the address search entry cleared. 10610 * 10611 * buffer_fragment 10612 * Indicates that at least one of the rx buffers has been 10613 * fragmented. If set the FW should look at the rx_frag_info 10614 * descriptor described below. 10615 * 10616 * mpdu_length_err 10617 * Indicates that the MPDU was pre-maturely terminated 10618 * resulting in a truncated MPDU. Don't trust the MPDU length 10619 * field. 10620 * 10621 * tkip_mic_err 10622 * Indicates that the MPDU Michael integrity check failed 10623 * 10624 * decrypt_err 10625 * Indicates that the MPDU decrypt integrity check failed 10626 * 10627 * fcs_err 10628 * Indicates that the MPDU FCS check failed 10629 * 10630 * flow_idx_timeout 10631 * Indicates an unsuccessful flow search due to the expiring of 10632 * the search timer. 10633 * 10634 * flow_idx_invalid 10635 * flow id is not valid. 10636 * 10637 * amsdu_parser_error 10638 * A-MSDU could not be properly de-agregated. 10639 * 10640 * sa_idx_timeout 10641 * Indicates an unsuccessful search for the source MAC address 10642 * due to the expiring of the search timer. 10643 * 10644 * da_idx_timeout 10645 * Indicates an unsuccessful search for the destination MAC 10646 * address due to the expiring of the search timer. 10647 * 10648 * msdu_limit_error 10649 * Indicates that the MSDU threshold was exceeded and thus 10650 * all the rest of the MSDUs will not be scattered and will not 10651 * be decasulated but will be DMA'ed in RAW format as a single 10652 * MSDU buffer. 10653 * 10654 * da_is_valid 10655 * Indicates that OLE found a valid DA entry. 10656 * 10657 * da_is_mcbc 10658 * Field Only valid if da_is_valid is set. Indicates the DA address 10659 * was a Multicast or Broadcast address. 10660 * 10661 * sa_is_valid 10662 * Indicates that OLE found a valid SA entry. 10663 * 10664 * decrypt_status_code 10665 * Field provides insight into the decryption performed. Values are 10666 * defined in enum %RX_DESC_DECRYPT_STATUS_CODE*. 10667 * 10668 * rx_bitmap_not_updated 10669 * Frame is received, but RXPCU could not update the receive bitmap 10670 * due to (temporary) fifo constraints. 10671 * 10672 * msdu_done 10673 * If set indicates that the RX packet data, RX header data, RX 10674 * PPDU start descriptor, RX MPDU start/end descriptor, RX MSDU 10675 * start/end descriptors and RX Attention descriptor are all 10676 * valid. This bit must be in the last octet of the 10677 * descriptor. 10678 */ 10679 10680 #define RX_MPDU_START_INFO0_NDP_FRAME BIT(9) 10681 #define RX_MPDU_START_INFO0_PHY_ERR BIT(10) 10682 #define RX_MPDU_START_INFO0_PHY_ERR_MPDU_HDR BIT(11) 10683 #define RX_MPDU_START_INFO0_PROTO_VER_ERR BIT(12) 10684 #define RX_MPDU_START_INFO0_AST_LOOKUP_VALID BIT(13) 10685 10686 #define RX_MPDU_START_INFO1_MPDU_FCTRL_VALID BIT(0) 10687 #define RX_MPDU_START_INFO1_MPDU_DUR_VALID BIT(1) 10688 #define RX_MPDU_START_INFO1_MAC_ADDR1_VALID BIT(2) 10689 #define RX_MPDU_START_INFO1_MAC_ADDR2_VALID BIT(3) 10690 #define RX_MPDU_START_INFO1_MAC_ADDR3_VALID BIT(4) 10691 #define RX_MPDU_START_INFO1_MAC_ADDR4_VALID BIT(5) 10692 #define RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID BIT(6) 10693 #define RX_MPDU_START_INFO1_MPDU_QOS_CTRL_VALID BIT(7) 10694 #define RX_MPDU_START_INFO1_MPDU_HT_CTRL_VALID BIT(8) 10695 #define RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID BIT(9) 10696 #define RX_MPDU_START_INFO1_MPDU_FRAG_NUMBER GENMASK(13, 10) 10697 #define RX_MPDU_START_INFO1_MORE_FRAG_FLAG BIT(14) 10698 #define RX_MPDU_START_INFO1_FROM_DS BIT(16) 10699 #define RX_MPDU_START_INFO1_TO_DS BIT(17) 10700 #define RX_MPDU_START_INFO1_ENCRYPTED BIT(18) 10701 #define RX_MPDU_START_INFO1_MPDU_RETRY BIT(19) 10702 #define RX_MPDU_START_INFO1_MPDU_SEQ_NUM GENMASK(31, 20) 10703 10704 #define RX_MPDU_START_INFO2_EPD_EN BIT(0) 10705 #define RX_MPDU_START_INFO2_ALL_FRAME_ENCPD BIT(1) 10706 #define RX_MPDU_START_INFO2_ENC_TYPE GENMASK(5, 2) 10707 #define RX_MPDU_START_INFO2_VAR_WEP_KEY_WIDTH GENMASK(7, 6) 10708 #define RX_MPDU_START_INFO2_MESH_STA BIT(8) 10709 #define RX_MPDU_START_INFO2_BSSID_HIT BIT(9) 10710 #define RX_MPDU_START_INFO2_BSSID_NUM GENMASK(13, 10) 10711 #define RX_MPDU_START_INFO2_TID GENMASK(17, 14) 10712 #define RX_MPDU_START_INFO2_TID_WCN6855 GENMASK(18, 15) 10713 10714 #define RX_MPDU_START_INFO3_REO_DEST_IND GENMASK(4, 0) 10715 #define RX_MPDU_START_INFO3_FLOW_ID_TOEPLITZ BIT(7) 10716 #define RX_MPDU_START_INFO3_PKT_SEL_FP_UCAST_DATA BIT(8) 10717 #define RX_MPDU_START_INFO3_PKT_SEL_FP_MCAST_DATA BIT(9) 10718 #define RX_MPDU_START_INFO3_PKT_SEL_FP_CTRL_BAR BIT(10) 10719 #define RX_MPDU_START_INFO3_RXDMA0_SRC_RING_SEL GENMASK(12, 11) 10720 #define RX_MPDU_START_INFO3_RXDMA0_DST_RING_SEL GENMASK(14, 13) 10721 10722 #define RX_MPDU_START_INFO4_REO_QUEUE_DESC_HI GENMASK(7, 0) 10723 #define RX_MPDU_START_INFO4_RECV_QUEUE_NUM GENMASK(23, 8) 10724 #define RX_MPDU_START_INFO4_PRE_DELIM_ERR_WARN BIT(24) 10725 #define RX_MPDU_START_INFO4_FIRST_DELIM_ERR BIT(25) 10726 10727 #define RX_MPDU_START_INFO5_KEY_ID GENMASK(7, 0) 10728 #define RX_MPDU_START_INFO5_NEW_PEER_ENTRY BIT(8) 10729 #define RX_MPDU_START_INFO5_DECRYPT_NEEDED BIT(9) 10730 #define RX_MPDU_START_INFO5_DECAP_TYPE GENMASK(11, 10) 10731 #define RX_MPDU_START_INFO5_VLAN_TAG_C_PADDING BIT(12) 10732 #define RX_MPDU_START_INFO5_VLAN_TAG_S_PADDING BIT(13) 10733 #define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_C BIT(14) 10734 #define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_S BIT(15) 10735 #define RX_MPDU_START_INFO5_PRE_DELIM_COUNT GENMASK(27, 16) 10736 #define RX_MPDU_START_INFO5_AMPDU_FLAG BIT(28) 10737 #define RX_MPDU_START_INFO5_BAR_FRAME BIT(29) 10738 10739 #define RX_MPDU_START_INFO6_MPDU_LEN GENMASK(13, 0) 10740 #define RX_MPDU_START_INFO6_FIRST_MPDU BIT(14) 10741 #define RX_MPDU_START_INFO6_MCAST_BCAST BIT(15) 10742 #define RX_MPDU_START_INFO6_AST_IDX_NOT_FOUND BIT(16) 10743 #define RX_MPDU_START_INFO6_AST_IDX_TIMEOUT BIT(17) 10744 #define RX_MPDU_START_INFO6_POWER_MGMT BIT(18) 10745 #define RX_MPDU_START_INFO6_NON_QOS BIT(19) 10746 #define RX_MPDU_START_INFO6_NULL_DATA BIT(20) 10747 #define RX_MPDU_START_INFO6_MGMT_TYPE BIT(21) 10748 #define RX_MPDU_START_INFO6_CTRL_TYPE BIT(22) 10749 #define RX_MPDU_START_INFO6_MORE_DATA BIT(23) 10750 #define RX_MPDU_START_INFO6_EOSP BIT(24) 10751 #define RX_MPDU_START_INFO6_FRAGMENT BIT(25) 10752 #define RX_MPDU_START_INFO6_ORDER BIT(26) 10753 #define RX_MPDU_START_INFO6_UAPSD_TRIGGER BIT(27) 10754 #define RX_MPDU_START_INFO6_ENCRYPT_REQUIRED BIT(28) 10755 #define RX_MPDU_START_INFO6_DIRECTED BIT(29) 10756 10757 #define RX_MPDU_START_RAW_MPDU BIT(0) 10758 10759 struct rx_mpdu_start_ipq8074 { 10760 uint16_t info0; 10761 uint16_t phy_ppdu_id; 10762 uint16_t ast_index; 10763 uint16_t sw_peer_id; 10764 uint32_t info1; 10765 uint32_t info2; 10766 uint32_t pn[4]; 10767 uint32_t peer_meta_data; 10768 uint32_t info3; 10769 uint32_t reo_queue_desc_lo; 10770 uint32_t info4; 10771 uint32_t info5; 10772 uint32_t info6; 10773 uint16_t frame_ctrl; 10774 uint16_t duration; 10775 uint8_t addr1[IEEE80211_ADDR_LEN]; 10776 uint8_t addr2[IEEE80211_ADDR_LEN]; 10777 uint8_t addr3[IEEE80211_ADDR_LEN]; 10778 uint16_t seq_ctrl; 10779 uint8_t addr4[IEEE80211_ADDR_LEN]; 10780 uint16_t qos_ctrl; 10781 uint32_t ht_ctrl; 10782 uint32_t raw; 10783 } __packed; 10784 10785 #define RX_MPDU_START_INFO7_REO_DEST_IND GENMASK(4, 0) 10786 #define RX_MPDU_START_INFO7_LMAC_PEER_ID_MSB GENMASK(6, 5) 10787 #define RX_MPDU_START_INFO7_FLOW_ID_TOEPLITZ BIT(7) 10788 #define RX_MPDU_START_INFO7_PKT_SEL_FP_UCAST_DATA BIT(8) 10789 #define RX_MPDU_START_INFO7_PKT_SEL_FP_MCAST_DATA BIT(9) 10790 #define RX_MPDU_START_INFO7_PKT_SEL_FP_CTRL_BAR BIT(10) 10791 #define RX_MPDU_START_INFO7_RXDMA0_SRC_RING_SEL GENMASK(12, 11) 10792 #define RX_MPDU_START_INFO7_RXDMA0_DST_RING_SEL GENMASK(14, 13) 10793 10794 #define RX_MPDU_START_INFO8_REO_QUEUE_DESC_HI GENMASK(7, 0) 10795 #define RX_MPDU_START_INFO8_RECV_QUEUE_NUM GENMASK(23, 8) 10796 #define RX_MPDU_START_INFO8_PRE_DELIM_ERR_WARN BIT(24) 10797 #define RX_MPDU_START_INFO8_FIRST_DELIM_ERR BIT(25) 10798 10799 #define RX_MPDU_START_INFO9_EPD_EN BIT(0) 10800 #define RX_MPDU_START_INFO9_ALL_FRAME_ENCPD BIT(1) 10801 #define RX_MPDU_START_INFO9_ENC_TYPE GENMASK(5, 2) 10802 #define RX_MPDU_START_INFO9_VAR_WEP_KEY_WIDTH GENMASK(7, 6) 10803 #define RX_MPDU_START_INFO9_MESH_STA GENMASK(9, 8) 10804 #define RX_MPDU_START_INFO9_BSSID_HIT BIT(10) 10805 #define RX_MPDU_START_INFO9_BSSID_NUM GENMASK(14, 11) 10806 #define RX_MPDU_START_INFO9_TID GENMASK(18, 15) 10807 10808 #define RX_MPDU_START_INFO10_RXPCU_MPDU_FLTR GENMASK(1, 0) 10809 #define RX_MPDU_START_INFO10_SW_FRAME_GRP_ID GENMASK(8, 2) 10810 #define RX_MPDU_START_INFO10_NDP_FRAME BIT(9) 10811 #define RX_MPDU_START_INFO10_PHY_ERR BIT(10) 10812 #define RX_MPDU_START_INFO10_PHY_ERR_MPDU_HDR BIT(11) 10813 #define RX_MPDU_START_INFO10_PROTO_VER_ERR BIT(12) 10814 #define RX_MPDU_START_INFO10_AST_LOOKUP_VALID BIT(13) 10815 10816 #define RX_MPDU_START_INFO11_MPDU_FCTRL_VALID BIT(0) 10817 #define RX_MPDU_START_INFO11_MPDU_DUR_VALID BIT(1) 10818 #define RX_MPDU_START_INFO11_MAC_ADDR1_VALID BIT(2) 10819 #define RX_MPDU_START_INFO11_MAC_ADDR2_VALID BIT(3) 10820 #define RX_MPDU_START_INFO11_MAC_ADDR3_VALID BIT(4) 10821 #define RX_MPDU_START_INFO11_MAC_ADDR4_VALID BIT(5) 10822 #define RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID BIT(6) 10823 #define RX_MPDU_START_INFO11_MPDU_QOS_CTRL_VALID BIT(7) 10824 #define RX_MPDU_START_INFO11_MPDU_HT_CTRL_VALID BIT(8) 10825 #define RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID BIT(9) 10826 #define RX_MPDU_START_INFO11_MPDU_FRAG_NUMBER GENMASK(13, 10) 10827 #define RX_MPDU_START_INFO11_MORE_FRAG_FLAG BIT(14) 10828 #define RX_MPDU_START_INFO11_FROM_DS BIT(16) 10829 #define RX_MPDU_START_INFO11_TO_DS BIT(17) 10830 #define RX_MPDU_START_INFO11_ENCRYPTED BIT(18) 10831 #define RX_MPDU_START_INFO11_MPDU_RETRY BIT(19) 10832 #define RX_MPDU_START_INFO11_MPDU_SEQ_NUM GENMASK(31, 20) 10833 10834 #define RX_MPDU_START_INFO12_KEY_ID GENMASK(7, 0) 10835 #define RX_MPDU_START_INFO12_NEW_PEER_ENTRY BIT(8) 10836 #define RX_MPDU_START_INFO12_DECRYPT_NEEDED BIT(9) 10837 #define RX_MPDU_START_INFO12_DECAP_TYPE GENMASK(11, 10) 10838 #define RX_MPDU_START_INFO12_VLAN_TAG_C_PADDING BIT(12) 10839 #define RX_MPDU_START_INFO12_VLAN_TAG_S_PADDING BIT(13) 10840 #define RX_MPDU_START_INFO12_STRIP_VLAN_TAG_C BIT(14) 10841 #define RX_MPDU_START_INFO12_STRIP_VLAN_TAG_S BIT(15) 10842 #define RX_MPDU_START_INFO12_PRE_DELIM_COUNT GENMASK(27, 16) 10843 #define RX_MPDU_START_INFO12_AMPDU_FLAG BIT(28) 10844 #define RX_MPDU_START_INFO12_BAR_FRAME BIT(29) 10845 #define RX_MPDU_START_INFO12_RAW_MPDU BIT(30) 10846 10847 #define RX_MPDU_START_INFO13_MPDU_LEN GENMASK(13, 0) 10848 #define RX_MPDU_START_INFO13_FIRST_MPDU BIT(14) 10849 #define RX_MPDU_START_INFO13_MCAST_BCAST BIT(15) 10850 #define RX_MPDU_START_INFO13_AST_IDX_NOT_FOUND BIT(16) 10851 #define RX_MPDU_START_INFO13_AST_IDX_TIMEOUT BIT(17) 10852 #define RX_MPDU_START_INFO13_POWER_MGMT BIT(18) 10853 #define RX_MPDU_START_INFO13_NON_QOS BIT(19) 10854 #define RX_MPDU_START_INFO13_NULL_DATA BIT(20) 10855 #define RX_MPDU_START_INFO13_MGMT_TYPE BIT(21) 10856 #define RX_MPDU_START_INFO13_CTRL_TYPE BIT(22) 10857 #define RX_MPDU_START_INFO13_MORE_DATA BIT(23) 10858 #define RX_MPDU_START_INFO13_EOSP BIT(24) 10859 #define RX_MPDU_START_INFO13_FRAGMENT BIT(25) 10860 #define RX_MPDU_START_INFO13_ORDER BIT(26) 10861 #define RX_MPDU_START_INFO13_UAPSD_TRIGGER BIT(27) 10862 #define RX_MPDU_START_INFO13_ENCRYPT_REQUIRED BIT(28) 10863 #define RX_MPDU_START_INFO13_DIRECTED BIT(29) 10864 #define RX_MPDU_START_INFO13_AMSDU_PRESENT BIT(30) 10865 10866 struct rx_mpdu_start_qcn9074 { 10867 uint32_t info7; 10868 uint32_t reo_queue_desc_lo; 10869 uint32_t info8; 10870 uint32_t pn[4]; 10871 uint32_t info9; 10872 uint32_t peer_meta_data; 10873 uint16_t info10; 10874 uint16_t phy_ppdu_id; 10875 uint16_t ast_index; 10876 uint16_t sw_peer_id; 10877 uint32_t info11; 10878 uint32_t info12; 10879 uint32_t info13; 10880 uint16_t frame_ctrl; 10881 uint16_t duration; 10882 uint8_t addr1[IEEE80211_ADDR_LEN]; 10883 uint8_t addr2[IEEE80211_ADDR_LEN]; 10884 uint8_t addr3[IEEE80211_ADDR_LEN]; 10885 uint16_t seq_ctrl; 10886 uint8_t addr4[IEEE80211_ADDR_LEN]; 10887 uint16_t qos_ctrl; 10888 uint32_t ht_ctrl; 10889 } __packed; 10890 10891 struct rx_mpdu_start_wcn6855 { 10892 uint32_t info3; 10893 uint32_t reo_queue_desc_lo; 10894 uint32_t info4; 10895 uint32_t pn[4]; 10896 uint32_t info2; 10897 uint32_t peer_meta_data; 10898 uint16_t info0; 10899 uint16_t phy_ppdu_id; 10900 uint16_t ast_index; 10901 uint16_t sw_peer_id; 10902 uint32_t info1; 10903 uint32_t info5; 10904 uint32_t info6; 10905 uint16_t frame_ctrl; 10906 uint16_t duration; 10907 uint8_t addr1[IEEE80211_ADDR_LEN]; 10908 uint8_t addr2[IEEE80211_ADDR_LEN]; 10909 uint8_t addr3[IEEE80211_ADDR_LEN]; 10910 uint16_t seq_ctrl; 10911 uint8_t addr4[IEEE80211_ADDR_LEN]; 10912 uint16_t qos_ctrl; 10913 uint32_t ht_ctrl; 10914 } __packed; 10915 10916 /* rx_mpdu_start 10917 * 10918 * rxpcu_mpdu_filter_in_category 10919 * Field indicates what the reason was that this mpdu frame 10920 * was allowed to come into the receive path by rxpcu. Values 10921 * are defined in enum %RX_DESC_RXPCU_FILTER_*. 10922 * Note: for ndp frame, if it was expected because the preceding 10923 * NDPA was filter_pass, the setting rxpcu_filter_pass will be 10924 * used. This setting will also be used for every ndp frame in 10925 * case Promiscuous mode is enabled. 10926 * 10927 * sw_frame_group_id 10928 * SW processes frames based on certain classifications. Values 10929 * are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*. 10930 * 10931 * ndp_frame 10932 * Indicates that the received frame was an NDP frame. 10933 * 10934 * phy_err 10935 * Indicates that PHY error was received before MAC received data. 10936 * 10937 * phy_err_during_mpdu_header 10938 * PHY error was received before MAC received the complete MPDU 10939 * header which was needed for proper decoding. 10940 * 10941 * protocol_version_err 10942 * RXPCU detected a version error in the frame control field. 10943 * 10944 * ast_based_lookup_valid 10945 * AST based lookup for this frame has found a valid result. 10946 * 10947 * phy_ppdu_id 10948 * A ppdu counter value that PHY increments for every PPDU 10949 * received. The counter value wraps around. 10950 * 10951 * ast_index 10952 * This field indicates the index of the AST entry corresponding 10953 * to this MPDU. It is provided by the GSE module instantiated in 10954 * RXPCU. A value of 0xFFFF indicates an invalid AST index. 10955 * 10956 * sw_peer_id 10957 * This field indicates a unique peer identifier. It is set equal 10958 * to field 'sw_peer_id' from the AST entry. 10959 * 10960 * mpdu_frame_control_valid, mpdu_duration_valid, mpdu_qos_control_valid, 10961 * mpdu_ht_control_valid, frame_encryption_info_valid 10962 * Indicates that each fields have valid entries. 10963 * 10964 * mac_addr_adx_valid 10965 * Corresponding mac_addr_adx_{lo/hi} has valid entries. 10966 * 10967 * from_ds, to_ds 10968 * Valid only when mpdu_frame_control_valid is set. Indicates that 10969 * frame is received from DS and sent to DS. 10970 * 10971 * encrypted 10972 * Protected bit from the frame control. 10973 * 10974 * mpdu_retry 10975 * Retry bit from frame control. Only valid when first_msdu is set. 10976 * 10977 * mpdu_sequence_number 10978 * The sequence number from the 802.11 header. 10979 * 10980 * epd_en 10981 * If set, use EPD instead of LPD. 10982 * 10983 * all_frames_shall_be_encrypted 10984 * If set, all frames (data only?) shall be encrypted. If not, 10985 * RX CRYPTO shall set an error flag. 10986 * 10987 * encrypt_type 10988 * Values are defined in enum %HAL_ENCRYPT_TYPE_. 10989 * 10990 * mesh_sta 10991 * Indicates a Mesh (11s) STA. 10992 * 10993 * bssid_hit 10994 * BSSID of the incoming frame matched one of the 8 BSSID 10995 * register values. 10996 * 10997 * bssid_number 10998 * This number indicates which one out of the 8 BSSID register 10999 * values matched the incoming frame. 11000 * 11001 * tid 11002 * TID field in the QoS control field 11003 * 11004 * pn 11005 * The PN number. 11006 * 11007 * peer_meta_data 11008 * Meta data that SW has programmed in the Peer table entry 11009 * of the transmitting STA. 11010 * 11011 * rx_reo_queue_desc_addr_lo 11012 * Address (lower 32 bits) of the REO queue descriptor. 11013 * 11014 * rx_reo_queue_desc_addr_hi 11015 * Address (upper 8 bits) of the REO queue descriptor. 11016 * 11017 * receive_queue_number 11018 * Indicates the MPDU queue ID to which this MPDU link 11019 * descriptor belongs. 11020 * 11021 * pre_delim_err_warning 11022 * Indicates that a delimiter FCS error was found in between the 11023 * previous MPDU and this MPDU. Note that this is just a warning, 11024 * and does not mean that this MPDU is corrupted in any way. If 11025 * it is, there will be other errors indicated such as FCS or 11026 * decrypt errors. 11027 * 11028 * first_delim_err 11029 * Indicates that the first delimiter had a FCS failure. 11030 * 11031 * key_id 11032 * The key ID octet from the IV. 11033 * 11034 * new_peer_entry 11035 * Set if new RX_PEER_ENTRY TLV follows. If clear, RX_PEER_ENTRY 11036 * doesn't follow so RX DECRYPTION module either uses old peer 11037 * entry or not decrypt. 11038 * 11039 * decrypt_needed 11040 * When RXPCU sets bit 'ast_index_not_found or ast_index_timeout', 11041 * RXPCU will also ensure that this bit is NOT set. CRYPTO for that 11042 * reason only needs to evaluate this bit and non of the other ones 11043 * 11044 * decap_type 11045 * Used by the OLE during decapsulation. Values are defined in 11046 * enum %MPDU_START_DECAP_TYPE_*. 11047 * 11048 * rx_insert_vlan_c_tag_padding 11049 * rx_insert_vlan_s_tag_padding 11050 * Insert 4 byte of all zeros as VLAN tag or double VLAN tag if 11051 * the rx payload does not have VLAN. 11052 * 11053 * strip_vlan_c_tag_decap 11054 * strip_vlan_s_tag_decap 11055 * Strip VLAN or double VLAN during decapsulation. 11056 * 11057 * pre_delim_count 11058 * The number of delimiters before this MPDU. Note that this 11059 * number is cleared at PPDU start. If this MPDU is the first 11060 * received MPDU in the PPDU and this MPDU gets filtered-in, 11061 * this field will indicate the number of delimiters located 11062 * after the last MPDU in the previous PPDU. 11063 * 11064 * If this MPDU is located after the first received MPDU in 11065 * an PPDU, this field will indicate the number of delimiters 11066 * located between the previous MPDU and this MPDU. 11067 * 11068 * ampdu_flag 11069 * Received frame was part of an A-MPDU. 11070 * 11071 * bar_frame 11072 * Received frame is a BAR frame 11073 * 11074 * mpdu_length 11075 * MPDU length before decapsulation. 11076 * 11077 * first_mpdu..directed 11078 * See definition in RX attention descriptor 11079 * 11080 */ 11081 11082 enum rx_msdu_start_pkt_type { 11083 RX_MSDU_START_PKT_TYPE_11A, 11084 RX_MSDU_START_PKT_TYPE_11B, 11085 RX_MSDU_START_PKT_TYPE_11N, 11086 RX_MSDU_START_PKT_TYPE_11AC, 11087 RX_MSDU_START_PKT_TYPE_11AX, 11088 }; 11089 11090 enum rx_msdu_start_sgi { 11091 RX_MSDU_START_SGI_0_8_US, 11092 RX_MSDU_START_SGI_0_4_US, 11093 RX_MSDU_START_SGI_1_6_US, 11094 RX_MSDU_START_SGI_3_2_US, 11095 }; 11096 11097 enum rx_msdu_start_recv_bw { 11098 RX_MSDU_START_RECV_BW_20MHZ, 11099 RX_MSDU_START_RECV_BW_40MHZ, 11100 RX_MSDU_START_RECV_BW_80MHZ, 11101 RX_MSDU_START_RECV_BW_160MHZ, 11102 }; 11103 11104 enum rx_msdu_start_reception_type { 11105 RX_MSDU_START_RECEPTION_TYPE_SU, 11106 RX_MSDU_START_RECEPTION_TYPE_DL_MU_MIMO, 11107 RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA, 11108 RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA_MIMO, 11109 RX_MSDU_START_RECEPTION_TYPE_UL_MU_MIMO, 11110 RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA, 11111 RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA_MIMO, 11112 }; 11113 11114 #define RX_MSDU_START_INFO1_MSDU_LENGTH GENMASK(13, 0) 11115 #define RX_MSDU_START_INFO1_RSVD_1A BIT(14) 11116 #define RX_MSDU_START_INFO1_IPSEC_ESP BIT(15) 11117 #define RX_MSDU_START_INFO1_L3_OFFSET GENMASK(22, 16) 11118 #define RX_MSDU_START_INFO1_IPSEC_AH BIT(23) 11119 #define RX_MSDU_START_INFO1_L4_OFFSET GENMASK(31, 24) 11120 11121 #define RX_MSDU_START_INFO2_MSDU_NUMBER GENMASK(7, 0) 11122 #define RX_MSDU_START_INFO2_DECAP_TYPE GENMASK(9, 8) 11123 #define RX_MSDU_START_INFO2_IPV4 BIT(10) 11124 #define RX_MSDU_START_INFO2_IPV6 BIT(11) 11125 #define RX_MSDU_START_INFO2_TCP BIT(12) 11126 #define RX_MSDU_START_INFO2_UDP BIT(13) 11127 #define RX_MSDU_START_INFO2_IP_FRAG BIT(14) 11128 #define RX_MSDU_START_INFO2_TCP_ONLY_ACK BIT(15) 11129 #define RX_MSDU_START_INFO2_DA_IS_BCAST_MCAST BIT(16) 11130 #define RX_MSDU_START_INFO2_SELECTED_TOEPLITZ_HASH GENMASK(18, 17) 11131 #define RX_MSDU_START_INFO2_IP_FIXED_HDR_VALID BIT(19) 11132 #define RX_MSDU_START_INFO2_IP_EXTN_HDR_VALID BIT(20) 11133 #define RX_MSDU_START_INFO2_IP_TCP_UDP_HDR_VALID BIT(21) 11134 #define RX_MSDU_START_INFO2_MESH_CTRL_PRESENT BIT(22) 11135 #define RX_MSDU_START_INFO2_LDPC BIT(23) 11136 #define RX_MSDU_START_INFO2_IP4_IP6_NXT_HDR GENMASK(31, 24) 11137 #define RX_MSDU_START_INFO2_DECAP_FORMAT GENMASK(9, 8) 11138 11139 #define RX_MSDU_START_INFO3_USER_RSSI GENMASK(7, 0) 11140 #define RX_MSDU_START_INFO3_PKT_TYPE GENMASK(11, 8) 11141 #define RX_MSDU_START_INFO3_STBC BIT(12) 11142 #define RX_MSDU_START_INFO3_SGI GENMASK(14, 13) 11143 #define RX_MSDU_START_INFO3_RATE_MCS GENMASK(18, 15) 11144 #define RX_MSDU_START_INFO3_RECV_BW GENMASK(20, 19) 11145 #define RX_MSDU_START_INFO3_RECEPTION_TYPE GENMASK(23, 21) 11146 #define RX_MSDU_START_INFO3_MIMO_SS_BITMAP GENMASK(31, 24) 11147 11148 struct rx_msdu_start_ipq8074 { 11149 uint16_t info0; 11150 uint16_t phy_ppdu_id; 11151 uint32_t info1; 11152 uint32_t info2; 11153 uint32_t toeplitz_hash; 11154 uint32_t flow_id_toeplitz; 11155 uint32_t info3; 11156 uint32_t ppdu_start_timestamp; 11157 uint32_t phy_meta_data; 11158 } __packed; 11159 11160 struct rx_msdu_start_qcn9074 { 11161 uint16_t info0; 11162 uint16_t phy_ppdu_id; 11163 uint32_t info1; 11164 uint32_t info2; 11165 uint32_t toeplitz_hash; 11166 uint32_t flow_id_toeplitz; 11167 uint32_t info3; 11168 uint32_t ppdu_start_timestamp; 11169 uint32_t phy_meta_data; 11170 uint16_t vlan_ctag_c1; 11171 uint16_t vlan_stag_c1; 11172 } __packed; 11173 11174 struct rx_msdu_start_wcn6855 { 11175 uint16_t info0; 11176 uint16_t phy_ppdu_id; 11177 uint32_t info1; 11178 uint32_t info2; 11179 uint32_t toeplitz_hash; 11180 uint32_t flow_id_toeplitz; 11181 uint32_t info3; 11182 uint32_t ppdu_start_timestamp; 11183 uint32_t phy_meta_data; 11184 uint16_t vlan_ctag_ci; 11185 uint16_t vlan_stag_ci; 11186 } __packed; 11187 11188 /* rx_msdu_start 11189 * 11190 * rxpcu_mpdu_filter_in_category 11191 * Field indicates what the reason was that this mpdu frame 11192 * was allowed to come into the receive path by rxpcu. Values 11193 * are defined in enum %RX_DESC_RXPCU_FILTER_*. 11194 * 11195 * sw_frame_group_id 11196 * SW processes frames based on certain classifications. Values 11197 * are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*. 11198 * 11199 * phy_ppdu_id 11200 * A ppdu counter value that PHY increments for every PPDU 11201 * received. The counter value wraps around. 11202 * 11203 * msdu_length 11204 * MSDU length in bytes after decapsulation. 11205 * 11206 * ipsec_esp 11207 * Set if IPv4/v6 packet is using IPsec ESP. 11208 * 11209 * l3_offset 11210 * Depending upon mode bit, this field either indicates the 11211 * L3 offset in bytes from the start of the RX_HEADER or the IP 11212 * offset in bytes from the start of the packet after 11213 * decapsulation. The latter is only valid if ipv4_proto or 11214 * ipv6_proto is set. 11215 * 11216 * ipsec_ah 11217 * Set if IPv4/v6 packet is using IPsec AH 11218 * 11219 * l4_offset 11220 * Depending upon mode bit, this field either indicates the 11221 * L4 offset in bytes from the start of RX_HEADER (only valid 11222 * if either ipv4_proto or ipv6_proto is set to 1) or indicates 11223 * the offset in bytes to the start of TCP or UDP header from 11224 * the start of the IP header after decapsulation (Only valid if 11225 * tcp_proto or udp_proto is set). The value 0 indicates that 11226 * the offset is longer than 127 bytes. 11227 * 11228 * msdu_number 11229 * Indicates the MSDU number within a MPDU. This value is 11230 * reset to zero at the start of each MPDU. If the number of 11231 * MSDU exceeds 255 this number will wrap using modulo 256. 11232 * 11233 * decap_type 11234 * Indicates the format after decapsulation. Values are defined in 11235 * enum %MPDU_START_DECAP_TYPE_*. 11236 * 11237 * ipv4_proto 11238 * Set if L2 layer indicates IPv4 protocol. 11239 * 11240 * ipv6_proto 11241 * Set if L2 layer indicates IPv6 protocol. 11242 * 11243 * tcp_proto 11244 * Set if the ipv4_proto or ipv6_proto are set and the IP protocol 11245 * indicates TCP. 11246 * 11247 * udp_proto 11248 * Set if the ipv4_proto or ipv6_proto are set and the IP protocol 11249 * indicates UDP. 11250 * 11251 * ip_frag 11252 * Indicates that either the IP More frag bit is set or IP frag 11253 * number is non-zero. If set indicates that this is a fragmented 11254 * IP packet. 11255 * 11256 * tcp_only_ack 11257 * Set if only the TCP Ack bit is set in the TCP flags and if 11258 * the TCP payload is 0. 11259 * 11260 * da_is_bcast_mcast 11261 * The destination address is broadcast or multicast. 11262 * 11263 * toeplitz_hash 11264 * Actual chosen Hash. 11265 * 0 - Toeplitz hash of 2-tuple (IP source address, IP 11266 * destination address) 11267 * 1 - Toeplitz hash of 4-tuple (IP source address, 11268 * IP destination address, L4 (TCP/UDP) source port, 11269 * L4 (TCP/UDP) destination port) 11270 * 2 - Toeplitz of flow_id 11271 * 3 - Zero is used 11272 * 11273 * ip_fixed_header_valid 11274 * Fixed 20-byte IPv4 header or 40-byte IPv6 header parsed 11275 * fully within first 256 bytes of the packet 11276 * 11277 * ip_extn_header_valid 11278 * IPv6/IPv6 header, including IPv4 options and 11279 * recognizable extension headers parsed fully within first 256 11280 * bytes of the packet 11281 * 11282 * tcp_udp_header_valid 11283 * Fixed 20-byte TCP (excluding TCP options) or 8-byte UDP 11284 * header parsed fully within first 256 bytes of the packet 11285 * 11286 * mesh_control_present 11287 * When set, this MSDU includes the 'Mesh Control' field 11288 * 11289 * ldpc 11290 * 11291 * ip4_protocol_ip6_next_header 11292 * For IPv4, this is the 8 bit protocol field set). For IPv6 this 11293 * is the 8 bit next_header field. 11294 * 11295 * toeplitz_hash_2_or_4 11296 * Controlled by RxOLE register - If register bit set to 0, 11297 * Toeplitz hash is computed over 2-tuple IPv4 or IPv6 src/dest 11298 * addresses; otherwise, toeplitz hash is computed over 4-tuple 11299 * IPv4 or IPv6 src/dest addresses and src/dest ports. 11300 * 11301 * flow_id_toeplitz 11302 * Toeplitz hash of 5-tuple 11303 * {IP source address, IP destination address, IP source port, IP 11304 * destination port, L4 protocol} in case of non-IPSec. 11305 * 11306 * In case of IPSec - Toeplitz hash of 4-tuple 11307 * {IP source address, IP destination address, SPI, L4 protocol} 11308 * 11309 * The relevant Toeplitz key registers are provided in RxOLE's 11310 * instance of common parser module. These registers are separate 11311 * from the Toeplitz keys used by ASE/FSE modules inside RxOLE. 11312 * The actual value will be passed on from common parser module 11313 * to RxOLE in one of the WHO_* TLVs. 11314 * 11315 * user_rssi 11316 * RSSI for this user 11317 * 11318 * pkt_type 11319 * Values are defined in enum %RX_MSDU_START_PKT_TYPE_*. 11320 * 11321 * stbc 11322 * When set, use STBC transmission rates. 11323 * 11324 * sgi 11325 * Field only valid when pkt type is HT, VHT or HE. Values are 11326 * defined in enum %RX_MSDU_START_SGI_*. 11327 * 11328 * rate_mcs 11329 * MCS Rate used. 11330 * 11331 * receive_bandwidth 11332 * Full receive Bandwidth. Values are defined in enum 11333 * %RX_MSDU_START_RECV_*. 11334 * 11335 * reception_type 11336 * Indicates what type of reception this is and defined in enum 11337 * %RX_MSDU_START_RECEPTION_TYPE_*. 11338 * 11339 * mimo_ss_bitmap 11340 * Field only valid when 11341 * Reception_type is RX_MSDU_START_RECEPTION_TYPE_DL_MU_MIMO or 11342 * RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA_MIMO. 11343 * 11344 * Bitmap, with each bit indicating if the related spatial 11345 * stream is used for this STA 11346 * 11347 * LSB related to SS 0 11348 * 11349 * 0 - spatial stream not used for this reception 11350 * 1 - spatial stream used for this reception 11351 * 11352 * ppdu_start_timestamp 11353 * Timestamp that indicates when the PPDU that contained this MPDU 11354 * started on the medium. 11355 * 11356 * phy_meta_data 11357 * SW programmed Meta data provided by the PHY. Can be used for SW 11358 * to indicate the channel the device is on. 11359 */ 11360 11361 #define RX_MSDU_END_INFO0_RXPCU_MPDU_FITLER GENMASK(1, 0) 11362 #define RX_MSDU_END_INFO0_SW_FRAME_GRP_ID GENMASK(8, 2) 11363 11364 #define RX_MSDU_END_INFO1_KEY_ID GENMASK(7, 0) 11365 #define RX_MSDU_END_INFO1_CCE_SUPER_RULE GENMASK(13, 8) 11366 #define RX_MSDU_END_INFO1_CCND_TRUNCATE BIT(14) 11367 #define RX_MSDU_END_INFO1_CCND_CCE_DIS BIT(15) 11368 #define RX_MSDU_END_INFO1_EXT_WAPI_PN GENMASK(31, 16) 11369 11370 #define RX_MSDU_END_INFO2_REPORTED_MPDU_LEN GENMASK(13, 0) 11371 #define RX_MSDU_END_INFO2_FIRST_MSDU BIT(14) 11372 #define RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855 BIT(28) 11373 #define RX_MSDU_END_INFO2_LAST_MSDU BIT(15) 11374 #define RX_MSDU_END_INFO2_LAST_MSDU_WCN6855 BIT(29) 11375 #define RX_MSDU_END_INFO2_SA_IDX_TIMEOUT BIT(16) 11376 #define RX_MSDU_END_INFO2_DA_IDX_TIMEOUT BIT(17) 11377 #define RX_MSDU_END_INFO2_MSDU_LIMIT_ERR BIT(18) 11378 #define RX_MSDU_END_INFO2_FLOW_IDX_TIMEOUT BIT(19) 11379 #define RX_MSDU_END_INFO2_FLOW_IDX_INVALID BIT(20) 11380 #define RX_MSDU_END_INFO2_WIFI_PARSER_ERR BIT(21) 11381 #define RX_MSDU_END_INFO2_AMSDU_PARSET_ERR BIT(22) 11382 #define RX_MSDU_END_INFO2_SA_IS_VALID BIT(23) 11383 #define RX_MSDU_END_INFO2_DA_IS_VALID BIT(24) 11384 #define RX_MSDU_END_INFO2_DA_IS_MCBC BIT(25) 11385 #define RX_MSDU_END_INFO2_L3_HDR_PADDING GENMASK(27, 26) 11386 11387 #define RX_MSDU_END_INFO3_TCP_FLAG GENMASK(8, 0) 11388 #define RX_MSDU_END_INFO3_LRO_ELIGIBLE BIT(9) 11389 11390 #define RX_MSDU_END_INFO4_DA_OFFSET GENMASK(5, 0) 11391 #define RX_MSDU_END_INFO4_SA_OFFSET GENMASK(11, 6) 11392 #define RX_MSDU_END_INFO4_DA_OFFSET_VALID BIT(12) 11393 #define RX_MSDU_END_INFO4_SA_OFFSET_VALID BIT(13) 11394 #define RX_MSDU_END_INFO4_L3_TYPE GENMASK(31, 16) 11395 11396 #define RX_MSDU_END_INFO5_MSDU_DROP BIT(0) 11397 #define RX_MSDU_END_INFO5_REO_DEST_IND GENMASK(5, 1) 11398 #define RX_MSDU_END_INFO5_FLOW_IDX GENMASK(25, 6) 11399 11400 struct rx_msdu_end_ipq8074 { 11401 uint16_t info0; 11402 uint16_t phy_ppdu_id; 11403 uint16_t ip_hdr_cksum; 11404 uint16_t tcp_udp_cksum; 11405 uint32_t info1; 11406 uint32_t ext_wapi_pn[2]; 11407 uint32_t info2; 11408 uint32_t ipv6_options_crc; 11409 uint32_t tcp_seq_num; 11410 uint32_t tcp_ack_num; 11411 uint16_t info3; 11412 uint16_t window_size; 11413 uint32_t info4; 11414 uint32_t rule_indication[2]; 11415 uint16_t sa_idx; 11416 uint16_t da_idx; 11417 uint32_t info5; 11418 uint32_t fse_metadata; 11419 uint16_t cce_metadata; 11420 uint16_t sa_sw_peer_id; 11421 } __packed; 11422 11423 struct rx_msdu_end_wcn6855 { 11424 uint16_t info0; 11425 uint16_t phy_ppdu_id; 11426 uint16_t ip_hdr_cksum; 11427 uint16_t reported_mpdu_len; 11428 uint32_t info1; 11429 uint32_t ext_wapi_pn[2]; 11430 uint32_t info4; 11431 uint32_t ipv6_options_crc; 11432 uint32_t tcp_seq_num; 11433 uint32_t tcp_ack_num; 11434 uint16_t info3; 11435 uint16_t window_size; 11436 uint32_t info2; 11437 uint16_t sa_idx; 11438 uint16_t da_idx; 11439 uint32_t info5; 11440 uint32_t fse_metadata; 11441 uint16_t cce_metadata; 11442 uint16_t sa_sw_peer_id; 11443 uint32_t rule_indication[2]; 11444 uint32_t info6; 11445 uint32_t info7; 11446 } __packed; 11447 11448 #define RX_MSDU_END_MPDU_LENGTH_INFO GENMASK(13, 0) 11449 11450 #define RX_MSDU_END_INFO2_DA_OFFSET GENMASK(5, 0) 11451 #define RX_MSDU_END_INFO2_SA_OFFSET GENMASK(11, 6) 11452 #define RX_MSDU_END_INFO2_DA_OFFSET_VALID BIT(12) 11453 #define RX_MSDU_END_INFO2_SA_OFFSET_VALID BIT(13) 11454 #define RX_MSDU_END_INFO2_L3_TYPE GENMASK(31, 16) 11455 11456 #define RX_MSDU_END_INFO4_SA_IDX_TIMEOUT BIT(0) 11457 #define RX_MSDU_END_INFO4_DA_IDX_TIMEOUT BIT(1) 11458 #define RX_MSDU_END_INFO4_MSDU_LIMIT_ERR BIT(2) 11459 #define RX_MSDU_END_INFO4_FLOW_IDX_TIMEOUT BIT(3) 11460 #define RX_MSDU_END_INFO4_FLOW_IDX_INVALID BIT(4) 11461 #define RX_MSDU_END_INFO4_WIFI_PARSER_ERR BIT(5) 11462 #define RX_MSDU_END_INFO4_AMSDU_PARSER_ERR BIT(6) 11463 #define RX_MSDU_END_INFO4_SA_IS_VALID BIT(7) 11464 #define RX_MSDU_END_INFO4_DA_IS_VALID BIT(8) 11465 #define RX_MSDU_END_INFO4_DA_IS_MCBC BIT(9) 11466 #define RX_MSDU_END_INFO4_L3_HDR_PADDING GENMASK(11, 10) 11467 #define RX_MSDU_END_INFO4_FIRST_MSDU BIT(12) 11468 #define RX_MSDU_END_INFO4_LAST_MSDU BIT(13) 11469 11470 #define RX_MSDU_END_INFO6_AGGR_COUNT GENMASK(7, 0) 11471 #define RX_MSDU_END_INFO6_FLOW_AGGR_CONTN BIT(8) 11472 #define RX_MSDU_END_INFO6_FISA_TIMEOUT BIT(9) 11473 11474 struct rx_msdu_end_qcn9074 { 11475 uint16_t info0; 11476 uint16_t phy_ppdu_id; 11477 uint16_t ip_hdr_cksum; 11478 uint16_t mpdu_length_info; 11479 uint32_t info1; 11480 uint32_t rule_indication[2]; 11481 uint32_t info2; 11482 uint32_t ipv6_options_crc; 11483 uint32_t tcp_seq_num; 11484 uint32_t tcp_ack_num; 11485 uint16_t info3; 11486 uint16_t window_size; 11487 uint16_t tcp_udp_cksum; 11488 uint16_t info4; 11489 uint16_t sa_idx; 11490 uint16_t da_idx; 11491 uint32_t info5; 11492 uint32_t fse_metadata; 11493 uint16_t cce_metadata; 11494 uint16_t sa_sw_peer_id; 11495 uint32_t info6; 11496 uint16_t cum_l4_cksum; 11497 uint16_t cum_ip_length; 11498 } __packed; 11499 11500 /* rx_msdu_end 11501 * 11502 * rxpcu_mpdu_filter_in_category 11503 * Field indicates what the reason was that this mpdu frame 11504 * was allowed to come into the receive path by rxpcu. Values 11505 * are defined in enum %RX_DESC_RXPCU_FILTER_*. 11506 * 11507 * sw_frame_group_id 11508 * SW processes frames based on certain classifications. Values 11509 * are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*. 11510 * 11511 * phy_ppdu_id 11512 * A ppdu counter value that PHY increments for every PPDU 11513 * received. The counter value wraps around. 11514 * 11515 * ip_hdr_cksum 11516 * This can include the IP header checksum or the pseudo 11517 * header checksum used by TCP/UDP checksum. 11518 * 11519 * tcp_udp_chksum 11520 * The value of the computed TCP/UDP checksum. A mode bit 11521 * selects whether this checksum is the full checksum or the 11522 * partial checksum which does not include the pseudo header. 11523 * 11524 * key_id 11525 * The key ID octet from the IV. Only valid when first_msdu is set. 11526 * 11527 * cce_super_rule 11528 * Indicates the super filter rule. 11529 * 11530 * cce_classify_not_done_truncate 11531 * Classification failed due to truncated frame. 11532 * 11533 * cce_classify_not_done_cce_dis 11534 * Classification failed due to CCE global disable 11535 * 11536 * ext_wapi_pn* 11537 * Extension PN (packet number) which is only used by WAPI. 11538 * 11539 * reported_mpdu_length 11540 * MPDU length before decapsulation. Only valid when first_msdu is 11541 * set. This field is taken directly from the length field of the 11542 * A-MPDU delimiter or the preamble length field for non-A-MPDU 11543 * frames. 11544 * 11545 * first_msdu 11546 * Indicates the first MSDU of A-MSDU. If both first_msdu and 11547 * last_msdu are set in the MSDU then this is a non-aggregated MSDU 11548 * frame: normal MPDU. Interior MSDU in an A-MSDU shall have both 11549 * first_mpdu and last_mpdu bits set to 0. 11550 * 11551 * last_msdu 11552 * Indicates the last MSDU of the A-MSDU. MPDU end status is only 11553 * valid when last_msdu is set. 11554 * 11555 * sa_idx_timeout 11556 * Indicates an unsuccessful MAC source address search due to the 11557 * expiring of the search timer. 11558 * 11559 * da_idx_timeout 11560 * Indicates an unsuccessful MAC destination address search due to 11561 * the expiring of the search timer. 11562 * 11563 * msdu_limit_error 11564 * Indicates that the MSDU threshold was exceeded and thus all the 11565 * rest of the MSDUs will not be scattered and will not be 11566 * decapsulated but will be DMA'ed in RAW format as a single MSDU. 11567 * 11568 * flow_idx_timeout 11569 * Indicates an unsuccessful flow search due to the expiring of 11570 * the search timer. 11571 * 11572 * flow_idx_invalid 11573 * flow id is not valid. 11574 * 11575 * amsdu_parser_error 11576 * A-MSDU could not be properly de-agregated. 11577 * 11578 * sa_is_valid 11579 * Indicates that OLE found a valid SA entry. 11580 * 11581 * da_is_valid 11582 * Indicates that OLE found a valid DA entry. 11583 * 11584 * da_is_mcbc 11585 * Field Only valid if da_is_valid is set. Indicates the DA address 11586 * was a Multicast of Broadcast address. 11587 * 11588 * l3_header_padding 11589 * Number of bytes padded to make sure that the L3 header will 11590 * always start of a Dword boundary. 11591 * 11592 * ipv6_options_crc 11593 * 32 bit CRC computed out of IP v6 extension headers. 11594 * 11595 * tcp_seq_number 11596 * TCP sequence number. 11597 * 11598 * tcp_ack_number 11599 * TCP acknowledge number. 11600 * 11601 * tcp_flag 11602 * TCP flags {NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN}. 11603 * 11604 * lro_eligible 11605 * Computed out of TCP and IP fields to indicate that this 11606 * MSDU is eligible for LRO. 11607 * 11608 * window_size 11609 * TCP receive window size. 11610 * 11611 * da_offset 11612 * Offset into MSDU buffer for DA. 11613 * 11614 * sa_offset 11615 * Offset into MSDU buffer for SA. 11616 * 11617 * da_offset_valid 11618 * da_offset field is valid. This will be set to 0 in case 11619 * of a dynamic A-MSDU when DA is compressed. 11620 * 11621 * sa_offset_valid 11622 * sa_offset field is valid. This will be set to 0 in case 11623 * of a dynamic A-MSDU when SA is compressed. 11624 * 11625 * l3_type 11626 * The 16-bit type value indicating the type of L3 later 11627 * extracted from LLC/SNAP, set to zero if SNAP is not 11628 * available. 11629 * 11630 * rule_indication 11631 * Bitmap indicating which of rules have matched. 11632 * 11633 * sa_idx 11634 * The offset in the address table which matches MAC source address 11635 * 11636 * da_idx 11637 * The offset in the address table which matches MAC destination 11638 * address. 11639 * 11640 * msdu_drop 11641 * REO shall drop this MSDU and not forward it to any other ring. 11642 * 11643 * reo_destination_indication 11644 * The id of the reo exit ring where the msdu frame shall push 11645 * after (MPDU level) reordering has finished. Values are defined 11646 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. 11647 * 11648 * flow_idx 11649 * Flow table index. 11650 * 11651 * fse_metadata 11652 * FSE related meta data. 11653 * 11654 * cce_metadata 11655 * CCE related meta data. 11656 * 11657 * sa_sw_peer_id 11658 * sw_peer_id from the address search entry corresponding to the 11659 * source address of the MSDU. 11660 */ 11661 11662 enum rx_mpdu_end_rxdma_dest_ring { 11663 RX_MPDU_END_RXDMA_DEST_RING_RELEASE, 11664 RX_MPDU_END_RXDMA_DEST_RING_FW, 11665 RX_MPDU_END_RXDMA_DEST_RING_SW, 11666 RX_MPDU_END_RXDMA_DEST_RING_REO, 11667 }; 11668 11669 #define RX_MPDU_END_INFO1_UNSUP_KTYPE_SHORT_FRAME BIT(11) 11670 #define RX_MPDU_END_INFO1_RX_IN_TX_DECRYPT_BYT BIT(12) 11671 #define RX_MPDU_END_INFO1_OVERFLOW_ERR BIT(13) 11672 #define RX_MPDU_END_INFO1_MPDU_LEN_ERR BIT(14) 11673 #define RX_MPDU_END_INFO1_TKIP_MIC_ERR BIT(15) 11674 #define RX_MPDU_END_INFO1_DECRYPT_ERR BIT(16) 11675 #define RX_MPDU_END_INFO1_UNENCRYPTED_FRAME_ERR BIT(17) 11676 #define RX_MPDU_END_INFO1_PN_FIELDS_VALID BIT(18) 11677 #define RX_MPDU_END_INFO1_FCS_ERR BIT(19) 11678 #define RX_MPDU_END_INFO1_MSDU_LEN_ERR BIT(20) 11679 #define RX_MPDU_END_INFO1_RXDMA0_DEST_RING GENMASK(22, 21) 11680 #define RX_MPDU_END_INFO1_RXDMA1_DEST_RING GENMASK(24, 23) 11681 #define RX_MPDU_END_INFO1_DECRYPT_STATUS_CODE GENMASK(27, 25) 11682 #define RX_MPDU_END_INFO1_RX_BITMAP_NOT_UPD BIT(28) 11683 11684 struct rx_mpdu_end { 11685 uint16_t info0; 11686 uint16_t phy_ppdu_id; 11687 uint32_t info1; 11688 } __packed; 11689 11690 /* rx_mpdu_end 11691 * 11692 * rxpcu_mpdu_filter_in_category 11693 * Field indicates what the reason was that this mpdu frame 11694 * was allowed to come into the receive path by rxpcu. Values 11695 * are defined in enum %RX_DESC_RXPCU_FILTER_*. 11696 * 11697 * sw_frame_group_id 11698 * SW processes frames based on certain classifications. Values 11699 * are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*. 11700 * 11701 * phy_ppdu_id 11702 * A ppdu counter value that PHY increments for every PPDU 11703 * received. The counter value wraps around. 11704 * 11705 * unsup_ktype_short_frame 11706 * This bit will be '1' when WEP or TKIP or WAPI key type is 11707 * received for 11ah short frame. Crypto will bypass the received 11708 * packet without decryption to RxOLE after setting this bit. 11709 * 11710 * rx_in_tx_decrypt_byp 11711 * Indicates that RX packet is not decrypted as Crypto is 11712 * busy with TX packet processing. 11713 * 11714 * overflow_err 11715 * RXPCU Receive FIFO ran out of space to receive the full MPDU. 11716 * Therefore this MPDU is terminated early and is thus corrupted. 11717 * 11718 * This MPDU will not be ACKed. 11719 * 11720 * RXPCU might still be able to correctly receive the following 11721 * MPDUs in the PPDU if enough fifo space became available in time. 11722 * 11723 * mpdu_length_err 11724 * Set by RXPCU if the expected MPDU length does not correspond 11725 * with the actually received number of bytes in the MPDU. 11726 * 11727 * tkip_mic_err 11728 * Set by Rx crypto when crypto detected a TKIP MIC error for 11729 * this MPDU. 11730 * 11731 * decrypt_err 11732 * Set by RX CRYPTO when CRYPTO detected a decrypt error for this 11733 * MPDU or CRYPTO received an encrypted frame, but did not get a 11734 * valid corresponding key id in the peer entry. 11735 * 11736 * unencrypted_frame_err 11737 * Set by RX CRYPTO when CRYPTO detected an unencrypted frame while 11738 * in the peer entry field 'All_frames_shall_be_encrypted' is set. 11739 * 11740 * pn_fields_contain_valid_info 11741 * Set by RX CRYPTO to indicate that there is a valid PN field 11742 * present in this MPDU. 11743 * 11744 * fcs_err 11745 * Set by RXPCU when there is an FCS error detected for this MPDU. 11746 * 11747 * msdu_length_err 11748 * Set by RXOLE when there is an msdu length error detected 11749 * in at least 1 of the MSDUs embedded within the MPDU. 11750 * 11751 * rxdma0_destination_ring 11752 * rxdma1_destination_ring 11753 * The ring to which RXDMA0/1 shall push the frame, assuming 11754 * no MPDU level errors are detected. In case of MPDU level 11755 * errors, RXDMA0/1 might change the RXDMA0/1 destination. Values 11756 * are defined in %enum RX_MPDU_END_RXDMA_DEST_RING_*. 11757 * 11758 * decrypt_status_code 11759 * Field provides insight into the decryption performed. Values 11760 * are defined in enum %RX_DESC_DECRYPT_STATUS_CODE_*. 11761 * 11762 * rx_bitmap_not_updated 11763 * Frame is received, but RXPCU could not update the receive bitmap 11764 * due to (temporary) fifo constraints. 11765 */ 11766 11767 /* Padding bytes to avoid TLV's spanning across 128 byte boundary */ 11768 #define HAL_RX_DESC_PADDING0_BYTES 4 11769 #define HAL_RX_DESC_PADDING1_BYTES 16 11770 11771 #define HAL_RX_DESC_HDR_STATUS_LEN 120 11772 11773 struct hal_rx_desc_ipq8074 { 11774 uint32_t msdu_end_tag; 11775 struct rx_msdu_end_ipq8074 msdu_end; 11776 uint32_t rx_attn_tag; 11777 struct rx_attention attention; 11778 uint32_t msdu_start_tag; 11779 struct rx_msdu_start_ipq8074 msdu_start; 11780 uint8_t rx_padding0[HAL_RX_DESC_PADDING0_BYTES]; 11781 uint32_t mpdu_start_tag; 11782 struct rx_mpdu_start_ipq8074 mpdu_start; 11783 uint32_t mpdu_end_tag; 11784 struct rx_mpdu_end mpdu_end; 11785 uint8_t rx_padding1[HAL_RX_DESC_PADDING1_BYTES]; 11786 uint32_t hdr_status_tag; 11787 uint32_t phy_ppdu_id; 11788 uint8_t hdr_status[HAL_RX_DESC_HDR_STATUS_LEN]; 11789 uint8_t msdu_payload[]; 11790 } __packed; 11791 11792 struct hal_rx_desc_qcn9074 { 11793 uint32_t msdu_end_tag; 11794 struct rx_msdu_end_qcn9074 msdu_end; 11795 uint32_t rx_attn_tag; 11796 struct rx_attention attention; 11797 uint32_t msdu_start_tag; 11798 struct rx_msdu_start_qcn9074 msdu_start; 11799 uint8_t rx_padding0[HAL_RX_DESC_PADDING0_BYTES]; 11800 uint32_t mpdu_start_tag; 11801 struct rx_mpdu_start_qcn9074 mpdu_start; 11802 uint32_t mpdu_end_tag; 11803 struct rx_mpdu_end mpdu_end; 11804 uint8_t rx_padding1[HAL_RX_DESC_PADDING1_BYTES]; 11805 uint32_t hdr_status_tag; 11806 uint32_t phy_ppdu_id; 11807 uint8_t hdr_status[HAL_RX_DESC_HDR_STATUS_LEN]; 11808 uint8_t msdu_payload[]; 11809 } __packed; 11810 11811 struct hal_rx_desc_wcn6855 { 11812 uint32_t msdu_end_tag; 11813 struct rx_msdu_end_wcn6855 msdu_end; 11814 uint32_t rx_attn_tag; 11815 struct rx_attention attention; 11816 uint32_t msdu_start_tag; 11817 struct rx_msdu_start_wcn6855 msdu_start; 11818 uint8_t rx_padding0[HAL_RX_DESC_PADDING0_BYTES]; 11819 uint32_t mpdu_start_tag; 11820 struct rx_mpdu_start_wcn6855 mpdu_start; 11821 uint32_t mpdu_end_tag; 11822 struct rx_mpdu_end mpdu_end; 11823 uint8_t rx_padding1[HAL_RX_DESC_PADDING1_BYTES]; 11824 uint32_t hdr_status_tag; 11825 uint32_t phy_ppdu_id; 11826 uint8_t hdr_status[HAL_RX_DESC_HDR_STATUS_LEN]; 11827 uint8_t msdu_payload[]; 11828 } __packed; 11829 11830 struct hal_rx_desc { 11831 union { 11832 struct hal_rx_desc_ipq8074 ipq8074; 11833 struct hal_rx_desc_qcn9074 qcn9074; 11834 struct hal_rx_desc_wcn6855 wcn6855; 11835 } u; 11836 } __packed; 11837 11838 #define HAL_RX_RU_ALLOC_TYPE_MAX 6 11839 #define RU_26 1 11840 #define RU_52 2 11841 #define RU_106 4 11842 #define RU_242 9 11843 #define RU_484 18 11844 #define RU_996 37 11845 11846 /* 11847 * dp.h 11848 */ 11849 11850 /* HTT definitions */ 11851 11852 #define HTT_TCL_META_DATA_TYPE BIT(0) 11853 #define HTT_TCL_META_DATA_VALID_HTT BIT(1) 11854 11855 /* vdev meta data */ 11856 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2) 11857 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10) 11858 #define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12) 11859 11860 /* peer meta data */ 11861 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2) 11862 11863 #define HTT_TX_WBM_COMP_STATUS_OFFSET 8 11864 11865 #define HTT_INVALID_PEER_ID 0xffff 11866 11867 /* HTT tx completion is overlaid in wbm_release_ring */ 11868 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(12, 9) 11869 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) 11870 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) 11871 11872 #define HTT_TX_WBM_COMP_INFO1_ACK_RSSI GENMASK(31, 24) 11873 #define HTT_TX_WBM_COMP_INFO2_SW_PEER_ID GENMASK(15, 0) 11874 #define HTT_TX_WBM_COMP_INFO2_VALID BIT(21) 11875 11876 struct htt_tx_wbm_completion { 11877 uint32_t info0; 11878 uint32_t info1; 11879 uint32_t info2; 11880 uint32_t info3; 11881 } __packed; 11882 11883 enum htt_h2t_msg_type { 11884 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 11885 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, 11886 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, 11887 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10, 11888 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, 11889 HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE = 0x17, 11890 }; 11891 11892 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0) 11893 11894 struct htt_ver_req_cmd { 11895 uint32_t ver_reg_info; 11896 } __packed; 11897 11898 enum htt_srng_ring_type { 11899 HTT_HW_TO_SW_RING, 11900 HTT_SW_TO_HW_RING, 11901 HTT_SW_TO_SW_RING, 11902 }; 11903 11904 enum htt_srng_ring_id { 11905 HTT_RXDMA_HOST_BUF_RING, 11906 HTT_RXDMA_MONITOR_STATUS_RING, 11907 HTT_RXDMA_MONITOR_BUF_RING, 11908 HTT_RXDMA_MONITOR_DESC_RING, 11909 HTT_RXDMA_MONITOR_DEST_RING, 11910 HTT_HOST1_TO_FW_RXBUF_RING, 11911 HTT_HOST2_TO_FW_RXBUF_RING, 11912 HTT_RXDMA_NON_MONITOR_DEST_RING, 11913 }; 11914 11915 /* host -> target HTT_SRING_SETUP message 11916 * 11917 * After target is booted up, Host can send SRING setup message for 11918 * each host facing LMAC SRING. Target setups up HW registers based 11919 * on setup message and confirms back to Host if response_required is set. 11920 * Host should wait for confirmation message before sending new SRING 11921 * setup message 11922 * 11923 * The message would appear as follows: 11924 * 11925 * |31 24|23 20|19|18 16|15|14 8|7 0| 11926 * |--------------- +-----------------+----------------+------------------| 11927 * | ring_type | ring_id | pdev_id | msg_type | 11928 * |----------------------------------------------------------------------| 11929 * | ring_base_addr_lo | 11930 * |----------------------------------------------------------------------| 11931 * | ring_base_addr_hi | 11932 * |----------------------------------------------------------------------| 11933 * |ring_misc_cfg_flag|ring_entry_size| ring_size | 11934 * |----------------------------------------------------------------------| 11935 * | ring_head_offset32_remote_addr_lo | 11936 * |----------------------------------------------------------------------| 11937 * | ring_head_offset32_remote_addr_hi | 11938 * |----------------------------------------------------------------------| 11939 * | ring_tail_offset32_remote_addr_lo | 11940 * |----------------------------------------------------------------------| 11941 * | ring_tail_offset32_remote_addr_hi | 11942 * |----------------------------------------------------------------------| 11943 * | ring_msi_addr_lo | 11944 * |----------------------------------------------------------------------| 11945 * | ring_msi_addr_hi | 11946 * |----------------------------------------------------------------------| 11947 * | ring_msi_data | 11948 * |----------------------------------------------------------------------| 11949 * | intr_timer_th |IM| intr_batch_counter_th | 11950 * |----------------------------------------------------------------------| 11951 * | reserved |RR|PTCF| intr_low_threshold | 11952 * |----------------------------------------------------------------------| 11953 * Where 11954 * IM = sw_intr_mode 11955 * RR = response_required 11956 * PTCF = prefetch_timer_cfg 11957 * 11958 * The message is interpreted as follows: 11959 * dword0 - b'0:7 - msg_type: This will be set to 11960 * HTT_H2T_MSG_TYPE_SRING_SETUP 11961 * b'8:15 - pdev_id: 11962 * 0 (for rings at SOC/UMAC level), 11963 * 1/2/3 mac id (for rings at LMAC level) 11964 * b'16:23 - ring_id: identify which ring is to setup, 11965 * more details can be got from enum htt_srng_ring_id 11966 * b'24:31 - ring_type: identify type of host rings, 11967 * more details can be got from enum htt_srng_ring_type 11968 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address 11969 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address 11970 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words 11971 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units 11972 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and 11973 * SW_TO_HW_RING. 11974 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. 11975 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo: 11976 * Lower 32 bits of memory address of the remote variable 11977 * storing the 4-byte word offset that identifies the head 11978 * element within the ring. 11979 * (The head offset variable has type uint32_t.) 11980 * Valid for HW_TO_SW and SW_TO_SW rings. 11981 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi: 11982 * Upper 32 bits of memory address of the remote variable 11983 * storing the 4-byte word offset that identifies the head 11984 * element within the ring. 11985 * (The head offset variable has type uint32_t.) 11986 * Valid for HW_TO_SW and SW_TO_SW rings. 11987 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo: 11988 * Lower 32 bits of memory address of the remote variable 11989 * storing the 4-byte word offset that identifies the tail 11990 * element within the ring. 11991 * (The tail offset variable has type uint32_t.) 11992 * Valid for HW_TO_SW and SW_TO_SW rings. 11993 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi: 11994 * Upper 32 bits of memory address of the remote variable 11995 * storing the 4-byte word offset that identifies the tail 11996 * element within the ring. 11997 * (The tail offset variable has type uint32_t.) 11998 * Valid for HW_TO_SW and SW_TO_SW rings. 11999 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 12000 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 12001 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 12002 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 12003 * dword10 - b'0:31 - ring_msi_data: MSI data 12004 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs 12005 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 12006 * dword11 - b'0:14 - intr_batch_counter_th: 12007 * batch counter threshold is in units of 4-byte words. 12008 * HW internally maintains and increments batch count. 12009 * (see SRING spec for detail description). 12010 * When batch count reaches threshold value, an interrupt 12011 * is generated by HW. 12012 * b'15 - sw_intr_mode: 12013 * This configuration shall be static. 12014 * Only programmed at power up. 12015 * 0: generate pulse style sw interrupts 12016 * 1: generate level style sw interrupts 12017 * b'16:31 - intr_timer_th: 12018 * The timer init value when timer is idle or is 12019 * initialized to start downcounting. 12020 * In 8us units (to cover a range of 0 to 524 ms) 12021 * dword12 - b'0:15 - intr_low_threshold: 12022 * Used only by Consumer ring to generate ring_sw_int_p. 12023 * Ring entries low threshold water mark, that is used 12024 * in combination with the interrupt timer as well as 12025 * the clearing of the level interrupt. 12026 * b'16:18 - prefetch_timer_cfg: 12027 * Used only by Consumer ring to set timer mode to 12028 * support Application prefetch handling. 12029 * The external tail offset/pointer will be updated 12030 * at following intervals: 12031 * 3'b000: (Prefetch feature disabled; used only for debug) 12032 * 3'b001: 1 usec 12033 * 3'b010: 4 usec 12034 * 3'b011: 8 usec (default) 12035 * 3'b100: 16 usec 12036 * Others: Reserved 12037 * b'19 - response_required: 12038 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response 12039 * b'20:31 - reserved: reserved for future use 12040 */ 12041 12042 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 12043 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8) 12044 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16) 12045 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24) 12046 12047 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0) 12048 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16) 12049 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25) 12050 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27) 12051 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28) 12052 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29) 12053 12054 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0) 12055 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15) 12056 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16) 12057 12058 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0) 12059 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG BIT(16) 12060 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19) 12061 12062 struct htt_srng_setup_cmd { 12063 uint32_t info0; 12064 uint32_t ring_base_addr_lo; 12065 uint32_t ring_base_addr_hi; 12066 uint32_t info1; 12067 uint32_t ring_head_off32_remote_addr_lo; 12068 uint32_t ring_head_off32_remote_addr_hi; 12069 uint32_t ring_tail_off32_remote_addr_lo; 12070 uint32_t ring_tail_off32_remote_addr_hi; 12071 uint32_t ring_msi_addr_lo; 12072 uint32_t ring_msi_addr_hi; 12073 uint32_t msi_data; 12074 uint32_t intr_info; 12075 uint32_t info2; 12076 } __packed; 12077 12078 /* host -> target FW PPDU_STATS config message 12079 * 12080 * @details 12081 * The following field definitions describe the format of the HTT host 12082 * to target FW for PPDU_STATS_CFG msg. 12083 * The message allows the host to configure the PPDU_STATS_IND messages 12084 * produced by the target. 12085 * 12086 * |31 24|23 16|15 8|7 0| 12087 * |-----------------------------------------------------------| 12088 * | REQ bit mask | pdev_mask | msg type | 12089 * |-----------------------------------------------------------| 12090 * Header fields: 12091 * - MSG_TYPE 12092 * Bits 7:0 12093 * Purpose: identifies this is a req to configure ppdu_stats_ind from target 12094 * Value: 0x11 12095 * - PDEV_MASK 12096 * Bits 8:15 12097 * Purpose: identifies which pdevs this PPDU stats configuration applies to 12098 * Value: This is a overloaded field, refer to usage and interpretation of 12099 * PDEV in interface document. 12100 * Bit 8 : Reserved for SOC stats 12101 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 12102 * Indicates MACID_MASK in DBS 12103 * - REQ_TLV_BIT_MASK 12104 * Bits 16:31 12105 * Purpose: each set bit indicates the corresponding PPDU stats TLV type 12106 * needs to be included in the target's PPDU_STATS_IND messages. 12107 * Value: refer htt_ppdu_stats_tlv_tag_t <<<??? 12108 * 12109 */ 12110 12111 struct htt_ppdu_stats_cfg_cmd { 12112 uint32_t msg; 12113 } __packed; 12114 12115 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0) 12116 #define HTT_PPDU_STATS_CFG_SOC_STATS BIT(8) 12117 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 9) 12118 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16) 12119 12120 enum htt_ppdu_stats_tag_type { 12121 HTT_PPDU_STATS_TAG_COMMON, 12122 HTT_PPDU_STATS_TAG_USR_COMMON, 12123 HTT_PPDU_STATS_TAG_USR_RATE, 12124 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64, 12125 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256, 12126 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS, 12127 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON, 12128 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64, 12129 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256, 12130 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS, 12131 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH, 12132 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY, 12133 HTT_PPDU_STATS_TAG_INFO, 12134 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD, 12135 12136 /* New TLV's are added above to this line */ 12137 HTT_PPDU_STATS_TAG_MAX, 12138 }; 12139 12140 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \ 12141 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \ 12142 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \ 12143 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \ 12144 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \ 12145 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \ 12146 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \ 12147 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY)) 12148 12149 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \ 12150 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \ 12151 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \ 12152 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \ 12153 BIT(HTT_PPDU_STATS_TAG_INFO) | \ 12154 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \ 12155 HTT_PPDU_STATS_TAG_DEFAULT) 12156 12157 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message 12158 * 12159 * details: 12160 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to 12161 * configure RXDMA rings. 12162 * The configuration is per ring based and includes both packet subtypes 12163 * and PPDU/MPDU TLVs. 12164 * 12165 * The message would appear as follows: 12166 * 12167 * |31 26|25|24|23 16|15 8|7 0| 12168 * |-----------------+----------------+----------------+---------------| 12169 * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type | 12170 * |-------------------------------------------------------------------| 12171 * | rsvd2 | ring_buffer_size | 12172 * |-------------------------------------------------------------------| 12173 * | packet_type_enable_flags_0 | 12174 * |-------------------------------------------------------------------| 12175 * | packet_type_enable_flags_1 | 12176 * |-------------------------------------------------------------------| 12177 * | packet_type_enable_flags_2 | 12178 * |-------------------------------------------------------------------| 12179 * | packet_type_enable_flags_3 | 12180 * |-------------------------------------------------------------------| 12181 * | tlv_filter_in_flags | 12182 * |-------------------------------------------------------------------| 12183 * Where: 12184 * PS = pkt_swap 12185 * SS = status_swap 12186 * The message is interpreted as follows: 12187 * dword0 - b'0:7 - msg_type: This will be set to 12188 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG 12189 * b'8:15 - pdev_id: 12190 * 0 (for rings at SOC/UMAC level), 12191 * 1/2/3 mac id (for rings at LMAC level) 12192 * b'16:23 - ring_id : Identify the ring to configure. 12193 * More details can be got from enum htt_srng_ring_id 12194 * b'24 - status_swap: 1 is to swap status TLV 12195 * b'25 - pkt_swap: 1 is to swap packet TLV 12196 * b'26:31 - rsvd1: reserved for future use 12197 * dword1 - b'0:16 - ring_buffer_size: size of buffers referenced by rx ring, 12198 * in byte units. 12199 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 12200 * - b'16:31 - rsvd2: Reserved for future use 12201 * dword2 - b'0:31 - packet_type_enable_flags_0: 12202 * Enable MGMT packet from 0b0000 to 0b1001 12203 * bits from low to high: FP, MD, MO - 3 bits 12204 * FP: Filter_Pass 12205 * MD: Monitor_Direct 12206 * MO: Monitor_Other 12207 * 10 mgmt subtypes * 3 bits -> 30 bits 12208 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs 12209 * dword3 - b'0:31 - packet_type_enable_flags_1: 12210 * Enable MGMT packet from 0b1010 to 0b1111 12211 * bits from low to high: FP, MD, MO - 3 bits 12212 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs 12213 * dword4 - b'0:31 - packet_type_enable_flags_2: 12214 * Enable CTRL packet from 0b0000 to 0b1001 12215 * bits from low to high: FP, MD, MO - 3 bits 12216 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs 12217 * dword5 - b'0:31 - packet_type_enable_flags_3: 12218 * Enable CTRL packet from 0b1010 to 0b1111, 12219 * MCAST_DATA, UCAST_DATA, NULL_DATA 12220 * bits from low to high: FP, MD, MO - 3 bits 12221 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs 12222 * dword6 - b'0:31 - tlv_filter_in_flags: 12223 * Filter in Attention/MPDU/PPDU/Header/User tlvs 12224 * Refer to CFG_TLV_FILTER_IN_FLAG defs 12225 */ 12226 12227 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 12228 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 12229 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 12230 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 12231 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 12232 12233 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0) 12234 12235 enum htt_rx_filter_tlv_flags { 12236 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0), 12237 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1), 12238 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2), 12239 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3), 12240 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4), 12241 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5), 12242 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6), 12243 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7), 12244 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8), 12245 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9), 12246 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10), 12247 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11), 12248 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12), 12249 }; 12250 12251 enum htt_rx_mgmt_pkt_filter_tlv_flags0 { 12252 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0), 12253 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1), 12254 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2), 12255 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3), 12256 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4), 12257 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5), 12258 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6), 12259 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7), 12260 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8), 12261 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9), 12262 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10), 12263 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11), 12264 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12), 12265 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13), 12266 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14), 12267 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15), 12268 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16), 12269 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17), 12270 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18), 12271 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19), 12272 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20), 12273 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21), 12274 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22), 12275 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23), 12276 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24), 12277 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25), 12278 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26), 12279 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27), 12280 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28), 12281 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29), 12282 }; 12283 12284 enum htt_rx_mgmt_pkt_filter_tlv_flags1 { 12285 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0), 12286 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1), 12287 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2), 12288 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3), 12289 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4), 12290 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5), 12291 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6), 12292 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7), 12293 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8), 12294 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9), 12295 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10), 12296 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11), 12297 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12), 12298 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13), 12299 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14), 12300 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15), 12301 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16), 12302 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17), 12303 }; 12304 12305 enum htt_rx_ctrl_pkt_filter_tlv_flags2 { 12306 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0), 12307 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1), 12308 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2), 12309 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3), 12310 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4), 12311 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5), 12312 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6), 12313 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7), 12314 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8), 12315 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9), 12316 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10), 12317 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11), 12318 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12), 12319 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13), 12320 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14), 12321 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15), 12322 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16), 12323 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17), 12324 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18), 12325 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19), 12326 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20), 12327 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21), 12328 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22), 12329 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23), 12330 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24), 12331 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25), 12332 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26), 12333 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27), 12334 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28), 12335 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29), 12336 }; 12337 12338 enum htt_rx_ctrl_pkt_filter_tlv_flags3 { 12339 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0), 12340 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1), 12341 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2), 12342 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3), 12343 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4), 12344 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5), 12345 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6), 12346 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7), 12347 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8), 12348 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9), 12349 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10), 12350 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11), 12351 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12), 12352 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13), 12353 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14), 12354 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15), 12355 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16), 12356 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17), 12357 }; 12358 12359 enum htt_rx_data_pkt_filter_tlv_flasg3 { 12360 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18), 12361 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19), 12362 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20), 12363 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21), 12364 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22), 12365 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23), 12366 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24), 12367 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25), 12368 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26), 12369 }; 12370 12371 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \ 12372 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 12373 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 12374 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 12375 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 12376 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 12377 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 12378 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 12379 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 12380 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 12381 12382 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \ 12383 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 12384 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 12385 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 12386 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 12387 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 12388 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 12389 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 12390 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 12391 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 12392 12393 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \ 12394 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 12395 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 12396 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 12397 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 12398 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 12399 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 12400 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 12401 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 12402 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 12403 12404 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 12405 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 12406 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 12407 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 12408 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 12409 12410 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 12411 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 12412 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 12413 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 12414 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 12415 12416 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 12417 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 12418 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 12419 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 12420 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 12421 12422 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 12423 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 12424 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 12425 12426 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 12427 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 12428 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 12429 12430 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 12431 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 12432 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 12433 12434 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 12435 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 12436 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 12437 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 12438 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 12439 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 12440 12441 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 12442 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 12443 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 12444 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 12445 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 12446 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 12447 12448 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 12449 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 12450 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 12451 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 12452 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 12453 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 12454 12455 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 12456 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 12457 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 12458 12459 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 12460 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 12461 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 12462 12463 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 12464 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 12465 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 12466 12467 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \ 12468 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \ 12469 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 12470 12471 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \ 12472 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \ 12473 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 12474 12475 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \ 12476 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \ 12477 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 12478 12479 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \ 12480 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \ 12481 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 12482 12483 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \ 12484 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \ 12485 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 12486 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 12487 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 12488 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 12489 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 12490 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 12491 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 12492 12493 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \ 12494 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \ 12495 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 12496 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 12497 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 12498 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 12499 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 12500 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 12501 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 12502 12503 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3 12504 12505 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3 12506 12507 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3 12508 12509 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3 12510 12511 #define HTT_RX_MON_FILTER_TLV_FLAGS \ 12512 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 12513 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 12514 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 12515 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 12516 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 12517 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 12518 12519 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \ 12520 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 12521 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 12522 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 12523 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 12524 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 12525 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 12526 12527 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \ 12528 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 12529 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 12530 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 12531 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 12532 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 12533 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 12534 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 12535 HTT_RX_FILTER_TLV_FLAGS_ATTENTION) 12536 12537 struct htt_rx_ring_selection_cfg_cmd { 12538 uint32_t info0; 12539 uint32_t info1; 12540 uint32_t pkt_type_en_flags0; 12541 uint32_t pkt_type_en_flags1; 12542 uint32_t pkt_type_en_flags2; 12543 uint32_t pkt_type_en_flags3; 12544 uint32_t rx_filter_tlv; 12545 } __packed; 12546 12547 struct htt_rx_ring_tlv_filter { 12548 uint32_t rx_filter; /* see htt_rx_filter_tlv_flags */ 12549 uint32_t pkt_filter_flags0; /* MGMT */ 12550 uint32_t pkt_filter_flags1; /* MGMT */ 12551 uint32_t pkt_filter_flags2; /* CTRL */ 12552 uint32_t pkt_filter_flags3; /* DATA */ 12553 }; 12554 12555 #define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 12556 #define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 12557 12558 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ENABLE BIT(0) 12559 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ZERO_MPDUS_END BIT(1) 12560 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_NON_ZERO_MPDUS_END BIT(2) 12561 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_RELEASE_RING GENMASK(10, 3) 12562 12563 /* Enumeration for full monitor mode destination ring select 12564 * 0 - REO destination ring select 12565 * 1 - FW destination ring select 12566 * 2 - SW destination ring select 12567 * 3 - Release destination ring select 12568 */ 12569 enum htt_rx_full_mon_release_ring { 12570 HTT_RX_MON_RING_REO, 12571 HTT_RX_MON_RING_FW, 12572 HTT_RX_MON_RING_SW, 12573 HTT_RX_MON_RING_RELEASE, 12574 }; 12575 12576 struct htt_rx_full_monitor_mode_cfg_cmd { 12577 uint32_t info0; 12578 uint32_t cfg; 12579 } __packed; 12580 12581 /* HTT message target->host */ 12582 12583 enum htt_t2h_msg_type { 12584 HTT_T2H_MSG_TYPE_VERSION_CONF, 12585 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 12586 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 12587 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 12588 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 12589 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 12590 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e, 12591 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f, 12592 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d, 12593 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, 12594 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24, 12595 }; 12596 12597 #define HTT_TARGET_VERSION_MAJOR 3 12598 12599 #define HTT_T2H_MSG_TYPE GENMASK(7, 0) 12600 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8) 12601 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16) 12602 12603 struct htt_t2h_version_conf_msg { 12604 uint32_t version; 12605 } __packed; 12606 12607 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8) 12608 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16) 12609 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0) 12610 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16) 12611 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0) 12612 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16) 12613 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16 12614 12615 struct htt_t2h_peer_map_event { 12616 uint32_t info; 12617 uint32_t mac_addr_l32; 12618 uint32_t info1; 12619 uint32_t info2; 12620 } __packed; 12621 12622 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID 12623 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID 12624 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \ 12625 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 12626 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M 12627 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 12628 12629 struct htt_t2h_peer_unmap_event { 12630 uint32_t info; 12631 uint32_t mac_addr_l32; 12632 uint32_t info1; 12633 } __packed; 12634 12635 struct htt_resp_msg { 12636 union { 12637 struct htt_t2h_version_conf_msg version_msg; 12638 struct htt_t2h_peer_map_event peer_map_ev; 12639 struct htt_t2h_peer_unmap_event peer_unmap_ev; 12640 }; 12641 } __packed; 12642 12643 #define HTT_BACKPRESSURE_EVENT_PDEV_ID_M GENMASK(15, 8) 12644 #define HTT_BACKPRESSURE_EVENT_RING_TYPE_M GENMASK(23, 16) 12645 #define HTT_BACKPRESSURE_EVENT_RING_ID_M GENMASK(31, 24) 12646 12647 #define HTT_BACKPRESSURE_EVENT_HP_M GENMASK(15, 0) 12648 #define HTT_BACKPRESSURE_EVENT_TP_M GENMASK(31, 16) 12649 12650 #define HTT_BACKPRESSURE_UMAC_RING_TYPE 0 12651 #define HTT_BACKPRESSURE_LMAC_RING_TYPE 1 12652 12653 enum htt_backpressure_umac_ringid { 12654 HTT_SW_RING_IDX_REO_REO2SW1_RING, 12655 HTT_SW_RING_IDX_REO_REO2SW2_RING, 12656 HTT_SW_RING_IDX_REO_REO2SW3_RING, 12657 HTT_SW_RING_IDX_REO_REO2SW4_RING, 12658 HTT_SW_RING_IDX_REO_WBM2REO_LINK_RING, 12659 HTT_SW_RING_IDX_REO_REO2TCL_RING, 12660 HTT_SW_RING_IDX_REO_REO2FW_RING, 12661 HTT_SW_RING_IDX_REO_REO_RELEASE_RING, 12662 HTT_SW_RING_IDX_WBM_PPE_RELEASE_RING, 12663 HTT_SW_RING_IDX_TCL_TCL2TQM_RING, 12664 HTT_SW_RING_IDX_WBM_TQM_RELEASE_RING, 12665 HTT_SW_RING_IDX_WBM_REO_RELEASE_RING, 12666 HTT_SW_RING_IDX_WBM_WBM2SW0_RELEASE_RING, 12667 HTT_SW_RING_IDX_WBM_WBM2SW1_RELEASE_RING, 12668 HTT_SW_RING_IDX_WBM_WBM2SW2_RELEASE_RING, 12669 HTT_SW_RING_IDX_WBM_WBM2SW3_RELEASE_RING, 12670 HTT_SW_RING_IDX_REO_REO_CMD_RING, 12671 HTT_SW_RING_IDX_REO_REO_STATUS_RING, 12672 HTT_SW_UMAC_RING_IDX_MAX, 12673 }; 12674 12675 enum htt_backpressure_lmac_ringid { 12676 HTT_SW_RING_IDX_FW2RXDMA_BUF_RING, 12677 HTT_SW_RING_IDX_FW2RXDMA_STATUS_RING, 12678 HTT_SW_RING_IDX_FW2RXDMA_LINK_RING, 12679 HTT_SW_RING_IDX_SW2RXDMA_BUF_RING, 12680 HTT_SW_RING_IDX_WBM2RXDMA_LINK_RING, 12681 HTT_SW_RING_IDX_RXDMA2FW_RING, 12682 HTT_SW_RING_IDX_RXDMA2SW_RING, 12683 HTT_SW_RING_IDX_RXDMA2RELEASE_RING, 12684 HTT_SW_RING_IDX_RXDMA2REO_RING, 12685 HTT_SW_RING_IDX_MONITOR_STATUS_RING, 12686 HTT_SW_RING_IDX_MONITOR_BUF_RING, 12687 HTT_SW_RING_IDX_MONITOR_DESC_RING, 12688 HTT_SW_RING_IDX_MONITOR_DEST_RING, 12689 HTT_SW_LMAC_RING_IDX_MAX, 12690 }; 12691 12692 /* ppdu stats 12693 * 12694 * @details 12695 * The following field definitions describe the format of the HTT target 12696 * to host ppdu stats indication message. 12697 * 12698 * 12699 * |31 16|15 12|11 10|9 8|7 0 | 12700 * |----------------------------------------------------------------------| 12701 * | payload_size | rsvd |pdev_id|mac_id | msg type | 12702 * |----------------------------------------------------------------------| 12703 * | ppdu_id | 12704 * |----------------------------------------------------------------------| 12705 * | Timestamp in us | 12706 * |----------------------------------------------------------------------| 12707 * | reserved | 12708 * |----------------------------------------------------------------------| 12709 * | type-specific stats info | 12710 * | (see htt_ppdu_stats.h) | 12711 * |----------------------------------------------------------------------| 12712 * Header fields: 12713 * - MSG_TYPE 12714 * Bits 7:0 12715 * Purpose: Identifies this is a PPDU STATS indication 12716 * message. 12717 * Value: 0x1d 12718 * - mac_id 12719 * Bits 9:8 12720 * Purpose: mac_id of this ppdu_id 12721 * Value: 0-3 12722 * - pdev_id 12723 * Bits 11:10 12724 * Purpose: pdev_id of this ppdu_id 12725 * Value: 0-3 12726 * 0 (for rings at SOC level), 12727 * 1/2/3 PDEV -> 0/1/2 12728 * - payload_size 12729 * Bits 31:16 12730 * Purpose: total tlv size 12731 * Value: payload_size in bytes 12732 */ 12733 12734 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10) 12735 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16) 12736 12737 struct ath11k_htt_ppdu_stats_msg { 12738 uint32_t info; 12739 uint32_t ppdu_id; 12740 uint32_t timestamp; 12741 uint32_t rsvd; 12742 uint8_t data[]; 12743 } __packed; 12744 12745 struct htt_tlv { 12746 uint32_t header; 12747 uint8_t *value; 12748 } __packed; 12749 12750 #define HTT_TLV_TAG GENMASK(11, 0) 12751 #define HTT_TLV_LEN GENMASK(23, 12) 12752 12753 enum HTT_PPDU_STATS_BW { 12754 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0, 12755 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1, 12756 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2, 12757 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3, 12758 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4, 12759 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */ 12760 HTT_PPDU_STATS_BANDWIDTH_DYN = 6, 12761 }; 12762 12763 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0) 12764 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8) 12765 /* bw - HTT_PPDU_STATS_BW */ 12766 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16) 12767 12768 struct htt_ppdu_stats_common { 12769 uint32_t ppdu_id; 12770 uint16_t sched_cmdid; 12771 uint8_t ring_id; 12772 uint8_t num_users; 12773 uint32_t flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/ 12774 uint32_t chain_mask; 12775 uint32_t fes_duration_us; /* frame exchange sequence */ 12776 uint32_t ppdu_sch_eval_start_tstmp_us; 12777 uint32_t ppdu_sch_end_tstmp_us; 12778 uint32_t ppdu_start_tstmp_us; 12779 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted 12780 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted 12781 */ 12782 uint16_t phy_mode; 12783 uint16_t bw_mhz; 12784 } __packed; 12785 12786 enum htt_ppdu_stats_gi { 12787 HTT_PPDU_STATS_SGI_0_8_US, 12788 HTT_PPDU_STATS_SGI_0_4_US, 12789 HTT_PPDU_STATS_SGI_1_6_US, 12790 HTT_PPDU_STATS_SGI_3_2_US, 12791 }; 12792 12793 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0) 12794 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4) 12795 12796 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0) 12797 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1) 12798 12799 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0) 12800 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2) 12801 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3) 12802 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4) 12803 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8) 12804 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12) 12805 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16) 12806 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20) 12807 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24) 12808 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28) 12809 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29) 12810 12811 #define HTT_USR_RATE_PREAMBLE(_val) \ 12812 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M, _val) 12813 #define HTT_USR_RATE_BW(_val) \ 12814 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M, _val) 12815 #define HTT_USR_RATE_NSS(_val) \ 12816 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M, _val) 12817 #define HTT_USR_RATE_MCS(_val) \ 12818 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M, _val) 12819 #define HTT_USR_RATE_GI(_val) \ 12820 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M, _val) 12821 #define HTT_USR_RATE_DCM(_val) \ 12822 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M, _val) 12823 12824 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0) 12825 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2) 12826 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3) 12827 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4) 12828 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8) 12829 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12) 12830 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16) 12831 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20) 12832 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24) 12833 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28) 12834 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29) 12835 12836 struct htt_ppdu_stats_user_rate { 12837 uint8_t tid_num; 12838 uint8_t reserved0; 12839 uint16_t sw_peer_id; 12840 uint32_t info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/ 12841 uint16_t ru_end; 12842 uint16_t ru_start; 12843 uint16_t resp_ru_end; 12844 uint16_t resp_ru_start; 12845 uint32_t info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */ 12846 uint32_t rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */ 12847 /* Note: resp_rate_info is only valid for if resp_type is UL */ 12848 uint32_t resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */ 12849 } __packed; 12850 12851 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0) 12852 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8) 12853 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9) 12854 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11) 12855 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14) 12856 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16) 12857 12858 #define HTT_TX_INFO_IS_AMSDU(_flags) \ 12859 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M, _flags) 12860 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \ 12861 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M, _flags) 12862 #define HTT_TX_INFO_RATECODE(_flags) \ 12863 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M, _flags) 12864 #define HTT_TX_INFO_PEERID(_flags) \ 12865 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M, _flags) 12866 12867 struct htt_tx_ppdu_stats_info { 12868 struct htt_tlv tlv_hdr; 12869 uint32_t tx_success_bytes; 12870 uint32_t tx_retry_bytes; 12871 uint32_t tx_failed_bytes; 12872 uint32_t flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */ 12873 uint16_t tx_success_msdus; 12874 uint16_t tx_retry_msdus; 12875 uint16_t tx_failed_msdus; 12876 uint16_t tx_duration; /* united in us */ 12877 } __packed; 12878 12879 enum htt_ppdu_stats_usr_compln_status { 12880 HTT_PPDU_STATS_USER_STATUS_OK, 12881 HTT_PPDU_STATS_USER_STATUS_FILTERED, 12882 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT, 12883 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH, 12884 HTT_PPDU_STATS_USER_STATUS_ABORT, 12885 }; 12886 12887 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0) 12888 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4) 12889 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8) 12890 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9) 12891 12892 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \ 12893 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M, _val) 12894 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \ 12895 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M, _val) 12896 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \ 12897 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M, _val) 12898 12899 struct htt_ppdu_stats_usr_cmpltn_cmn { 12900 uint8_t status; 12901 uint8_t tid_num; 12902 uint16_t sw_peer_id; 12903 /* RSSI value of last ack packet (units = dB above noise floor) */ 12904 uint32_t ack_rssi; 12905 uint16_t mpdu_tried; 12906 uint16_t mpdu_success; 12907 uint32_t flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/ 12908 } __packed; 12909 12910 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0) 12911 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9) 12912 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25) 12913 12914 #define HTT_PPDU_STATS_NON_QOS_TID 16 12915 12916 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status { 12917 uint32_t ppdu_id; 12918 uint16_t sw_peer_id; 12919 uint16_t reserved0; 12920 uint32_t info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */ 12921 uint16_t current_seq; 12922 uint16_t start_seq; 12923 uint32_t success_bytes; 12924 } __packed; 12925 12926 struct htt_ppdu_stats_usr_cmn_array { 12927 struct htt_tlv tlv_hdr; 12928 uint32_t num_ppdu_stats; 12929 /* tx_ppdu_stats_info is filled by multiple struct htt_tx_ppdu_stats_info 12930 * elements. 12931 * tx_ppdu_stats_info is variable length, with length = 12932 * number_of_ppdu_stats * sizeof (struct htt_tx_ppdu_stats_info) 12933 */ 12934 struct htt_tx_ppdu_stats_info tx_ppdu_info[]; 12935 } __packed; 12936 12937 struct htt_ppdu_user_stats { 12938 uint16_t peer_id; 12939 uint32_t tlv_flags; 12940 bool is_valid_peer_id; 12941 struct htt_ppdu_stats_user_rate rate; 12942 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn; 12943 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba; 12944 }; 12945 12946 #define HTT_PPDU_STATS_MAX_USERS 8 12947 #define HTT_PPDU_DESC_MAX_DEPTH 16 12948 12949 struct htt_ppdu_stats { 12950 struct htt_ppdu_stats_common common; 12951 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS]; 12952 }; 12953 12954 struct htt_ppdu_stats_info { 12955 uint32_t ppdu_id; 12956 struct htt_ppdu_stats ppdu_stats; 12957 #if 0 12958 struct list_head list; 12959 #endif 12960 }; 12961 12962 /* @brief target -> host packet log message 12963 * 12964 * @details 12965 * The following field definitions describe the format of the packet log 12966 * message sent from the target to the host. 12967 * The message consists of a 4-octet header,followed by a variable number 12968 * of 32-bit character values. 12969 * 12970 * |31 16|15 12|11 10|9 8|7 0| 12971 * |------------------------------------------------------------------| 12972 * | payload_size | rsvd |pdev_id|mac_id| msg type | 12973 * |------------------------------------------------------------------| 12974 * | payload | 12975 * |------------------------------------------------------------------| 12976 * - MSG_TYPE 12977 * Bits 7:0 12978 * Purpose: identifies this as a pktlog message 12979 * Value: HTT_T2H_MSG_TYPE_PKTLOG 12980 * - mac_id 12981 * Bits 9:8 12982 * Purpose: identifies which MAC/PHY instance generated this pktlog info 12983 * Value: 0-3 12984 * - pdev_id 12985 * Bits 11:10 12986 * Purpose: pdev_id 12987 * Value: 0-3 12988 * 0 (for rings at SOC level), 12989 * 1/2/3 PDEV -> 0/1/2 12990 * - payload_size 12991 * Bits 31:16 12992 * Purpose: explicitly specify the payload size 12993 * Value: payload size in bytes (payload size is a multiple of 4 bytes) 12994 */ 12995 struct htt_pktlog_msg { 12996 uint32_t hdr; 12997 uint8_t payload[]; 12998 }; 12999 13000 /* @brief host -> target FW extended statistics retrieve 13001 * 13002 * @details 13003 * The following field definitions describe the format of the HTT host 13004 * to target FW extended stats retrieve message. 13005 * The message specifies the type of stats the host wants to retrieve. 13006 * 13007 * |31 24|23 16|15 8|7 0| 13008 * |-----------------------------------------------------------| 13009 * | reserved | stats type | pdev_mask | msg type | 13010 * |-----------------------------------------------------------| 13011 * | config param [0] | 13012 * |-----------------------------------------------------------| 13013 * | config param [1] | 13014 * |-----------------------------------------------------------| 13015 * | config param [2] | 13016 * |-----------------------------------------------------------| 13017 * | config param [3] | 13018 * |-----------------------------------------------------------| 13019 * | reserved | 13020 * |-----------------------------------------------------------| 13021 * | cookie LSBs | 13022 * |-----------------------------------------------------------| 13023 * | cookie MSBs | 13024 * |-----------------------------------------------------------| 13025 * Header fields: 13026 * - MSG_TYPE 13027 * Bits 7:0 13028 * Purpose: identifies this is a extended stats upload request message 13029 * Value: 0x10 13030 * - PDEV_MASK 13031 * Bits 8:15 13032 * Purpose: identifies the mask of PDEVs to retrieve stats from 13033 * Value: This is a overloaded field, refer to usage and interpretation of 13034 * PDEV in interface document. 13035 * Bit 8 : Reserved for SOC stats 13036 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 13037 * Indicates MACID_MASK in DBS 13038 * - STATS_TYPE 13039 * Bits 23:16 13040 * Purpose: identifies which FW statistics to upload 13041 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 13042 * - Reserved 13043 * Bits 31:24 13044 * - CONFIG_PARAM [0] 13045 * Bits 31:0 13046 * Purpose: give an opaque configuration value to the specified stats type 13047 * Value: stats-type specific configuration value 13048 * Refer to htt_stats.h for interpretation for each stats sub_type 13049 * - CONFIG_PARAM [1] 13050 * Bits 31:0 13051 * Purpose: give an opaque configuration value to the specified stats type 13052 * Value: stats-type specific configuration value 13053 * Refer to htt_stats.h for interpretation for each stats sub_type 13054 * - CONFIG_PARAM [2] 13055 * Bits 31:0 13056 * Purpose: give an opaque configuration value to the specified stats type 13057 * Value: stats-type specific configuration value 13058 * Refer to htt_stats.h for interpretation for each stats sub_type 13059 * - CONFIG_PARAM [3] 13060 * Bits 31:0 13061 * Purpose: give an opaque configuration value to the specified stats type 13062 * Value: stats-type specific configuration value 13063 * Refer to htt_stats.h for interpretation for each stats sub_type 13064 * - Reserved [31:0] for future use. 13065 * - COOKIE_LSBS 13066 * Bits 31:0 13067 * Purpose: Provide a mechanism to match a target->host stats confirmation 13068 * message with its preceding host->target stats request message. 13069 * Value: LSBs of the opaque cookie specified by the host-side requestor 13070 * - COOKIE_MSBS 13071 * Bits 31:0 13072 * Purpose: Provide a mechanism to match a target->host stats confirmation 13073 * message with its preceding host->target stats request message. 13074 * Value: MSBs of the opaque cookie specified by the host-side requestor 13075 */ 13076 13077 struct htt_ext_stats_cfg_hdr { 13078 uint8_t msg_type; 13079 uint8_t pdev_mask; 13080 uint8_t stats_type; 13081 uint8_t reserved; 13082 } __packed; 13083 13084 struct htt_ext_stats_cfg_cmd { 13085 struct htt_ext_stats_cfg_hdr hdr; 13086 uint32_t cfg_param0; 13087 uint32_t cfg_param1; 13088 uint32_t cfg_param2; 13089 uint32_t cfg_param3; 13090 uint32_t reserved; 13091 uint32_t cookie_lsb; 13092 uint32_t cookie_msb; 13093 } __packed; 13094 13095 /* htt stats config default params */ 13096 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0 13097 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff 13098 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff 13099 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff 13100 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff 13101 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff 13102 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00 13103 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00 13104 13105 /* HTT_DBG_EXT_STATS_PEER_INFO 13106 * PARAMS: 13107 * @config_param0: 13108 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request 13109 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t 13110 * [Bit31 : Bit16] sw_peer_id 13111 * @config_param1: 13112 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum) 13113 * 0 bit htt_peer_stats_cmn_tlv 13114 * 1 bit htt_peer_details_tlv 13115 * 2 bit htt_tx_peer_rate_stats_tlv 13116 * 3 bit htt_rx_peer_rate_stats_tlv 13117 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv 13118 * 5 bit htt_rx_tid_stats_tlv 13119 * 6 bit htt_msdu_flow_stats_tlv 13120 * @config_param2: [Bit31 : Bit0] mac_addr31to0 13121 * @config_param3: [Bit15 : Bit0] mac_addr47to32 13122 * [Bit31 : Bit16] reserved 13123 */ 13124 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0) 13125 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f 13126 13127 /* Used to set different configs to the specified stats type.*/ 13128 struct htt_ext_stats_cfg_params { 13129 uint32_t cfg0; 13130 uint32_t cfg1; 13131 uint32_t cfg2; 13132 uint32_t cfg3; 13133 }; 13134 13135 /* @brief target -> host extended statistics upload 13136 * 13137 * @details 13138 * The following field definitions describe the format of the HTT target 13139 * to host stats upload confirmation message. 13140 * The message contains a cookie echoed from the HTT host->target stats 13141 * upload request, which identifies which request the confirmation is 13142 * for, and a single stats can span over multiple HTT stats indication 13143 * due to the HTT message size limitation so every HTT ext stats indication 13144 * will have tag-length-value stats information elements. 13145 * The tag-length header for each HTT stats IND message also includes a 13146 * status field, to indicate whether the request for the stat type in 13147 * question was fully met, partially met, unable to be met, or invalid 13148 * (if the stat type in question is disabled in the target). 13149 * A Done bit 1's indicate the end of the of stats info elements. 13150 * 13151 * 13152 * |31 16|15 12|11|10 8|7 5|4 0| 13153 * |--------------------------------------------------------------| 13154 * | reserved | msg type | 13155 * |--------------------------------------------------------------| 13156 * | cookie LSBs | 13157 * |--------------------------------------------------------------| 13158 * | cookie MSBs | 13159 * |--------------------------------------------------------------| 13160 * | stats entry length | rsvd | D| S | stat type | 13161 * |--------------------------------------------------------------| 13162 * | type-specific stats info | 13163 * | (see htt_stats.h) | 13164 * |--------------------------------------------------------------| 13165 * Header fields: 13166 * - MSG_TYPE 13167 * Bits 7:0 13168 * Purpose: Identifies this is a extended statistics upload confirmation 13169 * message. 13170 * Value: 0x1c 13171 * - COOKIE_LSBS 13172 * Bits 31:0 13173 * Purpose: Provide a mechanism to match a target->host stats confirmation 13174 * message with its preceding host->target stats request message. 13175 * Value: LSBs of the opaque cookie specified by the host-side requestor 13176 * - COOKIE_MSBS 13177 * Bits 31:0 13178 * Purpose: Provide a mechanism to match a target->host stats confirmation 13179 * message with its preceding host->target stats request message. 13180 * Value: MSBs of the opaque cookie specified by the host-side requestor 13181 * 13182 * Stats Information Element tag-length header fields: 13183 * - STAT_TYPE 13184 * Bits 7:0 13185 * Purpose: identifies the type of statistics info held in the 13186 * following information element 13187 * Value: htt_dbg_ext_stats_type 13188 * - STATUS 13189 * Bits 10:8 13190 * Purpose: indicate whether the requested stats are present 13191 * Value: htt_dbg_ext_stats_status 13192 * - DONE 13193 * Bits 11 13194 * Purpose: 13195 * Indicates the completion of the stats entry, this will be the last 13196 * stats conf HTT segment for the requested stats type. 13197 * Value: 13198 * 0 -> the stats retrieval is ongoing 13199 * 1 -> the stats retrieval is complete 13200 * - LENGTH 13201 * Bits 31:16 13202 * Purpose: indicate the stats information size 13203 * Value: This field specifies the number of bytes of stats information 13204 * that follows the element tag-length header. 13205 * It is expected but not required that this length is a multiple of 13206 * 4 bytes. 13207 */ 13208 13209 #define HTT_T2H_EXT_STATS_INFO1_DONE BIT(11) 13210 #define HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16) 13211 13212 struct ath11k_htt_extd_stats_msg { 13213 uint32_t info0; 13214 uint64_t cookie; 13215 uint32_t info1; 13216 uint8_t data[]; 13217 } __packed; 13218 13219 #define HTT_MAC_ADDR_L32_0 GENMASK(7, 0) 13220 #define HTT_MAC_ADDR_L32_1 GENMASK(15, 8) 13221 #define HTT_MAC_ADDR_L32_2 GENMASK(23, 16) 13222 #define HTT_MAC_ADDR_L32_3 GENMASK(31, 24) 13223 #define HTT_MAC_ADDR_H16_0 GENMASK(7, 0) 13224 #define HTT_MAC_ADDR_H16_1 GENMASK(15, 8) 13225