1 /* $OpenBSD: r92creg.h,v 1.25 2020/06/11 00:56:12 jmatthew Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define R92C_MAX_CHAINS 2 21 #define R92C_MAX_TX_PWR 0x3f 22 #define R92C_H2C_NBOX 4 23 24 /* 25 * MAC registers. 26 */ 27 /* System Configuration. */ 28 #define R92C_SYS_ISO_CTRL 0x000 29 #define R92C_SYS_FUNC_EN 0x002 30 #define R92C_APS_FSMCO 0x004 31 #define R92C_SYS_CLKR 0x008 32 #define R92C_AFE_MISC 0x010 33 #define R92C_SPS0_CTRL 0x011 34 #define R92C_SYS_SWR_CTRL2 0x014 35 #define R92C_SPS_OCP_CFG 0x018 36 #define R92C_RSV_CTRL 0x01c 37 #define R92C_RF_CTRL 0x01f 38 #define R92C_LDOA15_CTRL 0x020 39 #define R92C_LDOV12D_CTRL 0x021 40 #define R92C_LDOHCI12_CTRL 0x022 41 #define R92C_LPLDO_CTRL 0x023 42 #define R92C_AFE_XTAL_CTRL 0x024 43 #define R92C_AFE_PLL_CTRL 0x028 44 #define R92C_AFE_CTRL3 0x02c 45 #define R92C_EFUSE_CTRL 0x030 46 #define R92C_EFUSE_TEST 0x034 47 #define R92C_PWR_DATA 0x038 48 #define R92C_CAL_TIMER 0x03c 49 #define R92C_ACLK_MON 0x03e 50 #define R92C_GPIO_MUXCFG 0x040 51 #define R92C_GPIO_IO_SEL 0x042 52 #define R92C_MAC_PINMUX_CFG 0x043 53 #define R92C_GPIO_PIN_CTRL 0x044 54 #define R92C_GPIO_INTM 0x048 55 #define R92C_LEDCFG0 0x04c 56 #define R92C_LEDCFG1 0x04d 57 #define R92C_LEDCFG2 0x04e 58 #define R92C_LEDCFG3 0x04f 59 #define R92C_FSIMR 0x050 60 #define R92C_FSISR 0x054 61 #define R92C_HSIMR 0x058 62 #define R92C_HSISR 0x05c 63 #define R92C_AFE_XTAL_CTRL_EXT 0x078 64 #define R88E_XCK_OUT_CTRL 0x07c 65 #define R92E_LDO_SWR_CTRL 0x07c 66 #define R92C_MCUFWDL 0x080 67 #define R92C_HMEBOX_EXT(idx) (0x088 + (idx) * 2) 68 #define R88E_HIMR 0x0b0 69 #define R88E_HISR 0x0b4 70 #define R88E_HIMRE 0x0b8 71 #define R88E_HISRE 0x0bc 72 #define R92C_EFUSE_ACCESS 0x0cf 73 #define R92C_BIST_SCAN 0x0d0 74 #define R92C_BIST_RPT 0x0d4 75 #define R92C_BIST_ROM_RPT 0x0d8 76 #define R92C_USB_SIE_INTF 0x0e0 77 #define R92C_PCIE_MIO_INTF 0x0e4 78 #define R92C_PCIE_MIO_INTD 0x0e8 79 #define R92C_HPON_FSM 0x0ec 80 #define R92C_SYS_CFG 0x0f0 81 /* MAC General Configuration. */ 82 #define R92C_CR 0x100 83 #define R92C_MSR 0x102 84 #define R92C_PBP 0x104 85 #define R92C_TRXDMA_CTRL 0x10c 86 #define R92C_TRXFF_BNDY 0x114 87 #define R92C_TRXFF_STATUS 0x118 88 #define R92C_RXFF_PTR 0x11c 89 #define R92C_HIMR 0x120 90 #define R92C_HISR 0x124 91 #define R92C_HIMRE 0x128 92 #define R92C_HISRE 0x12c 93 #define R92C_CPWM 0x12f 94 #define R92C_FWIMR 0x130 95 #define R92C_FWISR 0x134 96 #define R92C_PKTBUF_DBG_CTRL 0x140 97 #define R92C_PKTBUF_DBG_DATA_L 0x144 98 #define R92C_PKTBUF_DBG_DATA_H 0x148 99 #define R92C_TC0_CTRL(i) (0x150 + (i) * 4) 100 #define R92C_TCUNIT_BASE 0x164 101 #define R92C_MBIST_START 0x174 102 #define R92C_MBIST_DONE 0x178 103 #define R92C_MBIST_FAIL 0x17c 104 #define R88E_32K_CTRL 0x194 105 #define R92C_C2HEVT_MSG 0x1a0 106 #define R92C_C2HEVT_CLEAR 0x1af 107 #define R92C_C2HEVT_MSG_TEST 0x1b8 108 #define R92C_MCUTST_1 0x1c0 109 #define R92C_FMETHR 0x1c8 110 #define R92C_HMETFR 0x1cc 111 #define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4) 112 #define R92C_LLT_INIT 0x1e0 113 #define R92C_BB_ACCESS_CTRL 0x1e8 114 #define R92C_BB_ACCESS_DATA 0x1ec 115 #define R88E_HMEBOX_EXT(idx) (0x1f0 + (idx) * 4) 116 /* Tx DMA Configuration. */ 117 #define R92C_RQPN 0x200 118 #define R92C_FIFOPAGE 0x204 119 #define R92C_TDECTRL 0x208 120 #define R92C_TXDMA_OFFSET_CHK 0x20c 121 #define R92C_TXDMA_STATUS 0x210 122 #define R92C_RQPN_NPQ 0x214 123 #define R92E_AUTO_LLT 0x224 124 #define R92E_DWBCN1_CTRL 0x228 125 /* Rx DMA Configuration. */ 126 #define R92C_RXDMA_AGG_PG_TH 0x280 127 #define R92C_RXPKT_NUM 0x284 128 #define R88E_RXDMA_CTRL 0x286 129 #define R92C_RXDMA_STATUS 0x288 130 #define R92E_RXDMA_PRO 0x290 131 132 #define R92C_PCIE_CTRL_REG 0x300 133 #define R92C_INT_MIG 0x304 134 #define R92C_BCNQ_DESA 0x308 135 #define R92C_HQ_DESA 0x310 136 #define R92C_MGQ_DESA 0x318 137 #define R92C_VOQ_DESA 0x320 138 #define R92C_VIQ_DESA 0x328 139 #define R92C_BEQ_DESA 0x330 140 #define R92C_BKQ_DESA 0x338 141 #define R92C_RX_DESA 0x340 142 #define R92C_DBI 0x348 143 #define R92C_MDIO 0x354 144 #define R92C_DBG_SEL 0x360 145 #define R92C_PCIE_HRPWM 0x361 146 #define R92C_PCIE_HCPWM 0x363 147 #define R92C_UART_CTRL 0x364 148 #define R92C_UART_TX_DES 0x370 149 #define R92C_UART_RX_DES 0x378 150 151 #define R92C_VOQ_INFORMATION 0x0400 152 #define R92C_VIQ_INFORMATION 0x0404 153 #define R92C_BEQ_INFORMATION 0x0408 154 #define R92C_BKQ_INFORMATION 0x040C 155 #define R92C_MGQ_INFORMATION 0x0410 156 #define R92C_HGQ_INFORMATION 0x0414 157 #define R92C_BCNQ_INFORMATION 0x0418 158 #define R92C_CPU_MGQ_INFORMATION 0x041C 159 160 /* Protocol Configuration. */ 161 #define R92C_FWHW_TXQ_CTRL 0x420 162 #define R92C_HWSEQ_CTRL 0x423 163 #define R92C_TXPKTBUF_BCNQ_BDNY 0x424 164 #define R92C_TXPKTBUF_MGQ_BDNY 0x425 165 #define R92C_SPEC_SIFS 0x428 166 #define R92C_RL 0x42a 167 #define R92C_DARFRC 0x430 168 #define R92C_RARFRC 0x438 169 #define R92C_RRSR 0x440 170 #define R92C_ARFR(i) (0x444 + (i) * 4) 171 #define R92C_AGGLEN_LMT 0x458 172 #define R92C_AMPDU_MIN_SPACE 0x45c 173 #define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d 174 #define R92C_FAST_EDCA_CTRL 0x460 175 #define R92C_RD_RESP_PKT_TH 0x463 176 #define R92C_INIRTS_RATE_SEL 0x480 177 #define R92E_DATA_SC 0x483 178 #define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid)) 179 #define R92C_QUEUE_CTRL 0x4c6 180 #define R92C_MAX_AGGR_NUM 0x4ca 181 #define R92C_BAR_MODE_CTRL 0x4cc 182 #define R88E_TX_RPT_CTRL 0x4ec 183 #define R88E_TX_RPT_TIME 0x4f0 184 /* EDCA Configuration. */ 185 #define R92C_EDCA_VO_PARAM 0x500 186 #define R92C_EDCA_VI_PARAM 0x504 187 #define R92C_EDCA_BE_PARAM 0x508 188 #define R92C_EDCA_BK_PARAM 0x50c 189 #define R92C_BCNTCFG 0x510 190 #define R92C_PIFS 0x512 191 #define R92C_RDG_PIFS 0x513 192 #define R92C_SIFS_CCK 0x514 193 #define R92C_SIFS_OFDM 0x516 194 #define R92C_AGGR_BREAK_TIME 0x51a 195 #define R92C_SLOT 0x51b 196 #define R92C_TX_PTCL_CTRL 0x520 197 #define R92C_TXPAUSE 0x522 198 #define R92C_DIS_TXREQ_CLR 0x523 199 #define R92C_RD_CTRL 0x524 200 #define R92C_TBTT_PROHIBIT 0x540 201 #define R92C_RD_NAV_NXT 0x544 202 #define R92C_NAV_PROT_LEN 0x546 203 #define R92C_BCN_CTRL 0x550 204 #define R92C_BCN_CTRL1 0x551 205 #define R92C_MBID_NUM 0x552 206 #define R92C_DUAL_TSF_RST 0x553 207 #define R92C_BCN_INTERVAL 0x554 208 #define R92C_DRVERLYINT 0x558 209 #define R92C_BCNDMATIM 0x559 210 #define R92C_ATIMWND 0x55a 211 #define R92C_USTIME_TSF 0x55c 212 #define R92C_BCN_MAX_ERR 0x55d 213 #define R92C_RXTSF_OFFSET_CCK 0x55e 214 #define R92C_RXTSF_OFFSET_OFDM 0x55f 215 #define R92C_TSFTR 0x560 216 #define R92C_INIT_TSFTR 0x564 217 #define R92C_PSTIMER 0x580 218 #define R92C_TIMER0 0x584 219 #define R92C_TIMER1 0x588 220 #define R92C_ACMHWCTRL 0x5c0 221 #define R92C_ACMRSTCTRL 0x5c1 222 #define R92C_ACMAVG 0x5c2 223 #define R92C_VO_ADMTIME 0x5c4 224 #define R92C_VI_ADMTIME 0x5c6 225 #define R92C_BE_ADMTIME 0x5c8 226 #define R92C_EDCA_RANDOM_GEN 0x5cc 227 #define R92C_SCH_TXCMD 0x5d0 228 /* WMAC Configuration. */ 229 #define R92C_APSD_CTRL 0x600 230 #define R92C_BWOPMODE 0x603 231 #define R92C_TCR 0x604 232 #define R92C_RCR 0x608 233 #define R92C_RX_DRVINFO_SZ 0x60f 234 #define R92C_MACID 0x610 235 #define R92C_BSSID 0x618 236 #define R92C_MAR 0x620 237 #define R92C_MAC_SPEC_SIFS 0x63a 238 #define R92C_RESP_SIFS_CCK 0x63c 239 #define R92C_RESP_SIFS_OFDM 0x63e 240 #define R92C_ACKTO 0x640 241 #define R92C_NAV_UPPER 0x652 242 #define R92C_WMAC_TRXPTCL_CTL 0x668 243 #define R92C_CAMCMD 0x670 244 #define R92C_CAMWRITE 0x674 245 #define R92C_CAMREAD 0x678 246 #define R92C_CAMDBG 0x67c 247 #define R92C_SECCFG 0x680 248 #define R92C_RXFLTMAP0 0x6a0 249 #define R92C_RXFLTMAP1 0x6a2 250 #define R92C_RXFLTMAP2 0x6a4 251 252 #define R92C_CONFIG_ANT_A 0xb68 253 #define R92C_CONFIG_ANT_B 0xb6c 254 255 /* Bits for R92C_SYS_ISO_CTRL. */ 256 #define R92C_SYS_ISO_CTRL_MD2PP 0x0001 257 #define R92C_SYS_ISO_CTRL_UA2USB 0x0002 258 #define R92C_SYS_ISO_CTRL_UD2CORE 0x0004 259 #define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008 260 #define R92C_SYS_ISO_CTRL_PD2CORE 0x0010 261 #define R92C_SYS_ISO_CTRL_IP2MAC 0x0020 262 #define R92C_SYS_ISO_CTRL_DIOP 0x0040 263 #define R92C_SYS_ISO_CTRL_DIOE 0x0080 264 #define R92C_SYS_ISO_CTRL_EB2CORE 0x0100 265 #define R92C_SYS_ISO_CTRL_DIOR 0x0200 266 #define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000 267 #define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000 268 269 /* Bits for R92C_SYS_FUNC_EN. */ 270 #define R92C_SYS_FUNC_EN_BBRSTB 0x0001 271 #define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002 272 #define R92C_SYS_FUNC_EN_USBA 0x0004 273 #define R92C_SYS_FUNC_EN_UPLL 0x0008 274 #define R92C_SYS_FUNC_EN_USBD 0x0010 275 #define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020 276 #define R92C_SYS_FUNC_EN_PCIEA 0x0040 277 #define R92C_SYS_FUNC_EN_PPLL 0x0080 278 #define R92C_SYS_FUNC_EN_PCIED 0x0100 279 #define R92C_SYS_FUNC_EN_DIOE 0x0200 280 #define R92C_SYS_FUNC_EN_CPUEN 0x0400 281 #define R92C_SYS_FUNC_EN_DCORE 0x0800 282 #define R92C_SYS_FUNC_EN_ELDR 0x1000 283 #define R92C_SYS_FUNC_EN_DIO_RF 0x2000 284 #define R92C_SYS_FUNC_EN_HWPDN 0x4000 285 #define R92C_SYS_FUNC_EN_MREGEN 0x8000 286 287 /* Bits for R92C_APS_FSMCO. */ 288 #define R92C_APS_FSMCO_PFM_LDALL 0x00000001 289 #define R92C_APS_FSMCO_PFM_ALDN 0x00000002 290 #define R92C_APS_FSMCO_PFM_LDKP 0x00000004 291 #define R92C_APS_FSMCO_PFM_WOWL 0x00000008 292 #define R92C_APS_FSMCO_PDN_EN 0x00000010 293 #define R92C_APS_FSMCO_PDN_PL 0x00000020 294 #define R92C_APS_FSMCO_APFM_ONMAC 0x00000100 295 #define R92C_APS_FSMCO_APFM_OFF 0x00000200 296 #define R92C_APS_FSMCO_APFM_RSM 0x00000400 297 #define R92C_APS_FSMCO_AFSM_HSUS 0x00000800 298 #define R92C_APS_FSMCO_AFSM_PCIE 0x00001000 299 #define R92C_APS_FSMCO_APDM_MAC 0x00002000 300 #define R92C_APS_FSMCO_APDM_HOST 0x00004000 301 #define R92C_APS_FSMCO_APDM_HPDN 0x00008000 302 #define R92C_APS_FSMCO_RDY_MACON 0x00010000 303 #define R92C_APS_FSMCO_SUS_HOST 0x00020000 304 #define R92C_APS_FSMCO_ROP_ALD 0x00100000 305 #define R92C_APS_FSMCO_ROP_PWR 0x00200000 306 #define R92C_APS_FSMCO_ROP_SPS 0x00400000 307 #define R92C_APS_FSMCO_SOP_MRST 0x02000000 308 #define R92C_APS_FSMCO_SOP_FUSE 0x04000000 309 #define R92C_APS_FSMCO_SOP_ABG 0x08000000 310 #define R92C_APS_FSMCO_SOP_AMB 0x10000000 311 #define R92C_APS_FSMCO_SOP_RCK 0x20000000 312 #define R92C_APS_FSMCO_SOP_A8M 0x40000000 313 #define R92C_APS_FSMCO_XOP_BTCK 0x80000000 314 315 /* Bits for R92C_SYS_CLKR. */ 316 #define R92C_SYS_CLKR_ANAD16V_EN 0x00000001 317 #define R92C_SYS_CLKR_ANA8M 0x00000002 318 #define R92C_SYS_CLKR_MACSLP 0x00000010 319 #define R92C_SYS_CLKR_LOADER_EN 0x00000020 320 #define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080 321 #define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100 322 #define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200 323 #define R92C_SYS_CLKR_SEC_EN 0x00000400 324 #define R92C_SYS_CLKR_MAC_EN 0x00000800 325 #define R92C_SYS_CLKR_SYS_EN 0x00001000 326 #define R92C_SYS_CLKR_RING_EN 0x00002000 327 328 /* Bits for R92C_RSV_CTRL. */ 329 #define R92C_RSV_CTRL_WLOCK_ALL 0x0001 330 #define R92C_RSV_CTRL_WLOCK_00 0x0002 331 #define R92C_RSV_CTRL_WLOCK_04 0x0004 332 #define R92C_RSV_CTRL_WLOCK_08 0x0008 333 #define R92C_RSV_CTRL_WLOCK_40 0x0010 334 #define R92C_RSV_CTRL_R_DIS_PRST_0 0x0020 335 #define R92C_RSV_CTRL_R_DIS_PRST_1 0x0040 336 #define R92C_RSV_CTRL_LOCK_ALL_EN 0x0080 337 #define R88E_RSV_CTRL_MIO_EN 0x0100 338 #define R88E_RSV_CTRL_MCU_RST 0x0800 339 340 /* Bits for R92C_RF_CTRL. */ 341 #define R92C_RF_CTRL_EN 0x01 342 #define R92C_RF_CTRL_RSTB 0x02 343 #define R92C_RF_CTRL_SDMRSTB 0x04 344 345 /* Bits for R92C_LDOV12D_CTRL. */ 346 #define R92C_LDOV12D_CTRL_LDV12_EN 0x01 347 348 /* Bits for R92C_AFE_XTAL_CTRL. */ 349 #define R92C_AFE_XTAL_CTRL_ADDR_M 0x007ff800 350 #define R92C_AFE_XTAL_CTRL_ADDR_S 11 351 352 /* Bits for R88E_XCK_OUT_CTRL. */ 353 #define R88E_XCK_OUT_CTRL_EN 1 354 355 /* Bits for R92C_EFUSE_CTRL. */ 356 #define R92C_EFUSE_CTRL_DATA_M 0x000000ff 357 #define R92C_EFUSE_CTRL_DATA_S 0 358 #define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00 359 #define R92C_EFUSE_CTRL_ADDR_S 8 360 #define R92C_EFUSE_CTRL_VALID 0x80000000 361 362 /* Bits for R92C_GPIO_MUXCFG. */ 363 #define R92C_GPIO_MUXCFG_RFKILL 0x0008 364 #define R92C_GPIO_MUXCFG_ENBT 0x0020 365 #define R92C_GPIO_MUXCFG_ENSIC 0x1000 366 367 /* Bits for R92C_GPIO_IO_SEL. */ 368 #define R92C_GPIO_IO_SEL_RFKILL 0x0008 369 370 /* Bits for R92C_LEDCFG0. */ 371 #define R92C_LEDCFG0_DIS 0x08 372 373 /* Bits for R92C_LEDCFG1. */ 374 #define R92E_LEDSON 0x60 375 376 /* Bits for R92C_LEDCFG2. */ 377 #define R92C_LEDCFG2_EN 0x60 378 #define R92C_LEDCFG2_DIS 0x68 379 380 /* Bits for R92C_MCUFWDL. */ 381 #define R92C_MCUFWDL_EN 0x00000001 382 #define R92C_MCUFWDL_RDY 0x00000002 383 #define R92C_MCUFWDL_CHKSUM_RPT 0x00000004 384 #define R92C_MCUFWDL_MACINI_RDY 0x00000008 385 #define R92C_MCUFWDL_BBINI_RDY 0x00000010 386 #define R92C_MCUFWDL_RFINI_RDY 0x00000020 387 #define R92C_MCUFWDL_WINTINI_RDY 0x00000040 388 #define R92C_MCUFWDL_RAM_DL_SEL 0x00000080 /* 1: RAM, 0: ROM */ 389 #define R92C_MCUFWDL_PAGE_M 0x00070000 390 #define R92C_MCUFWDL_PAGE_S 16 391 #define R92C_MCUFWDL_ROM_DLEN 0x00080000 392 #define R92C_MCUFWDL_CPRST 0x00800000 393 394 /* Bits for R88E_HIMR. */ 395 #define R88E_HIMR_ROK 0x00000001 396 #define R88E_HIMR_RDU 0x00000002 397 #define R88E_HIMR_VODOK 0x00000004 398 #define R88E_HIMR_VIDOK 0x00000008 399 #define R88E_HIMR_BEDOK 0x00000010 400 #define R88E_HIMR_BKDOK 0x00000020 401 #define R88E_HIMR_MGNTDOK 0x00000040 402 #define R88E_HIMR_HIGHDOK 0x00000080 403 #define R88E_HIMR_CPWM 0x00000100 404 #define R88E_HIMR_CPWM2 0x00000200 405 #define R88E_HIMR_C2HCMD 0x00000400 406 #define R88E_HIMR_HISR1_IND_INT 0x00000800 407 #define R88E_HIMR_ATIMEND 0x00001000 408 #define R88E_HIMR_BCNDMAINT_E 0x00004000 409 #define R88E_HIMR_HSISR_IND_ON_INT 0x00008000 410 #define R88E_HIMR_BCNDOK0 0x00010000 411 #define R88E_HIMR_BCNDMAINT0 0x00100000 412 #define R88E_HIMR_TSF_BIT32_TOGGLE 0x01000000 413 #define R88E_HIMR_TBDOK 0x02000000 414 #define R88E_HIMR_TBDER 0x04000000 415 #define R88E_HIMR_GTINT3 0x08000000 416 #define R88E_HIMR_GTINT4 0x10000000 417 #define R88E_HIMR_PSTIMEOUT 0x20000000 418 #define R88E_HIMR_TXCCK 0x40000000 419 420 /* Bits for R88E_HIMRE.*/ 421 #define R88E_HIMRE_RXFOVW 0x00000100 422 #define R88E_HIMRE_TXFOVW 0x00000200 423 #define R88E_HIMRE_RXERR 0x00000400 424 #define R88E_HIMRE_TXERR 0x00000800 425 426 /* Bits for R88E_HSIMR */ 427 #define R88E_HSIMR_GPIO12_0_INT_EN 0x00000001 428 #define R88E_HSIMR_SPS_OCP_INT_EN 0x00000020 429 #define R88E_HSIMR_RON_INT_EN 0x00000040 430 #define R88E_HSIMR_PDN_INT_EN 0x00000080 431 #define R88E_HSIMR_GPIO9_INT_EN 0x02000000 432 433 /* Bits for R92C_EFUSE_ACCESS. */ 434 #define R92C_EFUSE_ACCESS_OFF 0x00 435 #define R92C_EFUSE_ACCESS_ON 0x69 436 437 /* Bits for R92C_HPON_FSM. */ 438 #define R92C_HPON_FSM_CHIP_BONDING_ID_S 22 439 #define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000 440 #define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1 441 442 /* Bits for R92C_SYS_CFG. */ 443 #define R92C_SYS_CFG_XCLK_VLD 0x00000001 444 #define R92C_SYS_CFG_ACLK_VLD 0x00000002 445 #define R92C_SYS_CFG_UCLK_VLD 0x00000004 446 #define R92C_SYS_CFG_PCLK_VLD 0x00000008 447 #define R92C_SYS_CFG_PCIRSTB 0x00000010 448 #define R92C_SYS_CFG_V15_VLD 0x00000020 449 #define R92C_SYS_CFG_TRP_B15V_EN 0x00000080 450 #define R92C_SYS_CFG_SIC_IDLE 0x00000100 451 #define R92C_SYS_CFG_BD_MAC2 0x00000200 452 #define R92C_SYS_CFG_BD_MAC1 0x00000400 453 #define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800 454 #define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000 455 #define R92C_SYS_CFG_CHIP_VER_RTL_S 12 456 #define R92C_SYS_CFG_BT_FUNC 0x00010000 457 #define R92C_SYS_CFG_VENDOR_UMC 0x00080000 458 #define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000 459 #define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000 460 #define R92C_SYS_CFG_TRP_BT_EN 0x01000000 461 #define R92E_SYS_CFG_SPSLDO_SEL 0x01000000 462 #define R92C_SYS_CFG_BD_PKG_SEL 0x02000000 463 #define R92C_SYS_CFG_BD_HCI_SEL 0x04000000 464 #define R92C_SYS_CFG_TYPE_92C 0x08000000 465 466 /* Bits for R92C_CR. */ 467 #define R92C_CR_HCI_TXDMA_EN 0x00000001 468 #define R92C_CR_HCI_RXDMA_EN 0x00000002 469 #define R92C_CR_TXDMA_EN 0x00000004 470 #define R92C_CR_RXDMA_EN 0x00000008 471 #define R92C_CR_PROTOCOL_EN 0x00000010 472 #define R92C_CR_SCHEDULE_EN 0x00000020 473 #define R92C_CR_MACTXEN 0x00000040 474 #define R92C_CR_MACRXEN 0x00000080 475 #define R92C_CR_ENSWBCN 0x00000100 476 #define R92C_CR_ENSEC 0x00000200 477 #define R92C_CR_CALTMR_EN 0x00000400 478 479 /* Bits for R92C_MSR. */ 480 #define R92C_MSR_NETTYPE_NOLINK 0x00 481 #define R92C_MSR_NETTYPE_ADHOC 0x01 482 #define R92C_MSR_NETTYPE_INFRA 0x02 483 #define R92C_MSR_NETTYPE_AP 0x03 484 #define R92C_MSR_NETTYPE_MASK 0x03 485 486 /* Bits for R92C_PBP. */ 487 #define R92C_PBP_PSRX_M 0x0f 488 #define R92C_PBP_PSRX_S 0 489 #define R92C_PBP_PSTX_M 0xf0 490 #define R92C_PBP_PSTX_S 4 491 #define R92C_PBP_64 0 492 #define R92C_PBP_128 1 493 #define R92C_PBP_256 2 494 #define R92C_PBP_512 3 495 #define R92C_PBP_1024 4 496 497 /* Bits for R92C_TRXDMA_CTRL. */ 498 #define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004 499 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030 500 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4 501 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0 502 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6 503 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300 504 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8 505 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00 506 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10 507 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000 508 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12 509 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000 510 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14 511 #define R92C_TRXDMA_CTRL_QUEUE_LOW 1 512 #define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2 513 #define R92C_TRXDMA_CTRL_QUEUE_HIGH 3 514 #define R92C_TRXDMA_CTRL_QMAP_M 0xfff0 515 #define R92C_TRXDMA_CTRL_QMAP_S 4 516 /* Shortcuts. */ 517 #define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0 518 #define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0 519 #define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0 520 #define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550 521 #define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0 522 #define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0 523 524 /* Bits for R92C_LLT_INIT. */ 525 #define R92C_LLT_INIT_DATA_M 0x000000ff 526 #define R92C_LLT_INIT_DATA_S 0 527 #define R92C_LLT_INIT_ADDR_M 0x0000ff00 528 #define R92C_LLT_INIT_ADDR_S 8 529 #define R92C_LLT_INIT_OP_M 0xc0000000 530 #define R92C_LLT_INIT_OP_S 30 531 #define R92C_LLT_INIT_OP_NO_ACTIVE 0 532 #define R92C_LLT_INIT_OP_WRITE 1 533 #define R92C_LLT_INIT_OP_READ 2 534 535 /* Bits for R92C_RQPN. */ 536 #define R92C_RQPN_HPQ_M 0x000000ff 537 #define R92C_RQPN_HPQ_S 0 538 #define R92C_RQPN_LPQ_M 0x0000ff00 539 #define R92C_RQPN_LPQ_S 8 540 #define R92C_RQPN_PUBQ_M 0x00ff0000 541 #define R92C_RQPN_PUBQ_S 16 542 #define R92C_RQPN_LD 0x80000000 543 544 /* Bits for R92C_TDECTRL. */ 545 #define R92C_TDECTRL_BLK_DESC_NUM_M 0x000000f0 546 #define R92C_TDECTRL_BLK_DESC_NUM_S 4 547 548 /* Bits for R92C_TXDMA_OFFSET_CHK. */ 549 #define R92C_TXDMA_OFFSET_CHK_DROP_DATA_EN 0x00000200 550 551 /* Bits for R92E_AUTO_LLT. */ 552 #define R92E_AUTO_LLT_EN 0x00010000 553 554 /* Bits for R92C_FWHW_TXQ_CTRL. */ 555 #define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80 556 557 /* Bits for R92C_SPEC_SIFS. */ 558 #define R92C_SPEC_SIFS_CCK_M 0x00ff 559 #define R92C_SPEC_SIFS_CCK_S 0 560 #define R92C_SPEC_SIFS_OFDM_M 0xff00 561 #define R92C_SPEC_SIFS_OFDM_S 8 562 563 /* Bits for R92C_RL. */ 564 #define R92C_RL_LRL_M 0x003f 565 #define R92C_RL_LRL_S 0 566 #define R92C_RL_SRL_M 0x3f00 567 #define R92C_RL_SRL_S 8 568 569 /* Bits for R92C_RRSR. */ 570 #define R92C_RRSR_RATE_BITMAP_M 0x000fffff 571 #define R92C_RRSR_RATE_BITMAP_S 0 572 #define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1 573 #define R92C_RRSR_RATE_ALL 0xfffff 574 #define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000 575 #define R92C_RRSR_RSC_UPSUBCHNL 0x00400000 576 #define R92C_RRSR_SHORT 0x00800000 577 578 /* Bits for R88E_TX_RPT_CTRL. */ 579 #define R88E_TX_RPT_CTRL_EN 0x01 580 #define R88E_TX_RPT_CTRL_TIMER_EN 0x02 581 582 /* Bits for R92C_EDCA_XX_PARAM. */ 583 #define R92C_EDCA_PARAM_AIFS_M 0x000000ff 584 #define R92C_EDCA_PARAM_AIFS_S 0 585 #define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00 586 #define R92C_EDCA_PARAM_ECWMIN_S 8 587 #define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000 588 #define R92C_EDCA_PARAM_ECWMAX_S 12 589 #define R92C_EDCA_PARAM_TXOP_M 0xffff0000 590 #define R92C_EDCA_PARAM_TXOP_S 16 591 592 /* Bits for R92C_ACMHWCTRL */ 593 #define R92C_ACMHW_HWEN 0x01 594 #define R92C_ACMHW_BEQEN 0x02 595 #define R92C_ACMHW_VIQEN 0x04 596 #define R92C_ACMHW_VOQEN 0x08 597 #define R92C_ACMHW_BEQSTATUS 0x10 598 #define R92C_ACMHW_VIQSTATUS 0x20 599 #define R92C_ACMHW_VOQSTATUS 0x40 600 601 /* Bits for R92C_TXPAUSE. */ 602 #define R92C_TXPAUSE_AC_VO 0x01 603 #define R92C_TXPAUSE_AC_VI 0x02 604 #define R92C_TXPAUSE_AC_BE 0x04 605 #define R92C_TXPAUSE_AC_BK 0x08 606 #define R92C_TXPAUSE_MGNT 0x10 607 #define R92C_TXPAUSE_HIGH 0x20 608 #define R92C_TXPAUSE_BCN 0x40 609 #define R92C_TXPAUSE_BCN_HIGH_MGNT 0x80 610 611 #define R92C_TXPAUSE_ALL (R92C_TXPAUSE_AC_VO | R92C_TXPAUSE_AC_VI | \ 612 R92C_TXPAUSE_AC_BE | R92C_TXPAUSE_AC_BK | \ 613 R92C_TXPAUSE_MGNT | R92C_TXPAUSE_HIGH | \ 614 R92C_TXPAUSE_BCN | R92C_TXPAUSE_BCN_HIGH_MGNT) 615 616 /* Bits for R92C_BCN_CTRL. */ 617 #define R92C_BCN_CTRL_EN_MBSSID 0x02 618 #define R92C_BCN_CTRL_TXBCN_RPT 0x04 619 #define R92C_BCN_CTRL_EN_BCN 0x08 620 #define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10 621 622 /* Bits for R92C_DRVERLYINT. */ 623 #define R92C_DRVERLYINT_INIT_TIME 0x05 624 625 /* Bits for R92C_BCNDMATIM. */ 626 #define R92C_BCNDMATIM_INIT_TIME 0x02 627 628 /* Bits for R92C_APSD_CTRL. */ 629 #define R92C_APSD_CTRL_OFF 0x40 630 #define R92C_APSD_CTRL_OFF_STATUS 0x80 631 632 /* Bits for R92C_BWOPMODE. */ 633 #define R92C_BWOPMODE_11J 0x01 634 #define R92C_BWOPMODE_5G 0x02 635 #define R92C_BWOPMODE_20MHZ 0x04 636 637 /* Bits for R92C_TCR. */ 638 #define R92C_TCR_TSFRST 0x00000001 639 #define R92C_TCR_DIS_GCLK 0x00000002 640 #define R92C_TCR_PAD_SEL 0x00000004 641 #define R92C_TCR_PWR_ST 0x00000040 642 #define R92C_TCR_PWRBIT_OW_EN 0x00000080 643 #define R92C_TCR_ACRC 0x00000100 644 #define R92C_TCR_CFENDFORM 0x00000200 645 #define R92C_TCR_ICV 0x00000400 646 #define R92C_TCR_ERRSTEN0 0x00001000 647 #define R92C_TCR_ERRSTEN1 0x00002000 648 #define R92C_TCR_ERRSTEN2 0x00004000 649 #define R92C_TCR_ERRSTEN3 0x00008000 650 651 /* Bits for R92C_RCR. */ 652 #define R92C_RCR_AAP 0x00000001 653 #define R92C_RCR_APM 0x00000002 654 #define R92C_RCR_AM 0x00000004 655 #define R92C_RCR_AB 0x00000008 656 #define R92C_RCR_ADD3 0x00000010 657 #define R92C_RCR_APWRMGT 0x00000020 658 #define R92C_RCR_CBSSID_DATA 0x00000040 659 #define R92C_RCR_CBSSID_BCN 0x00000080 660 #define R92C_RCR_ACRC32 0x00000100 661 #define R92C_RCR_AICV 0x00000200 662 #define R92C_RCR_ADF 0x00000800 663 #define R92C_RCR_ACF 0x00001000 664 #define R92C_RCR_AMF 0x00002000 665 #define R92C_RCR_HTC_LOC_CTRL 0x00004000 666 #define R92C_RCR_MFBEN 0x00400000 667 #define R92C_RCR_LSIGEN 0x00800000 668 #define R92C_RCR_ENMBID 0x01000000 669 #define R92C_RCR_APP_BA_SSN 0x08000000 670 #define R92C_RCR_APP_PHYSTS 0x10000000 671 #define R92C_RCR_APP_ICV 0x20000000 672 #define R92C_RCR_APP_MIC 0x40000000 673 #define R92C_RCR_APPFCS 0x80000000 674 675 /* Bits for R92C_WMAC_TRXPTCL_CTL. */ 676 #define R92C_WMAC_TRXPTCL_CTL_SHORT 0x00020000 677 #define R92C_WMAC_TRXPTCL_CTL_BW_20 0 678 #define R92C_WMAC_TRXPTCL_CTL_BW_40 0x00000080 679 #define R92C_WMAC_TRXPTCL_CTL_BW_80 0x00000100 680 #define R92C_WMAC_TRXPTCL_CTL_BW_MASK \ 681 (R92C_WMAC_TRXPTCL_CTL_BW_40 | \ 682 R92C_WMAC_TRXPTCL_CTL_BW_80) 683 684 /* Bits for R92C_CAMCMD. */ 685 #define R92C_CAMCMD_ADDR_M 0x0000ffff 686 #define R92C_CAMCMD_ADDR_S 0 687 #define R92C_CAMCMD_WRITE 0x00010000 688 #define R92C_CAMCMD_CLR 0x40000000 689 #define R92C_CAMCMD_POLLING 0x80000000 690 691 /* Bits for R92C_SECCFG. */ 692 #define R92C_SECCFG_TXUCKEY_DEF 0x0001 693 #define R92C_SECCFG_RXUCKEY_DEF 0x0002 694 #define R92C_SECCFG_TXENC_ENA 0x0004 695 #define R92C_SECCFG_RXENC_ENA 0x0008 696 #define R92C_SECCFG_CMP_A2 0x0010 697 #define R92C_SECCFG_MC_SRCH_DIS 0x0020 698 #define R92C_SECCFG_TXBCKEY_DEF 0x0040 699 #define R92C_SECCFG_RXBCKEY_DEF 0x0080 700 701 /* IMR */ 702 703 /*Beacon DMA interrupt 6 */ 704 #define R92C_IMR_BCNDMAINT6 0x80000000 705 /*Beacon DMA interrupt 5 */ 706 #define R92C_IMR_BCNDMAINT5 0x40000000 707 /*Beacon DMA interrupt 4 */ 708 #define R92C_IMR_BCNDMAINT4 0x20000000 709 /*Beacon DMA interrupt 3 */ 710 #define R92C_IMR_BCNDMAINT3 0x10000000 711 /*Beacon DMA interrupt 2 */ 712 #define R92C_IMR_BCNDMAINT2 0x08000000 713 /*Beacon DMA interrupt 1 */ 714 #define R92C_IMR_BCNDMAINT1 0x04000000 715 /*Beacon Queue DMA OK interrupt 8 */ 716 #define R92C_IMR_BCNDOK8 0x02000000 717 /*Beacon Queue DMA OK interrupt 7 */ 718 #define R92C_IMR_BCNDOK7 0x01000000 719 /*Beacon Queue DMA OK interrupt 6 */ 720 #define R92C_IMR_BCNDOK6 0x00800000 721 /*Beacon Queue DMA OK interrupt 5 */ 722 #define R92C_IMR_BCNDOK5 0x00400000 723 /*Beacon Queue DMA OK interrupt 4 */ 724 #define R92C_IMR_BCNDOK4 0x00200000 725 /*Beacon Queue DMA OK interrupt 3 */ 726 #define R92C_IMR_BCNDOK3 0x00100000 727 /*Beacon Queue DMA OK interrupt 2 */ 728 #define R92C_IMR_BCNDOK2 0x00080000 729 /*Beacon Queue DMA OK interrupt 1 */ 730 #define R92C_IMR_BCNDOK1 0x00040000 731 /*Timeout interrupt 2 */ 732 #define R92C_IMR_TIMEOUT2 0x00020000 733 /*Timeout interrupt 1 */ 734 #define R92C_IMR_TIMEOUT1 0x00010000 735 /*Transmit FIFO Overflow */ 736 #define R92C_IMR_TXFOVW 0x00008000 737 /*Power save time out interrupt */ 738 #define R92C_IMR_PSTIMEOUT 0x00004000 739 /*Beacon DMA interrupt 0 */ 740 #define R92C_IMR_BCNINT 0x00002000 741 /*Receive FIFO Overflow */ 742 #define R92C_IMR_RXFOVW 0x00001000 743 /*Receive Descriptor Unavailable */ 744 #define R92C_IMR_RDU 0x00000800 745 /*For 92C,ATIM Window End interrupt */ 746 #define R92C_IMR_ATIMEND 0x00000400 747 /*Beacon Queue DMA OK interrupt */ 748 #define R92C_IMR_BDOK 0x00000200 749 /*High Queue DMA OK interrupt */ 750 #define R92C_IMR_HIGHDOK 0x00000100 751 /*Transmit Beacon OK interrupt */ 752 #define R92C_IMR_TBDOK 0x00000080 753 /*Management Queue DMA OK interrupt */ 754 #define R92C_IMR_MGNTDOK 0x00000040 755 /*For 92C,Transmit Beacon Error interrupt */ 756 #define R92C_IMR_TBDER 0x00000020 757 /*AC_BK DMA OK interrupt */ 758 #define R92C_IMR_BKDOK 0x00000010 759 /*AC_BE DMA OK interrupt */ 760 #define R92C_IMR_BEDOK 0x00000008 761 /*AC_VI DMA OK interrupt */ 762 #define R92C_IMR_VIDOK 0x00000004 763 /*AC_VO DMA interrupt */ 764 #define R92C_IMR_VODOK 0x00000002 765 /*Receive DMA OK interrupt */ 766 #define R92C_IMR_ROK 0x00000001 767 768 #define R92C_IBSS_INT_MASK (R92C_IMR_BCNINT | R92C_IMR_TBDOK | \ 769 R92C_IMR_TBDER) 770 771 /* 772 * Baseband registers. 773 */ 774 #define R92C_FPGA0_RFMOD 0x800 775 #define R92C_FPGA0_TXINFO 0x804 776 #define R92C_FPGA0_POWER_SAVE 0x818 777 #define R92C_HSSI_PARAM1(chain) (0x820 + (chain) * 8) 778 #define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8) 779 #define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830) 780 #define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834) 781 #define R92C_TXAGC_A_CCK1_MCS32 0xe08 782 #define R92C_TXAGC_B_CCK1_55_MCS32 0x838 783 #define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c 784 #define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c) 785 #define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848) 786 #define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c) 787 #define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868) 788 #define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4) 789 #define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4) 790 #define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4) 791 #define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4) 792 #define R92C_FPGA0_ANAPARAM2 0x884 793 #define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4) 794 #define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4) 795 #define R92C_FPGA1_RFMOD 0x900 796 #define R92C_FPGA1_TXINFO 0x90c 797 #define R92C_CCK0_SYSTEM 0xa00 798 #define R92C_CCK0_AFESETTING 0xa04 799 #define R92C_OFDM0_TRXPATHENA 0xc04 800 #define R92C_OFDM0_TRMUXPAR 0xc08 801 #define R92C_OFDM0_RXIQIMBALANCE(chain) (0xc14 + (chain) * 8) 802 #define R92C_OFDM0_ECCATHRESHOLD 0xc4c 803 #define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8) 804 #define R92C_OFDM0_AGCPARAM1 0xc70 805 #define R92C_OFDM0_AGCRSSITABLE 0xc78 806 #define R92C_OFDM0_TXIQIMBALANCE(chain) (0xc80 + (chain) * 8) 807 #define R92C_OFDM0_TXAFE(chain) (0xc94 + (chain) * 8) 808 #define R92C_OFDM0_RXIQEXTANTA 0xca0 809 #define R92C_OFDM0_TX_PSDO_NOISE_WEIGHT 0xce4 810 #define R92C_OFDM1_LSTF 0xd00 811 812 #define R92C_FPGA0_IQK 0xe28 813 #define R92C_TX_IQK_TONE_A 0xe30 814 #define R92C_RX_IQK_TONE_A 0xe34 815 #define R92C_TX_IQK_PI_A 0xe38 816 #define R92C_RX_IQK_PI_A 0xe3c 817 #define R92C_TX_IQK 0xe40 818 #define R92C_RX_IQK 0xe44 819 #define R92C_IQK_AGC_PTS 0xe48 820 #define R92C_IQK_AGC_RSP 0xe4c 821 #define R92C_TX_IQK_TONE_B 0xe50 822 #define R92C_RX_IQK_TONE_B 0xe54 823 #define R92C_TX_IQK_PI_B 0xe58 824 #define R92C_RX_IQK_PI_B 0xe5c 825 #define R92C_IQK_AGC_CONT 0xe60 826 827 #define R92E_RX_WAIT_CCA 0xe70 828 829 #define R92C_TX_POWER_BEFORE_IQK_A 0xe94 830 #define R92C_TX_POWER_AFTER_IQK_A 0xe9c 831 #define R92C_RX_POWER_BEFORE_IQK_A 0xea0 832 #define R92C_RX_POWER_BEFORE_IQK_A_2 0xea4 833 #define R92C_RX_POWER_AFTER_IQK_A 0xea8 834 #define R92C_RX_POWER_AFTER_IQK_A_2 0xeac 835 836 /* Bits for R92C_FPGA[01]_RFMOD. */ 837 #define R92C_RFMOD_40MHZ 0x00000001 838 #define R92C_RFMOD_JAPAN 0x00000002 839 #define R92C_RFMOD_CCK_TXSC 0x00000030 840 #define R92C_RFMOD_CCK_EN 0x01000000 841 #define R92C_RFMOD_OFDM_EN 0x02000000 842 843 /* Bits for R92C_HSSI_PARAM1(i). */ 844 #define R92C_HSSI_PARAM1_PI 0x00000100 845 846 /* Bits for R92C_HSSI_PARAM2(i). */ 847 #define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200 848 #define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400 849 #define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800 850 #define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000 851 #define R92C_HSSI_PARAM2_READ_ADDR_S 23 852 #define R92C_HSSI_PARAM2_READ_EDGE 0x80000000 853 854 /* Bits for R92C_TXAGC_A_CCK1_MCS32. */ 855 #define R92C_TXAGC_A_CCK1_M 0x0000ff00 856 #define R92C_TXAGC_A_CCK1_S 8 857 858 /* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. */ 859 #define R92C_TXAGC_B_CCK11_M 0x000000ff 860 #define R92C_TXAGC_B_CCK11_S 0 861 #define R92C_TXAGC_A_CCK2_M 0x0000ff00 862 #define R92C_TXAGC_A_CCK2_S 8 863 #define R92C_TXAGC_A_CCK55_M 0x00ff0000 864 #define R92C_TXAGC_A_CCK55_S 16 865 #define R92C_TXAGC_A_CCK11_M 0xff000000 866 #define R92C_TXAGC_A_CCK11_S 24 867 868 /* Bits for R92C_TXAGC_B_CCK1_55_MCS32. */ 869 #define R92C_TXAGC_B_CCK1_M 0x0000ff00 870 #define R92C_TXAGC_B_CCK1_S 8 871 #define R92C_TXAGC_B_CCK2_M 0x00ff0000 872 #define R92C_TXAGC_B_CCK2_S 16 873 #define R92C_TXAGC_B_CCK55_M 0xff000000 874 #define R92C_TXAGC_B_CCK55_S 24 875 876 /* Bits for R92C_TXAGC_RATE18_06(x). */ 877 #define R92C_TXAGC_RATE06_M 0x000000ff 878 #define R92C_TXAGC_RATE06_S 0 879 #define R92C_TXAGC_RATE09_M 0x0000ff00 880 #define R92C_TXAGC_RATE09_S 8 881 #define R92C_TXAGC_RATE12_M 0x00ff0000 882 #define R92C_TXAGC_RATE12_S 16 883 #define R92C_TXAGC_RATE18_M 0xff000000 884 #define R92C_TXAGC_RATE18_S 24 885 886 /* Bits for R92C_TXAGC_RATE54_24(x). */ 887 #define R92C_TXAGC_RATE24_M 0x000000ff 888 #define R92C_TXAGC_RATE24_S 0 889 #define R92C_TXAGC_RATE36_M 0x0000ff00 890 #define R92C_TXAGC_RATE36_S 8 891 #define R92C_TXAGC_RATE48_M 0x00ff0000 892 #define R92C_TXAGC_RATE48_S 16 893 #define R92C_TXAGC_RATE54_M 0xff000000 894 #define R92C_TXAGC_RATE54_S 24 895 896 /* Bits for R92C_TXAGC_MCS03_MCS00(x). */ 897 #define R92C_TXAGC_MCS00_M 0x000000ff 898 #define R92C_TXAGC_MCS00_S 0 899 #define R92C_TXAGC_MCS01_M 0x0000ff00 900 #define R92C_TXAGC_MCS01_S 8 901 #define R92C_TXAGC_MCS02_M 0x00ff0000 902 #define R92C_TXAGC_MCS02_S 16 903 #define R92C_TXAGC_MCS03_M 0xff000000 904 #define R92C_TXAGC_MCS03_S 24 905 906 /* Bits for R92C_TXAGC_MCS07_MCS04(x). */ 907 #define R92C_TXAGC_MCS04_M 0x000000ff 908 #define R92C_TXAGC_MCS04_S 0 909 #define R92C_TXAGC_MCS05_M 0x0000ff00 910 #define R92C_TXAGC_MCS05_S 8 911 #define R92C_TXAGC_MCS06_M 0x00ff0000 912 #define R92C_TXAGC_MCS06_S 16 913 #define R92C_TXAGC_MCS07_M 0xff000000 914 #define R92C_TXAGC_MCS07_S 24 915 916 /* Bits for R92C_TXAGC_MCS11_MCS08(x). */ 917 #define R92C_TXAGC_MCS08_M 0x000000ff 918 #define R92C_TXAGC_MCS08_S 0 919 #define R92C_TXAGC_MCS09_M 0x0000ff00 920 #define R92C_TXAGC_MCS09_S 8 921 #define R92C_TXAGC_MCS10_M 0x00ff0000 922 #define R92C_TXAGC_MCS10_S 16 923 #define R92C_TXAGC_MCS11_M 0xff000000 924 #define R92C_TXAGC_MCS11_S 24 925 926 /* Bits for R92C_TXAGC_MCS15_MCS12(x). */ 927 #define R92C_TXAGC_MCS12_M 0x000000ff 928 #define R92C_TXAGC_MCS12_S 0 929 #define R92C_TXAGC_MCS13_M 0x0000ff00 930 #define R92C_TXAGC_MCS13_S 8 931 #define R92C_TXAGC_MCS14_M 0x00ff0000 932 #define R92C_TXAGC_MCS14_S 16 933 #define R92C_TXAGC_MCS15_M 0xff000000 934 #define R92C_TXAGC_MCS15_S 24 935 936 /* Bits for R92C_LSSI_PARAM(i). */ 937 #define R92C_LSSI_PARAM_DATA_M 0x000fffff 938 #define R92C_LSSI_PARAM_DATA_S 0 939 #define R92C_LSSI_PARAM_ADDR_M 0x03f00000 940 #define R92C_LSSI_PARAM_ADDR_S 20 941 #define R88E_LSSI_PARAM_ADDR_M 0x0ff00000 942 #define R88E_LSSI_PARAM_ADDR_S 20 943 944 /* Bits for R92C_FPGA0_ANAPARAM2. */ 945 #define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400 946 947 /* Bits for R92C_LSSI_READBACK(i). */ 948 #define R92C_LSSI_READBACK_DATA_M 0x000fffff 949 #define R92C_LSSI_READBACK_DATA_S 0 950 951 /* Bits for R92C_OFDM0_AGCCORE1(i). */ 952 #define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f 953 #define R92C_OFDM0_AGCCORE1_GAIN_S 0 954 955 956 /* 957 * USB registers. 958 */ 959 #define R92C_USB_INFO 0xfe17 960 #define R92C_USB_SPECIAL_OPTION 0xfe55 961 #define R92C_USB_HCPWM 0xfe57 962 #define R92C_USB_HRPWM 0xfe58 963 #define R92C_USB_DMA_AGG_TO 0xfe5b 964 #define R92C_USB_AGG_TO 0xfe5c 965 #define R92C_USB_AGG_TH 0xfe5d 966 #define R92C_USB_VID 0xfe60 967 #define R92C_USB_PID 0xfe62 968 #define R92C_USB_OPTIONAL 0xfe64 969 #define R92C_USB_EP 0xfe65 970 #define R92C_USB_PHY 0xfe68 971 #define R92C_USB_MAC_ADDR 0xfe70 972 #define R92C_USB_STRING 0xfe80 973 974 /* Bits for R92C_USB_SPECIAL_OPTION. */ 975 #define R92C_USB_SPECIAL_OPTION_AGG_EN 0x08 976 #define R92C_USB_SPECIAL_OPTION_INT_BULK_SEL 0x10 977 978 /* Bits for R92C_USB_EP. */ 979 #define R92C_USB_EP_HQ_M 0x000f 980 #define R92C_USB_EP_HQ_S 0 981 #define R92C_USB_EP_NQ_M 0x00f0 982 #define R92C_USB_EP_NQ_S 4 983 #define R92C_USB_EP_LQ_M 0x0f00 984 #define R92C_USB_EP_LQ_S 8 985 986 /* 987 * Firmware base address. 988 */ 989 #define R92C_FW_START_ADDR 0x1000 990 #define R92C_FW_PAGE_SIZE 4096 991 992 993 /* 994 * RF (6052) registers. 995 */ 996 #define R92C_RF_AC 0x00 997 #define R92C_RF_IQADJ_G(i) (0x01 + (i)) 998 #define R92C_RF_POW_TRSW 0x05 999 #define R92C_RF_GAIN_RX 0x06 1000 #define R92C_RF_GAIN_TX 0x07 1001 #define R92C_RF_TXM_IDAC 0x08 1002 #define R92C_RF_BS_IQGEN 0x0f 1003 #define R92C_RF_MODE1 0x10 1004 #define R92C_RF_MODE2 0x11 1005 #define R92C_RF_RX_AGC_HP 0x12 1006 #define R92C_RF_TX_AGC 0x13 1007 #define R92C_RF_BIAS 0x14 1008 #define R92C_RF_IPA 0x15 1009 #define R92C_RF_POW_ABILITY 0x17 1010 #define R92C_RF_CHNLBW 0x18 1011 #define R92C_RF_RX_G1 0x1a 1012 #define R92C_RF_RX_G2 0x1b 1013 #define R92C_RF_RX_BB2 0x1c 1014 #define R92C_RF_RX_BB1 0x1d 1015 #define R92C_RF_RCK1 0x1e 1016 #define R92C_RF_RCK2 0x1f 1017 #define R92C_RF_TX_G(i) (0x20 + (i)) 1018 #define R92C_RF_TX_BB1 0x23 1019 #define R92C_RF_T_METER 0x24 1020 #define R92C_RF_SYN_G(i) (0x25 + (i)) 1021 #define R92C_RF_RCK_OS 0x30 1022 #define R92C_RF_TXPA_G(i) (0x31 + (i)) 1023 #define R92E_RF_T_METER 0x42 1024 1025 /* Bits for R92C_RF_AC. */ 1026 #define R92C_RF_AC_MODE_M 0x70000 1027 #define R92C_RF_AC_MODE_S 16 1028 #define R92C_RF_AC_MODE_STANDBY 1 1029 1030 /* Bits for R92C_RF_CHNLBW. */ 1031 #define R92C_RF_CHNLBW_CHNL_M 0x003ff 1032 #define R92C_RF_CHNLBW_CHNL_S 0 1033 #define R92C_RF_CHNLBW_BW20 0x00400 1034 #define R88E_RF_CHNLBW_BW20 0x00c00 1035 #define R92C_RF_CHNLBW_LCSTART 0x08000 1036 1037 1038 /* 1039 * CAM entries. 1040 */ 1041 #define R92C_CAM_ENTRY_COUNT 32 1042 1043 #define R92C_CAM_CTL0(entry) ((entry) * 8 + 0) 1044 #define R92C_CAM_CTL1(entry) ((entry) * 8 + 1) 1045 #define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) 1046 1047 /* Bits for R92C_CAM_CTL0(i). */ 1048 #define R92C_CAM_KEYID_M 0x00000003 1049 #define R92C_CAM_KEYID_S 0 1050 #define R92C_CAM_ALGO_M 0x0000001c 1051 #define R92C_CAM_ALGO_S 2 1052 #define R92C_CAM_ALGO_NONE 0 1053 #define R92C_CAM_ALGO_WEP40 1 1054 #define R92C_CAM_ALGO_TKIP 2 1055 #define R92C_CAM_ALGO_AES 4 1056 #define R92C_CAM_ALGO_WEP104 5 1057 #define R92C_CAM_VALID 0x00008000 1058 #define R92C_CAM_MACLO_M 0xffff0000 1059 #define R92C_CAM_MACLO_S 16 1060 1061 /* Rate adaptation modes. */ 1062 #define R92C_RAID_11GN 1 1063 #define R92C_RAID_11N 3 1064 #define R92C_RAID_11BG 4 1065 #define R92C_RAID_11G 5 /* "pure" 11g */ 1066 #define R92C_RAID_11B 6 1067 1068 #define R92E_RAID_11BG 6 1069 #define R92E_RAID_11G 7 /* "pure" 11g */ 1070 #define R92E_RAID_11B 8 1071 1072 1073 /* Macros to access unaligned little-endian memory. */ 1074 #define LE_READ_2(x) ((x)[0] | (x)[1] << 8) 1075 #define LE_READ_4(x) ((x)[0] | (x)[1] << 8 | (x)[2] << 16 | (x)[3] << 24) 1076 1077 /* 1078 * Macros to access subfields in registers. 1079 */ 1080 /* Mask and Shift (getter). */ 1081 #define MS(val, field) \ 1082 (((val) & field##_M) >> field##_S) 1083 1084 /* Shift and Mask (setter). */ 1085 #define SM(field, val) \ 1086 (((val) << field##_S) & field##_M) 1087 1088 /* Rewrite. */ 1089 #define RW(var, field, val) \ 1090 (((var) & ~field##_M) | SM(field, val)) 1091 1092 /* 1093 * Firmware image header. 1094 */ 1095 struct r92c_fw_hdr { 1096 /* QWORD0 */ 1097 uint16_t signature; 1098 uint8_t category; 1099 uint8_t function; 1100 uint16_t version; 1101 uint16_t subversion; 1102 /* QWORD1 */ 1103 uint8_t month; 1104 uint8_t date; 1105 uint8_t hour; 1106 uint8_t minute; 1107 uint16_t ramcodesize; 1108 uint16_t reserved2; 1109 /* QWORD2 */ 1110 uint32_t svnidx; 1111 uint32_t reserved3; 1112 /* QWORD3 */ 1113 uint32_t reserved4; 1114 uint32_t reserved5; 1115 } __packed; 1116 1117 /* 1118 * Host to firmware commands. 1119 */ 1120 struct r92c_fw_cmd { 1121 uint8_t id; 1122 #define R92C_CMD_AP_OFFLOAD 0 1123 #define R92C_CMD_SET_PWRMODE 1 1124 #define R92C_CMD_JOINBSS_RPT 2 1125 #define R92C_CMD_RSVD_PAGE 3 1126 #define R92C_CMD_RSSI 4 1127 #define R92C_CMD_RSSI_SETTING 5 1128 #define R92C_CMD_MACID_CONFIG 6 1129 #define R92C_CMD_MACID_PS_MODE 7 1130 #define R92C_CMD_P2P_PS_OFFLOAD 8 1131 #define R92C_CMD_SELECTIVE_SUSPEND 9 1132 #define R92C_CMD_FLAG_EXT 0x80 1133 1134 uint8_t msg[5]; 1135 } __packed; 1136 1137 /* Structure for R92C_CMD_RSSI_SETTING. */ 1138 struct r92c_fw_cmd_rssi { 1139 uint8_t macid; 1140 uint8_t reserved; 1141 uint8_t pwdb; 1142 } __packed; 1143 1144 /* Structure for R92C_CMD_MACID_CONFIG. */ 1145 struct r92c_fw_cmd_macid_cfg { 1146 uint32_t mask; 1147 uint8_t macid; 1148 #define R92C_MACID_BSS 0 1149 #define R92C_MACID_BC 4 /* Broadcast. */ 1150 #define R92C_MACID_VALID 0x80 1151 #define R92C_MACID_SHORTGI 0x20 1152 } __packed; 1153 1154 /* Structure for R92C_CMD_SET_PWRMODE. */ 1155 struct r92c_fw_cmd_setpwrmode { 1156 uint8_t mode; 1157 uint8_t smartps; 1158 uint8_t bcn_time; /* 100ms increments */ 1159 } __packed; 1160 1161 #define R92E_CMD_KEEP_ALIVE 0x03 1162 #define R92E_CMD_SET_PWRMODE 0x20 1163 #define R92E_CMD_RSSI_REPORT 0x42 1164 1165 /* Structure for R92E_CMD_KEEP_ALIVE. */ 1166 struct r92e_fw_cmd_keepalive { 1167 uint8_t mode; 1168 uint8_t period; 1169 } __packed; 1170 1171 /* Structure for R92E_CMD_SET_PWRMODE. */ 1172 struct r92e_fw_cmd_setpwrmode { 1173 uint8_t mode; 1174 #define FWMODE_ACTIVE 0 1175 #define FWMODE_LOW_POWER 1 1176 #define FWMODE_WMMPS 2 1177 uint8_t smartps; 1178 #define SRTPS_LOW_POWER 0 1179 #define SRTPS_POLL 0x10 1180 #define SRTPS_WMMPS 0x20 1181 uint8_t awake_int; /* 100ms increments. */ 1182 uint8_t all_queue_apsd; 1183 uint8_t pwr_state; 1184 #define PS_PFOFF 0x00 1185 #define PS_RFON 0x04 1186 #define PS_ALLON 0x0c 1187 } __packed; 1188 1189 /* Structure for R92E_CMD_RSSI_REPORT. */ 1190 struct r92e_fw_cmd_rssi { 1191 uint8_t macid; 1192 uint8_t reserved; 1193 uint8_t pwdb; 1194 uint8_t reserved2; 1195 } __packed; 1196 1197 /* 1198 * RTL8192CU ROM image. 1199 */ 1200 struct r92c_rom { 1201 uint16_t id; /* 0x8129 */ 1202 uint8_t reserved1[5]; 1203 uint8_t dbg_sel; 1204 uint16_t reserved2; 1205 uint16_t vid; 1206 uint16_t pid; 1207 uint8_t usb_opt; 1208 uint8_t ep_setting; 1209 uint16_t reserved3; 1210 uint8_t usb_phy; 1211 uint8_t reserved4[3]; 1212 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1213 uint8_t string[61]; /* "Realtek" */ 1214 uint8_t subcustomer_id; 1215 uint8_t cck_tx_pwr[R92C_MAX_CHAINS][3]; 1216 uint8_t ht40_1s_tx_pwr[R92C_MAX_CHAINS][3]; 1217 uint8_t ht40_2s_tx_pwr_diff[3]; 1218 uint8_t ht20_tx_pwr_diff[3]; 1219 uint8_t ofdm_tx_pwr_diff[3]; 1220 uint8_t ht40_max_pwr[3]; 1221 uint8_t ht20_max_pwr[3]; 1222 uint8_t channel_plan; 1223 uint8_t tssi[R92C_MAX_CHAINS]; 1224 uint8_t thermal_meter; 1225 uint8_t rf_opt1; 1226 #define R92C_ROM_RF1_REGULATORY_M 0x07 1227 #define R92C_ROM_RF1_REGULATORY_S 0 1228 #define R92C_ROM_RF1_BOARD_TYPE_M 0xe0 1229 #define R92C_ROM_RF1_BOARD_TYPE_S 5 1230 #define R92C_BOARD_TYPE_DONGLE 0 1231 #define R92C_BOARD_TYPE_HIGHPA 1 1232 #define R92C_BOARD_TYPE_MINICARD 2 1233 #define R92C_BOARD_TYPE_SOLO 3 1234 #define R92C_BOARD_TYPE_COMBO 4 1235 1236 uint8_t rf_opt2; 1237 uint8_t rf_opt3; 1238 uint8_t rf_opt4; 1239 uint8_t reserved5; 1240 uint8_t version; 1241 uint8_t curstomer_id; 1242 } __packed; 1243 1244 struct r92e_tx_pwr { 1245 uint8_t cck_tx_pwr[6]; 1246 uint8_t ht40_tx_pwr[5]; 1247 uint8_t ht20_ofdm_tx_pwr_diff; 1248 #define R92E_ROM_TXPWR_HT20_DIFF_M 0xf0 1249 #define R92E_ROM_TXPWR_HT20_DIFF_S 4 1250 #define R92E_ROM_TXPWR_OFDM_DIFF_M 0x0f 1251 #define R92E_ROM_TXPWR_OFDM_DIFF_S 0 1252 1253 struct { 1254 uint8_t ht40_ht20_tx_pwr_diff; 1255 #define R92E_ROM_TXPWR_HT40_DIFF_M 0xf0 1256 #define R92E_ROM_TXPWR_HT40_DIFF_S 4 1257 #define R92E_ROM_TXPWR_HT20_2S_DIFF_M 0x0f 1258 #define R92E_ROM_TXPWR_HT20_2S_DIFF_S 0 1259 1260 uint8_t ofdm_cck_tx_pwr_diff; 1261 } __packed pwr_diff[3]; 1262 1263 uint8_t reserved[24]; 1264 } __packed; 1265 1266 struct r92e_rom { 1267 uint16_t id; 1268 uint8_t reserved[14]; 1269 struct r92e_tx_pwr txpwr_a; 1270 struct r92e_tx_pwr txpwr_b; 1271 uint8_t reserved2[84]; 1272 uint8_t channel_plan; 1273 uint8_t xtal_k; 1274 uint8_t thermal_meter; 1275 uint8_t iqk_lck; 1276 uint8_t pa_type; 1277 uint8_t lna_type_2g; 1278 uint8_t reserved3; 1279 uint8_t lna_type_5g; 1280 uint8_t reserved4; 1281 uint8_t rf_board_opt; 1282 uint8_t rf_feature_opt; 1283 uint8_t rf_bt_opt; 1284 uint8_t eeprom_version; 1285 uint8_t eeprom_customer_id; 1286 uint8_t reserved5[3]; 1287 uint8_t rf_antenna_option; 1288 uint8_t reserved6[6]; 1289 uint16_t vid; 1290 uint16_t pid; 1291 uint8_t usb_optional_function; 1292 uint8_t reserved9[2]; 1293 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1294 uint8_t reserved10[2]; 1295 uint8_t vendor[7]; 1296 uint8_t reserved11[2]; 1297 uint8_t device_name[11]; 1298 uint8_t reserved12[2]; 1299 uint8_t serial[11]; 1300 uint8_t reserved13[48]; 1301 uint8_t unknown[13]; 1302 uint8_t reserved14[195]; 1303 } __packed; 1304 1305 struct r88e_tx_pwr { 1306 uint8_t cck_tx_pwr[6]; 1307 uint8_t ht40_tx_pwr[5]; 1308 uint8_t ht20_ofdm_tx_pwr_diff; 1309 #define R88E_ROM_TXPWR_HT20_DIFF_M 0xf0 1310 #define R88E_ROM_TXPWR_HT20_DIFF_S 4 1311 #define R88E_ROM_TXPWR_OFDM_DIFF_M 0x0f 1312 #define R88E_ROM_TXPWR_OFDM_DIFF_S 0 1313 1314 } __packed; 1315 1316 /* 1317 * RTL8188E ROM images. 1318 */ 1319 struct r88e_rom { 1320 uint16_t id; 1321 uint8_t reserved1[14]; 1322 struct r88e_tx_pwr txpwr; 1323 uint8_t reserved2[156]; 1324 uint8_t channel_plan; 1325 uint8_t xtal; 1326 uint8_t thermal_meter; 1327 uint8_t reserved3[6]; 1328 uint8_t rf_board_opt; 1329 uint8_t rf_feature_opt; 1330 uint8_t rf_bt_opt; 1331 uint8_t version; 1332 uint8_t customer_id; 1333 uint8_t reserved4[3]; 1334 uint8_t rf_ant_opt; 1335 uint8_t reserved5[6]; 1336 union { 1337 #define r88ee_rom u.r88ee 1338 struct { 1339 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1340 uint16_t vid; 1341 uint16_t did; 1342 uint16_t svid; 1343 uint16_t smid; 1344 uint8_t reserved6[290]; 1345 } __packed r88ee; 1346 1347 #define r88eu_rom u.r88eu 1348 struct { 1349 uint16_t vid; 1350 uint16_t pid; 1351 uint8_t usb_opt; 1352 uint8_t reserved6[2]; 1353 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1354 uint8_t reserved7[2]; 1355 uint8_t string[33]; /* "Realtek" */ 1356 uint8_t reserved8[256]; 1357 } __packed r88eu; 1358 } u; 1359 } __packed; 1360 1361 /* 1362 * RTL8723A ROM images. 1363 */ 1364 struct r23a_rom { 1365 uint16_t id; /* 0x8129 */ /* 0x00 */ 1366 uint8_t reserved[14]; /* 0x02 */ 1367 1368 uint8_t tx_pwr_cck_a[3]; /* 0x10 */ 1369 uint8_t tx_pwr_cck_b[3]; /* 0x13 */ 1370 uint8_t tx_pwr_ht40_1s_a[3]; /* 0x16 */ 1371 uint8_t tx_pwr_ht40_1s_b[3]; /* 0x19 */ 1372 uint8_t tx_pwr_ht20_diff[3]; /* 0x1c */ 1373 uint8_t tx_pwr_ofdm_diff[3]; /* 0x1f */ 1374 1375 uint8_t ht40_max_pwr_offset[3]; /* 0x22 */ 1376 uint8_t ht20_max_pwr_offset[3]; /* 0x25 */ 1377 uint8_t channel_plan; /* 0x28 */ 1378 uint8_t tssi_a; /* 0x29 */ 1379 uint8_t thermal_meter; /* 0x2a */ 1380 uint8_t reserved2[5]; /* 0x2b */ 1381 1382 uint8_t version; /* 0x30 */ 1383 uint8_t customer_id; /* 0x31 */ 1384 uint8_t customer_id_min; /* 0x32 */ 1385 uint8_t reserved3[22]; /* 0x33 */ 1386 1387 uint16_t vid; /* 0x49 */ 1388 uint16_t did; /* 0x4b */ 1389 uint16_t svid; /* 0x4d */ 1390 uint16_t smid; /* 0x4f */ 1391 1392 uint8_t reserved4[3]; /* 0x51 */ 1393 uint8_t pwr_diff; /* 0x54 */ 1394 uint8_t reserved5[5]; /* 0x55 */ 1395 uint8_t cck_tx_pwr; /* 0x5a */ 1396 uint8_t reserved6[5]; /* 0x5b */ 1397 1398 uint8_t ht40_1s_tx_pwr; /* 0x60 */ 1399 uint8_t reserved7[5]; 1400 uint8_t ht40_2s_tx_pwr_diff; /* 0x66 */ 1401 uint8_t macaddr[IEEE80211_ADDR_LEN]; /* 0x67 */ 1402 uint8_t reserved8[10]; /* 0x6d */ 1403 1404 uint8_t tssi_b; /* 0x77 */ 1405 uint8_t xtal_k; /* 0x78 */ 1406 uint8_t rf_opt1; /* 0x79 */ 1407 uint8_t rf_opt2; /* 0x7a */ 1408 uint8_t rf_opt3; /* 0x7b */ 1409 uint8_t rf_opt4; /* 0x7c */ 1410 uint8_t reserved9[131]; /* 0x7d */ 1411 } __packed; 1412 1413 /* Rx PHY descriptor. */ 1414 struct r92c_rx_phystat { 1415 uint32_t phydw0; 1416 uint32_t phydw1; 1417 uint32_t phydw2; 1418 uint32_t phydw3; 1419 uint32_t phydw4; 1420 uint32_t phydw5; 1421 uint32_t phydw6; 1422 uint32_t phydw7; 1423 } __packed __attribute__((aligned(4))); 1424 1425 /* Rx PHY CCK descriptor. */ 1426 struct r92c_rx_cck { 1427 uint8_t adc_pwdb[4]; 1428 uint8_t sq_rpt; 1429 uint8_t agc_rpt; 1430 } __packed; 1431 1432 /* Tx report (type 1). */ 1433 struct r88e_tx_rpt_ccx { 1434 uint8_t rptb0; 1435 #define R88E_RPTB6_PKT_NUM_M 0x0e 1436 #define R88E_RPTB6_PKT_NUM_S 1 1437 #define R88E_RPTB0_INT_CCX 0x80 1438 1439 uint8_t rptb1; 1440 #define R88E_RPTB1_MACID_M 0x3f 1441 #define R88E_RPTB1_MACID_S 0 1442 #define R88E_RPTB1_PKT_OK 0x40 1443 #define R88E_RPTB1_BMC 0x80 1444 1445 uint8_t rptb2; 1446 #define R88E_RPTB2_RETRY_CNT_M 0x3f 1447 #define R88E_RPTB2_RETRY_CNT_S 0 1448 #define R88E_RPTB2_LIFE_EXPIRE 0x40 1449 #define R88E_RPTB2_RETRY_OVER 0x80 1450 1451 uint8_t queue_time_low; 1452 uint8_t queue_time_high; 1453 uint8_t final_rate; 1454 uint8_t rptb6; 1455 #define R88E_RPTB6_QSEL_M 0xf0 1456 #define R88E_RPTB6_QSEL_S 4 1457 1458 uint8_t rptb7; 1459 } __packed; 1460 1461 struct r88e_rx_phystat { 1462 uint8_t path_agc[2]; 1463 uint8_t ch_corr[2]; 1464 uint8_t sq_rpt; 1465 uint8_t agc_rpt; 1466 uint8_t rpt_b; 1467 uint8_t reserved1; 1468 uint8_t noise_power; 1469 int8_t path_cfotail[2]; 1470 uint8_t pcts_mask[2]; 1471 int8_t stream_rxevm[2]; 1472 uint8_t path_rxsnr[2]; 1473 uint8_t noise_power_db_lsb; 1474 uint8_t reserved2[3]; 1475 uint8_t stream_csi[2]; 1476 uint8_t stream_target_csi[2]; 1477 int8_t sig_evm; 1478 uint8_t reserved3; 1479 uint8_t reserved4; 1480 } __packed; 1481 1482 /* Rx MAC descriptor. */ 1483 1484 struct r92c_rx_desc_pci { 1485 uint32_t rxdw0; 1486 uint32_t rxdw1; 1487 uint32_t rxdw2; 1488 uint32_t rxdw3; 1489 uint32_t rxdw4; 1490 uint32_t rxdw5; 1491 uint32_t rxbufaddr; 1492 uint32_t rxbufaddr64; 1493 } __packed __attribute__((aligned(4))); 1494 1495 struct r92c_rx_desc_usb { 1496 uint32_t rxdw0; 1497 uint32_t rxdw1; 1498 uint32_t rxdw2; 1499 uint32_t rxdw3; 1500 uint32_t rxdw4; 1501 uint32_t rxdw5; 1502 } __packed __attribute__((aligned(4))); 1503 1504 #define R92C_RXDW0_PKTLEN_M 0x00003fff 1505 #define R92C_RXDW0_PKTLEN_S 0 1506 #define R92C_RXDW0_CRCERR 0x00004000 1507 #define R92C_RXDW0_ICVERR 0x00008000 1508 #define R92C_RXDW0_INFOSZ_M 0x000f0000 1509 #define R92C_RXDW0_INFOSZ_S 16 1510 #define R92C_RXDW0_QOS 0x00800000 1511 #define R92C_RXDW0_SHIFT_M 0x03000000 1512 #define R92C_RXDW0_SHIFT_S 24 1513 #define R92C_RXDW0_PHYST 0x04000000 1514 #define R92C_RXDW0_DECRYPTED 0x08000000 1515 #define R92C_RXDW0_LS 0x10000000 1516 #define R92C_RXDW0_FS 0x20000000 1517 #define R92C_RXDW0_EOR 0x40000000 1518 #define R92C_RXDW0_OWN 0x80000000 1519 1520 #define R92C_RXDW2_PKTCNT_M 0x00ff0000 1521 #define R92C_RXDW2_PKTCNT_S 16 1522 #define R92E_RXDW2_RPT_C2H 0x10000000 1523 1524 #define R92C_RXDW3_RATE_M 0x0000003f 1525 #define R92C_RXDW3_RATE_S 0 1526 #define R92C_RXDW3_HT 0x00000040 1527 #define R92C_RXDW3_HTC 0x00000400 1528 #define R88E_RXDW3_RPT_M 0x0000c000 1529 #define R88E_RXDW3_RPT_S 14 1530 #define R88E_RXDW3_RPT_RX 0 1531 #define R88E_RXDW3_RPT_TX1 1 1532 #define R88E_RXDW3_RPT_TX2 2 1533 #define R88E_RXDW3_RPT_HIS 3 1534 1535 /* Tx MAC descriptor. */ 1536 1537 struct r92c_tx_desc_pci { 1538 uint32_t txdw0; 1539 uint32_t txdw1; 1540 uint32_t txdw2; 1541 uint16_t txdw3; 1542 uint16_t txdseq; 1543 uint32_t txdw4; 1544 uint32_t txdw5; 1545 uint32_t txdw6; 1546 uint16_t txbufsize; 1547 uint16_t pad; 1548 uint32_t txbufaddr; 1549 uint32_t txbufaddr64; 1550 uint32_t nextdescaddr; 1551 uint32_t nextdescaddr64; 1552 uint32_t reserved[4]; 1553 } __packed __attribute__((aligned(4))); 1554 1555 struct r92c_tx_desc_usb { 1556 uint32_t txdw0; 1557 uint32_t txdw1; 1558 uint32_t txdw2; 1559 uint16_t txdw3; 1560 uint16_t txdseq; 1561 uint32_t txdw4; 1562 uint32_t txdw5; 1563 uint32_t txdw6; 1564 uint16_t txdsum; 1565 uint16_t pad; 1566 } __packed __attribute__((aligned(4))); 1567 1568 struct r92e_tx_desc_usb { 1569 uint32_t txdw0; 1570 uint32_t txdw1; 1571 uint32_t txdw2; 1572 uint32_t txdw3; 1573 uint32_t txdw4; 1574 uint32_t txdw5; 1575 uint32_t txdw6; 1576 uint16_t txdsum; 1577 uint16_t pad; 1578 uint32_t txdw7; 1579 uint16_t txdseq2; 1580 uint16_t txdw8; 1581 } __packed __attribute__((aligned(4))); 1582 1583 #define R92C_TXDW0_PKTLEN_M 0x0000ffff 1584 #define R92C_TXDW0_PKTLEN_S 0 1585 #define R92C_TXDW0_OFFSET_M 0x00ff0000 1586 #define R92C_TXDW0_OFFSET_S 16 1587 #define R92C_TXDW0_BMCAST 0x01000000 1588 #define R92C_TXDW0_LSG 0x04000000 1589 #define R92C_TXDW0_FSG 0x08000000 1590 #define R92C_TXDW0_OWN 0x80000000 1591 1592 #define R92C_TXDW1_MACID_M 0x0000001f 1593 #define R92C_TXDW1_MACID_S 0 1594 #define R88E_TXDW1_MACID_M 0x0000003f 1595 #define R88E_TXDW1_MACID_S 0 1596 #define R92E_TXDW1_MACID_M 0x0000007f 1597 #define R92E_TXDW1_MACID_S 0 1598 #define R92C_TXDW1_AGGEN 0x00000020 1599 #define R92C_TXDW1_AGGBK 0x00000040 1600 #define R92C_TXDW1_QSEL_M 0x00001f00 1601 #define R92C_TXDW1_QSEL_S 8 1602 #define R92C_TXDW1_QSEL_BE 0x00 1603 #define R92C_TXDW1_QSEL_BK 0x02 1604 #define R92C_TXDW1_QSEL_VI 0x05 1605 #define R92C_TXDW1_QSEL_VO 0x07 1606 #define R92C_TXDW1_QSEL_BEACON 0x10 1607 #define R92C_TXDW1_QSEL_HIGH 0x11 1608 #define R92C_TXDW1_QSEL_MGNT 0x12 1609 #define R92C_TXDW1_QSEL_CMD 0x13 1610 #define R92C_TXDW1_RAID_M 0x000f0000 1611 #define R92C_TXDW1_RAID_S 16 1612 #define R92C_TXDW1_CIPHER_M 0x00c00000 1613 #define R92C_TXDW1_CIPHER_S 22 1614 #define R92C_TXDW1_CIPHER_NONE 0 1615 #define R92C_TXDW1_CIPHER_RC4 1 1616 #define R92C_TXDW1_CIPHER_AES 3 1617 #define R92C_TXDW1_PKTOFF_M 0x7c000000 1618 #define R92C_TXDW1_PKTOFF_S 26 1619 1620 #define R88E_TXDW2_AGGBK 0x00010000 1621 #define R92C_TXDW2_CCX_RPT 0x00080000 1622 1623 #define R92E_TXDW3_DRVRATE 0x1000 1624 #define R23A_TXDW3_TXRPTEN 0x4000 1625 #define R92C_TXDW3_HWSEQEN 0x8000 1626 1627 #define R92C_TXDW4_RTSRATE_M 0x0000001f 1628 #define R92C_TXDW4_RTSRATE_S 0 1629 #define R92C_TXDW4_QOS 0x00000040 1630 #define R92C_TXDW4_HWSEQ 0x00000080 1631 #define R92C_TXDW4_DRVRATE 0x00000100 1632 #define R92C_TXDW4_CTS2SELF 0x00000800 1633 #define R92C_TXDW4_RTSEN 0x00001000 1634 #define R92C_TXDW4_HWRTSEN 0x00002000 1635 #define R92C_TXDW4_SCO_M 0x003f0000 1636 #define R92C_TXDW4_SCO_S 20 1637 #define R92C_TXDW4_SCO_SCA 1 1638 #define R92C_TXDW4_SCO_SCB 2 1639 #define R92C_TXDW4_SHORTPRE 0x01000000 1640 #define R92C_TXDW4_40MHZ 0x02000000 1641 #define R92C_TXDW4_RTS_SHORT 0x04000000 1642 1643 #define R92E_TXDW4_DATARATE_M 0x0000007f 1644 #define R92E_TXDW4_DATARATE_S 0 1645 #define R92E_TXDW4_DATARATEFB_M 0x00001f00 1646 #define R92E_TXDW4_DATARATEFB_S 8 1647 #define R92E_TXDW4_RTSRATEFB_M 0x0001e000 1648 #define R92E_TXDW4_RTSRATEFB_S 13 1649 #define R92E_TXDW4_RETRYLMT_ENA 0x00020000 1650 #define R92E_TXDW4_RETRYLMT_M 0x00fc0000 1651 #define R92E_TXDW4_RETRYLMT_S 18 1652 #define R92E_TXDW4_RTSRATE_M 0x1f000000 1653 #define R92E_TXDW4_RTSRATE_S 24 1654 1655 #define R92C_TXDW5_DATARATE_M 0x0000003f 1656 #define R92C_TXDW5_DATARATE_S 0 1657 #define R92C_TXDW5_SGI 0x00000040 1658 #define R92C_TXDW5_DATARATE_FBLIMIT_M 0x00001f00 1659 #define R92C_TXDW5_DATARATE_FBLIMIT_S 8 1660 #define R92C_TXDW5_RTSRATE_FBLIMIT_M 0x0001e000 1661 #define R92C_TXDW5_RTSRATE_FBLIMIT_S 13 1662 #define R92C_TXDW5_RETRY_LIMIT_ENABLE 0x00020000 1663 #define R92C_TXDW5_DATA_RETRY_LIMIT_M 0x00fc0000 1664 #define R92C_TXDW5_DATA_RETRY_LIMIT_S 18 1665 #define R92C_TXDW5_AGGNUM_M 0xff000000 1666 #define R92C_TXDW5_AGGNUM_S 24 1667 1668 #define R92E_TXDSEQ2_HWSEQ_S 11 1669 #define R92E_TXDSEQ2_HWSEQ_M 0x0000ffff 1670 1671 /* 1672 * C2H event structure. 1673 */ 1674 #define R92C_C2H_MSG_MAX_LEN 16 1675 1676 struct r92c_c2h_evt { 1677 uint8_t evtb0; 1678 #define R92C_C2H_EVTB0_ID_M 0x0f 1679 #define R92C_C2H_EVTB0_ID_S 0 1680 #define R92C_C2H_EVTB0_LEN_M 0xf0 1681 #define R92C_C2H_EVTB0_LEN_S 4 1682 1683 uint8_t seq; 1684 1685 /* Followed by payload (see below). */ 1686 } __packed; 1687 1688 /* Bits for R92C_C2HEVT_CLEAR. */ 1689 #define R92C_C2HEVT_HOST_CLOSE 0x00 1690 #define R92C_C2HEVT_FW_CLOSE 0xff 1691 1692 /* 1693 * C2H event types. 1694 */ 1695 #define R92C_C2HEVT_DEBUG 0 1696 #define R92C_C2HEVT_TX_REPORT 3 1697 #define R92C_C2HEVT_EXT_RA_RPT 6 1698 1699 /* Structure for R92C_C2H_EVT_TX_REPORT event. */ 1700 struct r92c_c2h_tx_rpt { 1701 uint8_t rptb0; 1702 #define R92C_RPTB0_RETRY_CNT_M 0x3f 1703 #define R92C_RPTB0_RETRY_CNT_S 0 1704 1705 uint8_t rptb1; /* XXX junk */ 1706 #define R92C_RPTB1_RTS_RETRY_CNT_M 0x3f 1707 #define R92C_RPTB1_RTS_RETRY_CNT_S 0 1708 1709 uint8_t queue_time_low; 1710 uint8_t queue_time_high; 1711 uint8_t rptb4; 1712 #define R92C_RPTB4_MISSED_PKT_NUM_M 0x1f 1713 #define R92C_RPTB4_MISSED_PKT_NUM_S 0 1714 1715 uint8_t rptb5; 1716 #define R92C_RPTB5_MACID_M 0x1f 1717 #define R92C_RPTB5_MACID_S 0 1718 #define R92C_RPTB5_DES1_FRAGSSN_M 0xe0 1719 #define R92C_RPTB5_DES1_FRAGSSN_S 5 1720 1721 uint8_t rptb6; 1722 #define R92C_RPTB6_RPT_PKT_NUM_M 0x1f 1723 #define R92C_RPTB6_RPT_PKT_NUM_S 0 1724 #define R92C_RPTB6_PKT_DROP 0x20 1725 #define R92C_RPTB6_LIFE_EXPIRE 0x40 1726 #define R92C_RPTB6_RETRY_OVER 0x80 1727 1728 uint8_t rptb7; 1729 #define R92C_RPTB7_EDCA_M 0x0f 1730 #define R92C_RPTB7_EDCA_S 0 1731 #define R92C_RPTB7_BMC 0x20 1732 #define R92C_RPTB7_PKT_OK 0x40 1733 #define R92C_RPTB7_INT_CCX 0x80 1734 } __packed; 1735 1736 struct r92e_c2h_tx_rpt { 1737 uint8_t rptb0; 1738 #define R92E_RPTB0_QSEL_M 0x1f 1739 #define R92E_RPTB0_QSEL_S 0 1740 #define R92E_RPTB0_BC 0x20 1741 #define R92E_RPTB0_LIFE_EXPIRE 0x40 1742 #define R92E_RPTB0_RETRY_OVER 0x80 1743 1744 uint8_t macid; 1745 1746 uint8_t rptb2; 1747 #define R92E_RPTB2_RETRY_CNT_M 0x3f 1748 #define R92E_RPTB2_RETRY_CNT_S 0 1749 1750 uint8_t queue_time_low; 1751 uint8_t queue_time_high; 1752 uint8_t final_rate; 1753 uint16_t reserved; 1754 } __packed; 1755 1756 /* 1757 * MAC initialization values. 1758 */ 1759 static const struct { 1760 uint16_t reg; 1761 uint8_t val; 1762 } rtl8192ce_mac[] = { 1763 { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 }, 1764 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 }, 1765 { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 }, 1766 { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, 1767 { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, 1768 { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, 1769 { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, 1770 { 0x45b, 0xb9 }, { 0x460, 0x88 }, { 0x461, 0x88 }, { 0x462, 0x06 }, 1771 { 0x463, 0x03 }, { 0x4c8, 0x04 }, { 0x4c9, 0x08 }, { 0x4cc, 0x02 }, 1772 { 0x4cd, 0x28 }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, 1773 { 0x502, 0x2f }, { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, 1774 { 0x506, 0x5e }, { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, 1775 { 0x50a, 0x5e }, { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, 1776 { 0x50e, 0x00 }, { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, 1777 { 0x515, 0x10 }, { 0x516, 0x0a }, { 0x517, 0x10 }, { 0x51a, 0x16 }, 1778 { 0x524, 0x0f }, { 0x525, 0x4f }, { 0x546, 0x20 }, { 0x547, 0x00 }, 1779 { 0x559, 0x02 }, { 0x55a, 0x02 }, { 0x55d, 0xff }, { 0x605, 0x30 }, 1780 { 0x608, 0x0e }, { 0x609, 0x2a }, { 0x652, 0x20 }, { 0x63c, 0x0a }, 1781 { 0x63d, 0x0e }, { 0x700, 0x21 }, { 0x701, 0x43 }, { 0x702, 0x65 }, 1782 { 0x703, 0x87 }, { 0x708, 0x21 }, { 0x709, 0x43 }, { 0x70a, 0x65 }, 1783 { 0x70b, 0x87 } 1784 }, rtl8188eu_mac[] = { 1785 { 0x026, 0x41 }, { 0x027, 0x35 }, { 0x040, 0x00 }, { 0x428, 0x0a }, 1786 { 0x429, 0x10 }, { 0x430, 0x00 }, { 0x431, 0x01 }, { 0x432, 0x02 }, 1787 { 0x433, 0x04 }, { 0x434, 0x05 }, { 0x435, 0x06 }, { 0x436, 0x07 }, 1788 { 0x437, 0x08 }, { 0x438, 0x00 }, { 0x439, 0x00 }, { 0x43a, 0x01 }, 1789 { 0x43b, 0x02 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, { 0x43e, 0x06 }, 1790 { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, { 0x442, 0x00 }, 1791 { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, { 0x447, 0x00 }, 1792 { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, { 0x45b, 0xb9 }, 1793 { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x480, 0x08 }, { 0x4c8, 0xff }, 1794 { 0x4c9, 0x08 }, { 0x4cc, 0xff }, { 0x4cd, 0xff }, { 0x4ce, 0x01 }, 1795 { 0x4d3, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, { 0x502, 0x2f }, 1796 { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, { 0x506, 0x5e }, 1797 { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, { 0x50a, 0x5e }, 1798 { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, { 0x50e, 0x00 }, 1799 { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, { 0x516, 0x0a }, 1800 { 0x525, 0x4f }, { 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 }, 1801 { 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a }, 1802 { 0x620, 0xff }, { 0x621, 0xff }, { 0x622, 0xff }, { 0x623, 0xff }, 1803 { 0x624, 0xff }, { 0x625, 0xff }, { 0x626, 0xff }, { 0x627, 0xff }, 1804 { 0x652, 0x20 }, { 0x63c, 0x0a }, { 0x63d, 0x0a }, { 0x63e, 0x0e }, 1805 { 0x63f, 0x0e }, { 0x640, 0x40 }, { 0x66e, 0x05 }, { 0x700, 0x21 }, 1806 { 0x701, 0x43 }, { 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 }, 1807 { 0x709, 0x43 }, { 0x70a, 0x65 }, { 0x70b, 0x87 } 1808 }, rtl8192cu_mac[] = { 1809 { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 }, 1810 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 }, 1811 { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 }, 1812 { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, 1813 { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, 1814 { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, 1815 { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, 1816 { 0x45b, 0xb9 }, { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x462, 0x08 }, 1817 { 0x463, 0x03 }, { 0x4c8, 0xff }, { 0x4c9, 0x08 }, { 0x4cc, 0xff }, 1818 { 0x4cd, 0xff }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, 1819 { 0x502, 0x2f }, { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, 1820 { 0x506, 0x5e }, { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, 1821 { 0x50a, 0x5e }, { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, 1822 { 0x50e, 0x00 }, { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, 1823 { 0x515, 0x10 }, { 0x516, 0x0a }, { 0x517, 0x10 }, { 0x51a, 0x16 }, 1824 { 0x524, 0x0f }, { 0x525, 0x4f }, { 0x546, 0x40 }, { 0x547, 0x00 }, 1825 { 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 }, { 0x55a, 0x02 }, 1826 { 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a }, 1827 { 0x652, 0x20 }, { 0x63c, 0x0a }, { 0x63d, 0x0e }, { 0x63e, 0x0a }, 1828 { 0x63f, 0x0e }, { 0x66e, 0x05 }, { 0x700, 0x21 }, { 0x701, 0x43 }, 1829 { 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 }, { 0x709, 0x43 }, 1830 { 0x70a, 0x65 }, { 0x70b, 0x87 } 1831 }, rtl8192eu_mac[]={ 1832 { 0x011, 0xeb }, { 0x012, 0x07 }, { 0x014, 0x75 }, { 0x303, 0xa7 }, 1833 { 0x421, 0x0f }, { 0x428, 0x0a }, { 0x429, 0x10 }, { 0x430, 0x00 }, 1834 { 0x431, 0x00 }, { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, 1835 { 0x435, 0x05 }, { 0x436, 0x07 }, { 0x437, 0x08 }, { 0x43c, 0x04 }, 1836 { 0x43d, 0x05 }, { 0x43e, 0x07 }, { 0x43f, 0x08 }, { 0x440, 0x5d }, 1837 { 0x441, 0x01 }, { 0x442, 0x00 }, { 0x444, 0x10 }, { 0x445, 0x00 }, 1838 { 0x446, 0x00 }, { 0x447, 0x00 }, { 0x448, 0x00 }, { 0x449, 0xf0 }, 1839 { 0x44a, 0x0f }, { 0x44b, 0x3e }, { 0x44c, 0x10 }, { 0x44d, 0x00 }, 1840 { 0x44e, 0x00 }, { 0x44f, 0x00 }, { 0x450, 0x00 }, { 0x451, 0xf0 }, 1841 { 0x452, 0x0f }, { 0x453, 0x00 }, { 0x456, 0x5e }, { 0x460, 0x66 }, 1842 { 0x461, 0x66 }, { 0x4c8, 0xff }, { 0x4c9, 0x08 }, { 0x4cc, 0xff }, 1843 { 0x4cd, 0xff }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, 1844 { 0x502, 0x2f }, { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, 1845 { 0x506, 0x5e }, { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, 1846 { 0x50a, 0x5e }, { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, 1847 { 0x50e, 0x00 }, { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, 1848 { 0x516, 0x0a }, { 0x525, 0x4f }, { 0x540, 0x12 }, { 0x541, 0x64 }, 1849 { 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 }, { 0x55c, 0x50 }, 1850 { 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a }, 1851 { 0x620, 0xff }, { 0x621, 0xff }, { 0x622, 0xff }, { 0x623, 0xff }, 1852 { 0x624, 0xff }, { 0x625, 0xff }, { 0x626, 0xff }, { 0x627, 0xff }, 1853 { 0x638, 0x50 }, { 0x63c, 0x0a }, { 0x63d, 0x0a }, { 0x63e, 0x0e }, 1854 { 0x63f, 0x0e }, { 0x640, 0x40 }, { 0x642, 0x40 }, { 0x643, 0x00 }, 1855 { 0x652, 0x2b }, { 0x66e, 0x05 }, { 0x700, 0x21 }, { 0x701, 0x43 }, 1856 { 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 }, { 0x709, 0x43 }, 1857 { 0x70a, 0x65 }, { 0x70b, 0x87 } 1858 }; 1859 1860 /* 1861 * Baseband initialization values. 1862 */ 1863 struct r92c_bb_prog { 1864 int count; 1865 const uint16_t *regs; 1866 const uint32_t *vals; 1867 int agccount; 1868 const uint32_t *agcvals; 1869 }; 1870 1871 /* 1872 * RTL8192CU and RTL8192CE-VAU. 1873 */ 1874 static const uint32_t rtl8192ce_bb_vals_1t[] = { 1875 0x0011800f, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1876 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1877 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1878 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1879 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1880 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1881 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1882 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1883 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1884 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1885 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1886 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1887 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1888 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1889 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1890 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1891 0x69543420, 0x43bc0094, 0x69543420, 0x433c0094, 0x00000000, 1892 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1893 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1894 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1895 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1896 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1897 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1898 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1899 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1900 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1901 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1902 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1903 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1904 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1905 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1906 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1907 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1908 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x631b25a0, 1909 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1910 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1911 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1912 0x00000000, 0x00000300, 1913 }; 1914 1915 static const uint16_t rtl8192ce_bb_regs[] = { 1916 0x024, 0x028, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 1917 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 1918 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 0x860, 1919 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 0x884, 1920 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 0x908, 1921 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 1922 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 0xc08, 1923 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 0xc2c, 1924 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 1925 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 1926 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 1927 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 1928 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 0xce0, 1929 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 0xd14, 1930 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 0xd48, 1931 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 0xd6c, 1932 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 1933 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 1934 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 1935 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4, 1936 0xed8, 0xedc, 0xee0, 0xeec, 0xf14, 0xf4c, 0xf00 1937 }; 1938 1939 static const uint32_t rtl8192ce_bb_vals[] = { 1940 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1941 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1942 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1943 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1944 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1945 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1946 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1947 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1948 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1949 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1950 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1951 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1952 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1953 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1954 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1955 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1956 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1957 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1958 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1959 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1960 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1961 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1962 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1963 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1964 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1965 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1966 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1967 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1968 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1969 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1970 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1971 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1972 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1973 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1974 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1975 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1976 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1977 0x00000000, 0x00000300 1978 }; 1979 1980 static const uint32_t rtl8192ce_bb_vals_2t[] = { 1981 0x0011800f, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1982 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1983 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1984 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1985 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1986 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1987 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1988 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1989 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1990 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1991 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1992 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1993 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1994 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1995 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1996 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1997 0x69543420, 0x43bc0094, 0x69543420, 0x433c0094, 0x00000000, 1998 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1999 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 2000 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 2001 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 2002 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 2003 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 2004 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 2005 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 2006 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 2007 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 2008 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 2009 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 2010 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 2011 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 2012 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 2013 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 2014 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 2015 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 2016 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 2017 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 2018 0x00000000, 0x00000300 2019 }; 2020 static const uint32_t rtl8192ce_agc_vals[] = { 2021 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 2022 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 2023 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 2024 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 2025 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 2026 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 2027 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 2028 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 2029 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 2030 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 2031 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 2032 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 2033 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 2034 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 2035 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 2036 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 2037 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 2038 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 2039 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 2040 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 2041 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 2042 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 2043 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 2044 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 2045 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 2046 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 2047 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 2048 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 2049 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 2050 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 2051 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 2052 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 2053 }; 2054 2055 static const struct r92c_bb_prog rtl8192ce_bb_prog = { 2056 nitems(rtl8192ce_bb_regs), 2057 rtl8192ce_bb_regs, 2058 rtl8192ce_bb_vals, 2059 nitems(rtl8192ce_agc_vals), 2060 rtl8192ce_agc_vals 2061 }; 2062 2063 static const struct r92c_bb_prog rtl8192ce_bb_prog_2t = { 2064 nitems(rtl8192ce_bb_regs), 2065 rtl8192ce_bb_regs, 2066 rtl8192ce_bb_vals_2t, 2067 nitems(rtl8192ce_agc_vals), 2068 rtl8192ce_agc_vals 2069 }; 2070 2071 static const struct r92c_bb_prog rtl8192ce_bb_prog_1t = { 2072 nitems(rtl8192ce_bb_regs), 2073 rtl8192ce_bb_regs, 2074 rtl8192ce_bb_vals_1t, 2075 nitems(rtl8192ce_agc_vals), 2076 rtl8192ce_agc_vals 2077 }; 2078 2079 /* 2080 * RTL8188CU. 2081 */ 2082 static const uint32_t rtl8192cu_bb_vals[] = { 2083 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 2084 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 2085 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 2086 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 2087 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 2088 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 2089 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 2090 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 2091 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 2092 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 2093 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 2094 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 2095 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 2096 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 2097 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 2098 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 2099 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 2100 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x0186115b, 2101 0x0000001f, 0x00b99612, 0x40000100, 0x20f60000, 0x40000100, 2102 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 2103 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 2104 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 2105 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 2106 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 2107 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 2108 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 2109 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 2110 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 2111 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 2112 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 2113 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 2114 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 2115 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 2116 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 2117 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 2118 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 2119 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 2120 0x00000000, 0x00000300 2121 }; 2122 2123 static const struct r92c_bb_prog rtl8192cu_bb_prog = { 2124 nitems(rtl8192ce_bb_regs), 2125 rtl8192ce_bb_regs, 2126 rtl8192cu_bb_vals, 2127 nitems(rtl8192ce_agc_vals), 2128 rtl8192ce_agc_vals 2129 }; 2130 2131 /* 2132 * RTL8188CE-VAU. 2133 */ 2134 static const uint32_t rtl8188ce_bb_vals[] = { 2135 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 2136 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 2137 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 2138 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 2139 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 2140 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 2141 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 2142 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 2143 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 2144 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 2145 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 2146 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 2147 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 2148 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 2149 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 2150 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 2151 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 2152 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 2153 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 2154 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 2155 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 2156 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 2157 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 2158 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 2159 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 2160 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 2161 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 2162 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 2163 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 2164 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 2165 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 2166 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 2167 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 2168 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 2169 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 2170 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 2171 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 2172 0x00000000, 0x00000300 2173 }; 2174 2175 static const uint32_t rtl8188ce_agc_vals[] = { 2176 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 2177 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 2178 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 2179 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 2180 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 2181 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 2182 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 2183 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 2184 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 2185 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 2186 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 2187 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 2188 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 2189 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 2190 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 2191 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 2192 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 2193 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 2194 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 2195 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 2196 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 2197 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 2198 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 2199 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 2200 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 2201 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 2202 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 2203 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 2204 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 2205 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 2206 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 2207 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 2208 }; 2209 2210 static const struct r92c_bb_prog rtl8188ce_bb_prog = { 2211 nitems(rtl8192ce_bb_regs), 2212 rtl8192ce_bb_regs, 2213 rtl8188ce_bb_vals, 2214 nitems(rtl8188ce_agc_vals), 2215 rtl8188ce_agc_vals 2216 }; 2217 2218 static const uint32_t rtl8188cu_bb_vals[] = { 2219 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 2220 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 2221 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 2222 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 2223 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 2224 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 2225 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 2226 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 2227 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 2228 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 2229 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 2230 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 2231 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 2232 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 2233 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 2234 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 2235 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 2236 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 2237 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 2238 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 2239 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 2240 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 2241 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 2242 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 2243 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 2244 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 2245 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 2246 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 2247 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 2248 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 2249 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 2250 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 2251 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 2252 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 2253 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 2254 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 2255 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 2256 0x00000000, 0x00000300 2257 }; 2258 2259 static const struct r92c_bb_prog rtl8188cu_bb_prog = { 2260 nitems(rtl8192ce_bb_regs), 2261 rtl8192ce_bb_regs, 2262 rtl8188cu_bb_vals, 2263 nitems(rtl8188ce_agc_vals), 2264 rtl8188ce_agc_vals 2265 }; 2266 2267 /* 2268 * RTL8188EU. 2269 */ 2270 static const uint16_t rtl8188eu_bb_regs[] = { 2271 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 0x81c, 0x820, 2272 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 0x840, 0x844, 2273 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 0x860, 0x864, 0x868, 2274 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 0x884, 0x888, 0x88c, 2275 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 0x908, 0x90c, 0x910, 2276 0x914, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 2277 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xa78, 0xa7c, 0xa80, 2278 0xb2c, 0xc00, 0xc04, 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 2279 0xc20, 0xc24, 0xc28, 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 2280 0xc44, 0xc48, 0xc4c, 0xc50, 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 2281 0xc68, 0xc6c, 0xc70, 0xc74, 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 2282 0xc8c, 0xc90, 0xc94, 0xc98, 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 2283 0xcb0, 0xcb4, 0xcb8, 0xcbc, 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 2284 0xcd4, 0xcd8, 0xcdc, 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 2285 0xd08, 0xd0c, 0xd10, 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 2286 0xd3c, 0xd40, 0xd44, 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 2287 0xd60, 0xd64, 0xd68, 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 2288 0xe08, 0xe10, 0xe14, 0xe18, 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 2289 0xe3c, 0xe40, 0xe44, 0xe48, 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 2290 0xe60, 0xe68, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 2291 0xe88, 0xe8c, 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xee8, 0xeec, 2292 0xf14, 0xf4c, 0xf00 2293 }; 2294 2295 static const uint32_t rtl8188eu_bb_vals[] = { 2296 0x80040000, 0x00000003, 0x0000fc00, 0x0000000a, 0x10001331, 2297 0x020c3d10, 0x02200385, 0x00000000, 0x01000100, 0x00390204, 2298 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 2299 0x00000000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, 2300 0x00000000, 0x00000000, 0x569a11a9, 0x01000014, 0x66f60110, 2301 0x061f0649, 0x00000000, 0x27272700, 0x07000760, 0x25004000, 2302 0x00000808, 0x00000000, 0xb0000c1c, 0x00000001, 0x00000000, 2303 0xccc000c0, 0x00000800, 0xfffffffe, 0x40302010, 0x00706050, 2304 0x00000000, 0x00000023, 0x00000000, 0x81121111, 0x00000002, 2305 0x00000201, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e7f120f, 2306 0x9500bb78, 0x1114d028, 0x00881117, 0x89140f00, 0x1a1b0000, 2307 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 2308 0x00000900, 0x225b0606, 0x218075b1, 0x80000000, 0x48071d40, 2309 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 0x40000100, 2310 0x08800000, 0x40000100, 0x00000000, 0x00000000, 0x00000000, 2311 0x00000000, 0x69e9ac47, 0x469652af, 0x49795994, 0x0a97971c, 2312 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 0x69553420, 2313 0x43bc0094, 0x00013169, 0x00250492, 0x00000000, 0x7112848b, 2314 0x47c00bff, 0x00000036, 0x2c7f000d, 0x020610db, 0x0000001f, 2315 0x00b91612, 0x390000e4, 0x20f60000, 0x40000100, 0x20200000, 2316 0x00091521, 0x00000000, 0x00121820, 0x00007f7f, 0x00000000, 2317 0x000300a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 2318 0x00000000, 0x28000000, 0x00000000, 0x00000000, 0x00000000, 2319 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 0x00766932, 2320 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 0x00000740, 2321 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 0x3333bc43, 2322 0x7a8f5b6f, 0xcc979975, 0x00000000, 0x80608000, 0x00000000, 2323 0x00127353, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 2324 0x6437140a, 0x00000000, 0x00000282, 0x30032064, 0x4653de68, 2325 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 0x322c2220, 2326 0x000e3c24, 0x2d2d2d2d, 0x2d2d2d2d, 0x0390272d, 0x2d2d2d2d, 2327 0x2d2d2d2d, 0x2d2d2d2d, 0x2d2d2d2d, 0x00000000, 0x1000dc1f, 2328 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 0x01004800, 2329 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 0x02140102, 2330 0x28160d05, 0x00000008, 0x001b25a4, 0x00c00014, 0x00c00014, 2331 0x01000014, 0x01000014, 0x01000014, 0x01000014, 0x00c00014, 2332 0x01000014, 0x00c00014, 0x00c00014, 0x00c00014, 0x00c00014, 2333 0x00000014, 0x00000014, 0x21555448, 0x01c00014, 0x00000003, 2334 0x00000000, 0x00000300 2335 }; 2336 2337 static const uint32_t rtl8188eu_agc_vals[] = { 2338 0xfb000001, 0xfb010001, 0xfb020001, 0xfb030001, 0xfb040001, 2339 0xfb050001, 0xfa060001, 0xf9070001, 0xf8080001, 0xf7090001, 2340 0xf60a0001, 0xf50b0001, 0xf40c0001, 0xf30d0001, 0xf20e0001, 2341 0xf10f0001, 0xf0100001, 0xef110001, 0xee120001, 0xed130001, 2342 0xec140001, 0xeb150001, 0xea160001, 0xe9170001, 0xe8180001, 2343 0xe7190001, 0xe61a0001, 0xe51b0001, 0xe41c0001, 0xe31d0001, 2344 0xe21e0001, 0xe11f0001, 0x8a200001, 0x89210001, 0x88220001, 2345 0x87230001, 0x86240001, 0x85250001, 0x84260001, 0x83270001, 2346 0x82280001, 0x6b290001, 0x6a2a0001, 0x692b0001, 0x682c0001, 2347 0x672d0001, 0x662e0001, 0x652f0001, 0x64300001, 0x63310001, 2348 0x62320001, 0x61330001, 0x46340001, 0x45350001, 0x44360001, 2349 0x43370001, 0x42380001, 0x41390001, 0x403a0001, 0x403b0001, 2350 0x403c0001, 0x403d0001, 0x403e0001, 0x403f0001, 0xfb400001, 2351 0xfb410001, 0xfb420001, 0xfb430001, 0xfb440001, 0xfb450001, 2352 0xfb460001, 0xfb470001, 0xfb480001, 0xfa490001, 0xf94a0001, 2353 0xf84b0001, 0xf74c0001, 0xf64d0001, 0xf54e0001, 0xf44f0001, 2354 0xf3500001, 0xf2510001, 0xf1520001, 0xf0530001, 0xef540001, 2355 0xee550001, 0xed560001, 0xec570001, 0xeb580001, 0xea590001, 2356 0xe95a0001, 0xe85b0001, 0xe75c0001, 0xe65d0001, 0xe55e0001, 2357 0xe45f0001, 0xe3600001, 0xe2610001, 0xc3620001, 0xc2630001, 2358 0xc1640001, 0x8b650001, 0x8a660001, 0x89670001, 0x88680001, 2359 0x87690001, 0x866a0001, 0x856b0001, 0x846c0001, 0x676d0001, 2360 0x666e0001, 0x656f0001, 0x64700001, 0x63710001, 0x62720001, 2361 0x61730001, 0x60740001, 0x46750001, 0x45760001, 0x44770001, 2362 0x43780001, 0x42790001, 0x417a0001, 0x407b0001, 0x407c0001, 2363 0x407d0001, 0x407e0001, 0x407f0001 2364 }; 2365 2366 static const struct r92c_bb_prog rtl8188eu_bb_prog = { 2367 nitems(rtl8188eu_bb_regs), 2368 rtl8188eu_bb_regs, 2369 rtl8188eu_bb_vals, 2370 nitems(rtl8188eu_agc_vals), 2371 rtl8188eu_agc_vals 2372 }; 2373 2374 /* 2375 * RTL8188RU. 2376 */ 2377 static const uint16_t rtl8188ru_bb_regs[] = { 2378 0x024, 0x028, 0x040, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 2379 0x818, 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 2380 0x83c, 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 2381 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 2382 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 2383 0x908, 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 2384 0xa1c, 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 2385 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 2386 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 2387 0xc50, 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 2388 0xc74, 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 2389 0xc98, 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 2390 0xcbc, 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 2391 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 2392 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 2393 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 2394 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 2395 0xe18, 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 2396 0xe48, 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 2397 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 2398 0xed4, 0xed8, 0xedc, 0xee0, 0xeec, 0xee8, 0xf14, 0xf4c, 0xf00 2399 }; 2400 2401 static const uint32_t rtl8188ru_bb_vals[] = { 2402 0x0011800d, 0x00ffdb83, 0x000c0004, 0x80040000, 0x00000001, 2403 0x0000fc00, 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 2404 0x00000000, 0x01000100, 0x00390204, 0x00000000, 0x00000000, 2405 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010000, 2406 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 2407 0x569a569a, 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 2408 0x32323200, 0x03000300, 0x22004000, 0x00000808, 0x00ffc3f1, 2409 0xc0083070, 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 2410 0xfffffffe, 0x40302010, 0x00706050, 0x00000000, 0x00000023, 2411 0x00000000, 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 2412 0x2e68120f, 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 2413 0x15160000, 0x070b0f12, 0x00000104, 0x00d30000, 0x101fbf00, 2414 0x00000007, 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 2415 0x08800000, 0x40000100, 0x08800000, 0x40000100, 0x00000000, 2416 0x00000000, 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 2417 0x49795994, 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 2418 0x007f037f, 0x6954342e, 0x43bc0094, 0x6954342f, 0x433c0094, 2419 0x00000000, 0x5116848b, 0x47c00bff, 0x00000036, 0x2c56000d, 2420 0x018610db, 0x0000001f, 0x00b91612, 0x24000090, 0x20f60000, 2421 0x24000090, 0x20200000, 0x00121820, 0x00000000, 0x00121820, 2422 0x00007f7f, 0x00000000, 0x00000080, 0x00000000, 0x00000000, 2423 0x00000000, 0x00000000, 0x00000000, 0x28000000, 0x00000000, 2424 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 2425 0x64b22427, 0x00766932, 0x00222222, 0x00000000, 0x37644302, 2426 0x2f97d40c, 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 2427 0xa0633333, 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 2428 0x80608000, 0x00000000, 0x00027293, 0x00000000, 0x00000000, 2429 0x00000000, 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 2430 0x30032064, 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 2431 0x1812362e, 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 2432 0x03902a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 2433 0x00000000, 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 2434 0x01007c00, 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 2435 0x10008c1f, 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 2436 0x631b25a0, 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 2437 0x081b25a0, 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 2438 0x631b25a0, 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 2439 0x31555448, 0x00000003, 0x00000000, 0x00000300 2440 }; 2441 2442 static const uint32_t rtl8188ru_agc_vals[] = { 2443 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 2444 0x7b050001, 0x7b060001, 0x7b070001, 0x7b080001, 0x7a090001, 2445 0x790a0001, 0x780b0001, 0x770c0001, 0x760d0001, 0x750e0001, 2446 0x740f0001, 0x73100001, 0x72110001, 0x71120001, 0x70130001, 2447 0x6f140001, 0x6e150001, 0x6d160001, 0x6c170001, 0x6b180001, 2448 0x6a190001, 0x691a0001, 0x681b0001, 0x671c0001, 0x661d0001, 2449 0x651e0001, 0x641f0001, 0x63200001, 0x62210001, 0x61220001, 2450 0x60230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 2451 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 2452 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 2453 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 2454 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 2455 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 2456 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 2457 0x7b460001, 0x7b470001, 0x7b480001, 0x7a490001, 0x794a0001, 2458 0x784b0001, 0x774c0001, 0x764d0001, 0x754e0001, 0x744f0001, 2459 0x73500001, 0x72510001, 0x71520001, 0x70530001, 0x6f540001, 2460 0x6e550001, 0x6d560001, 0x6c570001, 0x6b580001, 0x6a590001, 2461 0x695a0001, 0x685b0001, 0x675c0001, 0x665d0001, 0x655e0001, 2462 0x645f0001, 0x63600001, 0x62610001, 0x61620001, 0x60630001, 2463 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 2464 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 2465 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 2466 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 2467 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 2468 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 2469 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 2470 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 2471 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 2472 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 2473 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 2474 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 2475 }; 2476 2477 static const struct r92c_bb_prog rtl8188ru_bb_prog = { 2478 nitems(rtl8188ru_bb_regs), 2479 rtl8188ru_bb_regs, 2480 rtl8188ru_bb_vals, 2481 nitems(rtl8188ru_agc_vals), 2482 rtl8188ru_agc_vals 2483 }; 2484 2485 /* 2486 * RTL8723AE and RTL8723AU. 2487 */ 2488 2489 static const uint16_t rtl8723a_bb_regs[] = { 2490 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 0x81c, 0x820, 2491 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 0x840, 0x844, 2492 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 0x860, 0x864, 0x868, 2493 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 0x884, 0x888, 0x88c, 2494 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 0x908, 0x90c, 0xa00, 2495 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 0xa20, 0xa24, 2496 0xa28, 0xa2c, 0xa70, 0xa74, 0xa78, 0xc00, 0xc04, 0xc08, 0xc0c, 2497 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 0xc2c, 0xc30, 2498 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 0xc54, 2499 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 0xc78, 2500 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 0xc9c, 2501 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 0xcc0, 2502 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 0xce0, 0xce4, 2503 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 0xd14, 0xd18, 2504 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 0xd48, 0xd4c, 2505 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 0xd6c, 0xd70, 2506 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 0xe1c, 2507 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 0xe4c, 2508 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 0xe74, 2509 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4, 0xed8, 2510 0xedc, 0xee0, 0xeec, 0xf14, 0xf4c, 0xf00 2511 }; 2512 2513 static const uint32_t rtl8723a_bb_vals[] = { 2514 0x80040000, 0x00000003, 0x0000fc00, 0x0000000a, 0x10005388, 2515 0x020c3d10, 0x02200385, 0x00000000, 0x01000100, 0x00390004, 2516 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 2517 0x00000000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, 2518 0x00000000, 0x00000000, 0x569a569a, 0x001b25a4, 0x66f60110, 2519 0x061f0130, 0x00000000, 0x32323200, 0x07000760, 0x22004000, 2520 0x00000808, 0x00000000, 0xc0083070, 0x000004d5, 0x00000000, 2521 0xccc000c0, 0x00000800, 0xfffffffe, 0x40302010, 0x00706050, 2522 0x00000000, 0x00000023, 0x00000000, 0x81121111, 0x00d047c8, 2523 0x80ff000c, 0x8c838300, 0x2e68120f, 0x9500bb78, 0x11144028, 2524 0x00881117, 0x89140f00, 0x1a1b0000, 0x090e1317, 0x00000204, 2525 0x00d30000, 0x101fbf00, 0x00000007, 0x00000900, 0x48071d40, 2526 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 0x40000100, 2527 0x08800000, 0x40000100, 0x00000000, 0x00000000, 0x00000000, 2528 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 0x0a97971c, 2529 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 0x69543420, 2530 0x43bc0094, 0x69543420, 0x433c0094, 0x00000000, 0x7116848b, 2531 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 0x0000001f, 2532 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 0x20200000, 2533 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 0x00000000, 2534 0x00000080, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 2535 0x00000000, 0x28000000, 0x00000000, 0x00000000, 0x00000000, 2536 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 0x00766932, 2537 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 0x00080740, 2538 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 0x3333bc43, 2539 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 0x00000000, 2540 0x00027293, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 2541 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 0x4653de68, 2542 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 0x322c2220, 2543 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 0x2a2a2a2a, 2544 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 0x1000dc1f, 2545 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 0x01004800, 2546 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 0x02140102, 2547 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 0x631b25a0, 2548 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x631b25a0, 2549 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 2550 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 0x00000000, 2551 0x00000300 2552 }; 2553 2554 static const struct r92c_bb_prog rtl8723a_bb_prog = { 2555 nitems(rtl8723a_bb_regs), 2556 rtl8723a_bb_regs, 2557 rtl8723a_bb_vals, 2558 nitems(rtl8192ce_agc_vals), 2559 rtl8192ce_agc_vals 2560 }; 2561 2562 /* 2563 * RF initialization values. 2564 */ 2565 struct r92c_rf_prog { 2566 int count; 2567 const uint8_t *regs; 2568 const uint32_t *vals; 2569 }; 2570 2571 /* 2572 * RTL8192CU and RTL8192CE-VAU. 2573 */ 2574 static const uint8_t rtl8192ce_rf1_regs[] = { 2575 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 2576 0x0f, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 2577 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2a, 0x2b, 2578 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 2579 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 2580 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 2581 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 2582 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 2583 0x2c, 0x2a, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 2584 0x11, 0x10, 0x11, 0x10, 0x11, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 2585 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 2586 0x14, 0x14, 0x15, 0x15, 0x15, 0x15, 0x16, 0x16, 0x16, 0x16, 0x00, 2587 0x18, 0xfe, 0xfe, 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 2588 }; 2589 2590 static const uint32_t rtl8192ce_rf1_vals[] = { 2591 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 2592 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 2593 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 2594 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 2595 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 2596 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 2597 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 2598 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 2599 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 2600 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 2601 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 2602 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 2603 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 2604 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 2605 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 2606 0x71000, 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 2607 0x18493, 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 2608 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 2609 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 2610 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 2611 0x30159 2612 }; 2613 2614 static const uint8_t rtl8192ce_rf2_regs[] = { 2615 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 2616 0x0f, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 2617 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 0x14, 0x14, 0x15, 0x15, 2618 0x15, 0x15, 0x16, 0x16, 0x16, 0x16 2619 }; 2620 2621 static const uint32_t rtl8192ce_rf2_vals[] = { 2622 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 2623 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x32000, 0x71000, 2624 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 0x18493, 2625 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 0x1944c, 2626 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 0xcf424, 2627 0xe0330, 0xa0330, 0x60330, 0x20330 2628 }; 2629 2630 static const struct r92c_rf_prog rtl8192ce_rf_prog[] = { 2631 { 2632 nitems(rtl8192ce_rf1_regs), 2633 rtl8192ce_rf1_regs, 2634 rtl8192ce_rf1_vals 2635 }, 2636 { 2637 nitems(rtl8192ce_rf2_regs), 2638 rtl8192ce_rf2_regs, 2639 rtl8192ce_rf2_vals 2640 } 2641 }; 2642 2643 /* 2644 * RTL8188CE-VAU. 2645 */ 2646 static const uint32_t rtl8188ce_rf_vals[] = { 2647 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 2648 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 2649 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 2650 0x00000, 0x01558, 0x00060, 0x00483, 0x4f200, 0xec7d9, 0x577c0, 2651 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 2652 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 2653 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 2654 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 2655 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 2656 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 2657 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 2658 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 2659 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 2660 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 2661 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 2662 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 2663 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 2664 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 2665 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 2666 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 2667 0x30159 2668 }; 2669 2670 static const struct r92c_rf_prog rtl8188ce_rf_prog[] = { 2671 { 2672 nitems(rtl8192ce_rf1_regs), 2673 rtl8192ce_rf1_regs, 2674 rtl8188ce_rf_vals 2675 } 2676 }; 2677 2678 2679 /* 2680 * RTL8188CU. 2681 */ 2682 static const uint32_t rtl8188cu_rf_vals[] = { 2683 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 2684 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 2685 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 2686 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 2687 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 2688 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 2689 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 2690 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 2691 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 2692 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 2693 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 2694 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 2695 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 2696 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 2697 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 2698 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 2699 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 2700 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 2701 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 2702 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 2703 0x30159 2704 }; 2705 2706 static const struct r92c_rf_prog rtl8188cu_rf_prog[] = { 2707 { 2708 nitems(rtl8192ce_rf1_regs), 2709 rtl8192ce_rf1_regs, 2710 rtl8188cu_rf_vals 2711 } 2712 }; 2713 2714 /* 2715 * RTL8192EE and RTL8192EU. 2716 */ 2717 static const uint8_t rtl8192e_rf_regs[] = { 2718 0x7f, 0x81, 0x00, 0x08, 0x18, 0x19, 0x1b, 0x1e, 0x1f, 0x2f, 0x3f, 2719 0x42, 0x57, 0x58, 0x67, 0x83, 0xb0, 0xb1, 0xb2, 0xb4, 0xb5, 0xb6, 2720 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, 0xc0, 0xc1, 2721 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0x1c, 0xdf, 2722 0xef, 0x51, 0x52, 0x53, 0x56, 0x35, 0x35, 0x35, 0x36, 0x36, 0x36, 2723 0x36, 0x18, 0x5a, 0x19, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 2724 0x34, 0x34, 0x34, 0x34, 0x00, 0x84, 0x86, 0x87, 0x8e, 0x8f, 0xef, 2725 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 2726 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0xef, 0xfe, 0x18, 0xfe, 0xfe, 0xfe, 2727 0xfe, 0x1e, 0x1f, 0x00 2728 }; 2729 2730 static const uint32_t rtl8192e_rf_vals[] = { 2731 0x00082, 0x3fc00, 0x30000, 0x08400, 0x00407, 0x00012, 0x0394c, 2732 0x80009, 0x00880, 0x1a060, 0x00000, 0x060c0, 0xd0000, 0xbe180, 2733 0x01552, 0x00000, 0xff9f1, 0x55418, 0x8cc00, 0x43083, 0x08166, 2734 0x0803e, 0x1c69f, 0x0407f, 0x90001, 0x40001, 0x00400, 0x00078, 2735 0xb3333, 0x33340, 0x00000, 0x05999, 0x09999, 0x02400, 0x00009, 2736 0x40c91, 0x99999, 0x000a3, 0x88820, 0x76c06, 0x00000, 0x80000, 2737 0x00000, 0x00180, 0x001a0, 0x69545, 0x7e45e, 0x00071, 0x51ff3, 2738 0x000a8, 0x001e2, 0x002a8, 0x01c24, 0x09c24, 0x11c24, 0x19c24, 2739 0x00c07, 0x48000, 0x739d0, 0x0add7, 0x09dd4, 0x08dd1, 0x07dce, 2740 0x06dcb, 0x05dc8, 0x04dc5, 0x034cc, 0x0244f, 0x0144c, 0x00014, 2741 0x30159, 0x68180, 0x0014e, 0x49f80, 0x65540, 0x88000, 0x020a0, 2742 0xf02b0, 0xef7b0, 0xd4fb0, 0xcf060, 0xb0090, 0xa0080, 0x90080, 2743 0x8f780, 0x78730, 0x60fb0, 0x5ffa0, 0x40620, 0x37090, 0x20080, 2744 0x1f060, 0x0ffb0, 0x000a0, 0x00000, 0x0fc07, 0x00000, 0x00000, 2745 0x00000, 0x00000, 0x00001, 0x80000, 0x33e70 2746 }; 2747 2748 static const uint8_t rtl8192e_rf2_regs[] = { 2749 0x7f, 0x81, 0x00, 0x08, 0x18, 0x19, 0x1b, 0x1e, 0x1f, 0x2f, 0x3f, 2750 0x42, 0x57, 0x58, 0x67, 0x7f, 0x81, 0x83, 0x1c, 0xdf, 0xef, 0x51, 2751 0x52, 0x53, 0x56, 0x35, 0x35, 0x35, 0x36, 0x36, 0x36, 0x36, 0x18, 2752 0x5a, 0x19, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 2753 0x34, 0x34, 0x00, 0x84, 0x86, 0x87, 0x8e, 0x8f, 0xef, 0x3b, 0x3b, 2754 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 2755 0x3b, 0x3b, 0x3b, 0xef, 0x00, 0xfe, 0xfe, 0xfe, 0xfe, 0x1e, 0x1f, 2756 0x00 2757 }; 2758 2759 static const uint32_t rtl8192e_rf2_vals[] = { 2760 0x00082, 0x3fc00, 0x30000, 0x08400, 0x00407, 0x00012, 0x0394c, 2761 0x80009, 0x00880, 0x1a060, 0x00000, 0x060c0, 0xd0000, 0xbe180, 2762 0x01552, 0x00082, 0x3f000, 0x00000, 0x00000, 0x00180, 0x001a0, 2763 0x69545, 0x7e42e, 0x00071, 0x51ff3, 0x000a8, 0x001e0, 0x002a8, 2764 0x01ca8, 0x09c24, 0x11c24, 0x19c24, 0x00c07, 0x48000, 0x739d0, 2765 0x0add7, 0x09dd4, 0x08dd1, 0x07dce, 0x06dcb, 0x05dc8, 0x04dc5, 2766 0x034cc, 0x0244f, 0x0144c, 0x00014, 0x30159, 0x68180, 0x000ce, 2767 0x49f80, 0x65540, 0x88000, 0x020a0, 0xf02b0, 0xef7b0, 0xd4fb0, 2768 0xcf060, 0xb0090, 0xa0080, 0x90080, 0x8f780, 0x78730, 0x60fb0, 2769 0x5ffa0, 0x40620, 0x37090, 0x20080, 0x1f060, 0x0ffb0, 0x000a0, 2770 0x10159, 0x00000, 0x00000, 0x00000, 0x00000, 0x00001, 0x80000, 2771 0x33e70 2772 }; 2773 2774 static const struct r92c_rf_prog rtl8192e_rf_prog[] = { 2775 { 2776 nitems(rtl8192e_rf_regs), 2777 rtl8192e_rf_regs, 2778 rtl8192e_rf_vals 2779 }, 2780 { 2781 nitems(rtl8192e_rf2_regs), 2782 rtl8192e_rf2_regs, 2783 rtl8192e_rf2_vals 2784 } 2785 }; 2786 2787 /* 2788 * RTL8188EU. 2789 */ 2790 static const uint8_t rtl8188eu_rf_regs[] = { 2791 0x00, 0x08, 0x18, 0x19, 0x1e, 0x1f, 0x2f, 0x3f, 0x42, 0x57, 0x58, 2792 0x67, 0x83, 0xb0, 0xb1, 0xb2, 0xb4, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 2793 0xbb, 0xbf, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 2794 0xdf, 0xef, 0x51, 0x52, 0x53, 0x56, 0x35, 0x35, 0x35, 0x36, 0x36, 2795 0x36, 0x36, 0xb6, 0x18, 0x5a, 0x19, 0x34, 0x34, 0x34, 0x34, 0x34, 2796 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x00, 0x84, 0x86, 0x87, 0x8e, 2797 0x8f, 0xef, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 2798 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0xef, 0x00, 0x18, 0xfe, 2799 0xfe, 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 2800 }; 2801 2802 static const uint32_t rtl8188eu_rf_vals[] = { 2803 0x30000, 0x84000, 0x00407, 0x00012, 0x80009, 0x00880, 0x1a060, 2804 0x00000, 0x060c0, 0xd0000, 0xbe180, 0x01552, 0x00000, 0xff8fc, 2805 0x54400, 0xccc19, 0x43003, 0x4953e, 0x1c718, 0x060ff, 0x80001, 2806 0x40000, 0x00400, 0xc0000, 0x02400, 0x00009, 0x40c91, 0x99999, 2807 0x000a3, 0x88820, 0x76c06, 0x00000, 0x80000, 0x00180, 0x001a0, 2808 0x6b27d, 0x7e49d, 0x00073, 0x51ff3, 0x00086, 0x00186, 0x00286, 2809 0x01c25, 0x09c25, 0x11c25, 0x19c25, 0x48538, 0x00c07, 0x4bd00, 2810 0x739d0, 0x0adf3, 0x09df0, 0x08ded, 0x07dea, 0x06de7, 0x054ee, 2811 0x044eb, 0x034e8, 0x0246b, 0x01468, 0x0006d, 0x30159, 0x68200, 2812 0x000ce, 0x48a00, 0x65540, 0x88000, 0x020a0, 0xf02b0, 0xef7b0, 2813 0xd4fb0, 0xcf060, 0xb0090, 0xa0080, 0x90080, 0x8f780, 0x722b0, 2814 0x6f7b0, 0x54fb0, 0x4f060, 0x30090, 0x20080, 0x10080, 0x0f780, 2815 0x000a0, 0x10159, 0x0f407, 0x00000, 0x00000, 0x80003, 0x00000, 2816 0x00000, 0x00001, 0x80000, 0x33e60 2817 }; 2818 2819 static const struct r92c_rf_prog rtl8188eu_rf_prog[] = { 2820 { 2821 nitems(rtl8188eu_rf_regs), 2822 rtl8188eu_rf_regs, 2823 rtl8188eu_rf_vals 2824 } 2825 }; 2826 2827 /* 2828 * RTL8192EE and RTL8192EU. 2829 */ 2830 static const uint16_t rtl8192e_bb_regs[] = { 2831 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 0x81c, 0x820, 2832 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 0x840, 0x844, 2833 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 0x860, 0x864, 0x868, 2834 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 0x884, 0x888, 0x88c, 2835 0x890, 0x894, 0x898, 0x900, 0x904, 0x908, 0x90c, 0x910, 0x914, 2836 0x918, 0x91c, 0x924, 0x928, 0x92c, 0x930, 0x934, 0x938, 0x93c, 2837 0x940, 0x944, 0x94c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 2838 0xa18, 0xa1c, 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xa78, 2839 0xa7c, 0xa80, 0xb38, 0xc00, 0xc04, 0xc08, 0xc0c, 0xc10, 0xc14, 2840 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 0xc2c, 0xc30, 0xc34, 0xc38, 2841 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 0xc54, 0xc58, 0xc5c, 2842 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 0xc78, 0xc7c, 0xc80, 2843 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 0xc9c, 0xca0, 0xca4, 2844 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 0xcc0, 0xcc4, 0xcc8, 2845 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 0xce0, 0xce4, 0xce8, 0xcec, 2846 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 0xd14, 0xd18, 0xd1c, 0xd2c, 2847 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 0xd48, 0xd4c, 0xd50, 2848 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 0xd6c, 0xd70, 0xd74, 2849 0xd78, 0xd80, 0xd84, 0xd88, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 2850 0xe18, 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 2851 0xe48, 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 2852 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 2853 0xed4, 0xed8, 0xedc, 0xee0, 0xeec, 0xee4, 0xee8, 0xf14, 0xf4c, 2854 0xf00 2855 }; 2856 2857 static const uint32_t rtl8192e_bb_vals[] = { 2858 0x80040000, 0x00000003, 0x0000fc00, 0x0000000a, 0x10001331, 2859 0x020c3d10, 0x02220385, 0x00000000, 0x01000100, 0x00390204, 2860 0x01000100, 0x00390204, 0x32323232, 0x30303030, 0x30303030, 2861 0x30303030, 0x00010000, 0x00010000, 0x28282828, 0x28282828, 2862 0x00000000, 0x00000000, 0x009a009a, 0x01000014, 0x66f60000, 2863 0x061f0000, 0x30303030, 0x30303030, 0x00000000, 0x55004200, 2864 0x08080808, 0x00000000, 0xb0000c1c, 0x00000001, 0x00000000, 2865 0xcc0000c0, 0x00000800, 0xfffffffe, 0x40302010, 0x00000000, 2866 0x00000023, 0x00000000, 0x81121313, 0x806c0001, 0x00000001, 2867 0x00000000, 0x00010000, 0x00000001, 0x00000000, 0x00000000, 2868 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 2869 0x00000000, 0x00000008, 0x00d0c7c8, 0x81ff800c, 0x8c838300, 2870 0x2e68120f, 0x95009b78, 0x1114d028, 0x00881117, 0x89140f00, 2871 0x1a1b0000, 0x090e1317, 0x00000204, 0x00d30000, 0x101fff80, 2872 0x00000007, 0x00000900, 0x225b0606, 0x218075b1, 0x00000000, 2873 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 2874 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 2875 0x00000000, 0x00000000, 0x69e9ac47, 0x469652af, 0x49795994, 2876 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 2877 0x00340020, 0x0080801f, 0x00000020, 0x00248492, 0x00000000, 2878 0x7112848b, 0x47c00bff, 0x00000036, 0x00000600, 0x02013169, 2879 0x0000001f, 0x00b91612, 0x40000100, 0x21f60000, 0x40000100, 2880 0xa0e40000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 2881 0x00000000, 0x000300a0, 0x00000000, 0x00000000, 0x00000000, 2882 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 2883 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 2884 0x00766932, 0x00222222, 0x00040000, 0x77644302, 0x2f97d40c, 2885 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 2886 0x3333bc43, 0x7a8f5b6b, 0x0000007f, 0xcc979975, 0x00000000, 2887 0x80608000, 0x00000000, 0x00127353, 0x00000000, 0x00000000, 2888 0x00000000, 0x00000000, 0x6437140a, 0x00000000, 0x00000282, 2889 0x30032064, 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 2890 0x1812362e, 0x322c2220, 0x000e3c24, 0x01081008, 0x00000800, 2891 0xf0b50000, 0x30303030, 0x30303030, 0x03903030, 0x30303030, 2892 0x30303030, 0x30303030, 0x30303030, 0x00000000, 0x1000dc1f, 2893 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 0x01004800, 2894 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 0x02140102, 2895 0x28160d05, 0x00000008, 0x0fc05656, 0x03c09696, 0x03c09696, 2896 0x0c005656, 0x0c005656, 0x0c005656, 0x0c005656, 0x03c09696, 2897 0x0c005656, 0x03c09696, 0x03c09696, 0x03c09696, 0x03c09696, 2898 0x0000d6d6, 0x0000d6d6, 0x0fc01616, 0xb0000c1c, 0x00000001, 2899 0x00000003, 0x00000000, 0x00000300 2900 }; 2901 2902 static const uint32_t rtl8192eu_agc_vals[] = { 2903 0xfb000001, 0xfb010001, 0xfb020001, 0xfb030001, 0xfb040001, 2904 0xfb050001, 0xfb060001, 0xfa070001, 0xf9080001, 0xf8090001, 2905 0xf70a0001, 0xf60b0001, 0xf50c0001, 0xf40d0001, 0xf30e0001, 2906 0xf20f0001, 0xf1100001, 0xf0110001, 0xef120001, 0xee130001, 2907 0xed140001, 0xec150001, 0xeb160001, 0xea170001, 0xcd180001, 2908 0xcc190001, 0xcb1a0001, 0xca1b0001, 0xc91c0001, 0xc81d0001, 2909 0x071e0001, 0x061f0001, 0x05200001, 0x04210001, 0x03220001, 2910 0xaa230001, 0xa9240001, 0xa8250001, 0xa7260001, 0xa6270001, 2911 0x85280001, 0x84290001, 0x832a0001, 0x252b0001, 0x242c0001, 2912 0x232d0001, 0x222e0001, 0x672f0001, 0x66300001, 0x65310001, 2913 0x64320001, 0x63330001, 0x62340001, 0x61350001, 0x45360001, 2914 0x44370001, 0x43380001, 0x42390001, 0x413a0001, 0x403b0001, 2915 0x403c0001, 0x403d0001, 0x403e0001, 0x403f0001, 0xfb400001, 2916 0xfb410001, 0xfb420001, 0xfb430001, 0xfb440001, 0xfb450001, 2917 0xfb460001, 0xfa470001, 0xf9480001, 0xf8490001, 0xf74a0001, 2918 0xf64b0001, 0xf54c0001, 0xf44d0001, 0xf34e0001, 0xf24f0001, 2919 0xf1500001, 0xf0510001, 0xef520001, 0xee530001, 0xed540001, 2920 0xec550001, 0xeb560001, 0xea570001, 0xe9580001, 0xe8590001, 2921 0xe75a0001, 0xe65b0001, 0xe55c0001, 0xe45d0001, 0xe35e0001, 2922 0xe25f0001, 0xe1600001, 0x8a610001, 0x89620001, 0x88630001, 2923 0x87640001, 0x86650001, 0x85660001, 0x84670001, 0x83680001, 2924 0x82690001, 0x6b6a0001, 0x6a6b0001, 0x696c0001, 0x686d0001, 2925 0x676e0001, 0x666f0001, 0x65700001, 0x64710001, 0x63720001, 2926 0x62730001, 0x61740001, 0x49750001, 0x48760001, 0x47770001, 2927 0x46780001, 0x45790001, 0x447a0001, 0x437b0001, 0x427c0001, 2928 0x417d0001, 0x407e0001, 0x407f0001 2929 }; 2930 2931 static const struct r92c_bb_prog rtl8192eu_bb_prog = { 2932 nitems(rtl8192e_bb_regs), 2933 rtl8192e_bb_regs, 2934 rtl8192e_bb_vals, 2935 nitems(rtl8192eu_agc_vals), 2936 rtl8192eu_agc_vals 2937 }; 2938 2939 2940 /* 2941 * RTL8188RU. 2942 */ 2943 static const uint32_t rtl8188ru_rf_vals[] = { 2944 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb0, 2945 0x54867, 0x8992e, 0x0e529, 0x39ce7, 0x00451, 0x00000, 0x00255, 2946 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 2947 0x0083c, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x977c0, 2948 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 2949 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 2950 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 2951 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 2952 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 2953 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 2954 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 2955 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 2956 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 2957 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 2958 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0xd8000, 2959 0x90000, 0x51000, 0x12000, 0x28fb4, 0x24fa8, 0x207a4, 0x1c798, 2960 0x183a4, 0x14398, 0x101a4, 0x0c198, 0x080a4, 0x04098, 0x00014, 2961 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 2962 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 2963 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 2964 0x30159 2965 }; 2966 2967 static const struct r92c_rf_prog rtl8188ru_rf_prog[] = { 2968 { 2969 nitems(rtl8192ce_rf1_regs), 2970 rtl8192ce_rf1_regs, 2971 rtl8188ru_rf_vals 2972 } 2973 }; 2974 2975 /* 2976 * RTL8723AE and RTL8723AU. 2977 */ 2978 2979 static const uint8_t rtl8723a_rf_regs[] = { 2980 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 2981 0x0f, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 2982 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2a, 0x2b, 2983 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 2984 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 2985 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 2986 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 2987 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 2988 0x2c, 0x2a, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 2989 0x11, 0x10, 0x11, 0x10, 0x11, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 2990 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 2991 0x14, 0x14, 0x15, 0x15, 0x15, 0x15, 0x16, 0x16, 0x16, 0x16, 0x00, 2992 0x18, 0xfe, 0xfe, 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 2993 }; 2994 2995 static const uint32_t rtl8723a_rf_vals[] = { 2996 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1a3f1, 2997 0x14787, 0x896fe, 0x0e02c, 0x39ce7, 0x00451, 0x00000, 0x30355, 2998 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 2999 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x57730, 3000 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 3001 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 3002 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 3003 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 3004 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 3005 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 3006 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 3007 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 3008 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 3009 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 3010 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 3011 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 3012 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 3013 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f407, 0x8f424, 3014 0xcf424, 0x00339, 0x40339, 0x80339, 0xc0336, 0x10159, 0x0f401, 3015 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 3016 0x30159 3017 }; 3018 3019 static const struct r92c_rf_prog rtl8723a_rf_prog[] = { 3020 { 3021 nitems(rtl8723a_rf_regs), 3022 rtl8723a_rf_regs, 3023 rtl8723a_rf_vals 3024 } 3025 }; 3026 3027 struct r92c_txpwr { 3028 uint8_t pwr[3][28]; 3029 }; 3030 3031 /* 3032 * Per RF chain/group/rate Tx gain values. 3033 */ 3034 static const struct r92c_txpwr rtl8192cu_txagc[] = { 3035 { { /* Chain 0. */ 3036 { /* Group 0. */ 3037 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 3038 0x0c, 0x0c, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* OFDM6~54. */ 3039 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* MCS0~7. */ 3040 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02 /* MCS8~15. */ 3041 }, 3042 { /* Group 1. */ 3043 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 3044 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 3045 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 3046 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 3047 }, 3048 { /* Group 2. */ 3049 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 3050 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ 3051 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 3052 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 3053 } 3054 } }, 3055 { { /* Chain 1. */ 3056 { /* Group 0. */ 3057 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 3058 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 3059 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 3060 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 3061 }, 3062 { /* Group 1. */ 3063 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 3064 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 3065 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 3066 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 3067 }, 3068 { /* Group 2. */ 3069 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 3070 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ 3071 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 3072 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 3073 } 3074 } } 3075 }; 3076 3077 static const struct r92c_txpwr rtl8188ru_txagc[] = { 3078 { { /* Chain 0. */ 3079 { /* Group 0. */ 3080 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 3081 0x08, 0x08, 0x08, 0x06, 0x06, 0x04, 0x04, 0x00, /* OFDM6~54. */ 3082 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00, /* MCS0~7. */ 3083 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00 /* MCS8~15. */ 3084 }, 3085 { /* Group 1. */ 3086 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 3087 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 3088 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 3089 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 3090 }, 3091 { /* Group 2. */ 3092 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 3093 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 3094 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 3095 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 3096 } 3097 } } 3098 }; 3099