xref: /openbsd/sys/dev/ic/smc93cx6.c (revision 1821443c)
1 /*	$OpenBSD: smc93cx6.c,v 1.16 2003/08/15 23:41:47 fgsch Exp $	*/
2 /* $FreeBSD: sys/dev/aic7xxx/93cx6.c,v 1.5 2000/01/07 23:08:17 gibbs Exp $ */
3 /*
4  * Interface for the 93C66/56/46/26/06 serial eeprom parts.
5  *
6  * Copyright (c) 1995, 1996 Daniel M. Eischen
7  * All rights reserved.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice immediately at the beginning of the file, without modification,
14  *    this list of conditions, and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. Absolutely no warranty of function or purpose is made by the author
19  *    Daniel M. Eischen.
20  * 4. Modifications may be freely made to this file if the above conditions
21  *    are met.
22  */
23 
24 /*
25  *   The instruction set of the 93C66/56/46/26/06 chips are as follows:
26  *
27  *               Start  OP	    *
28  *     Function   Bit  Code  Address**  Data     Description
29  *     -------------------------------------------------------------------
30  *     READ        1    10   A5 - A0             Reads data stored in memory,
31  *                                               starting at specified address
32  *     EWEN        1    00   11XXXX              Write enable must precede
33  *                                               all programming modes
34  *     ERASE       1    11   A5 - A0             Erase register A5A4A3A2A1A0
35  *     WRITE       1    01   A5 - A0   D15 - D0  Writes register
36  *     ERAL        1    00   10XXXX              Erase all registers
37  *     WRAL        1    00   01XXXX    D15 - D0  Writes to all registers
38  *     EWDS        1    00   00XXXX              Disables all programming
39  *                                               instructions
40  *     *Note: A value of X for address is a don't care condition.
41  *    **Note: There are 8 address bits for the 93C56/66 chips unlike
42  *	      the 93C46/26/06 chips which have 6 address bits.
43  *
44  *   The 93C46 has a four wire interface: clock, chip select, data in, and
45  *   data out.  In order to perform one of the above functions, you need
46  *   to enable the chip select for a clock period (typically a minimum of
47  *   1 usec, with the clock high and low a minimum of 750 and 250 nsec
48  *   respectively).  While the chip select remains high, you can clock in
49  *   the instructions (above) starting with the start bit, followed by the
50  *   OP code, Address, and Data (if needed).  For the READ instruction, the
51  *   requested 16-bit register contents is read from the data out line but
52  *   is preceded by an initial zero (leading 0, followed by 16-bits, MSB
53  *   first).  The clock cycling from low to high initiates the next data
54  *   bit to be sent from the chip.
55  *
56  */
57 
58 #include <sys/param.h>
59 #include <sys/systm.h>
60 #include <machine/bus.h>
61 #include <dev/ic/smc93cx6var.h>
62 
63 /*
64  * Right now, we only have to read the SEEPROM.  But we make it easier to
65  * add other 93Cx6 functions.
66  */
67 static struct seeprom_cmd {
68   	unsigned char len;
69  	unsigned char bits[9];
70 } seeprom_read = {3, {1, 1, 0}};
71 
72 /*
73  * Wait for the SEERDY to go high; about 800 ns.
74  */
75 #define CLOCK_PULSE(sd, rdy)				\
76 	while ((SEEPROM_STATUS_INB(sd) & rdy) == 0) {	\
77 		;  /* Do nothing */			\
78 	}						\
79 	(void)SEEPROM_INB(sd);	/* Clear clock */
80 
81 /*
82  * Send a START condition and the given command
83  */
84 static void
85 send_seeprom_cmd(struct seeprom_descriptor *sd, struct seeprom_cmd *cmd)
86 {
87 	u_int8_t temp;
88 	int i = 0;
89 
90 	/* Send chip select for one clock cycle. */
91 	temp = sd->sd_MS ^ sd->sd_CS;
92 	SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
93 	CLOCK_PULSE(sd, sd->sd_RDY);
94 
95 	for (i = 0; i < cmd->len; i++) {
96 		if (cmd->bits[i] != 0)
97 			temp ^= sd->sd_DO;
98 		SEEPROM_OUTB(sd, temp);
99 		CLOCK_PULSE(sd, sd->sd_RDY);
100 		SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
101 		CLOCK_PULSE(sd, sd->sd_RDY);
102 		if (cmd->bits[i] != 0)
103 			temp ^= sd->sd_DO;
104 	}
105 }
106 
107 /*
108  * Clear CS put the chip in the reset state, where it can wait for new commands.
109  */
110 static void
111 reset_seeprom(struct seeprom_descriptor *sd)
112 {
113 	u_int8_t temp;
114 
115 	temp = sd->sd_MS;
116 	SEEPROM_OUTB(sd, temp);
117 	CLOCK_PULSE(sd, sd->sd_RDY);
118 	SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
119 	CLOCK_PULSE(sd, sd->sd_RDY);
120 	SEEPROM_OUTB(sd, temp);
121 	CLOCK_PULSE(sd, sd->sd_RDY);
122 }
123 
124 /*
125  * Read the serial EEPROM and returns 1 if successful and 0 if
126  * not successful.
127  */
128 int
129 read_seeprom(sd, buf, start_addr, count)
130 	struct seeprom_descriptor *sd;
131 	u_int16_t *buf;
132 	bus_size_t start_addr;
133 	bus_size_t count;
134 {
135 	int i = 0;
136 	u_int k = 0;
137 	u_int16_t v;
138 	u_int8_t temp;
139 
140 	/*
141 	 * Read the requested registers of the seeprom.  The loop
142 	 * will range from 0 to count-1.
143 	 */
144 	for (k = start_addr; k < count + start_addr; k++) {
145 		/*
146 		 * Now we're ready to send the read command followed by the
147 		 * address of the 16-bit register we want to read.
148 		 */
149 		send_seeprom_cmd(sd, &seeprom_read);
150 
151 		/* Send the 6 or 8 bit address (MSB first, LSB last). */
152 		temp = sd->sd_MS ^ sd->sd_CS;
153 		for (i = (sd->sd_chip - 1); i >= 0; i--) {
154 			if ((k & (1 << i)) != 0)
155 				temp ^= sd->sd_DO;
156 			SEEPROM_OUTB(sd, temp);
157 			CLOCK_PULSE(sd, sd->sd_RDY);
158 			SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
159 			CLOCK_PULSE(sd, sd->sd_RDY);
160 			if ((k & (1 << i)) != 0)
161 				temp ^= sd->sd_DO;
162 		}
163 
164 		/*
165 		 * Now read the 16 bit register.  An initial 0 precedes the
166 		 * register contents which begins with bit 15 (MSB) and ends
167 		 * with bit 0 (LSB).  The initial 0 will be shifted off the
168 		 * top of our word as we let the loop run from 0 to 16.
169 		 */
170 		v = 0;
171 		for (i = 16; i >= 0; i--) {
172 			SEEPROM_OUTB(sd, temp);
173 			CLOCK_PULSE(sd, sd->sd_RDY);
174 			v <<= 1;
175 			if (SEEPROM_DATA_INB(sd) & sd->sd_DI)
176 				v |= 1;
177 			SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
178 			CLOCK_PULSE(sd, sd->sd_RDY);
179 		}
180 
181 		buf[k - start_addr] = v;
182 
183 		/* Reset the chip select for the next command cycle. */
184 		reset_seeprom(sd);
185 	}
186 #ifdef AHC_DUMP_EEPROM
187 	printf("\nSerial EEPROM:\n\t");
188 	for (k = 0; k < count; k = k + 1) {
189 		if (((k % 8) == 0) && (k != 0)) {
190 			printf ("\n\t");
191 		}
192 		printf (" 0x%x", buf[k]);
193 	}
194 	printf ("\n");
195 #endif
196 	return (1);
197 }
198