1 /* $OpenBSD: tcic2.c,v 1.13 2019/12/31 10:05:32 mpi Exp $ */ 2 /* $NetBSD: tcic2.c,v 1.3 2000/01/13 09:38:17 joda Exp $ */ 3 4 #undef TCICDEBUG 5 6 /* 7 * Copyright (c) 1998, 1999 Christoph Badura. All rights reserved. 8 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Marc Horowitz. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/extent.h> 40 #include <sys/malloc.h> 41 #include <sys/kthread.h> 42 43 #include <machine/bus.h> 44 #include <machine/intr.h> 45 46 #include <dev/pcmcia/pcmciareg.h> 47 #include <dev/pcmcia/pcmciavar.h> 48 49 #include <dev/ic/tcic2reg.h> 50 #include <dev/ic/tcic2var.h> 51 52 #ifdef TCICDEBUG 53 int tcic_debug = 1; 54 #define DPRINTF(arg) if (tcic_debug) printf arg; 55 #else 56 #define DPRINTF(arg) 57 #endif 58 59 /* 60 * Individual drivers will allocate their own memory and io regions. Memory 61 * regions must be a multiple of 4k, aligned on a 4k boundary. 62 */ 63 64 #define TCIC_MEM_ALIGN TCIC_MEM_PAGESIZE 65 66 void tcic_attach_socket(struct tcic_handle *); 67 void tcic_init_socket(struct tcic_handle *); 68 69 int tcic_submatch(struct device *, void *, void *); 70 int tcic_print(void *arg, const char *pnp); 71 int tcic_intr_socket(struct tcic_handle *); 72 73 void tcic_attach_card(struct tcic_handle *); 74 void tcic_detach_card(struct tcic_handle *, int); 75 void tcic_deactivate_card(struct tcic_handle *); 76 77 void tcic_chip_do_mem_map(struct tcic_handle *, int); 78 void tcic_chip_do_io_map(struct tcic_handle *, int); 79 80 void tcic_create_event_thread(void *); 81 void tcic_event_thread(void *); 82 83 void tcic_queue_event(struct tcic_handle *, int); 84 85 struct cfdriver tcic_cd = { 86 NULL, "tcic", DV_DULL 87 }; 88 89 /* Map between irq numbers and internal representation */ 90 #if 1 91 int tcic_irqmap[] = 92 { 0, 0, 0, 3, 4, 5, 6, 7, 0, 0, 10, 1, 0, 0, 14, 0 }; 93 int tcic_valid_irqs = 0x4cf8; 94 #else 95 int tcic_irqmap[] = /* irqs 9 and 6 switched, some ISA cards */ 96 { 0, 0, 0, 3, 4, 5, 0, 7, 0, 6, 10, 1, 0, 0, 14, 0 }; 97 int tcic_valid_irqs = 0x4eb8; 98 #endif 99 100 int tcic_mem_speed = 250; /* memory access time in nanoseconds */ 101 int tcic_io_speed = 165; /* io access time in nanoseconds */ 102 103 /* 104 * Check various reserved and otherwise in their value restricted bits. 105 */ 106 int 107 tcic_check_reserved_bits(iot, ioh) 108 bus_space_tag_t iot; 109 bus_space_handle_t ioh; 110 { 111 int val, auxreg; 112 113 DPRINTF(("tcic: chkrsvd 1\n")); 114 /* R_ADDR bit 30:28 have a restricted range. */ 115 val = (bus_space_read_2(iot, ioh, TCIC_R_ADDR2) & TCIC_SS_MASK) 116 >> TCIC_SS_SHIFT; 117 if (val > 1) 118 return 0; 119 120 DPRINTF(("tcic: chkrsvd 2\n")); 121 /* R_SCTRL bits 6,2,1 are reserved. */ 122 val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL); 123 if (val & TCIC_SCTRL_RSVD) 124 return 0; 125 126 DPRINTF(("tcic: chkrsvd 3\n")); 127 /* R_ICSR bit 2 must be same as bit 3. */ 128 val = bus_space_read_1(iot, ioh, TCIC_R_ICSR); 129 if (((val >> 1) & 1) != ((val >> 2) & 1)) 130 return 0; 131 132 DPRINTF(("tcic: chkrsvd 4\n")); 133 /* R_IENA bits 7,2 are reserved. */ 134 val = bus_space_read_1(iot, ioh, TCIC_R_IENA); 135 if (val & TCIC_IENA_RSVD) 136 return 0; 137 138 DPRINTF(("tcic: chkrsvd 5\n")); 139 /* Some aux registers have reserved bits. */ 140 /* Which are we looking at? */ 141 auxreg = bus_space_read_1(iot, ioh, TCIC_R_MODE) 142 & TCIC_AR_MASK; 143 val = bus_space_read_2(iot, ioh, TCIC_R_AUX); 144 DPRINTF(("tcic: auxreg 0x%02x val 0x%04x\n", auxreg, val)); 145 switch (auxreg) { 146 case TCIC_AR_SYSCFG: 147 if (INVALID_AR_SYSCFG(val)) 148 return 0; 149 break; 150 case TCIC_AR_ILOCK: 151 if (INVALID_AR_ILOCK(val)) 152 return 0; 153 break; 154 case TCIC_AR_TEST: 155 if (INVALID_AR_TEST(val)) 156 return 0; 157 break; 158 } 159 160 DPRINTF(("tcic: chkrsvd 6\n")); 161 /* XXX fails if pcmcia bios is enabled. */ 162 /* Various bits set or not depending if in RESET mode. */ 163 val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL); 164 if (val & TCIC_SCTRL_RESET) { 165 DPRINTF(("tcic: chkrsvd 7\n")); 166 /* Address bits must be 0 */ 167 val = bus_space_read_2(iot, ioh, TCIC_R_ADDR); 168 if (val != 0) 169 return 0; 170 val = bus_space_read_2(iot, ioh, TCIC_R_ADDR2); 171 if (val != 0) 172 return 0; 173 DPRINTF(("tcic: chkrsvd 8\n")); 174 /* EDC bits must be 0 */ 175 val = bus_space_read_2(iot, ioh, TCIC_R_EDC); 176 if (val != 0) 177 return 0; 178 /* We're OK, so take it out of reset. XXX -chb */ 179 bus_space_write_1(iot, ioh, TCIC_R_SCTRL, 0); 180 } 181 else { /* not in RESET mode */ 182 int omode; 183 int val1, val2; 184 DPRINTF(("tcic: chkrsvd 9\n")); 185 /* Programming timers must have expired. */ 186 val = bus_space_read_1(iot, ioh, TCIC_R_SSTAT); 187 if ((val & (TCIC_SSTAT_6US|TCIC_SSTAT_10US|TCIC_SSTAT_PROGTIME)) 188 != (TCIC_SSTAT_6US|TCIC_SSTAT_10US|TCIC_SSTAT_PROGTIME)) 189 return 0; 190 DPRINTF(("tcic: chkrsvd 10\n")); 191 /* 192 * EDC bits should change on read from data space 193 * as long as either EDC or the data are nonzero. 194 */ 195 if ((bus_space_read_2(iot, ioh, TCIC_R_ADDR2) 196 & TCIC_ADDR2_INDREG) != 0) { 197 val1 = bus_space_read_2(iot, ioh, TCIC_R_EDC); 198 val2 = bus_space_read_2(iot, ioh, TCIC_R_DATA); 199 if (val1 | val2) { 200 val1 = bus_space_read_2(iot, ioh, TCIC_R_EDC); 201 if (val1 == val2) 202 return 0; 203 } 204 } 205 DPRINTF(("tcic: chkrsvd 11\n")); 206 /* XXX what does this check? -chb */ 207 omode = bus_space_read_1(iot, ioh, TCIC_R_MODE); 208 val1 = omode ^ TCIC_AR_MASK; 209 bus_space_write_1(iot, ioh, TCIC_R_MODE, val1); 210 val2 = bus_space_read_1(iot, ioh, TCIC_R_MODE); 211 bus_space_write_1(iot, ioh, TCIC_R_MODE, omode); 212 if ( val1 != val2) 213 return 0; 214 } 215 /* All tests passed */ 216 return 1; 217 } 218 219 /* 220 * Read chip ID from AR_ILOCK in test mode. 221 */ 222 int 223 tcic_chipid(iot, ioh) 224 bus_space_tag_t iot; 225 bus_space_handle_t ioh; 226 { 227 unsigned id, otest; 228 229 otest = tcic_read_aux_2(iot, ioh, TCIC_AR_TEST); 230 tcic_write_aux_2(iot, ioh, TCIC_AR_TEST, TCIC_TEST_DIAG); 231 id = tcic_read_aux_2(iot, ioh, TCIC_AR_ILOCK); 232 tcic_write_aux_2(iot, ioh, TCIC_AR_TEST, otest); 233 id &= TCIC_ILOCKTEST_ID_MASK; 234 id >>= TCIC_ILOCKTEST_ID_SHFT; 235 236 /* clear up IRQs inside tcic. XXX -chb */ 237 while (bus_space_read_1(iot, ioh, TCIC_R_ICSR)) 238 bus_space_write_1(iot, ioh, TCIC_R_ICSR, TCIC_ICSR_JAM); 239 240 return id; 241 } 242 /* 243 * Indicate whether the driver can handle the chip. 244 */ 245 int 246 tcic_chipid_known(id) 247 int id; 248 { 249 /* XXX only know how to handle DB86082 -chb */ 250 switch (id) { 251 case TCIC_CHIPID_DB86082_1: 252 case TCIC_CHIPID_DB86082A: 253 case TCIC_CHIPID_DB86082B_ES: 254 case TCIC_CHIPID_DB86082B: 255 case TCIC_CHIPID_DB86084_1: 256 case TCIC_CHIPID_DB86084A: 257 case TCIC_CHIPID_DB86184_1: 258 case TCIC_CHIPID_DB86072_1_ES: 259 case TCIC_CHIPID_DB86072_1: 260 return 1; 261 } 262 263 return 0; 264 } 265 266 char * 267 tcic_chipid_to_string(id) 268 int id; 269 { 270 switch (id) { 271 case TCIC_CHIPID_DB86082_1: 272 return ("Databook DB86082"); 273 case TCIC_CHIPID_DB86082A: 274 return ("Databook DB86082A"); 275 case TCIC_CHIPID_DB86082B_ES: 276 return ("Databook DB86082B-es"); 277 case TCIC_CHIPID_DB86082B: 278 return ("Databook DB86082B"); 279 case TCIC_CHIPID_DB86084_1: 280 return ("Databook DB86084"); 281 case TCIC_CHIPID_DB86084A: 282 return ("Databook DB86084A"); 283 case TCIC_CHIPID_DB86184_1: 284 return ("Databook DB86184"); 285 case TCIC_CHIPID_DB86072_1_ES: 286 return ("Databook DB86072-es"); 287 case TCIC_CHIPID_DB86072_1: 288 return ("Databook DB86072"); 289 } 290 291 return ("Unknown controller"); 292 } 293 /* 294 * Return bitmask of IRQs that the chip can handle. 295 * XXX should be table driven. 296 */ 297 int 298 tcic_validirqs(chipid) 299 int chipid; 300 { 301 switch (chipid) { 302 case TCIC_CHIPID_DB86082_1: 303 case TCIC_CHIPID_DB86082A: 304 case TCIC_CHIPID_DB86082B_ES: 305 case TCIC_CHIPID_DB86082B: 306 case TCIC_CHIPID_DB86084_1: 307 case TCIC_CHIPID_DB86084A: 308 case TCIC_CHIPID_DB86184_1: 309 case TCIC_CHIPID_DB86072_1_ES: 310 case TCIC_CHIPID_DB86072_1: 311 return tcic_valid_irqs; 312 } 313 return 0; 314 } 315 316 void 317 tcic_attach(sc) 318 struct tcic_softc *sc; 319 { 320 int i, reg; 321 322 /* set more chipset-dependent parameters in the softc. */ 323 switch (sc->chipid) { 324 case TCIC_CHIPID_DB86084_1: 325 case TCIC_CHIPID_DB86084A: 326 case TCIC_CHIPID_DB86184_1: 327 sc->pwrena = TCIC_PWR_ENA; 328 break; 329 default: 330 sc->pwrena = 0; 331 break; 332 } 333 334 /* set up global config registers */ 335 reg = TCIC_WAIT_SYNC | TCIC_WAIT_CCLK | TCIC_WAIT_RISING; 336 reg |= (tcic_ns2wscnt(250) & TCIC_WAIT_COUNT_MASK); 337 tcic_write_aux_1(sc->iot, sc->ioh, TCIC_AR_WCTL, TCIC_R_WCTL_WAIT, reg); 338 reg = TCIC_SYSCFG_MPSEL_RI | TCIC_SYSCFG_MCSFULL; 339 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg); 340 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK); 341 reg |= TCIC_ILOCK_HOLD_CCLK; 342 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK, reg); 343 344 /* the TCIC has two sockets */ 345 /* XXX should i check for actual presence of sockets? -chb */ 346 for (i = 0; i < TCIC_NSLOTS; i++) { 347 sc->handle[i].sc = sc; 348 sc->handle[i].sock = i; 349 sc->handle[i].flags = TCIC_FLAG_SOCKETP; 350 sc->handle[i].memwins 351 = sc->chipid == TCIC_CHIPID_DB86082_1 ? 4 : 5; 352 } 353 354 /* establish the interrupt */ 355 reg = tcic_read_1(&sc->handle[0], TCIC_R_IENA); 356 tcic_write_1(&sc->handle[0], TCIC_R_IENA, 357 (reg & ~TCIC_IENA_CFG_MASK) | TCIC_IENA_CFG_HIGH); 358 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG); 359 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, 360 (reg & ~TCIC_SYSCFG_IRQ_MASK) | tcic_irqmap[sc->irq]); 361 362 /* XXX block interrupts? */ 363 364 for (i = 0; i < TCIC_NSLOTS; i++) { 365 /* XXX make more clear what happens here -chb */ 366 tcic_sel_sock(&sc->handle[i]); 367 tcic_write_ind_2(&sc->handle[i], TCIC_IR_SCF1_N(i), 0); 368 tcic_write_ind_2(&sc->handle[i], TCIC_IR_SCF2_N(i), 369 (TCIC_SCF2_MCD|TCIC_SCF2_MWP|TCIC_SCF2_MRDY 370 #if 1 /* XXX explain byte routing issue */ 371 |TCIC_SCF2_MLBAT2|TCIC_SCF2_MLBAT1|TCIC_SCF2_IDBR)); 372 #else 373 |TCIC_SCF2_MLBAT2|TCIC_SCF2_MLBAT1)); 374 #endif 375 tcic_write_1(&sc->handle[i], TCIC_R_MODE, 0); 376 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG); 377 reg &= ~TCIC_SYSCFG_AUTOBUSY; 378 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg); 379 SIMPLEQ_INIT(&sc->handle[i].events); 380 } 381 382 if ((sc->handle[0].flags & TCIC_FLAG_SOCKETP) || 383 (sc->handle[1].flags & TCIC_FLAG_SOCKETP)) { 384 printf("%s: %s has ", sc->dev.dv_xname, 385 tcic_chipid_to_string(sc->chipid)); 386 387 if ((sc->handle[0].flags & TCIC_FLAG_SOCKETP) && 388 (sc->handle[1].flags & TCIC_FLAG_SOCKETP)) 389 printf("sockets A and B\n"); 390 else if (sc->handle[0].flags & TCIC_FLAG_SOCKETP) 391 printf("socket A only\n"); 392 else 393 printf("socket B only\n"); 394 395 } 396 } 397 398 void 399 tcic_attach_sockets(sc) 400 struct tcic_softc *sc; 401 { 402 int i; 403 404 for (i = 0; i < TCIC_NSLOTS; i++) 405 if (sc->handle[i].flags & TCIC_FLAG_SOCKETP) 406 tcic_attach_socket(&sc->handle[i]); 407 } 408 409 void 410 tcic_attach_socket(h) 411 struct tcic_handle *h; 412 { 413 struct pcmciabus_attach_args paa; 414 415 /* initialize the rest of the handle */ 416 417 h->shutdown = 0; 418 h->memalloc = 0; 419 h->ioalloc = 0; 420 h->ih_irq = 0; 421 422 /* now, config one pcmcia device per socket */ 423 424 paa.paa_busname = "pcmcia"; 425 paa.pct = (pcmcia_chipset_tag_t) h->sc->pct; 426 paa.pch = (pcmcia_chipset_handle_t) h; 427 paa.iobase = h->sc->iobase; 428 paa.iosize = h->sc->iosize; 429 430 h->pcmcia = config_found_sm(&h->sc->dev, &paa, tcic_print, 431 tcic_submatch); 432 433 /* if there's actually a pcmcia device attached, initialize the slot */ 434 435 if (h->pcmcia) 436 tcic_init_socket(h); 437 else 438 h->flags &= ~TCIC_FLAG_SOCKETP; 439 } 440 441 void 442 tcic_create_event_thread(arg) 443 void *arg; 444 { 445 struct tcic_handle *h = arg; 446 char name[MAXCOMLEN+1]; 447 const char *cs; 448 449 switch (h->sock) { 450 case 0: 451 cs = "0"; 452 break; 453 case 1: 454 cs = "1"; 455 break; 456 default: 457 panic("tcic_create_event_thread: unknown tcic socket"); 458 } 459 460 snprintf(name, sizeof name, "%s,%s", h->sc->dev.dv_xname, cs); 461 if (kthread_create(tcic_event_thread, h, &h->event_thread, name)) { 462 printf("%s: unable to create event thread for sock 0x%02x\n", 463 h->sc->dev.dv_xname, h->sock); 464 panic("tcic_create_event_thread"); 465 } 466 } 467 468 void 469 tcic_event_thread(arg) 470 void *arg; 471 { 472 struct tcic_handle *h = arg; 473 struct tcic_event *pe; 474 int s; 475 476 while (h->shutdown == 0) { 477 s = splhigh(); 478 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 479 splx(s); 480 tsleep_nsec(&h->events, PWAIT, "tcicev", INFSLP); 481 continue; 482 } 483 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 484 splx(s); 485 486 switch (pe->pe_type) { 487 case TCIC_EVENT_INSERTION: 488 DPRINTF(("%s: insertion event\n", h->sc->dev.dv_xname)); 489 tcic_attach_card(h); 490 break; 491 492 case TCIC_EVENT_REMOVAL: 493 DPRINTF(("%s: removal event\n", h->sc->dev.dv_xname)); 494 tcic_detach_card(h, DETACH_FORCE); 495 break; 496 497 default: 498 panic("tcic_event_thread: unknown event %d", 499 pe->pe_type); 500 } 501 free(pe, M_TEMP, 0); 502 } 503 504 h->event_thread = NULL; 505 506 /* In case parent is waiting for us to exit. */ 507 wakeup(h->sc); 508 509 kthread_exit(0); 510 } 511 512 513 void 514 tcic_init_socket(h) 515 struct tcic_handle *h; 516 { 517 int reg; 518 519 /* select this socket's config registers */ 520 tcic_sel_sock(h); 521 522 /* set up the socket to interrupt on card detect */ 523 reg = tcic_read_ind_2(h, TCIC_IR_SCF2_N(h->sock)); 524 tcic_write_ind_2(h, TCIC_IR_SCF2_N(h->sock), reg & ~TCIC_SCF2_MCD); 525 526 /* enable CD irq in R_IENA */ 527 reg = tcic_read_2(h, TCIC_R_IENA); 528 tcic_write_2(h, TCIC_R_IENA, reg |= TCIC_IENA_CDCHG); 529 530 /* if there's a card there, then attach it. also save sstat */ 531 h->sstat = reg = tcic_read_1(h, TCIC_R_SSTAT) & TCIC_SSTAT_STAT_MASK; 532 if (reg & TCIC_SSTAT_CD) 533 tcic_attach_card(h); 534 } 535 536 int 537 tcic_submatch(parent, match, aux) 538 struct device *parent; 539 void *match; 540 void *aux; 541 { 542 struct cfdata *cf = match; 543 544 struct pcmciabus_attach_args *paa = aux; 545 struct tcic_handle *h = (struct tcic_handle *) paa->pch; 546 547 switch (h->sock) { 548 case 0: 549 if (cf->cf_loc[0 /* PCMCIABUSCF_CONTROLLER */] != 550 -1 /* PCMCIABUSCF_CONTROLLER_DEFAULT */ && 551 cf->cf_loc[0 /* PCMCIABUSCF_CONTROLLER */] != 0) 552 return 0; 553 if (cf->cf_loc[1 /* PCMCIABUSCF_SOCKET */] != 554 -1 /* PCMCIABUSCF_SOCKET_DEFAULT */ && 555 cf->cf_loc[1 /* PCMCIABUSCF_SOCKET */] != 0) 556 return 0; 557 558 break; 559 case 1: 560 if (cf->cf_loc[0 /* PCMCIABUSCF_CONTROLLER */] != 561 -1 /* PCMCIABUSCF_CONTROLLER_DEFAULT */ && 562 cf->cf_loc[0 /* PCMCIABUSCF_CONTROLLER */] != 0) 563 return 0; 564 if (cf->cf_loc[1 /* PCMCIABUSCF_SOCKET */] != 565 -1 /* PCMCIABUSCF_SOCKET_DEFAULT */ && 566 cf->cf_loc[1 /* PCMCIABUSCF_SOCKET */] != 1) 567 return 0; 568 569 break; 570 default: 571 panic("unknown tcic socket"); 572 } 573 574 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 575 } 576 577 int 578 tcic_print(arg, pnp) 579 void *arg; 580 const char *pnp; 581 { 582 struct pcmciabus_attach_args *paa = arg; 583 struct tcic_handle *h = (struct tcic_handle *) paa->pch; 584 585 /* Only "pcmcia"s can attach to "tcic"s... easy. */ 586 if (pnp) 587 printf("pcmcia at %s", pnp); 588 589 switch (h->sock) { 590 case 0: 591 printf(" socket 0"); 592 break; 593 case 1: 594 printf(" socket 1"); 595 break; 596 default: 597 panic("unknown tcic socket"); 598 } 599 return (UNCONF); 600 } 601 602 int 603 tcic_intr(arg) 604 void *arg; 605 { 606 struct tcic_softc *sc = arg; 607 int i, ret = 0; 608 609 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 610 611 for (i = 0; i < TCIC_NSLOTS; i++) 612 if (sc->handle[i].flags & TCIC_FLAG_SOCKETP) 613 ret += tcic_intr_socket(&sc->handle[i]); 614 615 return (ret ? 1 : 0); 616 } 617 618 int 619 tcic_intr_socket(h) 620 struct tcic_handle *h; 621 { 622 int icsr, rv; 623 624 rv = 0; 625 tcic_sel_sock(h); 626 icsr = tcic_read_1(h, TCIC_R_ICSR); 627 628 DPRINTF(("%s: %d icsr: 0x%02x \n", h->sc->dev.dv_xname, h->sock, icsr)); 629 630 /* XXX or should the next three be handled in tcic_intr? -chb */ 631 if (icsr & TCIC_ICSR_PROGTIME) { 632 DPRINTF(("%s: %02x PROGTIME\n", h->sc->dev.dv_xname, h->sock)); 633 rv = 1; 634 } 635 if (icsr & TCIC_ICSR_ILOCK) { 636 DPRINTF(("%s: %02x ILOCK\n", h->sc->dev.dv_xname, h->sock)); 637 rv = 1; 638 } 639 if (icsr & TCIC_ICSR_ERR) { 640 DPRINTF(("%s: %02x ERR\n", h->sc->dev.dv_xname, h->sock)); 641 rv = 1; 642 } 643 if (icsr & TCIC_ICSR_CDCHG) { 644 int sstat, delta; 645 646 /* compute what changed since last interrupt */ 647 sstat = tcic_read_aux_1(h->sc->iot, h->sc->ioh, 648 TCIC_AR_WCTL, TCIC_R_WCTL_XCSR) & TCIC_XCSR_STAT_MASK; 649 delta = h->sstat ^ sstat; 650 h->sstat = sstat; 651 652 if (delta) 653 rv = 1; 654 655 DPRINTF(("%s: %02x CDCHG %x\n", h->sc->dev.dv_xname, h->sock, 656 delta)); 657 658 /* 659 * XXX This should probably schedule something to happen 660 * after the interrupt handler completes 661 */ 662 663 if (delta & TCIC_SSTAT_CD) { 664 if (sstat & TCIC_SSTAT_CD) { 665 if (!(h->flags & TCIC_FLAG_CARDP)) { 666 DPRINTF(("%s: enqueuing INSERTION event\n", 667 h->sc->dev.dv_xname)); 668 tcic_queue_event(h, TCIC_EVENT_INSERTION); 669 } 670 } else { 671 if (h->flags & TCIC_FLAG_CARDP) { 672 /* Deactivate the card now. */ 673 DPRINTF(("%s: deactivating card\n", 674 h->sc->dev.dv_xname)); 675 tcic_deactivate_card(h); 676 677 DPRINTF(("%s: enqueuing REMOVAL event\n", 678 h->sc->dev.dv_xname)); 679 tcic_queue_event(h, TCIC_EVENT_REMOVAL); 680 } 681 } 682 } 683 if (delta & TCIC_SSTAT_RDY) { 684 DPRINTF(("%s: %02x READY\n", h->sc->dev.dv_xname, h->sock)); 685 /* shouldn't happen */ 686 } 687 if (delta & TCIC_SSTAT_LBAT1) { 688 DPRINTF(("%s: %02x LBAT1\n", h->sc->dev.dv_xname, h->sock)); 689 } 690 if (delta & TCIC_SSTAT_LBAT2) { 691 DPRINTF(("%s: %02x LBAT2\n", h->sc->dev.dv_xname, h->sock)); 692 } 693 if (delta & TCIC_SSTAT_WP) { 694 DPRINTF(("%s: %02x WP\n", h->sc->dev.dv_xname, h->sock)); 695 } 696 } 697 return rv; 698 } 699 700 void 701 tcic_queue_event(h, event) 702 struct tcic_handle *h; 703 int event; 704 { 705 struct tcic_event *pe; 706 int s; 707 708 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 709 if (pe == NULL) 710 panic("tcic_queue_event: can't allocate event"); 711 712 pe->pe_type = event; 713 s = splhigh(); 714 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 715 splx(s); 716 wakeup(&h->events); 717 } 718 void 719 tcic_attach_card(h) 720 struct tcic_handle *h; 721 { 722 DPRINTF(("tcic_attach_card\n")); 723 724 if (h->flags & TCIC_FLAG_CARDP) 725 panic("tcic_attach_card: already attached"); 726 727 /* call the MI attach function */ 728 729 pcmcia_card_attach(h->pcmcia); 730 731 h->flags |= TCIC_FLAG_CARDP; 732 } 733 734 void 735 tcic_detach_card(h, flags) 736 struct tcic_handle *h; 737 int flags; /* DETACH_* */ 738 { 739 DPRINTF(("tcic_detach_card\n")); 740 741 if (!(h->flags & TCIC_FLAG_CARDP)) 742 panic("tcic_detach_card: already detached"); 743 744 h->flags &= ~TCIC_FLAG_CARDP; 745 746 /* call the MI detach function */ 747 748 pcmcia_card_detach(h->pcmcia, flags); 749 750 } 751 752 void 753 tcic_deactivate_card(h) 754 struct tcic_handle *h; 755 { 756 int val, reg; 757 758 if (!(h->flags & TCIC_FLAG_CARDP)) 759 panic("tcic_deactivate_card: already detached"); 760 761 /* call the MI deactivate function */ 762 pcmcia_card_deactivate(h->pcmcia); 763 764 tcic_sel_sock(h); 765 766 /* XXX disable card detect resume and configuration reset??? */ 767 768 /* power down the socket */ 769 tcic_write_1(h, TCIC_R_PWR, 0); 770 771 /* reset the card XXX ? -chb */ 772 773 /* turn off irq's for this socket */ 774 reg = TCIC_IR_SCF1_N(h->sock); 775 val = tcic_read_ind_2(h, reg); 776 tcic_write_ind_2(h, reg, (val & ~TCIC_SCF1_IRQ_MASK)|TCIC_SCF1_IRQOFF); 777 reg = TCIC_IR_SCF2_N(h->sock); 778 val = tcic_read_ind_2(h, reg); 779 tcic_write_ind_2(h, reg, 780 (val | (TCIC_SCF2_MLBAT1|TCIC_SCF2_MLBAT2|TCIC_SCF2_MRDY 781 |TCIC_SCF2_MWP|TCIC_SCF2_MCD))); 782 } 783 784 /* XXX the following routine may need to be rewritten. -chb */ 785 int 786 tcic_chip_mem_alloc(pch, size, pcmhp) 787 pcmcia_chipset_handle_t pch; 788 bus_size_t size; 789 struct pcmcia_mem_handle *pcmhp; 790 { 791 struct tcic_handle *h = (struct tcic_handle *) pch; 792 bus_space_handle_t memh; 793 bus_addr_t addr; 794 bus_size_t sizepg; 795 int i, mask, mhandle; 796 797 /* out of sc->memh, allocate as many pages as necessary */ 798 799 /* 800 * The TCIC can map memory only in sizes that are 801 * powers of two, aligned at the natural boundary for the size. 802 */ 803 i = tcic_log2((u_int)size); 804 if ((1<<i) < size) 805 i++; 806 sizepg = max(i, TCIC_MEM_SHIFT) - (TCIC_MEM_SHIFT-1); 807 808 DPRINTF(("tcic_chip_mem_alloc: size %ld sizepg %ld\n", size, sizepg)); 809 810 /* can't allocate that much anyway */ 811 if (sizepg > TCIC_MEM_PAGES) /* XXX -chb */ 812 return 1; 813 814 mask = (1 << sizepg) - 1; 815 816 addr = 0; /* XXX gcc -Wuninitialized */ 817 mhandle = 0; /* XXX gcc -Wuninitialized */ 818 819 /* XXX i should be initialised to always lay on boundary. -chb */ 820 for (i = 0; i < (TCIC_MEM_PAGES + 1 - sizepg); i += sizepg) { 821 if ((h->sc->subregionmask & (mask << i)) == (mask << i)) { 822 if (bus_space_subregion(h->sc->memt, h->sc->memh, 823 i * TCIC_MEM_PAGESIZE, 824 sizepg * TCIC_MEM_PAGESIZE, &memh)) 825 return (1); 826 mhandle = mask << i; 827 addr = h->sc->membase + (i * TCIC_MEM_PAGESIZE); 828 h->sc->subregionmask &= ~(mhandle); 829 break; 830 } 831 } 832 833 if (i == (TCIC_MEM_PAGES + 1 - sizepg)) 834 return (1); 835 836 DPRINTF(("tcic_chip_mem_alloc bus addr 0x%lx+0x%lx\n", (u_long) addr, 837 (u_long) size)); 838 839 pcmhp->memt = h->sc->memt; 840 pcmhp->memh = memh; 841 pcmhp->addr = addr; 842 pcmhp->size = size; 843 pcmhp->mhandle = mhandle; 844 pcmhp->realsize = sizepg * TCIC_MEM_PAGESIZE; 845 846 return (0); 847 } 848 849 /* XXX the following routine may need to be rewritten. -chb */ 850 void 851 tcic_chip_mem_free(pch, pcmhp) 852 pcmcia_chipset_handle_t pch; 853 struct pcmcia_mem_handle *pcmhp; 854 { 855 struct tcic_handle *h = (struct tcic_handle *) pch; 856 857 h->sc->subregionmask |= pcmhp->mhandle; 858 } 859 860 void 861 tcic_chip_do_mem_map(h, win) 862 struct tcic_handle *h; 863 int win; 864 { 865 int reg, hwwin, wscnt; 866 867 int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 868 int mem8 = (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8; 869 DPRINTF(("tcic_chip_do_mem_map window %d: 0x%lx+0x%lx 0x%lx\n", 870 win, (u_long)h->mem[win].addr, (u_long)h->mem[win].size, 871 (u_long)h->mem[win].offset)); 872 /* 873 * the even windows are used for socket 0, 874 * the odd ones for socket 1. 875 */ 876 hwwin = (win << 1) + h->sock; 877 878 /* the WR_MEXT register is MBZ */ 879 tcic_write_ind_2(h, TCIC_WR_MEXT_N(hwwin), 0); 880 881 /* set the host base address and window size */ 882 if (h->mem[win].size2 <= 1) { 883 reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) & 884 TCIC_MBASE_ADDR_MASK) | TCIC_MBASE_4K; 885 } else { 886 reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) & 887 TCIC_MBASE_ADDR_MASK) | (h->mem[win].size2 >> 1); 888 } 889 tcic_write_ind_2(h, TCIC_WR_MBASE_N(hwwin), reg); 890 891 /* set the card address and address space */ 892 reg = 0; 893 reg = ((h->mem[win].offset >> TCIC_MEM_SHIFT) & TCIC_MMAP_ADDR_MASK); 894 reg |= (kind == PCMCIA_MEM_ATTR) ? TCIC_MMAP_ATTR : 0; 895 DPRINTF(("tcic_chip_do_map_mem window %d(%d) mmap 0x%04x\n", 896 win, hwwin, reg)); 897 tcic_write_ind_2(h, TCIC_WR_MMAP_N(hwwin), reg); 898 899 /* set the MCTL register */ 900 /* must save WSCNT field in case this is a DB86082 rev 0 */ 901 /* XXX why can't I do the following two in one statement? */ 902 reg = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)) & TCIC_MCTL_WSCNT_MASK; 903 reg |= TCIC_MCTL_ENA|TCIC_MCTL_QUIET; 904 reg |= mem8 ? TCIC_MCTL_B8 : 0; 905 reg |= (h->sock << TCIC_MCTL_SS_SHIFT) & TCIC_MCTL_SS_MASK; 906 #ifdef notyet /* XXX must get speed from CIS somehow. -chb */ 907 wscnt = tcic_ns2wscnt(h->mem[win].speed); 908 #else 909 wscnt = tcic_ns2wscnt(tcic_mem_speed); /* 300 is "save" default for CIS memory */ 910 #endif 911 if (h->sc->chipid == TCIC_CHIPID_DB86082_1) { 912 /* 913 * this chip has the wait state count in window 914 * register 7 - hwwin. 915 */ 916 int reg2; 917 reg2 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(7-hwwin)); 918 reg2 &= ~TCIC_MCTL_WSCNT_MASK; 919 reg2 |= wscnt & TCIC_MCTL_WSCNT_MASK; 920 tcic_write_ind_2(h, TCIC_WR_MCTL_N(7-hwwin), reg2); 921 } else { 922 reg |= wscnt & TCIC_MCTL_WSCNT_MASK; 923 } 924 tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), reg); 925 926 #ifdef TCICDEBUG 927 { 928 int r1, r2, r3; 929 930 r1 = tcic_read_ind_2(h, TCIC_WR_MBASE_N(hwwin)); 931 r2 = tcic_read_ind_2(h, TCIC_WR_MMAP_N(hwwin)); 932 r3 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)); 933 934 DPRINTF(("tcic_chip_do_mem_map window %d(%d): %04x %04x %04x\n", 935 win, hwwin, r1, r2, r3)); 936 } 937 #endif 938 } 939 940 /* XXX needs work */ 941 int 942 tcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 943 pcmcia_chipset_handle_t pch; 944 int kind; 945 bus_addr_t card_addr; 946 bus_size_t size; 947 struct pcmcia_mem_handle *pcmhp; 948 bus_size_t *offsetp; 949 int *windowp; 950 { 951 struct tcic_handle *h = (struct tcic_handle *) pch; 952 bus_addr_t busaddr; 953 long card_offset; 954 int i, win; 955 956 win = -1; 957 for (i = 0; i < h->memwins; i++) { 958 if ((h->memalloc & (1 << i)) == 0) { 959 win = i; 960 h->memalloc |= (1 << i); 961 break; 962 } 963 } 964 965 if (win == -1) 966 return (1); 967 968 *windowp = win; 969 970 /* XXX this is pretty gross */ 971 972 if (h->sc->memt != pcmhp->memt) 973 panic("tcic_chip_mem_map memt is bogus"); 974 975 busaddr = pcmhp->addr; 976 977 /* 978 * compute the address offset to the pcmcia address space for the 979 * tcic. this is intentionally signed. The masks and shifts below 980 * will cause TRT to happen in the tcic registers. Deal with making 981 * sure the address is aligned, and return the alignment offset. 982 */ 983 984 *offsetp = card_addr % TCIC_MEM_ALIGN; 985 card_addr -= *offsetp; 986 987 DPRINTF(("tcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 988 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 989 (u_long) card_addr)); 990 991 /* XXX we can't use size. -chb */ 992 /* 993 * include the offset in the size, and decrement size by one, since 994 * the hw wants start/stop 995 */ 996 size += *offsetp - 1; 997 998 card_offset = (((long) card_addr) - ((long) busaddr)); 999 1000 DPRINTF(("tcic_chip_mem_map window %d card_offset 0x%lx\n", 1001 win, (u_long)card_offset)); 1002 1003 h->mem[win].addr = busaddr; 1004 h->mem[win].size = size; 1005 h->mem[win].size2 = tcic_log2((u_int)pcmhp->realsize) - TCIC_MEM_SHIFT; 1006 h->mem[win].offset = card_offset; 1007 h->mem[win].kind = kind; 1008 1009 tcic_chip_do_mem_map(h, win); 1010 1011 return (0); 1012 } 1013 1014 void 1015 tcic_chip_mem_unmap(pch, window) 1016 pcmcia_chipset_handle_t pch; 1017 int window; 1018 { 1019 struct tcic_handle *h = (struct tcic_handle *) pch; 1020 int reg, hwwin; 1021 1022 if (window >= h->memwins) 1023 panic("tcic_chip_mem_unmap: window out of range"); 1024 1025 hwwin = (window << 1) + h->sock; 1026 reg = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)); 1027 reg &= ~TCIC_MCTL_ENA; 1028 tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), reg); 1029 1030 h->memalloc &= ~(1 << window); 1031 } 1032 1033 int 1034 tcic_chip_io_alloc(pch, start, size, align, pcihp) 1035 pcmcia_chipset_handle_t pch; 1036 bus_addr_t start; 1037 bus_size_t size; 1038 bus_size_t align; 1039 struct pcmcia_io_handle *pcihp; 1040 { 1041 struct tcic_handle *h = (struct tcic_handle *) pch; 1042 bus_space_tag_t iot; 1043 bus_space_handle_t ioh; 1044 bus_addr_t ioaddr; 1045 int size2, flags = 0; 1046 1047 /* 1048 * Allocate some arbitrary I/O space. 1049 */ 1050 1051 DPRINTF(("tcic_chip_io_alloc req 0x%lx %ld %ld\n", 1052 (u_long) start, (u_long) size, (u_long) align)); 1053 /* 1054 * The TCIC can map I/O space only in sizes that are 1055 * powers of two, aligned at the natural boundary for the size. 1056 */ 1057 size2 = tcic_log2((u_int)size); 1058 if ((1 << size2) < size) 1059 size2++; 1060 /* can't allocate that much anyway */ 1061 if (size2 > 16) /* XXX 64K -chb */ 1062 return 1; 1063 if (align) { 1064 if ((1 << size2) != align) 1065 return 1; /* not suitably aligned */ 1066 } else { 1067 align = 1 << size2; /* no alignment given, make it natural */ 1068 } 1069 if (start & (align - 1)) 1070 return 1; /* not suitably aligned */ 1071 1072 iot = h->sc->iot; 1073 1074 if (start) { 1075 ioaddr = start; 1076 if (bus_space_map(iot, start, size, 0, &ioh)) 1077 return (1); 1078 DPRINTF(("tcic_chip_io_alloc map port %lx+%lx\n", 1079 (u_long) ioaddr, (u_long) size)); 1080 } else { 1081 flags |= PCMCIA_IO_ALLOCATED; 1082 if (bus_space_alloc(iot, h->sc->iobase, 1083 h->sc->iobase + h->sc->iosize, size, align, 0, 0, 1084 &ioaddr, &ioh)) 1085 return (1); 1086 DPRINTF(("tcic_chip_io_alloc alloc port %lx+%lx\n", 1087 (u_long) ioaddr, (u_long) size)); 1088 } 1089 1090 pcihp->iot = iot; 1091 pcihp->ioh = ioh; 1092 pcihp->addr = ioaddr; 1093 pcihp->size = size; 1094 pcihp->flags = flags; 1095 1096 return (0); 1097 } 1098 1099 void 1100 tcic_chip_io_free(pch, pcihp) 1101 pcmcia_chipset_handle_t pch; 1102 struct pcmcia_io_handle *pcihp; 1103 { 1104 bus_space_tag_t iot = pcihp->iot; 1105 bus_space_handle_t ioh = pcihp->ioh; 1106 bus_size_t size = pcihp->size; 1107 1108 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1109 bus_space_free(iot, ioh, size); 1110 else 1111 bus_space_unmap(iot, ioh, size); 1112 } 1113 1114 static int tcic_iowidth_map[] = 1115 { TCIC_ICTL_AUTOSZ, TCIC_ICTL_B8, TCIC_ICTL_B16 }; 1116 1117 void 1118 tcic_chip_do_io_map(h, win) 1119 struct tcic_handle *h; 1120 int win; 1121 { 1122 int reg, size2, iotiny, wbase, hwwin, wscnt; 1123 1124 DPRINTF(("tcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1125 win, (long) h->io[win].addr, (long) h->io[win].size, 1126 h->io[win].width * 8)); 1127 1128 /* 1129 * the even windows are used for socket 0, 1130 * the odd ones for socket 1. 1131 */ 1132 hwwin = (win << 1) + h->sock; 1133 1134 /* set the WR_BASE register */ 1135 /* XXX what if size isn't power of 2? -chb */ 1136 size2 = tcic_log2((u_int)h->io[win].size); 1137 DPRINTF(("tcic_chip_do_io_map win %d size2 %d\n", win, size2)); 1138 if (size2 < 1) { 1139 iotiny = TCIC_ICTL_TINY; 1140 wbase = h->io[win].addr; 1141 } else { 1142 iotiny = 0; 1143 /* XXX we should do better -chb */ 1144 wbase = h->io[win].addr | (1 << (size2 - 1)); 1145 } 1146 tcic_write_ind_2(h, TCIC_WR_IBASE_N(hwwin), wbase); 1147 1148 /* set the WR_ICTL register */ 1149 reg = TCIC_ICTL_ENA | TCIC_ICTL_QUIET; 1150 reg |= (h->sock << TCIC_ICTL_SS_SHIFT) & TCIC_ICTL_SS_MASK; 1151 reg |= iotiny | tcic_iowidth_map[h->io[win].width]; 1152 if (h->sc->chipid != TCIC_CHIPID_DB86082_1) 1153 reg |= TCIC_ICTL_PASS16; 1154 #ifdef notyet /* XXX must get speed from CIS somehow. -chb */ 1155 wscnt = tcic_ns2wscnt(h->io[win].speed); 1156 #else 1157 wscnt = tcic_ns2wscnt(tcic_io_speed); /* linux uses 0 as default */ 1158 #endif 1159 reg |= wscnt & TCIC_ICTL_WSCNT_MASK; 1160 tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), reg); 1161 1162 #ifdef TCICDEBUG 1163 { 1164 int r1, r2; 1165 1166 r1 = tcic_read_ind_2(h, TCIC_WR_IBASE_N(hwwin)); 1167 r2 = tcic_read_ind_2(h, TCIC_WR_ICTL_N(hwwin)); 1168 1169 DPRINTF(("tcic_chip_do_io_map window %d(%d): %04x %04x\n", 1170 win, hwwin, r1, r2)); 1171 } 1172 #endif 1173 } 1174 1175 int 1176 tcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1177 pcmcia_chipset_handle_t pch; 1178 int width; 1179 bus_addr_t offset; 1180 bus_size_t size; 1181 struct pcmcia_io_handle *pcihp; 1182 int *windowp; 1183 { 1184 struct tcic_handle *h = (struct tcic_handle *) pch; 1185 bus_addr_t ioaddr = pcihp->addr + offset; 1186 int i, win; 1187 #ifdef TCICDEBUG 1188 static char *width_names[] = { "auto", "io8", "io16" }; 1189 #endif 1190 1191 /* XXX Sanity check offset/size. */ 1192 1193 win = -1; 1194 for (i = 0; i < TCIC_IO_WINS; i++) { 1195 if ((h->ioalloc & (1 << i)) == 0) { 1196 win = i; 1197 h->ioalloc |= (1 << i); 1198 break; 1199 } 1200 } 1201 1202 if (win == -1) 1203 return (1); 1204 1205 *windowp = win; 1206 1207 /* XXX this is pretty gross */ 1208 1209 if (h->sc->iot != pcihp->iot) 1210 panic("tcic_chip_io_map iot is bogus"); 1211 1212 DPRINTF(("tcic_chip_io_map window %d %s port %lx+%lx\n", 1213 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1214 1215 /* XXX wtf is this doing here? */ 1216 1217 printf(" port 0x%lx", (u_long) ioaddr); 1218 if (size > 1) 1219 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1220 1221 h->io[win].addr = ioaddr; 1222 h->io[win].size = size; 1223 h->io[win].width = width; 1224 1225 tcic_chip_do_io_map(h, win); 1226 1227 return (0); 1228 } 1229 1230 void 1231 tcic_chip_io_unmap(pch, window) 1232 pcmcia_chipset_handle_t pch; 1233 int window; 1234 { 1235 struct tcic_handle *h = (struct tcic_handle *) pch; 1236 int reg, hwwin; 1237 1238 if (window >= TCIC_IO_WINS) 1239 panic("tcic_chip_io_unmap: window out of range"); 1240 1241 hwwin = (window << 1) + h->sock; 1242 reg = tcic_read_ind_2(h, TCIC_WR_ICTL_N(hwwin)); 1243 reg &= ~TCIC_ICTL_ENA; 1244 tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), reg); 1245 1246 h->ioalloc &= ~(1 << window); 1247 } 1248 1249 void 1250 tcic_chip_socket_enable(pch) 1251 pcmcia_chipset_handle_t pch; 1252 { 1253 struct tcic_handle *h = (struct tcic_handle *) pch; 1254 int cardtype, reg, win; 1255 1256 tcic_sel_sock(h); 1257 1258 /* 1259 * power down the socket to reset it. 1260 * put card reset into high-z, put chip outputs to card into high-z 1261 */ 1262 1263 tcic_write_1(h, TCIC_R_PWR, 0); 1264 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1265 reg |= TCIC_ILOCK_CWAIT; 1266 reg &= ~(TCIC_ILOCK_CRESET|TCIC_ILOCK_CRESENA); 1267 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1268 tcic_write_1(h, TCIC_R_SCTRL, 0); /* clear TCIC_SCTRL_ENA */ 1269 1270 /* power up the socket */ 1271 1272 /* turn on VCC, turn of VPP */ 1273 reg = TCIC_PWR_VCC_N(h->sock) | TCIC_PWR_VPP_N(h->sock) | h->sc->pwrena; 1274 if (h->sc->pwrena) /* this is a '84 type chip */ 1275 reg |= TCIC_PWR_VCC5V; 1276 tcic_write_1(h, TCIC_R_PWR, reg); 1277 delay(10000); 1278 1279 /* enable reset and wiggle it to reset the card */ 1280 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1281 reg |= TCIC_ILOCK_CRESENA; 1282 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1283 /* XXX need bus_space_barrier here */ 1284 reg |= TCIC_ILOCK_CRESET; 1285 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1286 /* enable card signals */ 1287 tcic_write_1(h, TCIC_R_SCTRL, TCIC_SCTRL_ENA); 1288 delay(10); /* wait 10 us */ 1289 1290 /* clear the reset flag */ 1291 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1292 reg &= ~(TCIC_ILOCK_CRESET); 1293 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1294 1295 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1296 delay(20000); 1297 1298 /* wait for the chip to finish initializing */ 1299 tcic_wait_ready(h); 1300 1301 /* WWW */ 1302 /* zero out the address windows */ 1303 1304 /* writing to WR_MBASE_N disables the window */ 1305 for (win = 0; win < h->memwins; win++) { 1306 tcic_write_ind_2(h, TCIC_WR_MBASE_N((win<<1)+h->sock), 0); 1307 } 1308 /* writing to WR_IBASE_N disables the window */ 1309 for (win = 0; win < TCIC_IO_WINS; win++) { 1310 tcic_write_ind_2(h, TCIC_WR_IBASE_N((win<<1)+h->sock), 0); 1311 } 1312 1313 /* set the card type */ 1314 1315 cardtype = pcmcia_card_gettype(h->pcmcia); 1316 1317 #if 0 1318 reg = tcic_read_ind_2(h, TCIC_IR_SCF1_N(h->sock)); 1319 reg &= ~TCIC_SCF1_IRQ_MASK; 1320 #else 1321 reg = 0; 1322 #endif 1323 reg |= ((cardtype == PCMCIA_IFTYPE_IO) ? 1324 TCIC_SCF1_IOSTS : 0); 1325 reg |= tcic_irqmap[h->ih_irq]; /* enable interrupts */ 1326 reg &= ~TCIC_SCF1_IRQOD; 1327 tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), reg); 1328 1329 DPRINTF(("%s: tcic_chip_socket_enable %d cardtype %s 0x%02x\n", 1330 h->sc->dev.dv_xname, h->sock, 1331 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1332 1333 /* reinstall all the memory and io mappings */ 1334 1335 for (win = 0; win < h->memwins; win++) 1336 if (h->memalloc & (1 << win)) 1337 tcic_chip_do_mem_map(h, win); 1338 1339 for (win = 0; win < TCIC_IO_WINS; win++) 1340 if (h->ioalloc & (1 << win)) 1341 tcic_chip_do_io_map(h, win); 1342 } 1343 1344 void 1345 tcic_chip_socket_disable(pch) 1346 pcmcia_chipset_handle_t pch; 1347 { 1348 struct tcic_handle *h = (struct tcic_handle *) pch; 1349 int val; 1350 1351 DPRINTF(("tcic_chip_socket_disable\n")); 1352 1353 tcic_sel_sock(h); 1354 1355 /* disable interrupts */ 1356 val = tcic_read_ind_2(h, TCIC_IR_SCF1_N(h->sock)); 1357 val &= TCIC_SCF1_IRQ_MASK; 1358 tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), val); 1359 1360 /* disable the output signals */ 1361 tcic_write_1(h, TCIC_R_SCTRL, 0); 1362 val = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1363 val &= ~TCIC_ILOCK_CRESENA; 1364 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, val); 1365 1366 /* power down the socket */ 1367 tcic_write_1(h, TCIC_R_PWR, 0); 1368 } 1369 1370 /* 1371 * XXX The following is Linux driver but doesn't match the table 1372 * in the manual. 1373 */ 1374 int 1375 tcic_ns2wscnt(ns) 1376 int ns; 1377 { 1378 if (ns < 14) { 1379 return 0; 1380 } else { 1381 return (2*(ns-14))/70; /* XXX assumes 14.31818 MHz clock. */ 1382 } 1383 } 1384 1385 int 1386 tcic_log2(val) 1387 u_int val; 1388 { 1389 int i, l2; 1390 1391 l2 = i = 0; 1392 while (val) { 1393 if (val & 1) 1394 l2 = i; 1395 i++; 1396 val >>= 1; 1397 } 1398 return l2; 1399 } 1400