1*5fcca410Smk /* $OpenBSD: uhareg.h,v 1.5 2010/06/30 19:06:16 mk Exp $ */ 2c0981ad2Sniklas /* $NetBSD: uhareg.h,v 1.2 1996/09/01 00:54:41 mycroft Exp $ */ 3c0981ad2Sniklas 4c0981ad2Sniklas /* 5c0981ad2Sniklas * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. 6c0981ad2Sniklas * 7c0981ad2Sniklas * Redistribution and use in source and binary forms, with or without 8c0981ad2Sniklas * modification, are permitted provided that the following conditions 9c0981ad2Sniklas * are met: 10c0981ad2Sniklas * 1. Redistributions of source code must retain the above copyright 11c0981ad2Sniklas * notice, this list of conditions and the following disclaimer. 12c0981ad2Sniklas * 2. Redistributions in binary form must reproduce the above copyright 13c0981ad2Sniklas * notice, this list of conditions and the following disclaimer in the 14c0981ad2Sniklas * documentation and/or other materials provided with the distribution. 15c0981ad2Sniklas * 3. All advertising materials mentioning features or use of this software 16c0981ad2Sniklas * must display the following acknowledgement: 17c0981ad2Sniklas * This product includes software developed by Charles M. Hannum. 18c0981ad2Sniklas * 4. The name of the author may not be used to endorse or promote products 19c0981ad2Sniklas * derived from this software without specific prior written permission. 20c0981ad2Sniklas * 21c0981ad2Sniklas * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22c0981ad2Sniklas * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23c0981ad2Sniklas * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24c0981ad2Sniklas * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25c0981ad2Sniklas * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26c0981ad2Sniklas * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27c0981ad2Sniklas * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28c0981ad2Sniklas * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29c0981ad2Sniklas * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30c0981ad2Sniklas * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31c0981ad2Sniklas */ 32c0981ad2Sniklas 33c0981ad2Sniklas /* 34c0981ad2Sniklas * Ported for use with the UltraStor 14f by Gary Close (gclose@wvnvms.wvnet.edu) 35c0981ad2Sniklas * Slight fixes to timeouts to run with the 34F 36c0981ad2Sniklas * Thanks to Julian Elischer for advice and help with this port. 37c0981ad2Sniklas * 38c0981ad2Sniklas * Originally written by Julian Elischer (julian@tfs.com) 39c0981ad2Sniklas * for TRW Financial Systems for use under the MACH(2.5) operating system. 40c0981ad2Sniklas * 41c0981ad2Sniklas * TRW Financial Systems, in accordance with their agreement with Carnegie 42c0981ad2Sniklas * Mellon University, makes this software available to CMU to distribute 43c0981ad2Sniklas * or use in any manner that they see fit as long as this message is kept with 44c0981ad2Sniklas * the software. For this reason TFS also grants any other persons or 45c0981ad2Sniklas * organisations permission to use or modify this software. 46c0981ad2Sniklas * 47c0981ad2Sniklas * TFS supplies this software to be publicly redistributed 48c0981ad2Sniklas * on the understanding that TFS is not responsible for the correct 49c0981ad2Sniklas * functioning of this software in any circumstances. 50c0981ad2Sniklas * 51c0981ad2Sniklas * commenced: Sun Sep 27 18:14:01 PDT 1992 52c0981ad2Sniklas * slight mod to make work with 34F as well: Wed Jun 2 18:05:48 WST 1993 53c0981ad2Sniklas */ 54c0981ad2Sniklas 55c0981ad2Sniklas typedef u_long physaddr; 56c0981ad2Sniklas typedef u_long physlen; 57c0981ad2Sniklas 58c0981ad2Sniklas /************************** board definitions *******************************/ 59c0981ad2Sniklas /* 60c0981ad2Sniklas * I/O Port Interface 61c0981ad2Sniklas */ 62c0981ad2Sniklas #define U14_LMASK 0x0000 /* local doorbell mask reg */ 63c0981ad2Sniklas #define U14_LINT 0x0001 /* local doorbell int/stat reg */ 64c0981ad2Sniklas #define U14_SMASK 0x0002 /* system doorbell mask reg */ 65c0981ad2Sniklas #define U14_SINT 0x0003 /* system doorbell int/stat reg */ 66c0981ad2Sniklas #define U14_ID 0x0004 /* product id reg (2 ports) */ 67c0981ad2Sniklas #define U14_CONFIG 0x0006 /* config reg (2 ports) */ 68c0981ad2Sniklas #define U14_OGMPTR 0x0008 /* outgoing mail ptr (4 ports) */ 69c0981ad2Sniklas #define U14_ICMPTR 0x000c /* incoming mail ptr (4 ports) */ 70c0981ad2Sniklas 71c0981ad2Sniklas #define U24_CONFIG 0x0005 /* config reg (3 ports) */ 72c0981ad2Sniklas #define U24_LMASK 0x000c /* local doorbell mask reg */ 73c0981ad2Sniklas #define U24_LINT 0x000d /* local doorbell int/stat reg */ 74c0981ad2Sniklas #define U24_SMASK 0x000e /* system doorbell mask reg */ 75c0981ad2Sniklas #define U24_SINT 0x000f /* system doorbell int/stat reg */ 76c0981ad2Sniklas #define U24_OGMCMD 0x0016 /* outgoing commands */ 77c0981ad2Sniklas #define U24_OGMPTR 0x0017 /* outgoing mail ptr (4 ports) */ 78c0981ad2Sniklas #define U24_ICMCMD 0x001b /* incoming commands */ 79c0981ad2Sniklas #define U24_ICMPTR 0x001c /* incoming mail ptr (4 ports) */ 80c0981ad2Sniklas 81c0981ad2Sniklas /* 82c0981ad2Sniklas * UHA_LMASK bits (read only) 83c0981ad2Sniklas */ 84c0981ad2Sniklas #define UHA_LDIE 0x80 /* local doorbell int enabled */ 85c0981ad2Sniklas #define UHA_SRSTE 0x40 /* soft reset enabled */ 86c0981ad2Sniklas #define UHA_ABORTEN 0x10 /* abort MSCP enabled */ 87c0981ad2Sniklas #define UHA_OGMINTEN 0x01 /* outgoing mail interrupt enabled */ 88c0981ad2Sniklas 89c0981ad2Sniklas /* 90c0981ad2Sniklas * UHA_LINT bits (read only) 91c0981ad2Sniklas */ 92c0981ad2Sniklas #define U14_LDIP 0x80 /* local doorbell int pending */ 93c0981ad2Sniklas #define U24_LDIP 0x02 /* local doorbell int pending */ 94c0981ad2Sniklas 95c0981ad2Sniklas /* 96c0981ad2Sniklas * UHA_LINT bits (write only) 97c0981ad2Sniklas */ 98c0981ad2Sniklas #define U14_OGMFULL 0x01 /* outgoing mailbox is full */ 99c0981ad2Sniklas #define U14_ABORT 0x10 /* abort MSCP */ 100c0981ad2Sniklas 101c0981ad2Sniklas #define U24_OGMFULL 0x02 /* outgoing mailbox is full */ 102c0981ad2Sniklas 103c0981ad2Sniklas #define UHA_SBRST 0x40 /* scsi bus reset */ 104c0981ad2Sniklas #define UHA_ADRST 0x80 /* adapter soft reset */ 105c0981ad2Sniklas #define UHA_ASRST 0xc0 /* adapter and scsi reset */ 106c0981ad2Sniklas 107c0981ad2Sniklas /* 108c0981ad2Sniklas * UHA_SMASK bits (read/write) 109c0981ad2Sniklas */ 110c0981ad2Sniklas #define UHA_ENSINT 0x80 /* enable system doorbell interrupt */ 111c0981ad2Sniklas #define UHA_EN_ABORT_COMPLETE 0x10 /* enable abort MSCP complete int */ 112c0981ad2Sniklas #define UHA_ENICM 0x01 /* enable ICM interrupt */ 113c0981ad2Sniklas 114c0981ad2Sniklas /* 115c0981ad2Sniklas * UHA_SINT bits (read) 116c0981ad2Sniklas */ 117c0981ad2Sniklas #define U14_SDIP 0x80 /* system doorbell int pending */ 118c0981ad2Sniklas #define U24_SDIP 0x02 /* system doorbell int pending */ 119c0981ad2Sniklas 120c0981ad2Sniklas #define UHA_ABORT_SUCC 0x10 /* abort MSCP successful */ 121c0981ad2Sniklas #define UHA_ABORT_FAIL 0x18 /* abort MSCP failed */ 122c0981ad2Sniklas 123c0981ad2Sniklas /* 124c0981ad2Sniklas * UHA_SINT bits (write) 125c0981ad2Sniklas */ 126c0981ad2Sniklas #define U14_ICM_ACK 0x01 /* acknowledge ICM and clear */ 127c0981ad2Sniklas #define U24_ICM_ACK 0x02 /* acknowledge ICM and clear */ 128c0981ad2Sniklas 129c0981ad2Sniklas #define UHA_ABORT_ACK 0x18 /* acknowledge status and clear */ 130c0981ad2Sniklas 131c0981ad2Sniklas /* 132c0981ad2Sniklas * U14_CONFIG bits (read only) 133c0981ad2Sniklas */ 134c0981ad2Sniklas #define U14_DMA_CH5 0x0000 /* DMA channel 5 */ 135c0981ad2Sniklas #define U14_DMA_CH6 0x4000 /* 6 */ 136c0981ad2Sniklas #define U14_DMA_CH7 0x8000 /* 7 */ 137c0981ad2Sniklas #define U14_DMA_MASK 0xc000 138c0981ad2Sniklas #define U14_IRQ15 0x0000 /* IRQ 15 */ 139c0981ad2Sniklas #define U14_IRQ14 0x1000 /* 14 */ 140c0981ad2Sniklas #define U14_IRQ11 0x2000 /* 11 */ 141c0981ad2Sniklas #define U14_IRQ10 0x3000 /* 10 */ 142c0981ad2Sniklas #define U14_IRQ_MASK 0x3000 143c0981ad2Sniklas #define U14_HOSTID_MASK 0x0007 144c0981ad2Sniklas 145c0981ad2Sniklas /* 146c0981ad2Sniklas * U24_CONFIG bits (read only) 147c0981ad2Sniklas */ 148c0981ad2Sniklas #define U24_MAGIC1 0x08 149c0981ad2Sniklas #define U24_IRQ15 0x10 150c0981ad2Sniklas #define U24_IRQ14 0x20 151c0981ad2Sniklas #define U24_IRQ11 0x40 152c0981ad2Sniklas #define U24_IRQ10 0x80 153c0981ad2Sniklas #define U24_IRQ_MASK 0xf0 154c0981ad2Sniklas 155c0981ad2Sniklas #define U24_MAGIC2 0x04 156c0981ad2Sniklas 157c0981ad2Sniklas #define U24_HOSTID_MASK 0x07 158c0981ad2Sniklas 159c0981ad2Sniklas /* 160c0981ad2Sniklas * EISA registers (offset from slot base) 161c0981ad2Sniklas */ 162c0981ad2Sniklas #define EISA_VENDOR 0x0c80 /* vendor ID (2 ports) */ 163c0981ad2Sniklas #define EISA_MODEL 0x0c82 /* model number (2 ports) */ 164c0981ad2Sniklas #define EISA_CONTROL 0x0c84 165c0981ad2Sniklas #define EISA_RESET 0x04 166c0981ad2Sniklas #define EISA_ERROR 0x02 167c0981ad2Sniklas #define EISA_ENABLE 0x01 168c0981ad2Sniklas 169c0981ad2Sniklas /* 170c0981ad2Sniklas * host_stat error codes 171c0981ad2Sniklas */ 172c0981ad2Sniklas #define UHA_NO_ERR 0x00 /* No error supposedly */ 173c0981ad2Sniklas #define UHA_SBUS_ABORT_ERR 0x84 /* scsi bus abort error */ 174c0981ad2Sniklas #define UHA_SBUS_TIMEOUT 0x91 /* scsi bus selection timeout */ 175c0981ad2Sniklas #define UHA_SBUS_OVER_UNDER 0x92 /* scsi bus over/underrun */ 176c0981ad2Sniklas #define UHA_BAD_SCSI_CMD 0x96 /* illegal scsi command */ 177c0981ad2Sniklas #define UHA_AUTO_SENSE_ERR 0x9b /* auto request sense err */ 178c0981ad2Sniklas #define UHA_SBUS_RES_ERR 0xa3 /* scsi bus reset error */ 179c0981ad2Sniklas #define UHA_BAD_SG_LIST 0xff /* invalid scatter gath list */ 180c0981ad2Sniklas 181c0981ad2Sniklas #define UHA_NSEG 33 /* number of dma segments supported */ 182c0981ad2Sniklas 183c0981ad2Sniklas struct uha_dma_seg { 184c0981ad2Sniklas physaddr seg_addr; 185c0981ad2Sniklas physlen seg_len; 186c0981ad2Sniklas }; 187c0981ad2Sniklas 188c0981ad2Sniklas struct uha_mscp { 189c0981ad2Sniklas u_char opcode:3; 190c0981ad2Sniklas #define UHA_HAC 0x01 /* host adapter command */ 191c0981ad2Sniklas #define UHA_TSP 0x02 /* target scsi pass through command */ 192c0981ad2Sniklas #define UHA_SDR 0x04 /* scsi device reset */ 193c0981ad2Sniklas u_char xdir:2; /* xfer direction */ 194c0981ad2Sniklas #define UHA_SDET 0x00 /* determined by scsi command */ 195c0981ad2Sniklas #define UHA_SDIN 0x01 /* scsi data in */ 196c0981ad2Sniklas #define UHA_SDOUT 0x02 /* scsi data out */ 197c0981ad2Sniklas #define UHA_NODATA 0x03 /* no data xfer */ 198c0981ad2Sniklas u_char dcn:1; /* disable disconnect for this command */ 199c0981ad2Sniklas u_char ca:1; /* cache control */ 200c0981ad2Sniklas u_char sgth:1; /* scatter gather flag */ 201c0981ad2Sniklas u_char target:3; 202c0981ad2Sniklas u_char chan:2; /* scsi channel (always 0 for 14f) */ 203c0981ad2Sniklas u_char lun:3; 204c0981ad2Sniklas physaddr data_addr; 205c0981ad2Sniklas physlen data_length; 206c0981ad2Sniklas physaddr link_addr; 207c0981ad2Sniklas u_char link_id; 208c0981ad2Sniklas u_char sg_num; /* number of scat gath segs */ 209c0981ad2Sniklas /*in s-g list if sg flag is */ 210c0981ad2Sniklas /*set. starts at 1, 8bytes per */ 211c0981ad2Sniklas u_char req_sense_length; 212c0981ad2Sniklas u_char scsi_cmd_length; 213c0981ad2Sniklas struct scsi_generic scsi_cmd; 214c0981ad2Sniklas u_char host_stat; 215c0981ad2Sniklas u_char target_stat; 216c0981ad2Sniklas physaddr sense_ptr; /* if 0 no auto sense */ 217c0981ad2Sniklas 218c0981ad2Sniklas struct uha_dma_seg uha_dma[UHA_NSEG]; 219c0981ad2Sniklas struct scsi_sense_data mscp_sense; 220c0981ad2Sniklas /*-----------------end of hardware supported fields----------------*/ 221*5fcca410Smk SLIST_ENTRY(uha_mscp) chain; 222c0981ad2Sniklas struct uha_mscp *nexthash; 223c0981ad2Sniklas long hashkey; 224c0981ad2Sniklas struct scsi_xfer *xs; /* the scsi_xfer for this cmd */ 225c0981ad2Sniklas int flags; 226c0981ad2Sniklas #define MSCP_ALLOC 0x01 227c0981ad2Sniklas #define MSCP_ABORT 0x02 228c0981ad2Sniklas int timeout; 229b8468dd4Savsm } __packed; 230c0981ad2Sniklas 231