1 /* $OpenBSD: aic7xxx_reg.h,v 1.3 1997/11/07 08:07:16 niklas Exp $*/ 2 3 /* 4 * Aic7xxx register and scratch ram definitions. 5 * 6 * Copyright (c) 1994, 1995, 1996 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice immediately at the beginning of the file, without modification, 14 * this list of conditions, and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * This header is shared by the sequencer code and the kernel level driver. 37 * 38 * All page numbers refer to the Adaptec AIC-7770 Data Book availible from 39 * Adaptec's Technical Documents Department 1-800-934-2766 40 */ 41 42 /* 43 * SCSI Sequence Control (p. 3-11). 44 * Each bit, when set starts a specific SCSI sequence on the bus 45 */ 46 #define SCSISEQ 0x000 47 #define TEMODEO 0x80 48 #define ENSELO 0x40 49 #define ENSELI 0x20 50 #define ENRSELI 0x10 51 #define ENAUTOATNO 0x08 52 #define ENAUTOATNI 0x04 53 #define ENAUTOATNP 0x02 54 #define SCSIRSTO 0x01 55 56 /* 57 * SCSI Transfer Control 0 Register (pp. 3-13). 58 * Controls the SCSI module data path. 59 */ 60 #define SXFRCTL0 0x001 61 #define DFON 0x80 62 #define DFPEXP 0x40 63 #define ULTRAEN 0x20 64 #define CLRSTCNT 0x10 65 #define SPIOEN 0x08 66 #define SCAMEN 0x04 67 #define CLRCHN 0x02 68 /* UNUSED 0x01 */ 69 70 /* 71 * SCSI Transfer Control 1 Register (pp. 3-14,15). 72 * Controls the SCSI module data path. 73 */ 74 #define SXFRCTL1 0x002 75 #define BITBUCKET 0x80 76 #define SWRAPEN 0x40 77 #define ENSPCHK 0x20 78 #define STIMESEL 0x18 79 #define ENSTIMER 0x04 80 #define ACTNEGEN 0x02 81 #define STPWEN 0x01 /* Powered Termination */ 82 83 /* 84 * SCSI Control Signal Read Register (p. 3-15). 85 * Reads the actual state of the SCSI bus pins 86 */ 87 #define SCSISIGI 0x003 88 #define CDI 0x80 89 #define IOI 0x40 90 #define MSGI 0x20 91 #define ATNI 0x10 92 #define SELI 0x08 93 #define BSYI 0x04 94 #define REQI 0x02 95 #define ACKI 0x01 96 97 /* 98 * Possible phases in SCSISIGI 99 */ 100 #define PHASE_MASK 0xe0 101 #define P_DATAOUT 0x00 102 #define P_DATAIN 0x40 103 #define P_COMMAND 0x80 104 #define P_MESGOUT 0xa0 105 #define P_STATUS 0xc0 106 #define P_MESGIN 0xe0 107 /* 108 * SCSI Contol Signal Write Register (p. 3-16). 109 * Writing to this register modifies the control signals on the bus. Only 110 * those signals that are allowed in the current mode (Initiator/Target) are 111 * asserted. 112 */ 113 #define SCSISIGO 0x003 114 #define CDO 0x80 115 #define IOO 0x40 116 #define MSGO 0x20 117 #define ATNO 0x10 118 #define SELO 0x08 119 #define BSYO 0x04 120 #define REQO 0x02 121 #define ACKO 0x01 122 123 /* 124 * SCSI Rate Control (p. 3-17). 125 * Contents of this register determine the Synchronous SCSI data transfer 126 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the 127 * SOFS (3:0) bits disables synchronous data transfers. Any offset value 128 * greater than 0 enables synchronous transfers. 129 */ 130 #define SCSIRATE 0x004 131 #define WIDEXFER 0x80 /* Wide transfer control */ 132 #define SXFR 0x70 /* Sync transfer rate */ 133 #define SOFS 0x0f /* Sync offset */ 134 135 /* 136 * SCSI ID (p. 3-18). 137 * Contains the ID of the board and the current target on the 138 * selected channel. 139 */ 140 #define SCSIID 0x005 141 #define TID 0xf0 /* Target ID mask */ 142 #define OID 0x0f /* Our ID mask */ 143 144 /* 145 * SCSI Latched Data (p. 3-19). 146 * Read/Write latchs used to transfer data on the SCSI bus during 147 * Automatic or Manual PIO mode. SCSIDATH can be used for the 148 * upper byte of a 16bit wide asyncronouse data phase transfer. 149 */ 150 #define SCSIDATL 0x006 151 #define SCSIDATH 0x007 152 153 /* 154 * SCSI Transfer Count (pp. 3-19,20) 155 * These registers count down the number of bytes transfered 156 * across the SCSI bus. The counter is decremented only once 157 * the data has been safely transfered. SDONE in SSTAT0 is 158 * set when STCNT goes to 0 159 */ 160 #define STCNT 0x008 161 #define STCNT0 0x008 162 #define STCNT1 0x009 163 #define STCNT2 0x00a 164 165 /* 166 * Clear SCSI Interrupt 0 (p. 3-20) 167 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 168 */ 169 #define CLRSINT0 0x00b 170 #define CLRSELDO 0x40 171 #define CLRSELDI 0x20 172 #define CLRSELINGO 0x10 173 #define CLRSWRAP 0x08 174 /* UNUSED 0x04 */ 175 #define CLRSPIORDY 0x02 176 /* UNUSED 0x01 */ 177 178 /* 179 * SCSI Status 0 (p. 3-21) 180 * Contains one set of SCSI Interrupt codes 181 * These are most likely of interest to the sequencer 182 */ 183 #define SSTAT0 0x00b 184 #define TARGET 0x80 /* Board acting as target */ 185 #define SELDO 0x40 /* Selection Done */ 186 #define SELDI 0x20 /* Board has been selected */ 187 #define SELINGO 0x10 /* Selection In Progress */ 188 #define SWRAP 0x08 /* 24bit counter wrap */ 189 #define SDONE 0x04 /* STCNT = 0x000000 */ 190 #define SPIORDY 0x02 /* SCSI PIO Ready */ 191 #define DMADONE 0x01 /* DMA transfer completed */ 192 193 /* 194 * Clear SCSI Interrupt 1 (p. 3-23) 195 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 196 */ 197 #define CLRSINT1 0x00c 198 #define CLRSELTIMEO 0x80 199 #define CLRATNO 0x40 200 #define CLRSCSIRSTI 0x20 201 /* UNUSED 0x10 */ 202 #define CLRBUSFREE 0x08 203 #define CLRSCSIPERR 0x04 204 #define CLRPHASECHG 0x02 205 #define CLRREQINIT 0x01 206 207 /* 208 * SCSI Status 1 (p. 3-24) 209 */ 210 #define SSTAT1 0x00c 211 #define SELTO 0x80 212 #define ATNTARG 0x40 213 #define SCSIRSTI 0x20 214 #define PHASEMIS 0x10 215 #define BUSFREE 0x08 216 #define SCSIPERR 0x04 217 #define PHASECHG 0x02 218 #define REQINIT 0x01 219 220 /* 221 * SCSI Interrupt Mode 1 (pp. 3-28,29) 222 * Setting any bit will enable the corresponding function 223 * in SIMODE1 to interrupt via the IRQ pin. 224 */ 225 #define SIMODE1 0x011 226 #define ENSELTIMO 0x80 227 #define ENATNTARG 0x40 228 #define ENSCSIRST 0x20 229 #define ENPHASEMIS 0x10 230 #define ENBUSFREE 0x08 231 #define ENSCSIPERR 0x04 232 #define ENPHASECHG 0x02 233 #define ENREQINIT 0x01 234 235 /* 236 * SCSI Data Bus (High) (p. 3-29) 237 * This register reads data on the SCSI Data bus directly. 238 */ 239 #define SCSIBUSL 0x012 240 #define SCSIBUSH 0x013 241 242 /* 243 * SCSI/Host Address (p. 3-30) 244 * These registers hold the host address for the byte about to be 245 * transfered on the SCSI bus. They are counted up in the same 246 * manner as STCNT is counted down. SHADDR should always be used 247 * to determine the address of the last byte transfered since HADDR 248 * can be squewed by write ahead. 249 */ 250 #define SHADDR 0x014 251 #define SHADDR0 0x014 252 #define SHADDR1 0x015 253 #define SHADDR2 0x016 254 #define SHADDR3 0x017 255 256 /* 257 * Selection/Reselection ID (p. 3-31) 258 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 259 * device did not set its own ID. 260 */ 261 #define SELID 0x019 262 #define SELID_MASK 0xf0 263 #define ONEBIT 0x08 264 /* UNUSED 0x07 */ 265 266 /* 267 * SCSI Block Control (p. 3-32) 268 * Controls Bus type and channel selection. In a twin channel configuration 269 * addresses 0x00-0x1e are gated to the appropriate channel based on this 270 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 271 * on a wide bus. 272 */ 273 #define SBLKCTL 0x01f 274 #define DIAGLEDEN 0x80 /* Aic78X0 only */ 275 #define DIAGLEDON 0x40 /* Aic78X0 only */ 276 #define AUTOFLUSHDIS 0x20 277 /* UNUSED 0x10 */ 278 #define SELBUS_MASK 0x0a 279 #define SELBUSB 0x08 280 /* UNUSED 0x04 */ 281 #define SELWIDE 0x02 282 /* UNUSED 0x01 */ 283 #define SELNARROW 0x00 284 285 /* 286 * Sequencer Control (p. 3-33) 287 * Error detection mode and speed configuration 288 */ 289 #define SEQCTL 0x060 290 #define PERRORDIS 0x80 291 #define PAUSEDIS 0x40 292 #define FAILDIS 0x20 293 #define FASTMODE 0x10 294 #define BRKADRINTEN 0x08 295 #define STEP 0x04 296 #define SEQRESET 0x02 297 #define LOADRAM 0x01 298 299 /* 300 * Sequencer RAM Data (p. 3-34) 301 * Single byte window into the Scratch Ram area starting at the address 302 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write 303 * four bytes in sucessesion. The SEQADDRs will increment after the most 304 * significant byte is written 305 */ 306 #define SEQRAM 0x061 307 308 /* 309 * Sequencer Address Registers (p. 3-35) 310 * Only the first bit of SEQADDR1 holds addressing information 311 */ 312 #define SEQADDR0 0x062 313 #define SEQADDR1 0x063 314 #define SEQADDR1_MASK 0x01 315 316 /* 317 * Accumulator 318 * We cheat by passing arguments in the Accumulator up to the kernel driver 319 */ 320 #define ACCUM 0x064 321 322 #define SINDEX 0x065 323 #define DINDEX 0x066 324 #define ALLZEROS 0x06a 325 #define NONE 0x06a 326 #define SINDIR 0x06c 327 #define DINDIR 0x06d 328 #define FUNCTION1 0x06e 329 330 /* 331 * Host Address (p. 3-48) 332 * This register contains the address of the byte about 333 * to be transfered across the host bus. 334 */ 335 #define HADDR 0x088 336 #define HADDR0 0x088 337 #define HADDR1 0x089 338 #define HADDR2 0x08a 339 #define HADDR3 0x08b 340 341 #define HCNT 0x08c 342 #define HCNT0 0x08c 343 #define HCNT1 0x08d 344 #define HCNT2 0x08e 345 /* 346 * SCB Pointer (p. 3-49) 347 * Gate one of the four SCBs into the SCBARRAY window. 348 */ 349 #define SCBPTR 0x090 350 351 /* 352 * Board Control (p. 3-43) 353 */ 354 #define BCTL 0x084 355 /* RSVD 0xf0 */ 356 #define ACE 0x08 /* Support for external processors */ 357 /* RSVD 0x06 */ 358 #define ENABLE 0x01 359 360 /* 361 * On the aic78X0 chips, Board Control is replaced by the DSCommand 362 * register (p. 4-64) 363 */ 364 #define DSCOMMAND 0x084 365 #define CACHETHEN 0x80 /* Cache Threshold enable */ 366 #define DPARCKEN 0x40 /* Data Parity Check Enable */ 367 #define MPARCKEN 0x20 /* Memory Parity Check Enable */ 368 #define EXTREQLCK 0x10 /* External Request Lock */ 369 370 /* 371 * Bus On/Off Time (p. 3-44) 372 */ 373 #define BUSTIME 0x085 374 #define BOFF 0xf0 375 #define BON 0x0f 376 377 /* 378 * Bus Speed (p. 3-45) 379 */ 380 #define BUSSPD 0x086 381 #define DFTHRSH 0xc0 382 #define STBOFF 0x38 383 #define STBON 0x07 384 #define DFTHRSH_100 0xc0 385 386 /* 387 * Host Control (p. 3-47) R/W 388 * Overal host control of the device. 389 */ 390 #define HCNTRL 0x087 391 /* UNUSED 0x80 */ 392 #define POWRDN 0x40 393 /* UNUSED 0x20 */ 394 #define SWINT 0x10 395 #define IRQMS 0x08 396 #define PAUSE 0x04 397 #define INTEN 0x02 398 #define CHIPRST 0x01 399 #define CHIPRSTACK 0x01 400 401 /* 402 * Interrupt Status (p. 3-50) 403 * Status for system interrupts 404 */ 405 #define INTSTAT 0x091 406 #define SEQINT_MASK 0xf1 /* SEQINT Status Codes */ 407 #define BAD_PHASE 0x01 /* unknown scsi bus phase */ 408 #define SEND_REJECT 0x11 /* sending a message reject */ 409 #define NO_IDENT 0x21 /* no IDENTIFY after reconnect*/ 410 #define NO_MATCH 0x31 /* no cmd match for reconnect */ 411 #define SDTR_MSG 0x41 /* SDTR message received */ 412 #define WDTR_MSG 0x51 /* WDTR message received */ 413 #define REJECT_MSG 0x61 /* Reject message received */ 414 #define BAD_STATUS 0x71 /* Bad status from target */ 415 #define RESIDUAL 0x81 /* Residual byte count != 0 */ 416 #define ABORT_TAG 0x91 /* Sent an ABORT_TAG message */ 417 #define AWAITING_MSG 0xa1 /* 418 * Kernel requested to specify 419 * a message to this target 420 * (command was null), so tell 421 * it that it can fill the 422 * message buffer. 423 */ 424 #define IMMEDDONE 0xb1 /* 425 * An immediate command has 426 * completed 427 */ 428 #define MSG_BUFFER_BUSY 0xc1 /* 429 * Sequencer wants to use the 430 * message buffer, but it 431 * already contains a message 432 */ 433 #define MSGIN_PHASEMIS 0xd1 /* 434 * Target changed phase on us 435 * when we were expecting 436 * another msgin byte. 437 */ 438 #define DATA_OVERRUN 0xe1 /* 439 * Target attempted to write 440 * beyond the bounds of its 441 * command. 442 */ 443 #define BRKADRINT 0x08 444 #define SCSIINT 0x04 445 #define CMDCMPLT 0x02 446 #define SEQINT 0x01 447 #define INT_PEND (BRKADRINT | SEQINT | SCSIINT | CMDCMPLT) 448 449 /* 450 * Hard Error (p. 3-53) 451 * Reporting of catastrophic errors. You usually cannot recover from 452 * these without a full board reset. 453 */ 454 #define ERROR 0x092 455 /* UNUSED 0xf0 */ 456 #define PARERR 0x08 457 #define ILLOPCODE 0x04 458 #define ILLSADDR 0x02 459 #define ILLHADDR 0x01 460 461 /* 462 * Clear Interrupt Status (p. 3-52) 463 */ 464 #define CLRINT 0x092 465 #define CLRBRKADRINT 0x08 466 #define CLRSCSIINT 0x04 467 #define CLRCMDINT 0x02 468 #define CLRSEQINT 0x01 469 470 #define DFCNTRL 0x093 471 #define WIDEODD 0x40 472 #define SCSIEN 0x20 473 #define SDMAEN 0x10 474 #define SDMAENACK 0x10 475 #define HDMAEN 0x08 476 #define HDMAENACK 0x08 477 #define DIRECTION 0x04 478 #define FIFOFLUSH 0x02 479 #define FIFORESET 0x01 480 481 #define DFSTATUS 0x094 482 #define HDONE 0x08 483 #define FIFOEMP 0x01 484 485 #define DFDAT 0x099 486 487 /* 488 * SCB Auto Increment (p. 3-59) 489 * Byte offset into the SCB Array and an optional bit to allow auto 490 * incrementing of the address during download and upload operations 491 */ 492 #define SCBCNT 0x09a 493 #define SCBAUTO 0x80 494 #define SCBCNT_MASK 0x1f 495 496 /* 497 * Queue In FIFO (p. 3-60) 498 * Input queue for queued SCBs (commands that the seqencer has yet to start) 499 */ 500 #define QINFIFO 0x09b 501 502 /* 503 * Queue In Count (p. 3-60) 504 * Number of queued SCBs 505 */ 506 #define QINCNT 0x09c 507 508 /* 509 * Queue Out FIFO (p. 3-61) 510 * Queue of SCBs that have completed and await the host 511 */ 512 #define QOUTFIFO 0x09d 513 514 /* 515 * Queue Out Count (p. 3-61) 516 * Number of queued SCBs in the Out FIFO 517 */ 518 #define QOUTCNT 0x09e 519 520 /* 521 * SCB Definition (p. 5-4) 522 * The two reserved bytes at SCBARRAY+1[23] are expected to be set to 523 * zero. Bit 3 in SCBARRAY+0 is used as an internal flag to indicate 524 * whether or not to DMA an SCB from host ram. This flag prevents the 525 * "re-fetching" of transactions that are requed because the target is 526 * busy with another command. We also use bits 6 & 7 to indicate whether 527 * or not to initiate SDTR or WDTR repectively when starting this command. 528 */ 529 #define SCBARRAY 0x0a0 530 #define SCB_CONTROL 0x0a0 531 #define NEEDWDTR 0x80 532 #define DISCENB 0x40 533 #define TAG_ENB 0x20 534 #define NEEDSDTR 0x10 535 #define DISCONNECTED 0x04 536 #define SCB_TAG_TYPE 0x03 537 #define SCB_TCL 0x0a1 538 #define SCB_TARGET_STATUS 0x0a2 539 #define SCB_SGCOUNT 0x0a3 540 #define SCB_SGPTR 0x0a4 541 #define SCB_SGPTR0 0x0a4 542 #define SCB_SGPTR1 0x0a5 543 #define SCB_SGPTR2 0x0a6 544 #define SCB_SGPTR3 0x0a7 545 #define SCB_RESID_SGCNT 0x0a8 546 #define SCB_RESID_DCNT 0x0a9 547 #define SCB_RESID_DCNT0 0x0a9 548 #define SCB_RESID_DCNT1 0x0aa 549 #define SCB_RESID_DCNT2 0x0ab 550 #define SCB_DATAPTR 0x0ac 551 #define SCB_DATAPTR0 0x0ac 552 #define SCB_DATAPTR1 0x0ad 553 #define SCB_DATAPTR2 0x0ae 554 #define SCB_DATAPTR3 0x0af 555 #define SCB_DATACNT 0x0b0 556 #define SCB_DATACNT0 0x0b0 557 #define SCB_DATACNT1 0x0b1 558 #define SCB_DATACNT2 0x0b2 559 /* UNUSED - QUAD PADDING 0x0b3 */ 560 #define SCB_CMDPTR 0x0b4 561 #define SCB_CMDPTR0 0x0b4 562 #define SCB_CMDPTR1 0x0b5 563 #define SCB_CMDPTR2 0x0b6 564 #define SCB_CMDPTR3 0x0b7 565 #define SCB_CMDLEN 0x0b8 566 #define SCB_TAG 0x0b9 567 #define SCB_NEXT 0x0ba 568 #define SCB_PREV 0x0bb 569 570 #ifdef __linux__ 571 #define SG_SIZEOF 0x0c /* sizeof(struct scatterlist) */ 572 #else 573 #define SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */ 574 #endif 575 576 /* --------------------- AHA-2840-only definitions -------------------- */ 577 578 #define SEECTL_2840 0x0c0 579 /* UNUSED 0xf8 */ 580 #define CS_2840 0x04 581 #define CK_2840 0x02 582 #define DO_2840 0x01 583 584 #define STATUS_2840 0x0c1 585 #define EEPROM_TF 0x80 586 #define BIOS_SEL 0x60 587 #define ADSEL 0x1e 588 #define DI_2840 0x01 589 590 /* --------------------- AIC-7870-only definitions -------------------- */ 591 592 #define DSPCISTATUS 0x086 593 594 /* 595 * Serial EEPROM Control (p. 4-92 in 7870 Databook) 596 * Controls the reading and writing of an external serial 1-bit 597 * EEPROM Device. In order to access the serial EEPROM, you must 598 * first set the SEEMS bit that generates a request to the memory 599 * port for access to the serial EEPROM device. When the memory 600 * port is not busy servicing another request, it reconfigures 601 * to allow access to the serial EEPROM. When this happens, SEERDY 602 * gets set high to verify that the memory port access has been 603 * granted. 604 * 605 * After successful arbitration for the memory port, the SEECS bit of 606 * the SEECTL register is connected to the chip select. The SEECK, 607 * SEEDO, and SEEDI are connected to the clock, data out, and data in 608 * lines respectively. The SEERDY bit of SEECTL is useful in that it 609 * gives us an 800 nsec timer. After a write to the SEECTL register, 610 * the SEERDY goes high 800 nsec later. The one exception to this is 611 * when we first request access to the memory port. The SEERDY goes 612 * high to signify that access has been granted and, for this case, has 613 * no implied timing. 614 * 615 * See 93cx6.c for detailed information on the protocol necessary to 616 * read the serial EEPROM. 617 */ 618 #define SEECTL 0x01e 619 #define EXTARBACK 0x80 620 #define EXTARBREQ 0x40 621 #define SEEMS 0x20 622 #define SEERDY 0x10 623 #define SEECS 0x08 624 #define SEECK 0x04 625 #define SEEDO 0x02 626 #define SEEDI 0x01 627 628 /* ---------------------- Scratch RAM Offsets ------------------------- */ 629 /* These offsets are either to values that are initialized by the board's 630 * BIOS or are specified by the sequencer code. 631 * 632 * The host adapter card (at least the BIOS) uses 20-2f for SCSI 633 * device information, 32-33 and 5a-5f as well. As it turns out, the 634 * BIOS trashes 20-2f, writing the synchronous negotiation results 635 * on top of the BIOS values, so we re-use those for our per-target 636 * scratchspace (actually a value that can be copied directly into 637 * SCSIRATE). The kernel driver will enable synchronous negotiation 638 * for all targets that have a value other than 0 in the lower four 639 * bits of the target scratch space. This should work regardless of 640 * whether the bios has been installed. 641 */ 642 643 /* 644 * 1 byte per target starting at this address for configuration values 645 */ 646 #define TARG_SCRATCH 0x020 647 648 /* 649 * The sequencer will stick the frist byte of any rejected message here so 650 * we can see what is getting thrown away. Extended messages put the 651 * extended message type in REJBYTE_EXT. 652 */ 653 #define REJBYTE 0x030 654 #define REJBYTE_EXT 0x031 655 656 /* 657 * Bit vector of targets that have disconnection disabled. 658 */ 659 #define DISC_DSB 0x032 660 #define DISC_DSB_A 0x032 661 #define DISC_DSB_B 0x033 662 663 /* 664 * Length of pending message 665 */ 666 #define MSG_LEN 0x034 667 668 /* We reserve 8bytes to store outgoing messages */ 669 #define MSG0 0x035 670 #define COMP_MSG0 0xcb /* 2's complement of MSG0 */ 671 #define MSG1 0x036 672 #define MSG2 0x037 673 #define MSG3 0x038 674 #define MSG4 0x039 675 #define MSG5 0x03a 676 #define MSG6 0x03b 677 #define MSG7 0x03c 678 679 /* 680 * These are offsets into the card's scratch ram. Some of the values are 681 * specified in the AHA2742 technical reference manual and are initialized 682 * by the BIOS at boot time. 683 */ 684 #define LASTPHASE 0x03d 685 #define ARG_1 0x03e 686 #define MAXOFFSET 0x01 687 #define RETURN_1 0x03f 688 #define SEND_WDTR 0x80 689 #define SEND_SDTR 0x60 690 #define SEND_SENSE 0x40 691 #define SEND_REJ 0x20 692 #define SCB_PAGEDIN 0x10 693 694 #define SIGSTATE 0x040 695 696 #define DMAPARAMS 0x041 /* Parameters for DMA Logic */ 697 698 #define SG_COUNT 0x042 699 #define SG_NEXT 0x043 /* working value of SG pointer */ 700 #define SG_NEXT0 0x043 701 #define SG_NEXT1 0x044 702 #define SG_NEXT2 0x045 703 #define SG_NEXT3 0x046 704 705 #define SCBCOUNT 0x047 /* 706 * Number of SCBs supported by 707 * this card. 708 */ 709 #define COMP_SCBCOUNT 0x048 /* 710 * Two's compliment of SCBCOUNT 711 */ 712 #define QCNTMASK 0x049 /* 713 * Mask of bits to test against 714 * when looking at the Queue Count 715 * registers. Works around a bug 716 * on aic7850 chips. 717 */ 718 #define FLAGS 0x04a 719 #define SINGLE_BUS 0x00 720 #define TWIN_BUS 0x01 721 #define WIDE_BUS 0x02 722 #define PAGESCBS 0x04 723 #define DPHASE 0x10 724 #define SELECTED 0x20 725 #define IDENTIFY_SEEN 0x40 726 #define RESELECTED 0x80 727 728 #define SAVED_TCL 0x04b /* 729 * Temporary storage for the 730 * target/channel/lun of a 731 * reconnecting target 732 */ 733 #define ACTIVE_A 0x04c 734 #define ACTIVE_B 0x04d 735 #define WAITING_SCBH 0x04e /* 736 * head of list of SCBs awaiting 737 * selection 738 */ 739 #define DISCONNECTED_SCBH 0x04f /* 740 * head of list of SCBs that are 741 * disconnected. Used for SCB 742 * paging. 743 */ 744 #define SCB_LIST_NULL 0xff 745 746 #define SAVED_LINKPTR 0x050 747 #define SAVED_SCBPTR 0x051 748 #define ULTRA_ENB 0x052 749 #define ULTRA_ENB_B 0x053 750 751 #define SCSICONF 0x05a 752 #define RESET_SCSI 0x40 753 754 #define HOSTCONF 0x05d 755 756 #define HA_274_BIOSCTRL 0x05f 757 #define BIOSMODE 0x30 758 #define BIOSDISABLED 0x30 759 #define CHANNEL_B_PRIMARY 0x08 760 761 /* Message codes */ 762 #define MSG_EXTENDED 0x01 763 #define MSG_SDTR 0x01 764 #define MSG_WDTR 0x03 765 #define MSG_SDPTRS 0x02 766 #define MSG_RDPTRS 0x03 767 #define MSG_DISCONNECT 0x04 768 #define MSG_INITIATOR_DET_ERROR 0x05 769 #define MSG_ABORT 0x06 770 #define MSG_REJECT 0x07 771 #define MSG_NOP 0x08 772 #define MSG_MSG_PARITY_ERROR 0x09 773 #define MSG_BUS_DEVICE_RESET 0x0c 774 #define MSG_ABORT_TAG 0x0d 775 #define MSG_SIMPLE_TAG 0x20 776 #define MSG_IDENTIFY 0x80 777 778 /* WDTR Message values */ 779 #define BUS_8_BIT 0x00 780 #define BUS_16_BIT 0x01 781 #define BUS_32_BIT 0x02 782 783 #define MAX_OFFSET_8BIT 0x0f 784 #define MAX_OFFSET_16BIT 0x08 785