1 /* $OpenBSD: atphy.c,v 1.6 2011/06/17 09:59:52 kevlo Exp $ */ 2 3 /*- 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for the Attansic F1 10/100/1000 PHY. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/device.h> 38 #include <sys/socket.h> 39 40 #include <net/if.h> 41 #include <net/if_media.h> 42 43 #include <dev/mii/mii.h> 44 #include <dev/mii/miivar.h> 45 #include <dev/mii/miidevs.h> 46 47 /* Special Control Register */ 48 #define ATPHY_SCR 0x10 49 #define ATPHY_SCR_JABBER_DISABLE 0x0001 50 #define ATPHY_SCR_POLARITY_REVERSAL 0x0002 51 #define ATPHY_SCR_SQE_TEST 0x0004 52 #define ATPHY_SCR_MAC_PDOWN 0x0008 53 #define ATPHY_SCR_CLK125_DISABLE 0x0010 54 #define ATPHY_SCR_MDI_MANUAL_MODE 0x0000 55 #define ATPHY_SCR_MDIX_MANUAL_MODE 0x0020 56 #define ATPHY_SCR_AUTO_X_1000T 0x0040 57 #define ATPHY_SCR_AUTO_X_MODE 0x0060 58 #define ATPHY_SCR_10BT_EXT_ENABLE 0x0080 59 #define ATPHY_SCR_MII_5BIT_ENABLE 0x0100 60 #define ATPHY_SCR_SCRAMBLER_DISABLE 0x0200 61 #define ATPHY_SCR_FORCE_LINK_GOOD 0x0400 62 #define ATPHY_SCR_ASSERT_CRS_ON_TX 0x0800 63 64 /* Special Status Register. */ 65 #define ATPHY_SSR 0x11 66 #define ATPHY_SSR_SPD_DPLX_RESOLVED 0x0800 67 #define ATPHY_SSR_DUPLEX 0x2000 68 #define ATPHY_SSR_SPEED_MASK 0xC000 69 #define ATPHY_SSR_10MBS 0x0000 70 #define ATPHY_SSR_100MBS 0x4000 71 #define ATPHY_SSR_1000MBS 0x8000 72 73 int atphy_service(struct mii_softc *, struct mii_data *, int); 74 void atphy_attach(struct device *, struct device *, void *); 75 int atphy_match(struct device *, void *, void *); 76 void atphy_reset(struct mii_softc *); 77 void atphy_status(struct mii_softc *); 78 int atphy_mii_phy_auto(struct mii_softc *); 79 80 const struct mii_phy_funcs atphy_funcs = { 81 atphy_service, atphy_status, atphy_reset, 82 }; 83 84 static const struct mii_phydesc atphys[] = { 85 { MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F1, 86 MII_STR_ATHEROS_F1 }, 87 { MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F1_7, 88 MII_STR_ATHEROS_F1_7 }, 89 { MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F2, 90 MII_STR_ATHEROS_F2 }, 91 { 0, 0, 92 NULL }, 93 }; 94 95 struct cfattach atphy_ca = { 96 sizeof (struct mii_softc), atphy_match, atphy_attach, 97 mii_phy_detach, mii_phy_activate 98 }; 99 100 struct cfdriver atphy_cd = { 101 NULL, "atphy", DV_DULL 102 }; 103 104 int 105 atphy_match(struct device *parent, void *match, void *aux) 106 { 107 struct mii_attach_args *ma = aux; 108 109 if (mii_phy_match(ma, atphys) != NULL) 110 return (10); 111 112 return (0); 113 } 114 115 void 116 atphy_attach(struct device *parent, struct device *self, void *aux) 117 { 118 struct mii_softc *sc = (struct mii_softc *)self; 119 struct mii_attach_args *ma = aux; 120 struct mii_data *mii = ma->mii_data; 121 const struct mii_phydesc *mpd; 122 123 mpd = mii_phy_match(ma, atphys); 124 printf(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 125 126 sc->mii_inst = mii->mii_instance; 127 sc->mii_phy = ma->mii_phyno; 128 sc->mii_funcs = &atphy_funcs; 129 sc->mii_model = MII_MODEL(ma->mii_id2); 130 sc->mii_pdata = mii; 131 sc->mii_flags = ma->mii_flags; 132 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 133 134 sc->mii_flags |= MIIF_NOLOOP; 135 136 PHY_RESET(sc); 137 138 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 139 if (sc->mii_capabilities & BMSR_EXTSTAT) 140 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 141 142 mii_phy_add_media(sc); 143 } 144 145 int 146 atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 147 { 148 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 149 uint16_t anar, bmcr, bmsr; 150 151 switch (cmd) { 152 case MII_POLLSTAT: 153 /* 154 * If we're not polling our PHY instance, just return. 155 */ 156 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 157 return (0); 158 break; 159 160 case MII_MEDIACHG: 161 /* 162 * If the media indicates a different PHY instance, 163 * isolate ourselves. 164 */ 165 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 166 bmcr = PHY_READ(sc, MII_BMCR); 167 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 168 return (0); 169 } 170 171 /* 172 * If the interface is not up, don't do anything. 173 */ 174 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 175 break; 176 177 bmcr = 0; 178 switch (IFM_SUBTYPE(ife->ifm_media)) { 179 case IFM_AUTO: 180 case IFM_1000_T: 181 atphy_mii_phy_auto(sc); 182 goto done; 183 case IFM_100_TX: 184 bmcr = BMCR_S100; 185 break; 186 case IFM_10_T: 187 bmcr = BMCR_S10; 188 break; 189 case IFM_NONE: 190 bmcr = PHY_READ(sc, MII_BMCR); 191 /* 192 * XXX 193 * Due to an unknown reason powering down PHY resulted 194 * in unexpected results such as inaccessibility of 195 * hardware of freshly rebooted system. Disable 196 * powering down PHY until I got more information for 197 * Attansic/Atheros PHY hardwares. 198 */ 199 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 200 goto done; 201 default: 202 return (EINVAL); 203 } 204 205 anar = mii_anar(ife->ifm_media); 206 if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) { 207 bmcr |= BMCR_FDX; 208 /* Enable pause. */ 209 if (sc->mii_flags & MIIF_DOPAUSE) 210 anar |= ANAR_PAUSE_TOWARDS; 211 } 212 213 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | 214 EXTSR_1000THDX)) != 0) 215 PHY_WRITE(sc, MII_100T2CR, 0); 216 PHY_WRITE(sc, MII_ANAR, anar); 217 218 /* 219 * Reset the PHY so all changes take effect. 220 */ 221 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET | BMCR_AUTOEN | 222 BMCR_STARTNEG); 223 done: 224 break; 225 226 case MII_TICK: 227 /* 228 * If we're not currently selected, just return. 229 */ 230 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 231 return (0); 232 233 /* 234 * Is the interface even up? 235 */ 236 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 237 return (0); 238 239 /* 240 * Only used for autonegotiation. 241 */ 242 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 243 sc->mii_ticks = 0; 244 break; 245 } 246 247 /* 248 * Check for link. 249 * Read the status register twice; BMSR_LINK is latch-low. 250 */ 251 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 252 if (bmsr & BMSR_LINK) { 253 sc->mii_ticks = 0; 254 break; 255 } 256 257 /* Announce link loss right after it happens. */ 258 if (sc->mii_ticks++ == 0) 259 break; 260 261 /* 262 * Only retry autonegotiation every mii_anegticks seconds. 263 */ 264 if (sc->mii_ticks <= sc->mii_anegticks) 265 return (0); 266 267 sc->mii_ticks = 0; 268 atphy_mii_phy_auto(sc); 269 break; 270 } 271 272 /* Update the media status. */ 273 mii_phy_status(sc); 274 275 /* Callback if something changed. */ 276 mii_phy_update(sc, cmd); 277 return (0); 278 } 279 280 void 281 atphy_status(struct mii_softc *sc) 282 { 283 struct mii_data *mii = sc->mii_pdata; 284 uint32_t bmsr, bmcr, gsr, ssr; 285 286 mii->mii_media_status = IFM_AVALID; 287 mii->mii_media_active = IFM_ETHER; 288 289 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 290 if (bmsr & BMSR_LINK) 291 mii->mii_media_status |= IFM_ACTIVE; 292 293 bmcr = PHY_READ(sc, MII_BMCR); 294 if (bmcr & BMCR_ISO) { 295 mii->mii_media_active |= IFM_NONE; 296 mii->mii_media_status = 0; 297 return; 298 } 299 300 if (bmcr & BMCR_LOOP) 301 mii->mii_media_active |= IFM_LOOP; 302 303 ssr = PHY_READ(sc, ATPHY_SSR); 304 if (!(ssr & ATPHY_SSR_SPD_DPLX_RESOLVED)) { 305 /* Erg, still trying, I guess... */ 306 mii->mii_media_active |= IFM_NONE; 307 return; 308 } 309 310 switch (ssr & ATPHY_SSR_SPEED_MASK) { 311 case ATPHY_SSR_1000MBS: 312 mii->mii_media_active |= IFM_1000_T; 313 /* 314 * atphy(4) has a valid link so reset mii_ticks. 315 * Resetting mii_ticks is needed in order to 316 * detect link loss after auto-negotiation. 317 */ 318 sc->mii_ticks = 0; 319 break; 320 case ATPHY_SSR_100MBS: 321 mii->mii_media_active |= IFM_100_TX; 322 sc->mii_ticks = 0; 323 break; 324 case ATPHY_SSR_10MBS: 325 mii->mii_media_active |= IFM_10_T; 326 sc->mii_ticks = 0; 327 break; 328 default: 329 mii->mii_media_active |= IFM_NONE; 330 return; 331 } 332 333 if (ssr & ATPHY_SSR_DUPLEX) 334 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc); 335 else 336 mii->mii_media_active |= IFM_HDX; 337 338 gsr = PHY_READ(sc, MII_100T2SR); 339 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 340 gsr & GTSR_MS_RES) 341 mii->mii_media_active |= IFM_ETH_MASTER; 342 } 343 344 void 345 atphy_reset(struct mii_softc *sc) 346 { 347 uint32_t reg; 348 int i; 349 350 /* Take PHY out of power down mode. */ 351 PHY_WRITE(sc, 29, 0x29); 352 PHY_WRITE(sc, 30, 0); 353 354 reg = PHY_READ(sc, ATPHY_SCR); 355 /* Enable automatic crossover. */ 356 reg |= ATPHY_SCR_AUTO_X_MODE; 357 /* Disable power down. */ 358 reg &= ~ATPHY_SCR_MAC_PDOWN; 359 /* Enable CRS on Tx. */ 360 reg |= ATPHY_SCR_ASSERT_CRS_ON_TX; 361 /* Auto correction for reversed cable polarity. */ 362 reg |= ATPHY_SCR_POLARITY_REVERSAL; 363 PHY_WRITE(sc, ATPHY_SCR, reg); 364 365 /* Workaround F1 bug to reset phy. */ 366 atphy_mii_phy_auto(sc); 367 368 for (i = 0; i < 1000; i++) { 369 DELAY(1); 370 if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0) 371 break; 372 } 373 } 374 375 int 376 atphy_mii_phy_auto(struct mii_softc *sc) 377 { 378 uint16_t anar; 379 380 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 381 if (sc->mii_flags & MIIF_DOPAUSE) 382 anar |= ANAR_PAUSE_TOWARDS; 383 PHY_WRITE(sc, MII_ANAR, anar); 384 if (sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) 385 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | 386 GTCR_ADV_1000THDX); 387 else if (sc->mii_model == MII_MODEL_ATHEROS_F1) { 388 /* 389 * AR8132 has 10/100 PHY and the PHY uses the same 390 * model number of F1 gigabit PHY. The PHY has no 391 * ability to establish gigabit link so explicitly 392 * disable 1000baseT configuration for the PHY. 393 * Otherwise, there is a case that atphy(4) could 394 * not establish a link against gigabit link partner 395 * unless the link partner supports down-shifting. 396 */ 397 PHY_WRITE(sc, MII_100T2CR, 0); 398 } 399 PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 400 401 return (EJUSTRETURN); 402 } 403