1 /* $OpenBSD: ofw_misc.h,v 1.31 2023/09/21 20:26:17 kettenis Exp $ */ 2 /* 3 * Copyright (c) 2017-2021 Mark Kettenis 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _DEV_OFW_MISC_H_ 19 #define _DEV_OFW_MISC_H_ 20 21 /* Register maps */ 22 23 void regmap_register(int, bus_space_tag_t, bus_space_handle_t, bus_size_t); 24 25 struct regmap; 26 struct regmap *regmap_bycompatible(char *); 27 struct regmap *regmap_bynode(int); 28 struct regmap *regmap_byphandle(uint32_t); 29 30 uint32_t regmap_read_4(struct regmap *, bus_size_t); 31 void regmap_write_4(struct regmap *, bus_size_t, uint32_t); 32 33 /* Interface support */ 34 35 struct ifnet; 36 37 struct if_device { 38 int if_node; 39 struct ifnet *if_ifp; 40 41 LIST_ENTRY(if_device) if_list; 42 uint32_t if_phandle; 43 }; 44 45 void if_register(struct if_device *); 46 47 struct ifnet *if_bynode(int); 48 struct ifnet *if_byphandle(uint32_t); 49 50 /* PHY support */ 51 52 #define PHY_NONE 0 53 #define PHY_TYPE_SATA 1 54 #define PHY_TYPE_PCIE 2 55 #define PHY_TYPE_USB2 3 56 #define PHY_TYPE_USB3 4 57 #define PHY_TYPE_UFS 5 58 59 struct phy_device { 60 int pd_node; 61 void *pd_cookie; 62 int (*pd_enable)(void *, uint32_t *); 63 64 LIST_ENTRY(phy_device) pd_list; 65 uint32_t pd_phandle; 66 uint32_t pd_cells; 67 }; 68 69 void phy_register(struct phy_device *); 70 71 int phy_enable_prop_idx(int, char *, int); 72 int phy_enable_idx(int, int); 73 int phy_enable(int, const char *); 74 75 /* I2C support */ 76 77 struct i2c_controller; 78 struct i2c_bus { 79 int ib_node; 80 struct i2c_controller *ib_ic; 81 82 LIST_ENTRY(i2c_bus) ib_list; 83 uint32_t ib_phandle; 84 }; 85 86 void i2c_register(struct i2c_bus *); 87 88 struct i2c_controller *i2c_bynode(int); 89 struct i2c_controller *i2c_byphandle(uint32_t); 90 91 /* SFP support */ 92 93 struct if_sffpage; 94 struct sfp_device { 95 int sd_node; 96 void *sd_cookie; 97 int (*sd_enable)(void *, int); 98 int (*sd_get_sffpage)(void *, struct if_sffpage *); 99 100 LIST_ENTRY(sfp_device) sd_list; 101 uint32_t sd_phandle; 102 }; 103 104 void sfp_register(struct sfp_device *); 105 106 struct mii_data; 107 int sfp_enable(uint32_t); 108 int sfp_disable(uint32_t); 109 int sfp_add_media(uint32_t, struct mii_data *); 110 int sfp_get_sffpage(uint32_t, struct if_sffpage *); 111 112 /* PWM support */ 113 114 #define PWM_POLARITY_INVERTED 0x00000001 115 116 struct pwm_state { 117 uint32_t ps_period; 118 uint32_t ps_pulse_width; 119 uint32_t ps_flags; 120 int ps_enabled; 121 }; 122 123 struct pwm_device { 124 int pd_node; 125 void *pd_cookie; 126 int (*pd_get_state)(void *, uint32_t *, struct pwm_state *); 127 int (*pd_set_state)(void *, uint32_t *, struct pwm_state *); 128 129 LIST_ENTRY(pwm_device) pd_list; 130 uint32_t pd_phandle; 131 uint32_t pd_cells; 132 }; 133 134 void pwm_register(struct pwm_device *); 135 136 int pwm_init_state(uint32_t *cells, struct pwm_state *ps); 137 int pwm_get_state(uint32_t *cells, struct pwm_state *ps); 138 int pwm_set_state(uint32_t *cells, struct pwm_state *ps); 139 140 /* Non-volatile memory support */ 141 142 struct nvmem_device { 143 int nd_node; 144 void *nd_cookie; 145 int (*nd_read)(void *, bus_addr_t, void *, bus_size_t); 146 int (*nd_write)(void *, bus_addr_t, const void *, bus_size_t); 147 148 LIST_ENTRY(nvmem_device) nd_list; 149 uint32_t nd_phandle; 150 }; 151 152 void nvmem_register(struct nvmem_device *); 153 int nvmem_read(uint32_t, bus_addr_t, void *, bus_size_t); 154 int nvmem_read_cell(int, const char *name, void *, bus_size_t); 155 int nvmem_write_cell(int, const char *name, const void *, bus_size_t); 156 157 /* Port/endpoint interface support */ 158 159 struct endpoint; 160 161 struct device_ports { 162 int dp_node; 163 void *dp_cookie; 164 165 int (*dp_ep_activate)(void *, struct endpoint *, void *); 166 void *(*dp_ep_get_cookie)(void *, struct endpoint *); 167 168 LIST_HEAD(, device_port) dp_ports; 169 }; 170 171 struct device_port { 172 int dp_node; 173 uint32_t dp_phandle; 174 uint32_t dp_reg; 175 struct device_ports *dp_ports; 176 LIST_ENTRY(device_port) dp_list; 177 LIST_HEAD(, endpoint) dp_endpoints; 178 }; 179 180 enum endpoint_type { 181 EP_DRM_BRIDGE = 1, /* struct drm_bridge */ 182 EP_DRM_CONNECTOR, /* struct drm_connector */ 183 EP_DRM_CRTC, /* struct drm_crtc */ 184 EP_DRM_ENCODER, /* struct drm_encoder */ 185 EP_DRM_PANEL, /* struct drm_panel */ 186 EP_DAI_DEVICE, /* struct dai_device */ 187 EP_USB_CONTROLLER_PORT, /* struct usb_controller_port */ 188 }; 189 190 struct usb_controller_port { 191 void *up_cookie; 192 void (*up_connect)(void *); 193 void (*up_disconnect)(void *); 194 }; 195 196 struct endpoint { 197 int ep_node; 198 uint32_t ep_phandle; 199 uint32_t ep_reg; 200 enum endpoint_type ep_type; 201 struct device_port *ep_port; 202 LIST_ENTRY(endpoint) ep_list; 203 LIST_ENTRY(endpoint) ep_plist; 204 }; 205 206 void device_ports_register(struct device_ports *, enum endpoint_type); 207 struct device_ports *device_ports_byphandle(uint32_t); 208 int device_port_activate(uint32_t, void *); 209 struct endpoint *endpoint_byreg(struct device_ports *, uint32_t, uint32_t); 210 struct endpoint *endpoint_remote(struct endpoint *); 211 int endpoint_activate(struct endpoint *, void *); 212 void *endpoint_get_cookie(struct endpoint *); 213 214 /* Digital audio interface support */ 215 216 struct dai_device { 217 int dd_node; 218 void *dd_cookie; 219 const void *dd_hw_if; 220 int (*dd_set_format)(void *, uint32_t, uint32_t, uint32_t); 221 int (*dd_set_sysclk)(void *, uint32_t); 222 int (*dd_set_tdm_slot)(void *, int); 223 224 LIST_ENTRY(dai_device) dd_list; 225 uint32_t dd_phandle; 226 227 struct device_ports dd_ports; 228 }; 229 230 void dai_register(struct dai_device *); 231 struct dai_device *dai_byphandle(uint32_t); 232 233 #define DAI_FORMAT_I2S 0 234 #define DAI_FORMAT_RJ 1 235 #define DAI_FORMAT_LJ 2 236 #define DAI_FORMAT_DSPA 3 237 #define DAI_FORMAT_DSPB 4 238 #define DAI_FORMAT_AC97 5 239 #define DAI_FORMAT_PDM 6 240 #define DAI_FORMAT_MSB 7 241 #define DAI_FORMAT_LSB 8 242 243 #define DAI_POLARITY_NB (0 << 0) 244 #define DAI_POLARITY_IB (1 << 0) 245 #define DAI_POLARITY_NF (0 << 1) 246 #define DAI_POLARITY_IF (1 << 1) 247 248 #define DAI_CLOCK_CBS (0 << 0) 249 #define DAI_CLOCK_CBM (1 << 0) 250 #define DAI_CLOCK_CFS (0 << 1) 251 #define DAI_CLOCK_CFM (1 << 1) 252 253 /* MII support */ 254 255 struct mii_bus { 256 int md_node; 257 void *md_cookie; 258 int (*md_readreg)(struct device *, int, int); 259 void (*md_writereg)(struct device *, int, int, int); 260 261 LIST_ENTRY(mii_bus) md_list; 262 }; 263 264 void mii_register(struct mii_bus *); 265 struct mii_bus *mii_bynode(int); 266 struct mii_bus *mii_byphandle(uint32_t); 267 268 /* IOMMU support */ 269 270 struct iommu_device { 271 int id_node; 272 void *id_cookie; 273 bus_dma_tag_t (*id_map)(void *, uint32_t *, bus_dma_tag_t); 274 void (*id_reserve)(void *, uint32_t *, bus_addr_t, bus_size_t); 275 276 LIST_ENTRY(iommu_device) id_list; 277 uint32_t id_phandle; 278 }; 279 280 void iommu_device_register(struct iommu_device *); 281 int iommu_device_lookup(int, uint32_t *, uint32_t *); 282 int iommu_device_lookup_pci(int, uint32_t, uint32_t *, uint32_t *); 283 bus_dma_tag_t iommu_device_map(int, bus_dma_tag_t); 284 bus_dma_tag_t iommu_device_map_pci(int, uint32_t, bus_dma_tag_t); 285 void iommu_reserve_region_pci(int, uint32_t, bus_addr_t, bus_size_t); 286 287 /* Mailbox support */ 288 289 struct mbox_client { 290 void (*mc_rx_callback)(void *); 291 void *mc_rx_arg; 292 int mc_flags; 293 #define MC_WAKEUP 0x00000001 294 }; 295 296 struct mbox_channel; 297 298 struct mbox_device { 299 int md_node; 300 void *md_cookie; 301 void *(*md_channel)(void *, uint32_t *, struct mbox_client *); 302 int (*md_recv)(void *, void *, size_t); 303 int (*md_send)(void *, const void *, size_t); 304 305 LIST_ENTRY(mbox_device) md_list; 306 uint32_t md_phandle; 307 uint32_t md_cells; 308 }; 309 310 void mbox_register(struct mbox_device *); 311 312 struct mbox_channel *mbox_channel(int, const char *, struct mbox_client *); 313 struct mbox_channel *mbox_channel_idx(int, int, struct mbox_client *); 314 315 int mbox_send(struct mbox_channel *, const void *, size_t); 316 int mbox_recv(struct mbox_channel *, void *, size_t); 317 318 /* hwlock support */ 319 320 struct hwlock_device { 321 int hd_node; 322 void *hd_cookie; 323 int (*hd_lock)(void *, uint32_t *, int); 324 325 LIST_ENTRY(hwlock_device) hd_list; 326 uint32_t hd_phandle; 327 uint32_t hd_cells; 328 }; 329 330 void hwlock_register(struct hwlock_device *); 331 332 int hwlock_lock_idx(int, int); 333 int hwlock_lock_idx_timeout(int, int, int); 334 int hwlock_unlock_idx(int, int); 335 336 #endif /* _DEV_OFW_MISC_H_ */ 337