1 /* $OpenBSD: ahc_pci.c,v 1.59 2020/07/05 21:54:44 krw Exp $ */ 2 /* $NetBSD: ahc_pci.c,v 1.43 2003/08/18 09:16:22 taca Exp $ */ 3 4 /* 5 * Product specific probe and attach routines for: 6 * 3940, 2940, aic7895, aic7890, aic7880, 7 * aic7870, aic7860 and aic7850 SCSI controllers 8 * 9 * Copyright (c) 1994-2001 Justin T. Gibbs. 10 * Copyright (c) 2000-2001 Adaptec Inc. 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions, and the following disclaimer, 18 * without modification. 19 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 20 * substantially similar to the "NO WARRANTY" disclaimer below 21 * ("Disclaimer") and any redistribution must be conditioned upon 22 * including a substantially similar Disclaimer requirement for further 23 * binary redistribution. 24 * 3. Neither the names of the above-listed copyright holders nor the names 25 * of any contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * Alternatively, this software may be distributed under the terms of the 29 * GNU General Public License ("GPL") version 2 as published by the Free 30 * Software Foundation. 31 * 32 * NO WARRANTY 33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 34 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 35 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 36 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 37 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 42 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 43 * POSSIBILITY OF SUCH DAMAGES. 44 * 45 * $Id: ahc_pci.c,v 1.59 2020/07/05 21:54:44 krw Exp $ 46 * 47 * //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#57 $ 48 * 49 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.22 2003/01/20 20:44:55 gibbs Exp $ 50 */ 51 /* 52 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 53 */ 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/queue.h> 60 #include <sys/device.h> 61 #include <sys/reboot.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 70 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 71 72 #include <dev/ic/aic7xxx_openbsd.h> 73 #include <dev/ic/aic7xxx_inline.h> 74 75 #ifndef __i386__ 76 #define AHC_ALLOW_MEMIO 77 #endif 78 79 static __inline uint64_t 80 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 81 { 82 uint64_t id; 83 84 id = subvendor 85 | (subdevice << 16) 86 | ((uint64_t)vendor << 32) 87 | ((uint64_t)device << 48); 88 89 return (id); 90 } 91 92 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 93 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 94 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 95 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull 96 #define ID_9005_SISL_ID 0x0005900500000000ull 97 #define ID_AIC7850 0x5078900400000000ull 98 #define ID_AHA_2902_04_10_15_20_30C 0x5078900478509004ull 99 #define ID_AIC7855 0x5578900400000000ull 100 #define ID_AIC7859 0x3860900400000000ull 101 #define ID_AHA_2930CU 0x3860900438699004ull 102 #define ID_AIC7860 0x6078900400000000ull 103 #define ID_AIC7860C 0x6078900478609004ull 104 #define ID_AHA_1480A 0x6075900400000000ull 105 #define ID_AHA_2940AU_0 0x6178900400000000ull 106 #define ID_AHA_2940AU_1 0x6178900478619004ull 107 #define ID_AHA_2940AU_CN 0x2178900478219004ull 108 #define ID_AHA_2930C_VAR 0x6038900438689004ull 109 110 #define ID_AIC7870 0x7078900400000000ull 111 #define ID_AHA_2940 0x7178900400000000ull 112 #define ID_AHA_3940 0x7278900400000000ull 113 #define ID_AHA_398X 0x7378900400000000ull 114 #define ID_AHA_2944 0x7478900400000000ull 115 #define ID_AHA_3944 0x7578900400000000ull 116 #define ID_AHA_4944 0x7678900400000000ull 117 118 #define ID_AIC7880 0x8078900400000000ull 119 #define ID_AIC7880_B 0x8078900478809004ull 120 #define ID_AHA_2940U 0x8178900400000000ull 121 #define ID_AHA_3940U 0x8278900400000000ull 122 #define ID_AHA_2944U 0x8478900400000000ull 123 #define ID_AHA_3944U 0x8578900400000000ull 124 #define ID_AHA_398XU 0x8378900400000000ull 125 #define ID_AHA_4944U 0x8678900400000000ull 126 #define ID_AHA_2940UB 0x8178900478819004ull 127 #define ID_AHA_2930U 0x8878900478889004ull 128 #define ID_AHA_2940U_PRO 0x8778900478879004ull 129 #define ID_AHA_2940U_CN 0x0078900478009004ull 130 131 #define ID_AIC7895 0x7895900478959004ull 132 #define ID_AIC7895_ARO 0x7890900478939004ull 133 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull 134 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 135 #define ID_AHA_3940AU 0x7895900478929004ull 136 #define ID_AHA_3944AU 0x7895900478949004ull 137 138 #define ID_AIC7890 0x001F9005000F9005ull 139 #define ID_AIC7890_ARO 0x00139005000F9005ull 140 #define ID_AAA_131U2 0x0013900500039005ull 141 #define ID_AHA_2930U2 0x0011900501819005ull 142 #define ID_AHA_2940U2B 0x00109005A1009005ull 143 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 144 #define ID_AHA_2940U2 0x00109005A1809005ull 145 #define ID_AHA_2950U2B 0x00109005E1009005ull 146 147 #define ID_AIC7892 0x008F9005FFFF9005ull 148 #define ID_AIC7892_ARO 0x00839005FFFF9005ull 149 #define ID_AHA_2915LP 0x0082900502109005ull 150 #define ID_AHA_29160 0x00809005E2A09005ull 151 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 152 #define ID_AHA_29160N 0x0080900562A09005ull 153 #define ID_AHA_29160C 0x0080900562209005ull 154 #define ID_AHA_29160B 0x00809005E2209005ull 155 #define ID_AHA_19160B 0x0081900562A19005ull 156 157 #define ID_AIC7896 0x005F9005FFFF9005ull 158 #define ID_AIC7896_ARO 0x00539005FFFF9005ull 159 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 160 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 161 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 162 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 163 164 #define ID_AIC7899 0x00CF9005FFFF9005ull 165 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull 166 #define ID_AHA_3960D 0x00C09005F6209005ull 167 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 168 169 #define ID_AIC7810 0x1078900400000000ull 170 #define ID_AIC7815 0x7815900400000000ull 171 172 #define DEVID_9005_TYPE(id) ((id) & 0xF) 173 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 174 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 175 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ 176 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 177 178 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 179 #define DEVID_9005_MAXRATE_U160 0x0 180 #define DEVID_9005_MAXRATE_ULTRA2 0x1 181 #define DEVID_9005_MAXRATE_ULTRA 0x2 182 #define DEVID_9005_MAXRATE_FAST 0x3 183 184 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 185 186 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 187 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 188 189 #define SUBID_9005_TYPE(id) ((id) & 0xF) 190 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 191 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 192 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 193 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 194 195 #define SUBID_9005_TYPE_KNOWN(id) \ 196 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 197 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 198 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 199 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 200 201 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 202 #define SUBID_9005_MAXRATE_ULTRA2 0x0 203 #define SUBID_9005_MAXRATE_ULTRA 0x1 204 #define SUBID_9005_MAXRATE_U160 0x2 205 #define SUBID_9005_MAXRATE_RESERVED 0x3 206 207 #define SUBID_9005_SEEPTYPE(id) \ 208 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 209 ? ((id) & 0xC0) >> 6 \ 210 : ((id) & 0x300) >> 8) 211 #define SUBID_9005_SEEPTYPE_NONE 0x0 212 #define SUBID_9005_SEEPTYPE_1K 0x1 213 #define SUBID_9005_SEEPTYPE_2K_4K 0x2 214 #define SUBID_9005_SEEPTYPE_RESERVED 0x3 215 #define SUBID_9005_AUTOTERM(id) \ 216 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 217 ? (((id) & 0x400) >> 10) == 0 \ 218 : (((id) & 0x40) >> 6) == 0) 219 220 #define SUBID_9005_NUMCHAN(id) \ 221 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 222 ? ((id) & 0x300) >> 8 \ 223 : ((id) & 0xC00) >> 10) 224 225 #define SUBID_9005_LEGACYCONN(id) \ 226 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 227 ? 0 \ 228 : ((id) & 0x80) >> 7) 229 230 #define SUBID_9005_MFUNCENB(id) \ 231 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 232 ? ((id) & 0x800) >> 11 \ 233 : ((id) & 0x1000) >> 12) 234 /* 235 * Informational only. Should use chip register to be 236 * certain, but may be use in identification strings. 237 */ 238 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 239 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 240 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000 241 242 static ahc_device_setup_t ahc_aic785X_setup; 243 static ahc_device_setup_t ahc_aic7860_setup; 244 static ahc_device_setup_t ahc_apa1480_setup; 245 static ahc_device_setup_t ahc_aic7870_setup; 246 static ahc_device_setup_t ahc_aha394X_setup; 247 static ahc_device_setup_t ahc_aha494X_setup; 248 static ahc_device_setup_t ahc_aha398X_setup; 249 static ahc_device_setup_t ahc_aic7880_setup; 250 static ahc_device_setup_t ahc_aha2940Pro_setup; 251 static ahc_device_setup_t ahc_aha394XU_setup; 252 static ahc_device_setup_t ahc_aha398XU_setup; 253 static ahc_device_setup_t ahc_aic7890_setup; 254 static ahc_device_setup_t ahc_aic7892_setup; 255 static ahc_device_setup_t ahc_aic7895_setup; 256 static ahc_device_setup_t ahc_aic7896_setup; 257 static ahc_device_setup_t ahc_aic7899_setup; 258 static ahc_device_setup_t ahc_aha29160C_setup; 259 static ahc_device_setup_t ahc_raid_setup; 260 static ahc_device_setup_t ahc_aha394XX_setup; 261 static ahc_device_setup_t ahc_aha494XX_setup; 262 static ahc_device_setup_t ahc_aha398XX_setup; 263 264 struct ahc_pci_identity ahc_pci_ident_table [] = 265 { 266 /* aic7850 based controllers */ 267 { 268 ID_AHA_2902_04_10_15_20_30C, 269 ID_ALL_MASK, 270 ahc_aic785X_setup 271 }, 272 /* aic7860 based controllers */ 273 { 274 ID_AHA_2930CU, 275 ID_ALL_MASK, 276 ahc_aic7860_setup 277 }, 278 { 279 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 280 ID_DEV_VENDOR_MASK, 281 ahc_apa1480_setup 282 }, 283 { 284 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 285 ID_DEV_VENDOR_MASK, 286 ahc_aic7860_setup 287 }, 288 { 289 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 290 ID_DEV_VENDOR_MASK, 291 ahc_aic7860_setup 292 }, 293 { 294 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 295 ID_DEV_VENDOR_MASK, 296 ahc_aic7860_setup 297 }, 298 /* aic7870 based controllers */ 299 { 300 ID_AHA_2940, 301 ID_ALL_MASK, 302 ahc_aic7870_setup 303 }, 304 { 305 ID_AHA_3940, 306 ID_ALL_MASK, 307 ahc_aha394X_setup 308 }, 309 { 310 ID_AHA_398X, 311 ID_ALL_MASK, 312 ahc_aha398X_setup 313 }, 314 { 315 ID_AHA_2944, 316 ID_ALL_MASK, 317 ahc_aic7870_setup 318 }, 319 { 320 ID_AHA_3944, 321 ID_ALL_MASK, 322 ahc_aha394X_setup 323 }, 324 { 325 ID_AHA_4944, 326 ID_ALL_MASK, 327 ahc_aha494X_setup 328 }, 329 /* aic7880 based controllers */ 330 { 331 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 332 ID_DEV_VENDOR_MASK, 333 ahc_aic7880_setup 334 }, 335 { 336 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 337 ID_DEV_VENDOR_MASK, 338 ahc_aha394XU_setup 339 }, 340 { 341 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 342 ID_DEV_VENDOR_MASK, 343 ahc_aic7880_setup 344 }, 345 { 346 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 347 ID_DEV_VENDOR_MASK, 348 ahc_aha394XU_setup 349 }, 350 { 351 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 352 ID_DEV_VENDOR_MASK, 353 ahc_aha398XU_setup 354 }, 355 { 356 /* 357 * XXX Don't know the slot numbers 358 * so we can't identify channels 359 */ 360 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 361 ID_DEV_VENDOR_MASK, 362 ahc_aic7880_setup 363 }, 364 { 365 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 366 ID_DEV_VENDOR_MASK, 367 ahc_aic7880_setup 368 }, 369 { 370 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 371 ID_DEV_VENDOR_MASK, 372 ahc_aha2940Pro_setup 373 }, 374 { 375 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 376 ID_DEV_VENDOR_MASK, 377 ahc_aic7880_setup 378 }, 379 /* Ignore all SISL (AAC on MB) based controllers. */ 380 { 381 ID_9005_SISL_ID, 382 ID_9005_SISL_MASK, 383 NULL 384 }, 385 /* aic7890 based controllers */ 386 { 387 ID_AHA_2930U2, 388 ID_ALL_MASK, 389 ahc_aic7890_setup 390 }, 391 { 392 ID_AHA_2940U2B, 393 ID_ALL_MASK, 394 ahc_aic7890_setup 395 }, 396 { 397 ID_AHA_2940U2_OEM, 398 ID_ALL_MASK, 399 ahc_aic7890_setup 400 }, 401 { 402 ID_AHA_2940U2, 403 ID_ALL_MASK, 404 ahc_aic7890_setup 405 }, 406 { 407 ID_AHA_2950U2B, 408 ID_ALL_MASK, 409 ahc_aic7890_setup 410 }, 411 { 412 ID_AIC7890_ARO, 413 ID_ALL_MASK, 414 ahc_aic7890_setup 415 }, 416 { 417 ID_AAA_131U2, 418 ID_ALL_MASK, 419 ahc_aic7890_setup 420 }, 421 /* aic7892 based controllers */ 422 { 423 ID_AHA_29160, 424 ID_ALL_MASK, 425 ahc_aic7892_setup 426 }, 427 { 428 ID_AHA_29160_CPQ, 429 ID_ALL_MASK, 430 ahc_aic7892_setup 431 }, 432 { 433 ID_AHA_29160N, 434 ID_ALL_MASK, 435 ahc_aic7892_setup 436 }, 437 { 438 ID_AHA_29160C, 439 ID_ALL_MASK, 440 ahc_aha29160C_setup 441 }, 442 { 443 ID_AHA_29160B, 444 ID_ALL_MASK, 445 ahc_aic7892_setup 446 }, 447 { 448 ID_AHA_19160B, 449 ID_ALL_MASK, 450 ahc_aic7892_setup 451 }, 452 { 453 ID_AIC7892_ARO, 454 ID_ALL_MASK, 455 ahc_aic7892_setup 456 }, 457 { 458 ID_AHA_2915LP, 459 ID_ALL_MASK, 460 ahc_aic7892_setup 461 }, 462 /* aic7895 based controllers */ 463 { 464 ID_AHA_2940U_DUAL, 465 ID_ALL_MASK, 466 ahc_aic7895_setup 467 }, 468 { 469 ID_AHA_3940AU, 470 ID_ALL_MASK, 471 ahc_aic7895_setup 472 }, 473 { 474 ID_AHA_3944AU, 475 ID_ALL_MASK, 476 ahc_aic7895_setup 477 }, 478 { 479 ID_AIC7895_ARO, 480 ID_AIC7895_ARO_MASK, 481 ahc_aic7895_setup 482 }, 483 /* aic7896/97 based controllers */ 484 { 485 ID_AHA_3950U2B_0, 486 ID_ALL_MASK, 487 ahc_aic7896_setup 488 }, 489 { 490 ID_AHA_3950U2B_1, 491 ID_ALL_MASK, 492 ahc_aic7896_setup 493 }, 494 { 495 ID_AHA_3950U2D_0, 496 ID_ALL_MASK, 497 ahc_aic7896_setup 498 }, 499 { 500 ID_AHA_3950U2D_1, 501 ID_ALL_MASK, 502 ahc_aic7896_setup 503 }, 504 { 505 ID_AIC7896_ARO, 506 ID_ALL_MASK, 507 ahc_aic7896_setup 508 }, 509 /* aic7899 based controllers */ 510 { 511 ID_AHA_3960D, 512 ID_ALL_MASK, 513 ahc_aic7899_setup 514 }, 515 { 516 ID_AHA_3960D_CPQ, 517 ID_ALL_MASK, 518 ahc_aic7899_setup 519 }, 520 { 521 ID_AIC7899_ARO, 522 ID_ALL_MASK, 523 ahc_aic7899_setup 524 }, 525 /* Generic chip probes for devices we don't know 'exactly' */ 526 { 527 ID_AIC7850 & ID_DEV_VENDOR_MASK, 528 ID_DEV_VENDOR_MASK, 529 ahc_aic785X_setup 530 }, 531 { 532 ID_AIC7855 & ID_DEV_VENDOR_MASK, 533 ID_DEV_VENDOR_MASK, 534 ahc_aic785X_setup 535 }, 536 { 537 ID_AIC7859 & ID_DEV_VENDOR_MASK, 538 ID_DEV_VENDOR_MASK, 539 ahc_aic7860_setup 540 }, 541 { 542 ID_AIC7860 & ID_DEV_VENDOR_MASK, 543 ID_DEV_VENDOR_MASK, 544 ahc_aic7860_setup 545 }, 546 { 547 ID_AIC7870 & ID_DEV_VENDOR_MASK, 548 ID_DEV_VENDOR_MASK, 549 ahc_aic7870_setup 550 }, 551 { 552 ID_AIC7880 & ID_DEV_VENDOR_MASK, 553 ID_DEV_VENDOR_MASK, 554 ahc_aic7880_setup 555 }, 556 { 557 ID_AIC7890 & ID_9005_GENERIC_MASK, 558 ID_9005_GENERIC_MASK, 559 ahc_aic7890_setup 560 }, 561 { 562 ID_AIC7892 & ID_9005_GENERIC_MASK, 563 ID_9005_GENERIC_MASK, 564 ahc_aic7892_setup 565 }, 566 { 567 ID_AIC7895 & ID_DEV_VENDOR_MASK, 568 ID_DEV_VENDOR_MASK, 569 ahc_aic7895_setup 570 }, 571 { 572 ID_AIC7896 & ID_9005_GENERIC_MASK, 573 ID_9005_GENERIC_MASK, 574 ahc_aic7896_setup 575 }, 576 { 577 ID_AIC7899 & ID_9005_GENERIC_MASK, 578 ID_9005_GENERIC_MASK, 579 ahc_aic7899_setup 580 }, 581 { 582 ID_AIC7810 & ID_DEV_VENDOR_MASK, 583 ID_DEV_VENDOR_MASK, 584 ahc_raid_setup 585 }, 586 { 587 ID_AIC7815 & ID_DEV_VENDOR_MASK, 588 ID_DEV_VENDOR_MASK, 589 ahc_raid_setup 590 } 591 }; 592 593 #define AHC_394X_SLOT_CHANNEL_A 4 594 #define AHC_394X_SLOT_CHANNEL_B 5 595 596 #define AHC_398X_SLOT_CHANNEL_A 4 597 #define AHC_398X_SLOT_CHANNEL_B 8 598 #define AHC_398X_SLOT_CHANNEL_C 12 599 600 #define AHC_494X_SLOT_CHANNEL_A 4 601 #define AHC_494X_SLOT_CHANNEL_B 5 602 #define AHC_494X_SLOT_CHANNEL_C 6 603 #define AHC_494X_SLOT_CHANNEL_D 7 604 605 #define DEVCONFIG 0x40 606 #define PCIERRGENDIS 0x80000000ul 607 #define SCBSIZE32 0x00010000ul /* aic789X only */ 608 #define REXTVALID 0x00001000ul /* ultra cards only */ 609 #define MPORTMODE 0x00000400ul /* aic7870+ only */ 610 #define RAMPSM 0x00000200ul /* aic7870+ only */ 611 #define VOLSENSE 0x00000100ul 612 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ 613 #define SCBRAMSEL 0x00000080ul 614 #define MRDCEN 0x00000040ul 615 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 616 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 617 #define BERREN 0x00000008ul 618 #define DACEN 0x00000004ul 619 #define STPWLEVEL 0x00000002ul 620 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 621 622 #define CSIZE_LATTIME 0x0c 623 #define CACHESIZE 0x0000003ful /* only 5 bits */ 624 #define LATTIME 0x0000ff00ul 625 626 /* PCI STATUS definitions */ 627 #define DPE 0x80 628 #define SSE 0x40 629 #define RMA 0x20 630 #define RTA 0x10 631 #define STA 0x08 632 #define DPR 0x01 633 634 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, 635 uint16_t subvendor, uint16_t subdevice); 636 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 637 static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 638 int pcheck, int fast, int large); 639 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 640 static int ahc_pci_chip_init(struct ahc_softc *ahc); 641 642 int ahc_pci_probe(struct device *, void *, void *); 643 void ahc_pci_attach(struct device *, struct device *, void *); 644 645 646 struct cfattach ahc_pci_ca = { 647 sizeof(struct ahc_softc), ahc_pci_probe, ahc_pci_attach 648 }; 649 650 const struct ahc_pci_identity * 651 ahc_find_pci_device(id, subid, func) 652 pcireg_t id, subid; 653 u_int func; 654 { 655 u_int64_t full_id; 656 const struct ahc_pci_identity *entry; 657 u_int i; 658 659 full_id = ahc_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 660 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 661 662 /* 663 * If the second function is not hooked up, ignore it. 664 * Unfortunately, not all MB vendors implement the 665 * subdevice ID as per the Adaptec spec, so do our best 666 * to sanity check it prior to accepting the subdevice 667 * ID as valid. 668 */ 669 if (func > 0 670 && ahc_9005_subdevinfo_valid(PCI_VENDOR(id), PCI_PRODUCT(id), 671 PCI_VENDOR(subid), PCI_PRODUCT(subid)) 672 && SUBID_9005_MFUNCENB(PCI_PRODUCT(subid)) == 0) 673 return (NULL); 674 675 for (i = 0; i < NUM_ELEMENTS(ahc_pci_ident_table); i++) { 676 entry = &ahc_pci_ident_table[i]; 677 if (entry->full_id == (full_id & entry->id_mask)) 678 return (entry); 679 } 680 return (NULL); 681 } 682 683 int 684 ahc_pci_probe(parent, match, aux) 685 struct device *parent; 686 void *match, *aux; 687 { 688 struct pci_attach_args *pa = aux; 689 const struct ahc_pci_identity *entry; 690 pcireg_t subid; 691 692 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 693 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); 694 return (entry != NULL && entry->setup != NULL) ? 1 : 0; 695 } 696 697 void 698 ahc_pci_attach(parent, self, aux) 699 struct device *parent, *self; 700 void *aux; 701 { 702 struct pci_attach_args *pa = aux; 703 const struct ahc_pci_identity *entry; 704 struct ahc_softc *ahc = (void *)self; 705 pcireg_t command; 706 u_int our_id = 0; 707 u_int sxfrctl1; 708 u_int scsiseq; 709 u_int sblkctl; 710 uint8_t dscommand0; 711 uint32_t devconfig; 712 int error; 713 pcireg_t subid; 714 int ioh_valid; 715 bus_space_tag_t st, iot; 716 bus_space_handle_t sh, ioh; 717 #ifdef AHC_ALLOW_MEMIO 718 int memh_valid; 719 bus_space_tag_t memt; 720 bus_space_handle_t memh; 721 pcireg_t memtype; 722 #endif 723 pci_intr_handle_t ih; 724 const char *intrstr; 725 struct ahc_pci_busdata *bd; 726 int i; 727 728 /* 729 * Instead of ahc_alloc() as in FreeBSD, do the few relevant 730 * initializations manually. 731 */ 732 LIST_INIT(&ahc->pending_scbs); 733 ahc->channel = 'A'; 734 ahc->seqctl = FASTMODE; 735 for (i = 0; i < AHC_NUM_TARGETS; i++) 736 TAILQ_INIT(&ahc->untagged_queues[i]); 737 738 /* 739 * SCSI_IS_SCSIBUS_B() must returns false until sc_channel_b 740 * has been properly initialized. 741 */ 742 ahc->sc_child_b = NULL; 743 744 ahc->dev_softc = pa; 745 746 ahc_set_name(ahc, ahc->sc_dev.dv_xname); 747 ahc->parent_dmat = pa->pa_dmat; 748 749 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 750 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); 751 if (entry == NULL) 752 return; 753 754 /* Keep information about the PCI bus */ 755 bd = malloc(sizeof (struct ahc_pci_busdata), M_DEVBUF, 756 M_NOWAIT | M_ZERO); 757 if (bd == NULL) { 758 printf("%s: unable to allocate bus-specific data\n", 759 ahc_name(ahc)); 760 return; 761 } 762 763 bd->pc = pa->pa_pc; 764 bd->tag = pa->pa_tag; 765 bd->func = pa->pa_function; 766 bd->dev = pa->pa_device; 767 bd->class = pa->pa_class; 768 769 ahc->bd = bd; 770 771 error = entry->setup(ahc); 772 if (error != 0) 773 return; 774 775 ioh_valid = 0; 776 777 #ifdef AHC_ALLOW_MEMIO 778 memh_valid = 0; 779 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR); 780 switch (memtype) { 781 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 782 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 783 memh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR, 784 memtype, 0, &memt, &memh, NULL, NULL, 0) == 0); 785 break; 786 default: 787 memh_valid = 0; 788 } 789 if (memh_valid == 0) 790 #endif 791 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR, 792 PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, NULL, 0) == 0); 793 #if 0 794 printf("%s: mem mapping: memt 0x%lx, memh 0x%lx, iot 0x%lx, ioh 0x%lx\n", 795 ahc_name(ahc), (u_long)memt, memh, (u_long)iot, ioh); 796 #endif 797 798 if (ioh_valid) { 799 st = iot; 800 sh = ioh; 801 #ifdef AHC_ALLOW_MEMIO 802 } else if (memh_valid) { 803 st = memt; 804 sh = memh; 805 #endif 806 } else { 807 printf(": unable to map registers\n"); 808 return; 809 } 810 ahc->tag = st; 811 ahc->bsh = sh; 812 813 ahc->chip |= AHC_PCI; 814 /* 815 * Before we continue probing the card, ensure that 816 * its interrupts are *disabled*. We don't want 817 * a misstep to hang the machine in an interrupt 818 * storm. 819 */ 820 ahc_intr_enable(ahc, FALSE); 821 822 /* 823 * XXX somehow reading this once fails on some sparc64 systems. 824 * This may be a problem in the sparc64 PCI code. Doing it 825 * twice works around it. 826 */ 827 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 828 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 829 830 /* 831 * If we need to support high memory, enable dual 832 * address cycles. This bit must be set to enable 833 * high address bit generation even if we are on a 834 * 64bit bus (PCI64BIT set in devconfig). 835 */ 836 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 837 838 if (1/*bootverbose*/) 839 printf("%s: Enabling 39Bit Addressing\n", 840 ahc_name(ahc)); 841 devconfig |= DACEN; 842 } 843 844 /* Ensure that pci error generation, a test feature, is disabled. */ 845 devconfig |= PCIERRGENDIS; 846 847 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 848 849 /* 850 * Disable PCI parity error reporting. Users typically 851 * do this to work around broken PCI chipsets that get 852 * the parity timing wrong and thus generate lots of spurious 853 * errors. 854 */ 855 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) { 856 command = pci_conf_read(pa->pa_pc, pa->pa_tag, 857 PCI_COMMAND_STATUS_REG); 858 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 859 command & ~PCI_COMMAND_PARITY_ENABLE); 860 } 861 862 /* On all PCI adapters, we allow SCB paging */ 863 ahc->flags |= AHC_PAGESCBS; 864 error = ahc_softc_init(ahc); 865 if (error != 0) 866 goto error_out; 867 868 ahc->bus_intr = ahc_pci_intr; 869 ahc->bus_chip_init = ahc_pci_chip_init; 870 871 /* Remember how the card was setup in case there is no SEEPROM */ 872 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 873 ahc_pause(ahc); 874 if ((ahc->features & AHC_ULTRA2) != 0) 875 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 876 else 877 our_id = ahc_inb(ahc, SCSIID) & OID; 878 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 879 scsiseq = ahc_inb(ahc, SCSISEQ); 880 } else { 881 sxfrctl1 = STPWEN; 882 our_id = 7; 883 scsiseq = 0; 884 } 885 886 error = ahc_reset(ahc, /*reinit*/FALSE); 887 if (error != 0) 888 goto error_out; 889 890 if ((ahc->features & AHC_DT) != 0) { 891 u_int sfunct; 892 893 /* Perform ALT-Mode Setup */ 894 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 895 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 896 ahc_outb(ahc, OPTIONMODE, 897 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 898 ahc_outb(ahc, SFUNCT, sfunct); 899 900 /* Normal mode setup */ 901 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 902 |TARGCRCENDEN); 903 } 904 905 if (pci_intr_map(pa, &ih)) { 906 printf("%s: couldn't map interrupt\n", ahc_name(ahc)); 907 ahc_free(ahc); 908 return; 909 } 910 intrstr = pci_intr_string(pa->pa_pc, ih); 911 ahc->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 912 ahc_platform_intr, ahc, ahc->sc_dev.dv_xname); 913 if (ahc->ih == NULL) { 914 printf(": couldn't establish interrupt"); 915 if (intrstr != NULL) 916 printf(" at %s", intrstr); 917 printf("\n"); 918 ahc_free(ahc); 919 return; 920 } else 921 printf(": %s\n", intrstr ? intrstr : "?"); 922 923 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 924 dscommand0 |= MPARCKEN|CACHETHEN; 925 if ((ahc->features & AHC_ULTRA2) != 0) { 926 927 /* 928 * DPARCKEN doesn't work correctly on 929 * some MBs so don't use it. 930 */ 931 dscommand0 &= ~DPARCKEN; 932 } 933 934 /* 935 * Handle chips that must have cache line 936 * streaming (dis/en)abled. 937 */ 938 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 939 dscommand0 |= CACHETHEN; 940 941 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 942 dscommand0 &= ~CACHETHEN; 943 944 ahc_outb(ahc, DSCOMMAND0, dscommand0); 945 946 ahc->pci_cachesize = 947 pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME) & CACHESIZE; 948 ahc->pci_cachesize *= 4; 949 950 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 951 && ahc->pci_cachesize == 4) { 952 pci_conf_write(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME, 0); 953 ahc->pci_cachesize = 0; 954 } 955 956 /* 957 * We cannot perform ULTRA speeds without the presence 958 * of the external precision resistor. 959 */ 960 if ((ahc->features & AHC_ULTRA) != 0) { 961 uint32_t devconfig; 962 963 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 964 if ((devconfig & REXTVALID) == 0) 965 ahc->features &= ~AHC_ULTRA; 966 } 967 968 ahc->seep_config = malloc(sizeof(*ahc->seep_config), M_DEVBUF, 969 M_NOWAIT | M_ZERO); 970 if (ahc->seep_config == NULL) 971 goto error_out; 972 973 /* See if we have a SEEPROM and perform auto-term */ 974 ahc_check_extport(ahc, &sxfrctl1); 975 976 /* 977 * Take the LED out of diagnostic mode 978 */ 979 sblkctl = ahc_inb(ahc, SBLKCTL); 980 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 981 982 if ((ahc->features & AHC_ULTRA2) != 0) { 983 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 984 } else { 985 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 986 } 987 988 if (ahc->flags & AHC_USEDEFAULTS) { 989 /* 990 * PCI Adapter default setup 991 * Should only be used if the adapter does not have 992 * a SEEPROM. 993 */ 994 /* See if someone else set us up already */ 995 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0 996 && scsiseq != 0) { 997 printf("%s: Using left over BIOS settings\n", 998 ahc_name(ahc)); 999 ahc->flags &= ~AHC_USEDEFAULTS; 1000 ahc->flags |= AHC_BIOS_ENABLED; 1001 } else { 1002 /* 1003 * Assume only one connector and always turn 1004 * on termination. 1005 */ 1006 our_id = 0x07; 1007 sxfrctl1 = STPWEN; 1008 } 1009 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 1010 1011 ahc->our_id = our_id; 1012 } 1013 1014 /* 1015 * Take a look to see if we have external SRAM. 1016 * We currently do not attempt to use SRAM that is 1017 * shared among multiple controllers. 1018 */ 1019 ahc_probe_ext_scbram(ahc); 1020 1021 /* 1022 * Record our termination setting for the 1023 * generic initialization routine. 1024 */ 1025 if ((sxfrctl1 & STPWEN) != 0) 1026 ahc->flags |= AHC_TERM_ENB_A; 1027 1028 /* 1029 * Save chip register configuration data for chip resets 1030 * that occur during runtime and resume events. 1031 */ 1032 ahc->bus_softc.pci_softc.devconfig = 1033 pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 1034 ahc->bus_softc.pci_softc.command = 1035 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1036 ahc->bus_softc.pci_softc.csize_lattime = 1037 pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME); 1038 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1039 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS); 1040 if ((ahc->features & AHC_DT) != 0) { 1041 u_int sfunct; 1042 1043 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 1044 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 1045 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE); 1046 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT); 1047 ahc_outb(ahc, SFUNCT, sfunct); 1048 ahc->bus_softc.pci_softc.crccontrol1 = 1049 ahc_inb(ahc, CRCCONTROL1); 1050 } 1051 if ((ahc->features & AHC_MULTI_FUNC) != 0) 1052 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR); 1053 1054 if ((ahc->features & AHC_ULTRA2) != 0) 1055 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH); 1056 1057 /* Core initialization */ 1058 if (ahc_init(ahc)) 1059 goto error_out; 1060 1061 ahc_attach(ahc); 1062 1063 return; 1064 1065 error_out: 1066 ahc_free(ahc); 1067 return; 1068 } 1069 1070 static int 1071 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, 1072 uint16_t subdevice, uint16_t subvendor) 1073 { 1074 int result; 1075 1076 /* Default to invalid. */ 1077 result = 0; 1078 if (vendor == 0x9005 1079 && subvendor == 0x9005 1080 && subdevice != device 1081 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { 1082 1083 switch (SUBID_9005_TYPE(subdevice)) { 1084 case SUBID_9005_TYPE_MB: 1085 break; 1086 case SUBID_9005_TYPE_CARD: 1087 case SUBID_9005_TYPE_LCCARD: 1088 /* 1089 * Currently only trust Adaptec cards to 1090 * get the sub device info correct. 1091 */ 1092 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) 1093 result = 1; 1094 break; 1095 case SUBID_9005_TYPE_RAID: 1096 break; 1097 default: 1098 break; 1099 } 1100 } 1101 return (result); 1102 } 1103 1104 1105 /* 1106 * Test for the presense of external sram in an 1107 * "unshared" configuration. 1108 */ 1109 static int 1110 ahc_ext_scbram_present(struct ahc_softc *ahc) 1111 { 1112 u_int chip; 1113 int ramps; 1114 int single_user; 1115 uint32_t devconfig; 1116 1117 chip = ahc->chip & AHC_CHIPID_MASK; 1118 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1119 single_user = (devconfig & MPORTMODE) != 0; 1120 1121 if ((ahc->features & AHC_ULTRA2) != 0) 1122 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 1123 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) 1124 /* 1125 * External SCBRAM arbitration is flakey 1126 * on these chips. Unfortunately this means 1127 * we don't use the extra SCB ram space on the 1128 * 3940AUW. 1129 */ 1130 ramps = 0; 1131 else if (chip >= AHC_AIC7870) 1132 ramps = (devconfig & RAMPSM) != 0; 1133 else 1134 ramps = 0; 1135 1136 if (ramps && single_user) 1137 return (1); 1138 return (0); 1139 } 1140 1141 /* 1142 * Enable external scbram. 1143 */ 1144 static void 1145 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 1146 int fast, int large) 1147 { 1148 uint32_t devconfig; 1149 1150 if (ahc->features & AHC_MULTI_FUNC) { 1151 /* 1152 * Set the SCB Base addr (highest address bit) 1153 * depending on which channel we are. 1154 */ 1155 ahc_outb(ahc, SCBBADDR, ahc->bd->func); 1156 } 1157 1158 ahc->flags &= ~AHC_LSCBS_ENABLED; 1159 if (large) 1160 ahc->flags |= AHC_LSCBS_ENABLED; 1161 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1162 if ((ahc->features & AHC_ULTRA2) != 0) { 1163 u_int dscommand0; 1164 1165 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1166 if (enable) 1167 dscommand0 &= ~INTSCBRAMSEL; 1168 else 1169 dscommand0 |= INTSCBRAMSEL; 1170 if (large) 1171 dscommand0 &= ~USCBSIZE32; 1172 else 1173 dscommand0 |= USCBSIZE32; 1174 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1175 } else { 1176 if (fast) 1177 devconfig &= ~EXTSCBTIME; 1178 else 1179 devconfig |= EXTSCBTIME; 1180 if (enable) 1181 devconfig &= ~SCBRAMSEL; 1182 else 1183 devconfig |= SCBRAMSEL; 1184 if (large) 1185 devconfig &= ~SCBSIZE32; 1186 else 1187 devconfig |= SCBSIZE32; 1188 } 1189 if (pcheck) 1190 devconfig |= EXTSCBPEN; 1191 else 1192 devconfig &= ~EXTSCBPEN; 1193 1194 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); 1195 } 1196 1197 /* 1198 * Take a look to see if we have external SRAM. 1199 * We currently do not attempt to use SRAM that is 1200 * shared among multiple controllers. 1201 */ 1202 static void 1203 ahc_probe_ext_scbram(struct ahc_softc *ahc) 1204 { 1205 int num_scbs; 1206 int test_num_scbs; 1207 int enable; 1208 int pcheck; 1209 int fast; 1210 int large; 1211 1212 enable = FALSE; 1213 pcheck = FALSE; 1214 fast = FALSE; 1215 large = FALSE; 1216 num_scbs = 0; 1217 1218 if (ahc_ext_scbram_present(ahc) == 0) 1219 goto done; 1220 1221 /* 1222 * Probe for the best parameters to use. 1223 */ 1224 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1225 num_scbs = ahc_probe_scbs(ahc); 1226 if (num_scbs == 0) { 1227 /* The SRAM wasn't really present. */ 1228 goto done; 1229 } 1230 enable = TRUE; 1231 1232 /* 1233 * Clear any outstanding parity error 1234 * and ensure that parity error reporting 1235 * is enabled. 1236 */ 1237 ahc_outb(ahc, SEQCTL, 0); 1238 ahc_outb(ahc, CLRINT, CLRPARERR); 1239 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1240 1241 /* Now see if we can do parity */ 1242 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1243 num_scbs = ahc_probe_scbs(ahc); 1244 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1245 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1246 pcheck = TRUE; 1247 1248 /* Clear any resulting parity error */ 1249 ahc_outb(ahc, CLRINT, CLRPARERR); 1250 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1251 1252 /* Now see if we can do fast timing */ 1253 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1254 test_num_scbs = ahc_probe_scbs(ahc); 1255 if (test_num_scbs == num_scbs 1256 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1257 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1258 fast = TRUE; 1259 1260 /* 1261 * See if we can use large SCBs and still maintain 1262 * the same overall count of SCBs. 1263 */ 1264 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1265 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1266 test_num_scbs = ahc_probe_scbs(ahc); 1267 if (test_num_scbs >= num_scbs) { 1268 large = TRUE; 1269 num_scbs = test_num_scbs; 1270 if (num_scbs >= 64) { 1271 /* 1272 * We have enough space to move the 1273 * "busy targets table" into SCB space 1274 * and make it qualify all the way to the 1275 * lun level. 1276 */ 1277 ahc->flags |= AHC_SCB_BTT; 1278 } 1279 } 1280 } 1281 done: 1282 /* 1283 * Disable parity error reporting until we 1284 * can load instruction ram. 1285 */ 1286 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1287 /* Clear any latched parity error */ 1288 ahc_outb(ahc, CLRINT, CLRPARERR); 1289 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1290 if (1/*bootverbose*/ && enable) { 1291 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1292 ahc_name(ahc), fast ? "fast" : "slow", 1293 pcheck ? ", parity checking enabled" : "", 1294 large ? 64 : 32); 1295 } 1296 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1297 } 1298 1299 #if 0 1300 /* 1301 * Perform some simple tests that should catch situations where 1302 * our registers are invalidly mapped. 1303 */ 1304 int 1305 ahc_pci_test_register_access(struct ahc_softc *ahc) 1306 { 1307 int error; 1308 u_int status1; 1309 uint32_t cmd; 1310 uint8_t hcntrl; 1311 1312 error = EIO; 1313 1314 /* 1315 * Enable PCI error interrupt status, but suppress NMIs 1316 * generated by SERR raised due to target aborts. 1317 */ 1318 cmd = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND); 1319 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND, 1320 cmd & ~PCIM_CMD_SERRESPEN); 1321 1322 /* 1323 * First a simple test to see if any 1324 * registers can be read. Reading 1325 * HCNTRL has no side effects and has 1326 * at least one bit that is guaranteed to 1327 * be zero so it is a good register to 1328 * use for this test. 1329 */ 1330 hcntrl = ahc_inb(ahc, HCNTRL); 1331 if (hcntrl == 0xFF) 1332 goto fail; 1333 1334 /* 1335 * Next create a situation where write combining 1336 * or read prefetching could be initiated by the 1337 * CPU or host bridge. Our device does not support 1338 * either, so look for data corruption and/or flagged 1339 * PCI errors. 1340 */ 1341 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); 1342 while (ahc_is_paused(ahc) == 0) 1343 ; 1344 ahc_outb(ahc, SEQCTL, PERRORDIS); 1345 ahc_outb(ahc, SCBPTR, 0); 1346 ahc_outl(ahc, SCB_BASE, 0x5aa555aa); 1347 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa) 1348 goto fail; 1349 1350 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1351 PCI_COMMAND_STATUS_REG + 1); 1352 if ((status1 & STA) != 0) 1353 goto fail; 1354 1355 error = 0; 1356 1357 fail: 1358 /* Silently clear any latched errors. */ 1359 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG + 1); 1360 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1361 status1, /*bytes*/1); 1362 ahc_outb(ahc, CLRINT, CLRPARERR); 1363 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1364 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 1365 return (error); 1366 } 1367 #endif 1368 1369 void 1370 ahc_pci_intr(struct ahc_softc *ahc) 1371 { 1372 u_int error; 1373 u_int status1; 1374 1375 error = ahc_inb(ahc, ERROR); 1376 if ((error & PCIERRSTAT) == 0) 1377 return; 1378 1379 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG); 1380 1381 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1382 ahc_name(ahc), 1383 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1384 1385 if (status1 & DPE) { 1386 printf("%s: Data Parity Error Detected during address " 1387 "or write data phase\n", ahc_name(ahc)); 1388 } 1389 if (status1 & SSE) { 1390 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1391 } 1392 if (status1 & RMA) { 1393 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1394 } 1395 if (status1 & RTA) { 1396 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1397 } 1398 if (status1 & STA) { 1399 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1400 } 1401 if (status1 & DPR) { 1402 printf("%s: Data Parity Error has been reported via PERR#\n", 1403 ahc_name(ahc)); 1404 } 1405 1406 /* Clear latched errors. */ 1407 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG, status1); 1408 1409 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1410 printf("%s: Latched PCIERR interrupt with " 1411 "no status bits set\n", ahc_name(ahc)); 1412 } else { 1413 ahc_outb(ahc, CLRINT, CLRPARERR); 1414 } 1415 1416 ahc_unpause(ahc); 1417 } 1418 1419 static int 1420 ahc_pci_chip_init(struct ahc_softc *ahc) 1421 { 1422 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0); 1423 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus); 1424 if ((ahc->features & AHC_DT) != 0) { 1425 u_int sfunct; 1426 1427 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 1428 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 1429 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode); 1430 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt); 1431 ahc_outb(ahc, SFUNCT, sfunct); 1432 ahc_outb(ahc, CRCCONTROL1, 1433 ahc->bus_softc.pci_softc.crccontrol1); 1434 } 1435 if ((ahc->features & AHC_MULTI_FUNC) != 0) 1436 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr); 1437 1438 if ((ahc->features & AHC_ULTRA2) != 0) 1439 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh); 1440 1441 return (ahc_chip_init(ahc)); 1442 } 1443 1444 static int 1445 ahc_aic785X_setup(struct ahc_softc *ahc) 1446 { 1447 uint8_t rev; 1448 1449 ahc->channel = 'A'; 1450 ahc->chip = AHC_AIC7850; 1451 ahc->features = AHC_AIC7850_FE; 1452 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1453 rev = PCI_REVISION(ahc->bd->class); 1454 if (rev >= 1) 1455 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1456 ahc->instruction_ram_size = 512; 1457 return (0); 1458 } 1459 1460 static int 1461 ahc_aic7860_setup(struct ahc_softc *ahc) 1462 { 1463 uint8_t rev; 1464 1465 ahc->channel = 'A'; 1466 ahc->chip = AHC_AIC7860; 1467 ahc->features = AHC_AIC7860_FE; 1468 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1469 rev = PCI_REVISION(ahc->bd->class); 1470 if (rev >= 1) 1471 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1472 ahc->instruction_ram_size = 512; 1473 return (0); 1474 } 1475 1476 static int 1477 ahc_apa1480_setup(struct ahc_softc *ahc) 1478 { 1479 int error; 1480 1481 error = ahc_aic7860_setup(ahc); 1482 if (error != 0) 1483 return (error); 1484 ahc->features |= AHC_REMOVABLE; 1485 return (0); 1486 } 1487 1488 static int 1489 ahc_aic7870_setup(struct ahc_softc *ahc) 1490 { 1491 1492 ahc->channel = 'A'; 1493 ahc->chip = AHC_AIC7870; 1494 ahc->features = AHC_AIC7870_FE; 1495 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1496 ahc->instruction_ram_size = 512; 1497 return (0); 1498 } 1499 1500 static int 1501 ahc_aha394X_setup(struct ahc_softc *ahc) 1502 { 1503 int error; 1504 1505 error = ahc_aic7870_setup(ahc); 1506 if (error == 0) 1507 error = ahc_aha394XX_setup(ahc); 1508 return (error); 1509 } 1510 1511 static int 1512 ahc_aha398X_setup(struct ahc_softc *ahc) 1513 { 1514 int error; 1515 1516 error = ahc_aic7870_setup(ahc); 1517 if (error == 0) 1518 error = ahc_aha398XX_setup(ahc); 1519 return (error); 1520 } 1521 1522 static int 1523 ahc_aha494X_setup(struct ahc_softc *ahc) 1524 { 1525 int error; 1526 1527 error = ahc_aic7870_setup(ahc); 1528 if (error == 0) 1529 error = ahc_aha494XX_setup(ahc); 1530 return (error); 1531 } 1532 1533 static int 1534 ahc_aic7880_setup(struct ahc_softc *ahc) 1535 { 1536 uint8_t rev; 1537 1538 ahc->channel = 'A'; 1539 ahc->chip = AHC_AIC7880; 1540 ahc->features = AHC_AIC7880_FE; 1541 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 1542 rev = PCI_REVISION(ahc->bd->class); 1543 if (rev >= 1) { 1544 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1545 } else { 1546 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1547 } 1548 ahc->instruction_ram_size = 512; 1549 return (0); 1550 } 1551 1552 static int 1553 ahc_aha2940Pro_setup(struct ahc_softc *ahc) 1554 { 1555 1556 ahc->flags |= AHC_INT50_SPEEDFLEX; 1557 return (ahc_aic7880_setup(ahc)); 1558 } 1559 1560 static int 1561 ahc_aha394XU_setup(struct ahc_softc *ahc) 1562 { 1563 int error; 1564 1565 error = ahc_aic7880_setup(ahc); 1566 if (error == 0) 1567 error = ahc_aha394XX_setup(ahc); 1568 return (error); 1569 } 1570 1571 static int 1572 ahc_aha398XU_setup(struct ahc_softc *ahc) 1573 { 1574 int error; 1575 1576 error = ahc_aic7880_setup(ahc); 1577 if (error == 0) 1578 error = ahc_aha398XX_setup(ahc); 1579 return (error); 1580 } 1581 1582 static int 1583 ahc_aic7890_setup(struct ahc_softc *ahc) 1584 { 1585 uint8_t rev; 1586 1587 ahc->channel = 'A'; 1588 ahc->chip = AHC_AIC7890; 1589 ahc->features = AHC_AIC7890_FE; 1590 ahc->flags |= AHC_NEWEEPROM_FMT; 1591 rev = PCI_REVISION(ahc->bd->class); 1592 if (rev == 0) 1593 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 1594 ahc->instruction_ram_size = 768; 1595 return (0); 1596 } 1597 1598 static int 1599 ahc_aic7892_setup(struct ahc_softc *ahc) 1600 { 1601 1602 ahc->channel = 'A'; 1603 ahc->chip = AHC_AIC7892; 1604 ahc->features = AHC_AIC7892_FE; 1605 ahc->flags |= AHC_NEWEEPROM_FMT; 1606 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1607 ahc->instruction_ram_size = 1024; 1608 return (0); 1609 } 1610 1611 static int 1612 ahc_aic7895_setup(struct ahc_softc *ahc) 1613 { 1614 uint8_t rev; 1615 1616 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1617 /* 1618 * The 'C' revision of the aic7895 has a few additional features. 1619 */ 1620 rev = PCI_REVISION(ahc->bd->class); 1621 if (rev >= 4) { 1622 ahc->chip = AHC_AIC7895C; 1623 ahc->features = AHC_AIC7895C_FE; 1624 } else { 1625 u_int command; 1626 1627 ahc->chip = AHC_AIC7895; 1628 ahc->features = AHC_AIC7895_FE; 1629 1630 /* 1631 * The BIOS disables the use of MWI transactions 1632 * since it does not have the MWI bug work around 1633 * we have. Disabling MWI reduces performance, so 1634 * turn it on again. 1635 */ 1636 command = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG); 1637 command |= PCI_COMMAND_INVALIDATE_ENABLE; 1638 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG, command); 1639 ahc->bugs |= AHC_PCI_MWI_BUG; 1640 } 1641 /* 1642 * XXX Does CACHETHEN really not work??? What about PCI retry? 1643 * on C level chips. Need to test, but for now, play it safe. 1644 */ 1645 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 1646 | AHC_CACHETHEN_BUG; 1647 1648 #if 0 1649 uint32_t devconfig; 1650 1651 /* 1652 * Cachesize must also be zero due to stray DAC 1653 * problem when sitting behind some bridges. 1654 */ 1655 pci_conf_write(ahc->bd->pc, ahc->bd->tag, CSIZE_LATTIME, 0); 1656 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1657 devconfig |= MRDCEN; 1658 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); 1659 #endif 1660 ahc->flags |= AHC_NEWEEPROM_FMT; 1661 ahc->instruction_ram_size = 512; 1662 return (0); 1663 } 1664 1665 static int 1666 ahc_aic7896_setup(struct ahc_softc *ahc) 1667 { 1668 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1669 ahc->chip = AHC_AIC7896; 1670 ahc->features = AHC_AIC7896_FE; 1671 ahc->flags |= AHC_NEWEEPROM_FMT; 1672 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 1673 ahc->instruction_ram_size = 768; 1674 return (0); 1675 } 1676 1677 static int 1678 ahc_aic7899_setup(struct ahc_softc *ahc) 1679 { 1680 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1681 ahc->chip = AHC_AIC7899; 1682 ahc->features = AHC_AIC7899_FE; 1683 ahc->flags |= AHC_NEWEEPROM_FMT; 1684 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1685 ahc->instruction_ram_size = 1024; 1686 return (0); 1687 } 1688 1689 static int 1690 ahc_aha29160C_setup(struct ahc_softc *ahc) 1691 { 1692 int error; 1693 1694 error = ahc_aic7899_setup(ahc); 1695 if (error != 0) 1696 return (error); 1697 ahc->features |= AHC_REMOVABLE; 1698 return (0); 1699 } 1700 1701 static int 1702 ahc_raid_setup(struct ahc_softc *ahc) 1703 { 1704 printf("RAID functionality unsupported\n"); 1705 return (ENXIO); 1706 } 1707 1708 static int 1709 ahc_aha394XX_setup(struct ahc_softc *ahc) 1710 { 1711 1712 switch (ahc->bd->dev) { 1713 case AHC_394X_SLOT_CHANNEL_A: 1714 ahc->channel = 'A'; 1715 break; 1716 case AHC_394X_SLOT_CHANNEL_B: 1717 ahc->channel = 'B'; 1718 break; 1719 default: 1720 printf("adapter at unexpected slot %d\n" 1721 "unable to map to a channel\n", 1722 ahc->bd->dev); 1723 ahc->channel = 'A'; 1724 } 1725 return (0); 1726 } 1727 1728 static int 1729 ahc_aha398XX_setup(struct ahc_softc *ahc) 1730 { 1731 1732 switch (ahc->bd->dev) { 1733 case AHC_398X_SLOT_CHANNEL_A: 1734 ahc->channel = 'A'; 1735 break; 1736 case AHC_398X_SLOT_CHANNEL_B: 1737 ahc->channel = 'B'; 1738 break; 1739 case AHC_398X_SLOT_CHANNEL_C: 1740 ahc->channel = 'C'; 1741 break; 1742 default: 1743 printf("adapter at unexpected slot %d\n" 1744 "unable to map to a channel\n", 1745 ahc->bd->dev); 1746 ahc->channel = 'A'; 1747 break; 1748 } 1749 ahc->flags |= AHC_LARGE_SEEPROM; 1750 return (0); 1751 } 1752 1753 static int 1754 ahc_aha494XX_setup(struct ahc_softc *ahc) 1755 { 1756 1757 switch (ahc->bd->dev) { 1758 case AHC_494X_SLOT_CHANNEL_A: 1759 ahc->channel = 'A'; 1760 break; 1761 case AHC_494X_SLOT_CHANNEL_B: 1762 ahc->channel = 'B'; 1763 break; 1764 case AHC_494X_SLOT_CHANNEL_C: 1765 ahc->channel = 'C'; 1766 break; 1767 case AHC_494X_SLOT_CHANNEL_D: 1768 ahc->channel = 'D'; 1769 break; 1770 default: 1771 printf("adapter at unexpected slot %d\n" 1772 "unable to map to a channel\n", 1773 ahc->bd->dev); 1774 ahc->channel = 'A'; 1775 } 1776 ahc->flags |= AHC_LARGE_SEEPROM; 1777 return (0); 1778 } 1779