1 /* $OpenBSD: auich.c,v 1.120 2024/09/04 07:54:52 mglocker Exp $ */
2
3 /*
4 * Copyright (c) 2000,2001 Michael Shalayeff
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /*
30 * AC'97 audio found on Intel 810/815/820/440MX chipsets.
31 * http://developer.intel.com/design/chipsets/datashts/290655.htm
32 * http://developer.intel.com/design/chipsets/manuals/298028.htm
33 * http://www.intel.com/design/chipsets/datashts/290714.htm
34 * http://www.intel.com/design/chipsets/datashts/290744.htm
35 */
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/malloc.h>
40 #include <sys/device.h>
41
42 #include <dev/pci/pcidevs.h>
43 #include <dev/pci/pcivar.h>
44
45 #include <sys/audioio.h>
46 #include <dev/audio_if.h>
47
48 #include <machine/bus.h>
49
50 #include <dev/ic/ac97.h>
51
52 /* 12.1.10 NAMBAR - native audio mixer base address register */
53 #define AUICH_NAMBAR 0x10
54 /* 12.1.11 NABMBAR - native audio bus mastering base address register */
55 #define AUICH_NABMBAR 0x14
56 #define AUICH_CFG 0x41
57 #define AUICH_CFG_IOSE 0x01
58 /* ICH4/ICH5/ICH6/ICH7 native audio mixer BAR */
59 #define AUICH_MMBAR 0x18
60 /* ICH4/ICH5/ICH6/ICH7 native bus mastering BAR */
61 #define AUICH_MBBAR 0x1c
62 #define AUICH_S2CR 0x10000000 /* tertiary codec ready */
63
64 /* table 12-3. native audio bus master control registers */
65 #define AUICH_BDBAR 0x00 /* 8-byte aligned address */
66 #define AUICH_CIV 0x04 /* 5 bits current index value */
67 #define AUICH_LVI 0x05 /* 5 bits last valid index value */
68 #define AUICH_LVI_MASK 0x1f
69 #define AUICH_STS 0x06 /* 16 bits status */
70 #define AUICH_FIFOE 0x10 /* fifo error */
71 #define AUICH_BCIS 0x08 /* r- buf cmplt int sts; wr ack */
72 #define AUICH_LVBCI 0x04 /* r- last valid bci, wr ack */
73 #define AUICH_CELV 0x02 /* current equals last valid */
74 #define AUICH_DCH 0x01 /* dma halted */
75 #define AUICH_ISTS_BITS "\020\01dch\02celv\03lvbci\04bcis\05fifoe"
76 #define AUICH_PICB 0x08 /* 16 bits */
77 #define AUICH_PIV 0x0a /* 5 bits prefetched index value */
78 #define AUICH_CTRL 0x0b /* control */
79 #define AUICH_IOCE 0x10 /* int on completion enable */
80 #define AUICH_FEIE 0x08 /* fifo error int enable */
81 #define AUICH_LVBIE 0x04 /* last valid buf int enable */
82 #define AUICH_RR 0x02 /* 1 - reset regs */
83 #define AUICH_RPBM 0x01 /* 1 - run, 0 - pause */
84
85 #define AUICH_PCMI 0x00
86 #define AUICH_PCMO 0x10
87 #define AUICH_MICI 0x20
88
89 #define AUICH_GCTRL 0x2c
90 #define AUICH_SSM_78 0x40000000 /* S/PDIF slots 7 and 8 */
91 #define AUICH_SSM_69 0x80000000 /* S/PDIF slots 6 and 9 */
92 #define AUICH_SSM_1011 0xc0000000 /* S/PDIF slots 10 and 11 */
93 #define AUICH_POM16 0x000000 /* PCM out precision 16bit */
94 #define AUICH_POM20 0x400000 /* PCM out precision 20bit */
95 #define AUICH_PCM246_MASK 0x300000
96 #define AUICH_PCM2 0x000000 /* 2ch output */
97 #define AUICH_PCM4 0x100000 /* 4ch output */
98 #define AUICH_PCM6 0x200000 /* 6ch output */
99 #define AUICH_SIS_PCM246_MASK 0x0000c0 /* SiS 7012 */
100 #define AUICH_SIS_PCM2 0x000000 /* SiS 7012 2ch output */
101 #define AUICH_SIS_PCM4 0x000040 /* SiS 7012 4ch output */
102 #define AUICH_SIS_PCM6 0x000080 /* SiS 7012 6ch output */
103 #define AUICH_S2RIE 0x40 /* int when tertiary codec resume */
104 #define AUICH_SRIE 0x20 /* int when 2ndary codec resume */
105 #define AUICH_PRIE 0x10 /* int when primary codec resume */
106 #define AUICH_ACLSO 0x08 /* aclink shut off */
107 #define AUICH_WRESET 0x04 /* warm reset */
108 #define AUICH_CRESET 0x02 /* cold reset */
109 #define AUICH_GIE 0x01 /* gpi int enable */
110 #define AUICH_GSTS 0x30
111 #define AUICH_MD3 0x20000 /* pwr-dn semaphore for modem */
112 #define AUICH_AD3 0x10000 /* pwr-dn semaphore for audio */
113 #define AUICH_RCS 0x08000 /* read completion status */
114 #define AUICH_B3S12 0x04000 /* bit 3 of slot 12 */
115 #define AUICH_B2S12 0x02000 /* bit 2 of slot 12 */
116 #define AUICH_B1S12 0x01000 /* bit 1 of slot 12 */
117 #define AUICH_SRI 0x00800 /* secondary resume int */
118 #define AUICH_PRI 0x00400 /* primary resume int */
119 #define AUICH_SCR 0x00200 /* secondary codec ready */
120 #define AUICH_PCR 0x00100 /* primary codec ready */
121 #define AUICH_MINT 0x00080 /* mic in int */
122 #define AUICH_POINT 0x00040 /* pcm out int */
123 #define AUICH_PIINT 0x00020 /* pcm in int */
124 #define AUICH_MOINT 0x00004 /* modem out int */
125 #define AUICH_MIINT 0x00002 /* modem in int */
126 #define AUICH_GSCI 0x00001 /* gpi status change */
127 #define AUICH_GSTS_BITS "\020\01gsci\02miict\03moint\06piint\07point\010mint\011pcr\012scr\013pri\014sri\015b1s12\016b2s12\017b3s12\020rcs\021ad3\022md3"
128 #define AUICH_CAS 0x34 /* 1/8 bit */
129 #define AUICH_SEMATIMO 1000 /* us */
130 #define AUICH_RESETIMO 500000 /* us */
131
132 #define ICH_SIS_NV_CTL 0x4c /* some SiS/NVIDIA register. From Linux */
133 #define ICH_SIS_CTL_UNMUTE 0x01 /* un-mute the output */
134
135 /*
136 * There are 32 buffer descriptors. Each can reference up to 2^16 16-bit
137 * samples.
138 */
139 #define AUICH_DMALIST_MAX 32
140 #define AUICH_DMASEG_MAX (65536*2)
141 struct auich_dmalist {
142 u_int32_t base;
143 u_int32_t len;
144 #define AUICH_DMAF_IOC 0x80000000 /* 1-int on complete */
145 #define AUICH_DMAF_BUP 0x40000000 /* 0-retrans last, 1-transmit 0 */
146 };
147
148 #define AUICH_FIXED_RATE 48000
149
150 struct auich_dma {
151 bus_dmamap_t map;
152 caddr_t addr;
153 bus_dma_segment_t segs[1];
154 int nsegs;
155 size_t size;
156 };
157
158 struct auich_cdata {
159 struct auich_dmalist ic_dmalist_pcmo[AUICH_DMALIST_MAX];
160 struct auich_dmalist ic_dmalist_pcmi[AUICH_DMALIST_MAX];
161 struct auich_dmalist ic_dmalist_mici[AUICH_DMALIST_MAX];
162 };
163
164 #define AUICH_CDOFF(x) offsetof(struct auich_cdata, x)
165 #define AUICH_PCMO_OFF(x) AUICH_CDOFF(ic_dmalist_pcmo[(x)])
166 #define AUICH_PCMI_OFF(x) AUICH_CDOFF(ic_dmalist_pcmi[(x)])
167 #define AUICH_MICI_OFF(x) AUICH_CDOFF(ic_dmalist_mici[(x)])
168
169 struct auich_softc {
170 struct device sc_dev;
171 void *sc_ih;
172
173 pcireg_t pci_id;
174 bus_space_tag_t iot;
175 bus_space_tag_t iot_mix;
176 bus_space_handle_t mix_ioh;
177 bus_space_handle_t aud_ioh;
178 bus_dma_tag_t dmat;
179
180 struct ac97_codec_if *codec_if;
181 struct ac97_host_if host_if;
182 int sc_spdif;
183
184 /* dma scatter-gather buffer lists */
185
186 bus_dmamap_t sc_cddmamap;
187 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
188
189 struct auich_cdata *sc_cdata;
190
191 struct auich_ring {
192 int qptr;
193 struct auich_dmalist *dmalist;
194
195 uint32_t start, p, end;
196 int blksize;
197
198 void (*intr)(void *);
199 void *arg;
200 int running;
201 size_t size;
202 uint32_t ap;
203 } pcmo, pcmi, mici;
204
205 struct auich_dma *sc_pdma; /* play */
206 struct auich_dma *sc_rdma; /* record */
207 struct auich_dma *sc_cdma; /* calibrate */
208
209 #ifdef AUICH_DEBUG
210 int pcmi_fifoe;
211 int pcmo_fifoe;
212 #endif
213
214 int suspend;
215 u_int16_t ext_ctrl;
216 int sc_sample_size;
217 int sc_sts_reg;
218 int sc_dmamap_flags;
219 int sc_ignore_codecready;
220 int flags;
221 int sc_ac97rate;
222
223 /* multi-channel control bits */
224 int sc_pcm246_mask;
225 int sc_pcm2;
226 int sc_pcm4;
227 int sc_pcm6;
228
229 u_int last_rrate;
230 u_int last_prate;
231 u_int last_pchan;
232 };
233
234 #ifdef AUICH_DEBUG
235 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0)
236 int auich_debug = 0x0002;
237 #define AUICH_DEBUG_CODECIO 0x0001
238 #define AUICH_DEBUG_DMA 0x0002
239 #define AUICH_DEBUG_INTR 0x0004
240 #else
241 #define DPRINTF(x,y) /* nothing */
242 #endif
243
244 struct cfdriver auich_cd = {
245 NULL, "auich", DV_DULL
246 };
247
248 int auich_match(struct device *, void *, void *);
249 void auich_attach(struct device *, struct device *, void *);
250 int auich_intr(void *);
251
252 int auich_activate(struct device *, int);
253
254 const struct cfattach auich_ca = {
255 sizeof(struct auich_softc), auich_match, auich_attach,
256 NULL, auich_activate
257 };
258
259 static const struct auich_devtype {
260 int vendor;
261 int product;
262 int options;
263 char name[8];
264 } auich_devices[] = {
265 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_ACA, 0, "ESB" },
266 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6321ESB_ACA, 0, "ESB2" },
267 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 0, "ICH" },
268 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 0, "ICH0" },
269 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 0, "ICH2" },
270 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_ACA, 0, "ICH3" },
271 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ACA, 0, "ICH4" },
272 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_ACA, 0, "ICH5" },
273 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_ACA, 0, "ICH6" },
274 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_ACA, 0, "ICH7" },
275 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 0, "440MX" },
276 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_ACA, 0, "SiS7012" },
277 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_ACA, 0, "nForce" },
278 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_ACA, 0, "nForce2" },
279 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_ACA,
280 0, "nForce2" },
281 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_ACA, 0, "nForce3" },
282 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_ACA,
283 0, "nForce3" },
284 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_AC, 0, "nForce4" },
285 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_AC97, 0, "MCP04" },
286 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_ACA, 0, "MCP51" },
287 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_ACA, 0, "AMD768" },
288 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_8111_ACA, 0, "AMD8111" },
289 };
290
291 int auich_open(void *, int);
292 void auich_close(void *);
293 int auich_set_params(void *, int, int, struct audio_params *,
294 struct audio_params *);
295 int auich_round_blocksize(void *, int);
296 void auich_halt_pipe(struct auich_softc *, int, struct auich_ring *);
297 int auich_halt_output(void *);
298 int auich_halt_input(void *);
299 int auich_set_port(void *, mixer_ctrl_t *);
300 int auich_get_port(void *, mixer_ctrl_t *);
301 int auich_query_devinfo(void *, mixer_devinfo_t *);
302 void *auich_allocm(void *, int, size_t, int, int);
303 void auich_freem(void *, void *, int);
304 size_t auich_round_buffersize(void *, int, size_t);
305 void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *);
306 void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *);
307 int auich_trigger_output(void *, void *, void *, int, void (*)(void *),
308 void *, struct audio_params *);
309 int auich_trigger_input(void *, void *, void *, int, void (*)(void *),
310 void *, struct audio_params *);
311 int auich_alloc_cdata(struct auich_softc *);
312 int auich_allocmem(struct auich_softc *, size_t, size_t, struct auich_dma *);
313 void auich_freemem(struct auich_softc *, struct auich_dma *);
314
315 void auich_resume(struct auich_softc *);
316
317 const struct audio_hw_if auich_hw_if = {
318 .open = auich_open,
319 .close = auich_close,
320 .set_params = auich_set_params,
321 .round_blocksize = auich_round_blocksize,
322 .halt_output = auich_halt_output,
323 .halt_input = auich_halt_input,
324 .set_port = auich_set_port,
325 .get_port = auich_get_port,
326 .query_devinfo = auich_query_devinfo,
327 .allocm = auich_allocm,
328 .freem = auich_freem,
329 .round_buffersize = auich_round_buffersize,
330 .trigger_output = auich_trigger_output,
331 .trigger_input = auich_trigger_input,
332 };
333
334 int auich_attach_codec(void *, struct ac97_codec_if *);
335 int auich_read_codec(void *, u_int8_t, u_int16_t *);
336 int auich_write_codec(void *, u_int8_t, u_int16_t);
337 void auich_reset_codec(void *);
338 enum ac97_host_flags auich_flags_codec(void *);
339 unsigned int auich_calibrate(struct auich_softc *);
340 void auich_spdif_event(void *, int);
341
342 int
auich_match(struct device * parent,void * match,void * aux)343 auich_match(struct device *parent, void *match, void *aux)
344 {
345 struct pci_attach_args *pa = aux;
346 int i;
347
348 for (i = nitems(auich_devices); i--;)
349 if (PCI_VENDOR(pa->pa_id) == auich_devices[i].vendor &&
350 PCI_PRODUCT(pa->pa_id) == auich_devices[i].product)
351 return 1;
352
353 return 0;
354 }
355
356 void
auich_attach(struct device * parent,struct device * self,void * aux)357 auich_attach(struct device *parent, struct device *self, void *aux)
358 {
359 struct auich_softc *sc = (struct auich_softc *)self;
360 struct pci_attach_args *pa = aux;
361 pci_intr_handle_t ih;
362 bus_size_t mix_size, aud_size;
363 pcireg_t csr;
364 const char *intrstr;
365 u_int32_t status;
366 int i;
367
368 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL &&
369 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801DB_ACA ||
370 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801EB_ACA ||
371 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801FB_ACA ||
372 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801GB_ACA)) {
373 /*
374 * Use native mode for ICH4/ICH5/ICH6/ICH7
375 */
376 if (pci_mapreg_map(pa, AUICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0,
377 &sc->iot_mix, &sc->mix_ioh, NULL, &mix_size, 0)) {
378 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, AUICH_CFG);
379 pci_conf_write(pa->pa_pc, pa->pa_tag, AUICH_CFG,
380 csr | AUICH_CFG_IOSE);
381 if (pci_mapreg_map(pa, AUICH_NAMBAR, PCI_MAPREG_TYPE_IO,
382 0, &sc->iot_mix, &sc->mix_ioh, NULL, &mix_size, 0)) {
383 printf(": can't map codec mem/io space\n");
384 return;
385 }
386 }
387
388 if (pci_mapreg_map(pa, AUICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0,
389 &sc->iot, &sc->aud_ioh, NULL, &aud_size, 0)) {
390 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, AUICH_CFG);
391 pci_conf_write(pa->pa_pc, pa->pa_tag, AUICH_CFG,
392 csr | AUICH_CFG_IOSE);
393 if (pci_mapreg_map(pa, AUICH_NABMBAR,
394 PCI_MAPREG_TYPE_IO, 0, &sc->iot,
395 &sc->aud_ioh, NULL, &aud_size, 0)) {
396 printf(": can't map device mem/io space\n");
397 goto fail_unmap_mix;
398 }
399 }
400 } else {
401 if (pci_mapreg_map(pa, AUICH_NAMBAR, PCI_MAPREG_TYPE_IO,
402 0, &sc->iot_mix, &sc->mix_ioh, NULL, &mix_size, 0)) {
403 printf(": can't map codec i/o space\n");
404 return;
405 }
406
407 if (pci_mapreg_map(pa, AUICH_NABMBAR, PCI_MAPREG_TYPE_IO,
408 0, &sc->iot, &sc->aud_ioh, NULL, &aud_size, 0)) {
409 printf(": can't map device i/o space\n");
410 goto fail_unmap_mix;
411 }
412 }
413 sc->dmat = pa->pa_dmat;
414 sc->pci_id = pa->pa_id;
415
416 if (pci_intr_map(pa, &ih)) {
417 printf(": can't map interrupt\n");
418 goto fail_unmap;
419 }
420 intrstr = pci_intr_string(pa->pa_pc, ih);
421 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO | IPL_MPSAFE,
422 auich_intr, sc, sc->sc_dev.dv_xname);
423 if (!sc->sc_ih) {
424 printf(": can't establish interrupt");
425 if (intrstr)
426 printf(" at %s", intrstr);
427 printf("\n");
428 goto fail_unmap;
429 }
430
431 for (i = nitems(auich_devices); i--;)
432 if (PCI_PRODUCT(pa->pa_id) == auich_devices[i].product)
433 break;
434
435 printf(": %s, %s\n", intrstr, auich_devices[i].name);
436
437 /* SiS 7012 needs special handling */
438 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS &&
439 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_7012_ACA) {
440 sc->sc_sts_reg = AUICH_PICB;
441 sc->sc_sample_size = 1;
442 sc->sc_pcm246_mask = AUICH_SIS_PCM246_MASK;
443 sc->sc_pcm2 = AUICH_SIS_PCM2;
444 sc->sc_pcm4 = AUICH_SIS_PCM4;
445 sc->sc_pcm6 = AUICH_SIS_PCM6;
446 /* un-mute output */
447 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL,
448 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) |
449 ICH_SIS_CTL_UNMUTE);
450 } else {
451 sc->sc_sts_reg = AUICH_STS;
452 sc->sc_sample_size = 2;
453 sc->sc_pcm246_mask = AUICH_PCM246_MASK;
454 sc->sc_pcm2 = AUICH_PCM2;
455 sc->sc_pcm4 = AUICH_PCM4;
456 sc->sc_pcm6 = AUICH_PCM6;
457 }
458
459 /* Workaround for a 440MX B-stepping erratum */
460 sc->sc_dmamap_flags = BUS_DMA_COHERENT;
461 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL &&
462 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82440MX_ACA) {
463 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE;
464 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname);
465 }
466
467 /* Set up DMA lists. */
468 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0;
469 if (auich_alloc_cdata(sc) != 0)
470 goto fail_disestablish_intr;
471
472 DPRINTF(AUICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n",
473 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist));
474
475 /* Reset codec and AC'97 */
476 auich_reset_codec(sc);
477 status = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GSTS);
478 if (!(status & AUICH_PCR)) { /* reset failure */
479 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL &&
480 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801DB_ACA ||
481 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801EB_ACA ||
482 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801FB_ACA ||
483 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801GB_ACA)) {
484 /* MSI 845G Max never return AUICH_PCR */
485 sc->sc_ignore_codecready = 1;
486 } else {
487 printf("%s: reset failed!\n", sc->sc_dev.dv_xname);
488 return;
489 }
490 }
491
492 sc->host_if.arg = sc;
493 sc->host_if.attach = auich_attach_codec;
494 sc->host_if.read = auich_read_codec;
495 sc->host_if.write = auich_write_codec;
496 sc->host_if.reset = auich_reset_codec;
497 sc->host_if.flags = auich_flags_codec;
498 sc->host_if.spdif_event = auich_spdif_event;
499 if (sc->sc_dev.dv_cfdata->cf_flags & 0x0001)
500 sc->flags = AC97_HOST_SWAPPED_CHANNELS;
501
502 if (ac97_attach(&sc->host_if) != 0)
503 goto fail_disestablish_intr;
504 sc->codec_if->vtbl->unlock(sc->codec_if);
505
506 audio_attach_mi(&auich_hw_if, sc, NULL, &sc->sc_dev);
507
508 /* Watch for power changes */
509 sc->suspend = DVACT_RESUME;
510
511 sc->sc_ac97rate = -1;
512 return;
513
514 fail_disestablish_intr:
515 pci_intr_disestablish(pa->pa_pc, sc->sc_ih);
516 fail_unmap:
517 bus_space_unmap(sc->iot, sc->aud_ioh, aud_size);
518 fail_unmap_mix:
519 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size);
520 }
521
522 int
auich_activate(struct device * self,int act)523 auich_activate(struct device *self, int act)
524 {
525 struct auich_softc *sc = (struct auich_softc *)self;
526
527 switch (act) {
528 case DVACT_RESUME:
529 auich_resume(sc);
530 break;
531 default:
532 break;
533 }
534 return (config_activate_children(self, act));
535 }
536
537 int
auich_read_codec(void * v,u_int8_t reg,u_int16_t * val)538 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val)
539 {
540 struct auich_softc *sc = v;
541 int i;
542
543 /* wait for an access semaphore */
544 for (i = AUICH_SEMATIMO; i-- &&
545 bus_space_read_1(sc->iot, sc->aud_ioh, AUICH_CAS) & 1; DELAY(1));
546
547 if (!sc->sc_ignore_codecready && i < 0) {
548 DPRINTF(AUICH_DEBUG_CODECIO,
549 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname));
550 return (-1);
551 }
552
553 *val = bus_space_read_2(sc->iot_mix, sc->mix_ioh, reg);
554 DPRINTF(AUICH_DEBUG_CODECIO, ("%s: read_codec(%x, %x)\n",
555 sc->sc_dev.dv_xname, reg, *val));
556 return (0);
557 }
558
559 int
auich_write_codec(void * v,u_int8_t reg,u_int16_t val)560 auich_write_codec(void *v, u_int8_t reg, u_int16_t val)
561 {
562 struct auich_softc *sc = v;
563 int i;
564
565 /* wait for an access semaphore */
566 for (i = AUICH_SEMATIMO; i-- &&
567 bus_space_read_1(sc->iot, sc->aud_ioh, AUICH_CAS) & 1; DELAY(1));
568
569 if (sc->sc_ignore_codecready || i >= 0) {
570 DPRINTF(AUICH_DEBUG_CODECIO, ("%s: write_codec(%x, %x)\n",
571 sc->sc_dev.dv_xname, reg, val));
572 bus_space_write_2(sc->iot_mix, sc->mix_ioh, reg, val);
573 return (0);
574 } else {
575 DPRINTF(AUICH_DEBUG_CODECIO,
576 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname));
577 return (-1);
578 }
579 }
580
581 int
auich_attach_codec(void * v,struct ac97_codec_if * cif)582 auich_attach_codec(void *v, struct ac97_codec_if *cif)
583 {
584 struct auich_softc *sc = v;
585
586 sc->codec_if = cif;
587 return 0;
588 }
589
590 void
auich_reset_codec(void * v)591 auich_reset_codec(void *v)
592 {
593 struct auich_softc *sc = v;
594 u_int32_t control;
595 int i;
596
597 control = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GCTRL);
598 control &= ~(AUICH_ACLSO | sc->sc_pcm246_mask);
599 control |= (control & AUICH_CRESET) ? AUICH_WRESET : AUICH_CRESET;
600 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GCTRL, control);
601
602 for (i = AUICH_RESETIMO; i-- &&
603 !(bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GSTS) & AUICH_PCR);
604 DELAY(1));
605
606 if (i < 0)
607 DPRINTF(AUICH_DEBUG_CODECIO,
608 ("%s: reset_codec timeout\n", sc->sc_dev.dv_xname));
609 }
610
611 enum ac97_host_flags
auich_flags_codec(void * v)612 auich_flags_codec(void *v)
613 {
614 struct auich_softc *sc = v;
615
616 return (sc->flags);
617 }
618
619 void
auich_spdif_event(void * v,int flag)620 auich_spdif_event(void *v, int flag)
621 {
622 struct auich_softc *sc = v;
623 sc->sc_spdif = flag;
624 }
625
626 int
auich_open(void * v,int flags)627 auich_open(void *v, int flags)
628 {
629 struct auich_softc *sc = v;
630
631 if (sc->sc_ac97rate == -1)
632 sc->sc_ac97rate = auich_calibrate(sc);
633
634 sc->codec_if->vtbl->lock(sc->codec_if);
635
636 return 0;
637 }
638
639 void
auich_close(void * v)640 auich_close(void *v)
641 {
642 struct auich_softc *sc = v;
643
644 sc->codec_if->vtbl->unlock(sc->codec_if);
645 }
646
647 int
auich_set_params(void * v,int setmode,int usemode,struct audio_params * play,struct audio_params * rec)648 auich_set_params(void *v, int setmode, int usemode,
649 struct audio_params *play, struct audio_params *rec)
650 {
651 struct auich_softc *sc = v;
652 struct ac97_codec_if *codec = sc->codec_if;
653 int error;
654 u_int orate;
655 u_int adj_rate;
656 u_int32_t control;
657 u_int16_t ext_id;
658
659 if (setmode & AUMODE_PLAY) {
660 /* only 16-bit 48kHz slinear_le if s/pdif enabled */
661 if (sc->sc_spdif) {
662 play->sample_rate = 48000;
663 play->precision = 16;
664 play->encoding = AUDIO_ENCODING_SLINEAR_LE;
665 }
666 }
667 if (setmode & AUMODE_PLAY) {
668 play->precision = 16;
669 switch(play->encoding) {
670 case AUDIO_ENCODING_SLINEAR_LE:
671 if (play->channels > 6)
672 play->channels = 6;
673 if (play->channels > 1)
674 play->channels &= ~1;
675 switch (play->channels) {
676 case 1:
677 play->channels = 2;
678 break;
679 case 2:
680 break;
681 case 4:
682 ext_id = codec->vtbl->get_caps(codec);
683 if (!(ext_id & AC97_EXT_AUDIO_SDAC))
684 play->channels = 2;
685 break;
686 case 6:
687 ext_id = codec->vtbl->get_caps(codec);
688 if ((ext_id & AC97_BITS_6CH) !=
689 AC97_BITS_6CH)
690 play->channels = 2;
691 break;
692 default:
693 return (EINVAL);
694 }
695 break;
696 default:
697 return (EINVAL);
698 }
699 play->bps = AUDIO_BPS(play->precision);
700 play->msb = 1;
701
702 orate = adj_rate = play->sample_rate;
703 if (sc->sc_ac97rate != 0)
704 adj_rate = orate * AUICH_FIXED_RATE / sc->sc_ac97rate;
705
706 play->sample_rate = adj_rate;
707 sc->last_prate = play->sample_rate;
708
709 error = ac97_set_rate(sc->codec_if,
710 AC97_REG_PCM_LFE_DAC_RATE, &play->sample_rate);
711 if (error)
712 return (error);
713
714 play->sample_rate = adj_rate;
715 error = ac97_set_rate(sc->codec_if,
716 AC97_REG_PCM_SURR_DAC_RATE, &play->sample_rate);
717 if (error)
718 return (error);
719
720 play->sample_rate = adj_rate;
721 error = ac97_set_rate(sc->codec_if,
722 AC97_REG_PCM_FRONT_DAC_RATE, &play->sample_rate);
723 if (error)
724 return (error);
725
726 if (play->sample_rate == adj_rate)
727 play->sample_rate = orate;
728
729 control = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GCTRL);
730 control &= ~(sc->sc_pcm246_mask);
731 if (play->channels == 4)
732 control |= sc->sc_pcm4;
733 else if (play->channels == 6)
734 control |= sc->sc_pcm6;
735 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GCTRL, control);
736
737 sc->last_pchan = play->channels;
738 }
739
740 if (setmode & AUMODE_RECORD) {
741 rec->channels = 2;
742 rec->precision = 16;
743 rec->encoding = AUDIO_ENCODING_SLINEAR_LE;
744 rec->bps = AUDIO_BPS(rec->precision);
745 rec->msb = 1;
746
747 orate = rec->sample_rate;
748 if (sc->sc_ac97rate != 0)
749 rec->sample_rate = orate * AUICH_FIXED_RATE /
750 sc->sc_ac97rate;
751 sc->last_rrate = rec->sample_rate;
752 error = ac97_set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE,
753 &rec->sample_rate);
754 if (error)
755 return (error);
756 rec->sample_rate = orate;
757 }
758
759 return (0);
760 }
761
762 int
auich_round_blocksize(void * v,int blk)763 auich_round_blocksize(void *v, int blk)
764 {
765 return (blk + 0x3f) & ~0x3f;
766 }
767
768
769 void
auich_halt_pipe(struct auich_softc * sc,int pipe,struct auich_ring * ring)770 auich_halt_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring)
771 {
772 int i;
773 uint32_t sts;
774
775 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL, 0);
776
777 /* wait for DMA halted and clear interrupt / event bits if needed */
778 for (i = 0; i < 1000; i++) {
779 sts = bus_space_read_2(sc->iot, sc->aud_ioh,
780 pipe + sc->sc_sts_reg);
781 if (sts & (AUICH_CELV | AUICH_LVBCI | AUICH_BCIS | AUICH_FIFOE))
782 bus_space_write_2(sc->iot, sc->aud_ioh,
783 pipe + sc->sc_sts_reg,
784 AUICH_CELV | AUICH_LVBCI |
785 AUICH_BCIS | AUICH_FIFOE);
786 if (sts & AUICH_DCH)
787 break;
788 DELAY(100);
789 }
790 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL, AUICH_RR);
791
792 if (i > 0)
793 DPRINTF(AUICH_DEBUG_DMA,
794 ("auich_halt_pipe: halt took %d cycles\n", i));
795
796 ring->running = 0;
797 }
798
799
800 int
auich_halt_output(void * v)801 auich_halt_output(void *v)
802 {
803 struct auich_softc *sc = v;
804
805 DPRINTF(AUICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname));
806
807 mtx_enter(&audio_lock);
808 auich_halt_pipe(sc, AUICH_PCMO, &sc->pcmo);
809
810 sc->pcmo.intr = NULL;
811 mtx_leave(&audio_lock);
812 return 0;
813 }
814
815 int
auich_halt_input(void * v)816 auich_halt_input(void *v)
817 {
818 struct auich_softc *sc = v;
819
820 DPRINTF(AUICH_DEBUG_DMA,
821 ("%s: halt_input\n", sc->sc_dev.dv_xname));
822
823 /* XXX halt both unless known otherwise */
824 mtx_enter(&audio_lock);
825 auich_halt_pipe(sc, AUICH_PCMI, &sc->pcmi);
826 auich_halt_pipe(sc, AUICH_MICI, &sc->mici);
827
828 sc->pcmi.intr = NULL;
829 mtx_leave(&audio_lock);
830 return 0;
831 }
832
833 int
auich_set_port(void * v,mixer_ctrl_t * cp)834 auich_set_port(void *v, mixer_ctrl_t *cp)
835 {
836 struct auich_softc *sc = v;
837 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp);
838 }
839
840 int
auich_get_port(void * v,mixer_ctrl_t * cp)841 auich_get_port(void *v, mixer_ctrl_t *cp)
842 {
843 struct auich_softc *sc = v;
844 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp);
845 }
846
847 int
auich_query_devinfo(void * v,mixer_devinfo_t * dp)848 auich_query_devinfo(void *v, mixer_devinfo_t *dp)
849 {
850 struct auich_softc *sc = v;
851 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp);
852 }
853
854 void *
auich_allocm(void * v,int direction,size_t size,int pool,int flags)855 auich_allocm(void *v, int direction, size_t size, int pool, int flags)
856 {
857 struct auich_softc *sc = v;
858 struct auich_dma *p;
859 int error;
860
861 /* can only use 1 segment */
862 if (size > AUICH_DMASEG_MAX) {
863 DPRINTF(AUICH_DEBUG_DMA,
864 ("%s: requested buffer size too large: %zd", \
865 sc->sc_dev.dv_xname, size));
866 return NULL;
867 }
868
869 p = malloc(sizeof(*p), pool, flags | M_ZERO);
870 if (!p)
871 return NULL;
872
873 error = auich_allocmem(sc, size, PAGE_SIZE, p);
874 if (error) {
875 free(p, pool, sizeof(*p));
876 return NULL;
877 }
878
879 if (direction == AUMODE_PLAY)
880 sc->sc_pdma = p;
881 else if (direction == AUMODE_RECORD)
882 sc->sc_rdma = p;
883 else
884 sc->sc_cdma = p;
885
886 return p->addr;
887 }
888
889 void
auich_freem(void * v,void * ptr,int pool)890 auich_freem(void *v, void *ptr, int pool)
891 {
892 struct auich_softc *sc;
893 struct auich_dma *p;
894
895 sc = v;
896 if (sc->sc_pdma != NULL && sc->sc_pdma->addr == ptr)
897 p = sc->sc_pdma;
898 else if (sc->sc_rdma != NULL && sc->sc_rdma->addr == ptr)
899 p = sc->sc_rdma;
900 else if (sc->sc_cdma != NULL && sc->sc_cdma->addr == ptr)
901 p = sc->sc_cdma;
902 else
903 return;
904
905 auich_freemem(sc, p);
906 free(p, pool, sizeof(*p));
907 }
908
909 size_t
auich_round_buffersize(void * v,int direction,size_t size)910 auich_round_buffersize(void *v, int direction, size_t size)
911 {
912 if (size > AUICH_DMALIST_MAX * AUICH_DMASEG_MAX)
913 size = AUICH_DMALIST_MAX * AUICH_DMASEG_MAX;
914
915 return size;
916 }
917
918 int
auich_intr(void * v)919 auich_intr(void *v)
920 {
921 struct auich_softc *sc = v;
922 int ret = 0, sts, gsts;
923
924 mtx_enter(&audio_lock);
925 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GSTS);
926 DPRINTF(AUICH_DEBUG_INTR, ("auich_intr: gsts=%b\n", gsts, AUICH_GSTS_BITS));
927
928 if (gsts & AUICH_POINT) {
929 sts = bus_space_read_2(sc->iot, sc->aud_ioh,
930 AUICH_PCMO + sc->sc_sts_reg);
931 DPRINTF(AUICH_DEBUG_INTR,
932 ("auich_intr: osts=%b\n", sts, AUICH_ISTS_BITS));
933
934 #ifdef AUICH_DEBUG
935 if (sts & AUICH_FIFOE) {
936 printf("%s: in fifo underrun # %u civ=%u ctrl=0x%x sts=%b\n",
937 sc->sc_dev.dv_xname, sc->pcmo_fifoe++,
938 bus_space_read_1(sc->iot, sc->aud_ioh,
939 AUICH_PCMO + AUICH_CIV),
940 bus_space_read_1(sc->iot, sc->aud_ioh,
941 AUICH_PCMO + AUICH_CTRL),
942 bus_space_read_2(sc->iot, sc->aud_ioh,
943 AUICH_PCMO + sc->sc_sts_reg),
944 AUICH_ISTS_BITS);
945 }
946 #endif
947
948 if (sts & AUICH_BCIS)
949 auich_intr_pipe(sc, AUICH_PCMO, &sc->pcmo);
950
951 /* int ack */
952 bus_space_write_2(sc->iot, sc->aud_ioh,
953 AUICH_PCMO + sc->sc_sts_reg, sts &
954 (AUICH_BCIS | AUICH_FIFOE));
955 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GSTS, AUICH_POINT);
956 ret++;
957 }
958
959 if (gsts & AUICH_PIINT) {
960 sts = bus_space_read_2(sc->iot, sc->aud_ioh,
961 AUICH_PCMI + sc->sc_sts_reg);
962 DPRINTF(AUICH_DEBUG_INTR,
963 ("auich_intr: ists=%b\n", sts, AUICH_ISTS_BITS));
964
965 #ifdef AUICH_DEBUG
966 if (sts & AUICH_FIFOE) {
967 printf("%s: in fifo overrun # %u civ=%u ctrl=0x%x sts=%b\n",
968 sc->sc_dev.dv_xname, sc->pcmi_fifoe++,
969 bus_space_read_1(sc->iot, sc->aud_ioh,
970 AUICH_PCMI + AUICH_CIV),
971 bus_space_read_1(sc->iot, sc->aud_ioh,
972 AUICH_PCMI + AUICH_CTRL),
973 bus_space_read_2(sc->iot, sc->aud_ioh,
974 AUICH_PCMI + sc->sc_sts_reg),
975 AUICH_ISTS_BITS);
976 }
977 #endif
978
979 if (sts & AUICH_BCIS)
980 auich_intr_pipe(sc, AUICH_PCMI, &sc->pcmi);
981
982 /* int ack */
983 bus_space_write_2(sc->iot, sc->aud_ioh,
984 AUICH_PCMI + sc->sc_sts_reg, sts &
985 (AUICH_BCIS | AUICH_FIFOE));
986 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GSTS, AUICH_PIINT);
987 ret++;
988 }
989
990 if (gsts & AUICH_MINT) {
991 sts = bus_space_read_2(sc->iot, sc->aud_ioh,
992 AUICH_MICI + sc->sc_sts_reg);
993 DPRINTF(AUICH_DEBUG_INTR,
994 ("auich_intr: ists=%b\n", sts, AUICH_ISTS_BITS));
995 #ifdef AUICH_DEBUG
996 if (sts & AUICH_FIFOE) {
997 printf("%s: in fifo overrun civ=%u ctrl=0x%x sts=%b\n",
998 sc->sc_dev.dv_xname,
999 bus_space_read_1(sc->iot, sc->aud_ioh,
1000 AUICH_MICI + AUICH_CIV),
1001 bus_space_read_1(sc->iot, sc->aud_ioh,
1002 AUICH_MICI + AUICH_CTRL),
1003 bus_space_read_2(sc->iot, sc->aud_ioh,
1004 AUICH_MICI + sc->sc_sts_reg),
1005 AUICH_ISTS_BITS);
1006 }
1007 #endif
1008 if (sts & AUICH_BCIS)
1009 auich_intr_pipe(sc, AUICH_MICI, &sc->mici);
1010
1011 /* int ack */
1012 bus_space_write_2(sc->iot, sc->aud_ioh,
1013 AUICH_MICI + sc->sc_sts_reg,
1014 sts + (AUICH_BCIS | AUICH_FIFOE));
1015
1016 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GSTS, AUICH_MINT);
1017 ret++;
1018 }
1019 mtx_leave(&audio_lock);
1020 return ret;
1021 }
1022
1023
1024 void
auich_trigger_pipe(struct auich_softc * sc,int pipe,struct auich_ring * ring)1025 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring)
1026 {
1027 int blksize, qptr, oqptr;
1028 struct auich_dmalist *q;
1029
1030 blksize = ring->blksize;
1031 qptr = oqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + AUICH_CIV);
1032
1033 /* XXX remove this when no one reports problems */
1034 if(oqptr >= AUICH_DMALIST_MAX) {
1035 printf("%s: Unexpected CIV: %d\n", sc->sc_dev.dv_xname, oqptr);
1036 qptr = oqptr = 0;
1037 }
1038
1039 do {
1040 q = &ring->dmalist[qptr];
1041 q->base = ring->p;
1042 q->len = (blksize / sc->sc_sample_size) | AUICH_DMAF_IOC;
1043
1044 DPRINTF(AUICH_DEBUG_INTR,
1045 ("auich_trigger_pipe: %p, %p = %x @ 0x%x qptr=%d\n",
1046 &ring->dmalist[qptr], q, q->len, q->base, qptr));
1047
1048 ring->p += blksize;
1049 if (ring->p >= ring->end)
1050 ring->p = ring->start;
1051
1052 qptr = (qptr + 1) & AUICH_LVI_MASK;
1053 } while (qptr != oqptr);
1054
1055 ring->qptr = qptr;
1056
1057 DPRINTF(AUICH_DEBUG_DMA,
1058 ("auich_trigger_pipe: qptr=%d\n", qptr));
1059
1060 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_LVI,
1061 (qptr - 1) & AUICH_LVI_MASK);
1062 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL,
1063 AUICH_IOCE | AUICH_FEIE | AUICH_RPBM);
1064
1065 ring->running = 1;
1066 }
1067
1068 void
auich_intr_pipe(struct auich_softc * sc,int pipe,struct auich_ring * ring)1069 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring)
1070 {
1071 int blksize, qptr, nqptr;
1072 struct auich_dmalist *q;
1073
1074 blksize = ring->blksize;
1075 qptr = ring->qptr;
1076 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + AUICH_CIV);
1077
1078 while (qptr != nqptr) {
1079 q = &ring->dmalist[qptr];
1080 q->base = ring->p;
1081 q->len = (blksize / sc->sc_sample_size) | AUICH_DMAF_IOC;
1082
1083 DPRINTF(AUICH_DEBUG_INTR,
1084 ("auich_intr: %p, %p = %x @ 0x%x qptr=%d\n",
1085 &ring->dmalist[qptr], q, q->len, q->base, qptr));
1086
1087 ring->p += blksize;
1088 if (ring->p >= ring->end)
1089 ring->p = ring->start;
1090
1091 qptr = (qptr + 1) & AUICH_LVI_MASK;
1092 if (ring->intr)
1093 ring->intr(ring->arg);
1094 else
1095 printf("auich_intr: got progress with intr==NULL\n");
1096
1097 ring->ap += blksize;
1098 if (ring->ap >= ring->size)
1099 ring->ap = 0;
1100 }
1101 ring->qptr = qptr;
1102
1103 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_LVI,
1104 (qptr - 1) & AUICH_LVI_MASK);
1105 }
1106
1107
1108 int
auich_trigger_output(void * v,void * start,void * end,int blksize,void (* intr)(void *),void * arg,struct audio_params * param)1109 auich_trigger_output(void *v, void *start, void *end, int blksize,
1110 void (*intr)(void *), void *arg, struct audio_params *param)
1111 {
1112 struct auich_softc *sc = v;
1113 struct auich_dma *p;
1114 size_t size;
1115 #ifdef AUICH_DEBUG
1116 uint16_t sts;
1117 sts = bus_space_read_2(sc->iot, sc->aud_ioh,
1118 AUICH_PCMO + sc->sc_sts_reg);
1119 DPRINTF(AUICH_DEBUG_DMA,
1120 ("auich_trigger_output(%p, %p, %d, %p, %p, %p) sts=%b\n",
1121 start, end, blksize, intr, arg, param, sts, AUICH_ISTS_BITS));
1122 #endif
1123
1124 if (sc->sc_pdma->addr == start)
1125 p = sc->sc_pdma;
1126 else
1127 return -1;
1128
1129 size = (size_t)((caddr_t)end - (caddr_t)start);
1130 sc->pcmo.size = size;
1131 sc->pcmo.intr = intr;
1132 sc->pcmo.arg = arg;
1133
1134 /*
1135 * The logic behind this is:
1136 * setup one buffer to play, then LVI dump out the rest
1137 * to the scatter-gather chain.
1138 */
1139 sc->pcmo.start = p->segs->ds_addr;
1140 sc->pcmo.p = sc->pcmo.start;
1141 sc->pcmo.end = sc->pcmo.start + size;
1142 sc->pcmo.blksize = blksize;
1143
1144 mtx_enter(&audio_lock);
1145 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_PCMO + AUICH_BDBAR,
1146 sc->sc_cddma + AUICH_PCMO_OFF(0));
1147 auich_trigger_pipe(sc, AUICH_PCMO, &sc->pcmo);
1148 mtx_leave(&audio_lock);
1149 return 0;
1150 }
1151
1152 int
auich_trigger_input(void * v,void * start,void * end,int blksize,void (* intr)(void *),void * arg,struct audio_params * param)1153 auich_trigger_input(void *v, void *start, void *end, int blksize,
1154 void (*intr)(void *), void *arg, struct audio_params *param)
1155 {
1156 struct auich_softc *sc = v;
1157 struct auich_dma *p;
1158 size_t size;
1159
1160 DPRINTF(AUICH_DEBUG_DMA,
1161 ("auich_trigger_input(%p, %p, %d, %p, %p, %p) sts=%b\n",
1162 start, end, blksize, intr, arg, param,
1163 bus_space_read_2(sc->iot, sc->aud_ioh,
1164 AUICH_PCMI + sc->sc_sts_reg),
1165 AUICH_ISTS_BITS));
1166
1167 if (sc->sc_rdma->addr == start)
1168 p = sc->sc_rdma;
1169 else
1170 return -1;
1171
1172 size = (size_t)((caddr_t)end - (caddr_t)start);
1173 sc->pcmi.size = size;
1174 sc->pcmi.intr = intr;
1175 sc->pcmi.arg = arg;
1176
1177 /*
1178 * The logic behind this is:
1179 * setup one buffer to play, then LVI dump out the rest
1180 * to the scatter-gather chain.
1181 */
1182 sc->pcmi.start = p->segs->ds_addr;
1183 sc->pcmi.p = sc->pcmi.start;
1184 sc->pcmi.end = sc->pcmi.start + size;
1185 sc->pcmi.blksize = blksize;
1186 mtx_enter(&audio_lock);
1187 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_BDBAR,
1188 sc->sc_cddma + AUICH_PCMI_OFF(0));
1189 auich_trigger_pipe(sc, AUICH_PCMI, &sc->pcmi);
1190 mtx_leave(&audio_lock);
1191 return 0;
1192 }
1193
1194
1195 int
auich_allocmem(struct auich_softc * sc,size_t size,size_t align,struct auich_dma * p)1196 auich_allocmem(struct auich_softc *sc, size_t size, size_t align,
1197 struct auich_dma *p)
1198 {
1199 int error;
1200
1201 p->size = size;
1202 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, p->segs, 1,
1203 &p->nsegs, BUS_DMA_NOWAIT);
1204 if (error) {
1205 DPRINTF(AUICH_DEBUG_DMA,
1206 ("%s: bus_dmamem_alloc failed: error %d\n",
1207 sc->sc_dev.dv_xname, error));
1208 return error;
1209 }
1210
1211 error = bus_dmamem_map(sc->dmat, p->segs, 1, p->size, &p->addr,
1212 BUS_DMA_NOWAIT | sc->sc_dmamap_flags);
1213 if (error) {
1214 DPRINTF(AUICH_DEBUG_DMA,
1215 ("%s: bus_dmamem_map failed: error %d\n",
1216 sc->sc_dev.dv_xname, error));
1217 goto free;
1218 }
1219
1220 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 0,
1221 BUS_DMA_NOWAIT, &p->map);
1222 if (error) {
1223 DPRINTF(AUICH_DEBUG_DMA,
1224 ("%s: bus_dmamap_create failed: error %d\n",
1225 sc->sc_dev.dv_xname, error));
1226 goto unmap;
1227 }
1228
1229 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL,
1230 BUS_DMA_NOWAIT);
1231 if (error) {
1232 DPRINTF(AUICH_DEBUG_DMA,
1233 ("%s: bus_dmamap_load failed: error %d\n",
1234 sc->sc_dev.dv_xname, error));
1235 goto destroy;
1236 }
1237 return 0;
1238
1239 destroy:
1240 bus_dmamap_destroy(sc->dmat, p->map);
1241 unmap:
1242 bus_dmamem_unmap(sc->dmat, p->addr, p->size);
1243 free:
1244 bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
1245 return error;
1246 }
1247
1248
1249 void
auich_freemem(struct auich_softc * sc,struct auich_dma * p)1250 auich_freemem(struct auich_softc *sc, struct auich_dma *p)
1251 {
1252 bus_dmamap_unload(sc->dmat, p->map);
1253 bus_dmamap_destroy(sc->dmat, p->map);
1254 bus_dmamem_unmap(sc->dmat, p->addr, p->size);
1255 bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
1256 }
1257
1258
1259
1260 int
auich_alloc_cdata(struct auich_softc * sc)1261 auich_alloc_cdata(struct auich_softc *sc)
1262 {
1263 bus_dma_segment_t seg;
1264 int error, rseg;
1265
1266 /*
1267 * Allocate the control data structure, and create and load the
1268 * DMA map for it.
1269 */
1270 if ((error = bus_dmamem_alloc(sc->dmat, sizeof(struct auich_cdata),
1271 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) {
1272 printf("%s: unable to allocate control data, error = %d\n",
1273 sc->sc_dev.dv_xname, error);
1274 goto fail_0;
1275 }
1276
1277 if ((error = bus_dmamem_map(sc->dmat, &seg, 1,
1278 sizeof(struct auich_cdata), (caddr_t *) &sc->sc_cdata,
1279 sc->sc_dmamap_flags)) != 0) {
1280 printf("%s: unable to map control data, error = %d\n",
1281 sc->sc_dev.dv_xname, error);
1282 goto fail_1;
1283 }
1284
1285 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1,
1286 sizeof(struct auich_cdata), 0, 0, &sc->sc_cddmamap)) != 0) {
1287 printf("%s: unable to create control data DMA map, "
1288 "error = %d\n", sc->sc_dev.dv_xname, error);
1289 goto fail_2;
1290 }
1291
1292 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, sc->sc_cdata,
1293 sizeof(struct auich_cdata), NULL, 0)) != 0) {
1294 printf("%s: unable to load control data DMA map, "
1295 "error = %d\n", sc->sc_dev.dv_xname, error);
1296 goto fail_3;
1297 }
1298
1299 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo;
1300 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi;
1301 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici;
1302
1303 return 0;
1304
1305 fail_3:
1306 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap);
1307 fail_2:
1308 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata,
1309 sizeof(struct auich_cdata));
1310 fail_1:
1311 bus_dmamem_free(sc->dmat, &seg, rseg);
1312 fail_0:
1313 return error;
1314 }
1315
1316 void
auich_resume(struct auich_softc * sc)1317 auich_resume(struct auich_softc *sc)
1318 {
1319 /* SiS 7012 needs special handling */
1320 if (PCI_VENDOR(sc->pci_id) == PCI_VENDOR_SIS &&
1321 PCI_PRODUCT(sc->pci_id) == PCI_PRODUCT_SIS_7012_ACA) {
1322 /* un-mute output */
1323 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL,
1324 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) |
1325 ICH_SIS_CTL_UNMUTE);
1326 }
1327
1328 ac97_resume(&sc->host_if, sc->codec_if);
1329 }
1330
1331 /* -------------------------------------------------------------------- */
1332 /* Calibrate card (some boards are overclocked and need scaling) */
1333
1334 unsigned int
auich_calibrate(struct auich_softc * sc)1335 auich_calibrate(struct auich_softc *sc)
1336 {
1337 struct timeval t1, t2;
1338 u_int8_t civ, ociv;
1339 uint16_t sts, osts;
1340 u_int32_t wait_us, actual_48k_rate, bytes, ac97rate;
1341 void *temp_buffer;
1342 struct auich_dma *p;
1343
1344 ac97rate = AUICH_FIXED_RATE;
1345 /*
1346 * Grab audio from input for fixed interval and compare how
1347 * much we actually get with what we expect. Interval needs
1348 * to be sufficiently short that no interrupts are
1349 * generated.
1350 * XXX: Is this true? We don't request any interrupts,
1351 * so why should the chip issue any?
1352 */
1353
1354 /* Setup a buffer */
1355 bytes = 16000;
1356 temp_buffer = auich_allocm(sc, 0, bytes, M_DEVBUF, M_NOWAIT);
1357 if (temp_buffer == NULL)
1358 return (ac97rate);
1359 if (sc->sc_cdma->addr == temp_buffer) {
1360 p = sc->sc_cdma;
1361 } else {
1362 printf("auich_calibrate: bad address %p\n", temp_buffer);
1363 return (ac97rate);
1364 }
1365
1366 /* get current CIV (usually 0 after reboot) */
1367 ociv = civ = bus_space_read_1(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_CIV);
1368 sc->pcmi.dmalist[civ].base = p->map->dm_segs[0].ds_addr;
1369 sc->pcmi.dmalist[civ].len = bytes / sc->sc_sample_size;
1370
1371
1372 /*
1373 * our data format is stereo, 16 bit so each sample is 4 bytes.
1374 * assuming we get 48000 samples per second, we get 192000 bytes/sec.
1375 * we're going to start recording with interrupts disabled and measure
1376 * the time taken for one block to complete. we know the block size,
1377 * we know the time in microseconds, we calculate the sample rate:
1378 *
1379 * actual_rate [bps] = bytes / (time [s] * 4)
1380 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4)
1381 * actual_rate [Hz] = (bytes * 250000) / time [us]
1382 */
1383
1384 /* prepare */
1385 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_BDBAR,
1386 sc->sc_cddma + AUICH_PCMI_OFF(0));
1387 /* we got only one valid sample, so set LVI to CIV
1388 * otherwise we provoke a AUICH_FIFOE FIFO error
1389 * which will confuse the chip later on. */
1390 bus_space_write_1(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_LVI,
1391 civ & AUICH_LVI_MASK);
1392
1393 /* start, but don't request any interrupts */
1394 microuptime(&t1);
1395 bus_space_write_1(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_CTRL,
1396 AUICH_RPBM);
1397
1398 /* XXX remove this sometime */
1399 osts = bus_space_read_2(sc->iot, sc->aud_ioh,
1400 AUICH_PCMI + sc->sc_sts_reg);
1401 /* wait */
1402 while(1) {
1403 microuptime(&t2);
1404 sts = bus_space_read_2(sc->iot, sc->aud_ioh,
1405 AUICH_PCMI + sc->sc_sts_reg);
1406 civ = bus_space_read_1(sc->iot, sc->aud_ioh,
1407 AUICH_PCMI + AUICH_CIV);
1408
1409 /* turn time delta into us */
1410 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) +
1411 t2.tv_usec - t1.tv_usec;
1412
1413 /* this should actually never happen because civ==lvi */
1414 if ((civ & AUICH_LVI_MASK) != (ociv & AUICH_LVI_MASK)) {
1415 printf("%s: ac97 CIV progressed after %d us sts=%b civ=%u\n",
1416 sc->sc_dev.dv_xname, wait_us, sts,
1417 AUICH_ISTS_BITS, civ);
1418 ociv = civ;
1419 }
1420 /* normal completion */
1421 if (sts & (AUICH_DCH | AUICH_CELV | AUICH_LVBCI))
1422 break;
1423 /*
1424 * check for strange changes in STS -
1425 * XXX remove it when everything is fine
1426 */
1427 if (sts != osts) {
1428 printf("%s: ac97 sts changed after %d us sts=%b civ=%u\n",
1429 sc->sc_dev.dv_xname, wait_us, sts,
1430 AUICH_ISTS_BITS, civ);
1431 osts = sts;
1432 }
1433 /*
1434 * timeout: we expect 83333 us for 48k sampling rate,
1435 * 600000 us will be enough even for 8k sampling rate
1436 */
1437 if (wait_us > 600000) {
1438 printf("%s: ac97 link rate timed out %d us sts=%b civ=%u\n",
1439 sc->sc_dev.dv_xname, wait_us, sts,
1440 AUICH_ISTS_BITS, civ);
1441 /* reset and clean up*/
1442 auich_halt_pipe(sc, AUICH_PCMI, &sc->pcmi);
1443 auich_halt_pipe(sc, AUICH_MICI, &sc->mici);
1444 auich_freem(sc, temp_buffer, M_DEVBUF);
1445 /* return default sample rate */
1446 return (ac97rate);
1447 }
1448 }
1449
1450 DPRINTF(AUICH_DEBUG_CODECIO,
1451 ("%s: ac97 link rate calibration took %d us sts=%b civ=%u\n",
1452 sc->sc_dev.dv_xname, wait_us, sts, AUICH_ISTS_BITS, civ));
1453
1454 /* reset and clean up */
1455 auich_halt_pipe(sc, AUICH_PCMI, &sc->pcmi);
1456 auich_halt_pipe(sc, AUICH_MICI, &sc->mici);
1457 auich_freem(sc, temp_buffer, M_DEVBUF);
1458
1459 #ifdef AUICH_DEBUG
1460 sts = bus_space_read_2(sc->iot, sc->aud_ioh,
1461 AUICH_PCMI + sc->sc_sts_reg);
1462 civ = bus_space_read_4(sc->iot, sc->aud_ioh,
1463 AUICH_PCMI + AUICH_CIV);
1464 printf("%s: after calibration and reset sts=%b civ=%u\n",
1465 sc->sc_dev.dv_xname, sts, AUICH_ISTS_BITS, civ);
1466 #endif
1467
1468 /* now finally calculate measured samplerate */
1469 actual_48k_rate = (bytes * 250000) / wait_us;
1470
1471 if (actual_48k_rate <= 48500)
1472 ac97rate = AUICH_FIXED_RATE;
1473 else
1474 ac97rate = actual_48k_rate;
1475
1476 DPRINTF(AUICH_DEBUG_CODECIO, ("%s: measured ac97 link rate at %d Hz",
1477 sc->sc_dev.dv_xname, actual_48k_rate));
1478 if (ac97rate != actual_48k_rate)
1479 DPRINTF(AUICH_DEBUG_CODECIO, (", will use %d Hz", ac97rate));
1480 DPRINTF(AUICH_DEBUG_CODECIO, ("\n"));
1481
1482 return (ac97rate);
1483 }
1484