1 /* $OpenBSD: auixpreg.h,v 1.2 2020/06/27 00:33:59 jsg Exp $ */ 2 /* $NetBSD: auixpreg.h,v 1.2 2005/01/12 00:28:03 reinoud Exp $ */ 3 4 /* 5 * Copyright (c) 2004, 2005 Reinoud Zandijk <reinoud@netbsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * NetBSD audio driver for ATI IXP-{150,200,...} audio driver hardware. 31 * 32 * Thanks are due to Takashi Iwai for the constants. 33 */ 34 35 36 #define ATI_IXP_CODECS 3 37 38 39 typedef struct atiixp_dma_desc { 40 u_int32_t addr; /* DMA buffer address */ 41 u_int16_t status; /* status bits; function unknown */ 42 u_int16_t size; /* size of this DMA packet in dwords */ 43 u_int32_t next; /* phys pointer to next packet descriptor */ 44 } __packed atiixp_dma_desc_t; 45 46 47 #define ATI_REG_ISR 0x00 /* interrupt source */ 48 #define ATI_REG_ISR_IN_XRUN (1U<<0) 49 #define ATI_REG_ISR_IN_STATUS (1U<<1) 50 #define ATI_REG_ISR_OUT_XRUN (1U<<2) 51 #define ATI_REG_ISR_OUT_STATUS (1U<<3) 52 #define ATI_REG_ISR_SPDF_XRUN (1U<<4) 53 #define ATI_REG_ISR_SPDF_STATUS (1U<<5) 54 #define ATI_REG_ISR_PHYS_INTR (1U<<8) 55 #define ATI_REG_ISR_PHYS_MISMATCH (1U<<9) 56 #define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10) 57 #define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11) 58 #define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12) 59 #define ATI_REG_ISR_NEW_FRAME (1U<<13) 60 61 #define ATI_REG_IER 0x04 /* interrupt enable */ 62 #define ATI_REG_IER_IN_XRUN_EN (1U<<0) 63 #define ATI_REG_IER_IO_STATUS_EN (1U<<1) 64 #define ATI_REG_IER_OUT_XRUN_EN (1U<<2) 65 #define ATI_REG_IER_OUT_XRUN_COND (1U<<3) 66 #define ATI_REG_IER_SPDF_XRUN_EN (1U<<4) 67 #define ATI_REG_IER_SPDF_STATUS_EN (1U<<5) 68 #define ATI_REG_IER_PHYS_INTR_EN (1U<<8) 69 #define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9) 70 #define ATI_REG_IER_CODEC0_INTR_EN (1U<<10) 71 #define ATI_REG_IER_CODEC1_INTR_EN (1U<<11) 72 #define ATI_REG_IER_CODEC2_INTR_EN (1U<<12) 73 #define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO) */ 74 #define ATI_REG_IER_SET_BUS_BUSY (1U<<14) /* (WO) audio is running */ 75 76 #define ATI_REG_CMD 0x08 /* command */ 77 #define ATI_REG_CMD_POWERDOWN (1U<<0) 78 #define ATI_REG_CMD_RECEIVE_EN (1U<<1) 79 #define ATI_REG_CMD_SEND_EN (1U<<2) 80 #define ATI_REG_CMD_STATUS_MEM (1U<<3) 81 #define ATI_REG_CMD_SPDF_OUT_EN (1U<<4) 82 #define ATI_REG_CMD_SPDF_STATUS_MEM (1U<<5) 83 #define ATI_REG_CMD_SPDF_THRESHOLD (3U<<6) 84 #define ATI_REG_CMD_SPDF_THRESHOLD_SHIFT 6 85 #define ATI_REG_CMD_IN_DMA_EN (1U<<8) 86 #define ATI_REG_CMD_OUT_DMA_EN (1U<<9) 87 #define ATI_REG_CMD_SPDF_DMA_EN (1U<<10) 88 #define ATI_REG_CMD_SPDF_OUT_STOPPED (1U<<11) 89 #define ATI_REG_CMD_SPDF_CONFIG_MASK (7U<<12) 90 #define ATI_REG_CMD_SPDF_CONFIG_34 (1U<<12) 91 #define ATI_REG_CMD_SPDF_CONFIG_78 (2U<<12) 92 #define ATI_REG_CMD_SPDF_CONFIG_69 (3U<<12) 93 #define ATI_REG_CMD_SPDF_CONFIG_01 (4U<<12) 94 #define ATI_REG_CMD_INTERLEAVE_SPDF (1U<<16) 95 #define ATI_REG_CMD_AUDIO_PRESENT (1U<<20) 96 #define ATI_REG_CMD_INTERLEAVE_IN (1U<<21) 97 #define ATI_REG_CMD_INTERLEAVE_OUT (1U<<22) 98 #define ATI_REG_CMD_LOOPBACK_EN (1U<<23) 99 #define ATI_REG_CMD_PACKED_DIS (1U<<24) 100 #define ATI_REG_CMD_BURST_EN (1U<<25) 101 #define ATI_REG_CMD_PANIC_EN (1U<<26) 102 #define ATI_REG_CMD_MODEM_PRESENT (1U<<27) 103 #define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28) 104 #define ATI_REG_CMD_AC_SOFT_RESET (1U<<29) 105 #define ATI_REG_CMD_AC_SYNC (1U<<30) 106 #define ATI_REG_CMD_AC_RESET (1U<<31) 107 108 #define ATI_REG_PHYS_OUT_ADDR 0x0c 109 #define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0) 110 #define ATI_REG_PHYS_OUT_RW (1U<<2) 111 #define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8) 112 #define ATI_REG_PHYS_OUT_ADDR_SHIFT 9 113 #define ATI_REG_PHYS_OUT_DATA_SHIFT 16 114 115 #define ATI_REG_PHYS_IN_ADDR 0x10 116 #define ATI_REG_PHYS_IN_READ_FLAG (1U<<8) 117 #define ATI_REG_PHYS_IN_ADDR_SHIFT 9 118 #define ATI_REG_PHYS_IN_DATA_SHIFT 16 119 120 #define ATI_REG_SLOTREQ 0x14 121 122 #define ATI_REG_COUNTER 0x18 123 #define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */ 124 #define ATI_REG_COUNTER_BITCLOCK (31U<<8) 125 126 #define ATI_REG_IN_FIFO_THRESHOLD 0x1c 127 128 #define ATI_REG_IN_DMA_LINKPTR 0x20 129 #define ATI_REG_IN_DMA_DT_START 0x24 /* RO */ 130 #define ATI_REG_IN_DMA_DT_NEXT 0x28 /* RO */ 131 #define ATI_REG_IN_DMA_DT_CUR 0x2c /* RO */ 132 #define ATI_REG_IN_DMA_DT_SIZE 0x30 133 134 #define ATI_REG_OUT_DMA_SLOT 0x34 135 #define ATI_REG_OUT_DMA_SLOT_BIT(x) (1U << ((x) - 3)) 136 #define ATI_REG_OUT_DMA_SLOT_MASK 0x1ff 137 #define ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800 138 #define ATI_REG_OUT_DMA_THRESHOLD_SHIFT 11 139 140 #define ATI_REG_OUT_DMA_LINKPTR 0x38 141 #define ATI_REG_OUT_DMA_DT_START 0x3c /* RO */ 142 #define ATI_REG_OUT_DMA_DT_NEXT 0x40 /* RO */ 143 #define ATI_REG_OUT_DMA_DT_CUR 0x44 /* RO */ 144 #define ATI_REG_OUT_DMA_DT_SIZE 0x48 145 146 #define ATI_REG_SPDF_CMD 0x4c 147 #define ATI_REG_SPDF_CMD_LFSR (1U<<4) 148 #define ATI_REG_SPDF_CMD_SINGLE_CH (1U<<5) 149 #define ATI_REG_SPDF_CMD_LFSR_ACC (0xff<<8) /* RO */ 150 151 #define ATI_REG_SPDF_DMA_LINKPTR 0x50 152 #define ATI_REG_SPDF_DMA_DT_START 0x54 /* RO */ 153 #define ATI_REG_SPDF_DMA_DT_NEXT 0x58 /* RO */ 154 #define ATI_REG_SPDF_DMA_DT_CUR 0x5c /* RO */ 155 #define ATI_REG_SPDF_DMA_DT_SIZE 0x60 156 157 #define ATI_REG_MODEM_MIRROR 0x7c 158 #define ATI_REG_AUDIO_MIRROR 0x80 159 160 #define ATI_REG_6CH_REORDER 0x84 /* reorder slots for 6ch */ 161 #define ATI_REG_6CH_REORDER_EN (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */ 162 163 #define ATI_REG_FIFO_FLUSH 0x88 164 #define ATI_REG_FIFO_OUT_FLUSH (1U<<0) 165 #define ATI_REG_FIFO_IN_FLUSH (1U<<1) 166 167 /* LINKPTR */ 168 #define ATI_REG_LINKPTR_EN (1U<<0) 169 170 /* [INT|OUT|SPDIF]_DMA_DT_SIZE */ 171 #define ATI_REG_DMA_DT_SIZE (0xffffU<<0) 172 #define ATI_REG_DMA_FIFO_USED (0x1fU<<16) 173 #define ATI_REG_DMA_FIFO_FREE (0x1fU<<21) 174 #define ATI_REG_DMA_STATE (7U<<26) 175