1 /* $OpenBSD: cs4280.c,v 1.11 2001/08/25 10:13:29 art Exp $ */ 2 /* $NetBSD: cs4280.c,v 1.5 2000/06/26 04:56:23 simonb Exp $ */ 3 4 /* 5 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Tatoku Ogaito 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Cirrus Logic CS4280 (and maybe CS461x) driver. 36 * Data sheets can be found 37 * http://www.cirrus.com/ftp/pubs/4280.pdf 38 * http://www.cirrus.com/ftp/pubs/4297.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 40 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 41 */ 42 43 /* 44 * TODO 45 * Implement MIDI 46 * Joystick support 47 */ 48 49 #ifdef CS4280_DEBUG 50 #ifndef MIDI_READY 51 #define MIDI_READY 52 #endif /* ! MIDI_READY */ 53 #endif 54 55 #ifdef MIDI_READY 56 #include "midi.h" 57 #endif 58 59 #if defined(CS4280_DEBUG) 60 #define DPRINTF(x) if (cs4280debug) printf x 61 #define DPRINTFN(n,x) if (cs4280debug>(n)) printf x 62 int cs4280debug = 0; 63 #else 64 #define DPRINTF(x) 65 #define DPRINTFN(n,x) 66 #endif 67 68 #include <sys/param.h> 69 #include <sys/systm.h> 70 #include <sys/kernel.h> 71 #include <sys/fcntl.h> 72 #include <sys/malloc.h> 73 #include <sys/device.h> 74 #include <sys/types.h> 75 #include <sys/systm.h> 76 77 #include <dev/pci/pcidevs.h> 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/cs4280reg.h> 80 #include <dev/microcode/cirruslogic/cs4280_image.h> 81 82 #include <sys/audioio.h> 83 #include <dev/audio_if.h> 84 #include <dev/midi_if.h> 85 #include <dev/mulaw.h> 86 #include <dev/auconv.h> 87 88 #include <dev/ic/ac97.h> 89 90 #include <machine/bus.h> 91 92 #define CSCC_PCI_BA0 0x10 93 #define CSCC_PCI_BA1 0x14 94 95 struct cs4280_dma { 96 bus_dmamap_t map; 97 caddr_t addr; /* real dma buffer */ 98 caddr_t dum; /* dummy buffer for audio driver */ 99 bus_dma_segment_t segs[1]; 100 int nsegs; 101 size_t size; 102 struct cs4280_dma *next; 103 }; 104 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 105 #define BUFADDR(p) ((void *)((p)->dum)) 106 #define KERNADDR(p) ((void *)((p)->addr)) 107 108 /* 109 * Software state 110 */ 111 struct cs4280_softc { 112 struct device sc_dev; 113 114 pci_intr_handle_t * sc_ih; 115 116 /* I/O (BA0) */ 117 bus_space_tag_t ba0t; 118 bus_space_handle_t ba0h; 119 120 /* BA1 */ 121 bus_space_tag_t ba1t; 122 bus_space_handle_t ba1h; 123 124 /* DMA */ 125 bus_dma_tag_t sc_dmatag; 126 struct cs4280_dma *sc_dmas; 127 128 void (*sc_pintr)(void *); /* dma completion intr handler */ 129 void *sc_parg; /* arg for sc_intr() */ 130 char *sc_ps, *sc_pe, *sc_pn; 131 int sc_pcount; 132 int sc_pi; 133 struct cs4280_dma *sc_pdma; 134 char *sc_pbuf; 135 #ifdef DIAGNOSTIC 136 char sc_prun; 137 #endif 138 139 void (*sc_rintr)(void *); /* dma completion intr handler */ 140 void *sc_rarg; /* arg for sc_intr() */ 141 char *sc_rs, *sc_re, *sc_rn; 142 int sc_rcount; 143 int sc_ri; 144 struct cs4280_dma *sc_rdma; 145 char *sc_rbuf; 146 int sc_rparam; /* record format */ 147 #ifdef DIAGNOSTIC 148 char sc_rrun; 149 #endif 150 151 #if NMIDI > 0 152 void (*sc_iintr)(void *, int); /* midi input ready handler */ 153 void (*sc_ointr)(void *); /* midi output ready handler */ 154 void *sc_arg; 155 #endif 156 157 u_int32_t pctl; 158 u_int32_t cctl; 159 160 struct ac97_codec_if *codec_if; 161 struct ac97_host_if host_if; 162 163 char sc_suspend; 164 void *sc_powerhook; /* Power Hook */ 165 u_int16_t ac97_reg[CS4280_SAVE_REG_MAX + 1]; /* Save ac97 registers */ 166 }; 167 168 #define BA0READ4(sc, r) bus_space_read_4((sc)->ba0t, (sc)->ba0h, (r)) 169 #define BA0WRITE4(sc, r, x) bus_space_write_4((sc)->ba0t, (sc)->ba0h, (r), (x)) 170 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 171 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 172 173 int cs4280_match __P((struct device *, void *, void *)); 174 void cs4280_attach __P((struct device *, struct device *, void *)); 175 int cs4280_intr __P((void *)); 176 void cs4280_reset __P((void *)); 177 int cs4280_download_image __P((struct cs4280_softc *)); 178 179 int cs4280_download(struct cs4280_softc *, const u_int32_t *, u_int32_t, u_int32_t); 180 int cs4280_allocmem __P((struct cs4280_softc *, size_t, size_t, 181 struct cs4280_dma *)); 182 int cs4280_freemem __P((struct cs4280_softc *, struct cs4280_dma *)); 183 184 #ifdef CS4280_DEBUG 185 int cs4280_check_images __P((struct cs4280_softc *)); 186 int cs4280_checkimage(struct cs4280_softc *, u_int32_t *, u_int32_t, 187 u_int32_t); 188 #endif 189 190 struct cfdriver clcs_cd = { 191 NULL, "clcs", DV_DULL 192 }; 193 194 struct cfattach clcs_ca = { 195 sizeof(struct cs4280_softc), cs4280_match, cs4280_attach 196 }; 197 198 int cs4280_init __P((struct cs4280_softc *, int)); 199 int cs4280_open __P((void *, int)); 200 void cs4280_close __P((void *)); 201 202 int cs4280_query_encoding __P((void *, struct audio_encoding *)); 203 int cs4280_set_params __P((void *, int, int, struct audio_params *, struct audio_params *)); 204 int cs4280_round_blocksize __P((void *, int)); 205 206 int cs4280_halt_output __P((void *)); 207 int cs4280_halt_input __P((void *)); 208 209 int cs4280_getdev __P((void *, struct audio_device *)); 210 211 int cs4280_mixer_set_port __P((void *, mixer_ctrl_t *)); 212 int cs4280_mixer_get_port __P((void *, mixer_ctrl_t *)); 213 int cs4280_query_devinfo __P((void *addr, mixer_devinfo_t *dip)); 214 void *cs4280_malloc __P((void *, u_long, int, int)); 215 void cs4280_free __P((void *, void *, int)); 216 u_long cs4280_round_buffersize __P((void *, u_long)); 217 paddr_t cs4280_mappage __P((void *, void *, off_t, int)); 218 int cs4280_get_props __P((void *)); 219 int cs4280_trigger_output __P((void *, void *, void *, int, void (*)(void *), 220 void *, struct audio_params *)); 221 int cs4280_trigger_input __P((void *, void *, void *, int, void (*)(void *), 222 void *, struct audio_params *)); 223 224 225 void cs4280_set_dac_rate __P((struct cs4280_softc *, int )); 226 void cs4280_set_adc_rate __P((struct cs4280_softc *, int )); 227 int cs4280_get_portnum_by_name __P((struct cs4280_softc *, char *, char *, 228 char *)); 229 int cs4280_src_wait __P((struct cs4280_softc *)); 230 int cs4280_attach_codec __P((void *sc, struct ac97_codec_if *)); 231 int cs4280_read_codec __P((void *sc, u_int8_t a, u_int16_t *d)); 232 int cs4280_write_codec __P((void *sc, u_int8_t a, u_int16_t d)); 233 void cs4280_reset_codec __P((void *sc)); 234 235 void cs4280_power __P((int, void *)); 236 237 void cs4280_clear_fifos __P((struct cs4280_softc *)); 238 239 #if NMIDI > 0 240 void cs4280_midi_close __P((void*)); 241 void cs4280_midi_getinfo __P((void *, struct midi_info *)); 242 int cs4280_midi_open __P((void *, int, void (*)(void *, int), 243 void (*)(void *), void *)); 244 int cs4280_midi_output __P((void *, int)); 245 #endif 246 247 struct audio_hw_if cs4280_hw_if = { 248 cs4280_open, 249 cs4280_close, 250 NULL, 251 cs4280_query_encoding, 252 cs4280_set_params, 253 cs4280_round_blocksize, 254 NULL, 255 NULL, 256 NULL, 257 NULL, 258 NULL, 259 cs4280_halt_output, 260 cs4280_halt_input, 261 NULL, 262 cs4280_getdev, 263 NULL, 264 cs4280_mixer_set_port, 265 cs4280_mixer_get_port, 266 cs4280_query_devinfo, 267 cs4280_malloc, 268 cs4280_free, 269 cs4280_round_buffersize, 270 0, /* cs4280_mappage, */ 271 cs4280_get_props, 272 cs4280_trigger_output, 273 cs4280_trigger_input, 274 }; 275 276 #if NMIDI > 0 277 struct midi_hw_if cs4280_midi_hw_if = { 278 cs4280_midi_open, 279 cs4280_midi_close, 280 cs4280_midi_output, 281 cs4280_midi_getinfo, 282 0, 283 }; 284 #endif 285 286 287 288 struct audio_device cs4280_device = { 289 "CS4280", 290 "", 291 "cs4280" 292 }; 293 294 295 int 296 cs4280_match(parent, ma, aux) 297 struct device *parent; 298 void *ma; 299 void *aux; 300 { 301 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 302 303 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 304 return (0); 305 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 || 306 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 || 307 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4614 || 308 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4615) { 309 return (1); 310 } 311 return (0); 312 } 313 314 int 315 cs4280_read_codec(sc_, add, data) 316 void *sc_; 317 u_int8_t add; 318 u_int16_t *data; 319 { 320 struct cs4280_softc *sc = sc_; 321 int n; 322 323 DPRINTFN(5,("read_codec: add=0x%02x ", add)); 324 /* 325 * Make sure that there is not data sitting around from a preivous 326 * uncompleted access. 327 */ 328 BA0READ4(sc, CS4280_ACSDA); 329 330 /* Set up AC97 control registers. */ 331 BA0WRITE4(sc, CS4280_ACCAD, add); 332 BA0WRITE4(sc, CS4280_ACCDA, 0); 333 BA0WRITE4(sc, CS4280_ACCTL, 334 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_CRW | ACCTL_DCV ); 335 336 if (cs4280_src_wait(sc) < 0) { 337 printf("%s: AC97 read prob. (DCV!=0) for add=0x%02x\n", 338 sc->sc_dev.dv_xname, add); 339 return (1); 340 } 341 342 /* wait for valid status bit is active */ 343 n = 0; 344 while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_VSTS)) { 345 delay(1); 346 while (++n > 1000) { 347 printf("%s: AC97 read fail (VSTS==0) for add=0x%02x\n", 348 sc->sc_dev.dv_xname, add); 349 return (1); 350 } 351 } 352 *data = BA0READ4(sc, CS4280_ACSDA); 353 DPRINTFN(5,("data=0x%04x\n", *data)); 354 return (0); 355 } 356 357 int 358 cs4280_write_codec(sc_, add, data) 359 void *sc_; 360 u_int8_t add; 361 u_int16_t data; 362 { 363 struct cs4280_softc *sc = sc_; 364 365 DPRINTFN(5,("write_codec: add=0x%02x data=0x%04x\n", add, data)); 366 BA0WRITE4(sc, CS4280_ACCAD, add); 367 BA0WRITE4(sc, CS4280_ACCDA, data); 368 BA0WRITE4(sc, CS4280_ACCTL, 369 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_DCV ); 370 371 if (cs4280_src_wait(sc) < 0) { 372 printf("%s: AC97 write fail (DCV!=0) for add=0x%02x data=" 373 "0x%04x\n", sc->sc_dev.dv_xname, add, data); 374 return (1); 375 } 376 return (0); 377 } 378 379 int 380 cs4280_src_wait(sc) 381 struct cs4280_softc *sc; 382 { 383 int n; 384 n = 0; 385 while ((BA0READ4(sc, CS4280_ACCTL) & ACCTL_DCV)) { 386 delay(1000); 387 while (++n > 1000) 388 return (-1); 389 } 390 return (0); 391 } 392 393 394 void 395 cs4280_set_adc_rate(sc, rate) 396 struct cs4280_softc *sc; 397 int rate; 398 { 399 /* calculate capture rate: 400 * 401 * capture_coefficient_increment = -round(rate*128*65536/48000; 402 * capture_phase_increment = floor(48000*65536*1024/rate); 403 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 404 * cy = floor(cx/200); 405 * capture_sample_rate_correction = cx - 200*cy; 406 * capture_delay = ceil(24*48000/rate); 407 * capture_num_triplets = floor(65536*rate/24000); 408 * capture_group_length = 24000/GCD(rate, 24000); 409 * where GCD means "Greatest Common Divisor". 410 * 411 * capture_coefficient_increment, capture_phase_increment and 412 * capture_num_triplets are 32-bit signed quantities. 413 * capture_sample_rate_correction and capture_group_length are 414 * 16-bit signed quantities. 415 * capture_delay is a 14-bit unsigned quantity. 416 */ 417 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 418 u_int16_t csrc, cgl, cdlay; 419 420 /* XXX 421 * Even though, embedded_audio_spec says capture rate range 11025 to 422 * 48000, dhwiface.cpp says, 423 * 424 * "We can only decimate by up to a factor of 1/9th the hardware rate. 425 * Return an error if an attempt is made to stray outside that limit." 426 * 427 * so assume range as 48000/9 to 48000 428 */ 429 430 if (rate < 8000) 431 rate = 8000; 432 if (rate > 48000) 433 rate = 48000; 434 435 cx = rate << 16; 436 cci = cx / 48000; 437 cx -= cci * 48000; 438 cx <<= 7; 439 cci <<= 7; 440 cci += cx / 48000; 441 cci = - cci; 442 443 cx = 48000 << 16; 444 cpi = cx / rate; 445 cx -= cpi * rate; 446 cx <<= 10; 447 cpi <<= 10; 448 cy = cx / rate; 449 cpi += cy; 450 cx -= cy * rate; 451 452 cy = cx / 200; 453 csrc = cx - 200*cy; 454 455 cdlay = ((48000 * 24) + rate - 1) / rate; 456 #if 0 457 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 458 #endif 459 460 cnt = rate << 16; 461 cnt /= 24000; 462 463 cgl = 1; 464 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 465 if (((rate / tmp1) * tmp1) != rate) 466 cgl *= 2; 467 } 468 if (((rate / 3) * 3) != rate) 469 cgl *= 3; 470 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 471 if (((rate / tmp1) * tmp1) != rate) 472 cgl *= 5; 473 } 474 #if 0 475 /* XXX what manual says */ 476 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 477 tmp1 |= csrc<<16; 478 BA1WRITE4(sc, CS4280_CSRC, tmp1); 479 #else 480 /* suggested by cs461x.c (ALSA driver) */ 481 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 482 #endif 483 484 #if 0 485 /* I am confused. The sample rate calculation section says 486 * cci *is* 32-bit signed quantity but in the parameter description 487 * section, CCI only assigned 16bit. 488 * I believe size of the variable. 489 */ 490 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 491 tmp1 |= cci<<16; 492 BA1WRITE4(sc, CS4280_CCI, tmp1); 493 #else 494 BA1WRITE4(sc, CS4280_CCI, cci); 495 #endif 496 497 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 498 tmp1 |= cdlay <<18; 499 BA1WRITE4(sc, CS4280_CD, tmp1); 500 501 BA1WRITE4(sc, CS4280_CPI, cpi); 502 503 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 504 tmp1 |= cgl; 505 BA1WRITE4(sc, CS4280_CGL, tmp1); 506 507 BA1WRITE4(sc, CS4280_CNT, cnt); 508 509 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 510 tmp1 |= cgl; 511 BA1WRITE4(sc, CS4280_CGC, tmp1); 512 } 513 514 void 515 cs4280_set_dac_rate(sc, rate) 516 struct cs4280_softc *sc; 517 int rate; 518 { 519 /* 520 * playback rate may range from 8000Hz to 48000Hz 521 * 522 * play_phase_increment = floor(rate*65536*1024/48000) 523 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 524 * py=floor(px/200) 525 * play_sample_rate_correction = px - 200*py 526 * 527 * play_phase_increment is a 32bit signed quantity. 528 * play_sample_rate_correction is a 16bit signed quantity. 529 */ 530 int32_t ppi; 531 int16_t psrc; 532 u_int32_t px, py; 533 534 if (rate < 8000) 535 rate = 8000; 536 if (rate > 48000) 537 rate = 48000; 538 px = rate << 16; 539 ppi = px/48000; 540 px -= ppi*48000; 541 ppi <<= 10; 542 px <<= 10; 543 py = px / 48000; 544 ppi += py; 545 px -= py*48000; 546 py = px/200; 547 px -= py*200; 548 psrc = px; 549 #if 0 550 /* what manual says */ 551 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 552 BA1WRITE4(sc, CS4280_PSRC, 553 ( ((psrc<<16) & PSRC_MASK) | px )); 554 #else 555 /* suggested by cs461x.c (ALSA driver) */ 556 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 557 #endif 558 BA1WRITE4(sc, CS4280_PPI, ppi); 559 } 560 561 void 562 cs4280_attach(parent, self, aux) 563 struct device *parent; 564 struct device *self; 565 void *aux; 566 { 567 struct cs4280_softc *sc = (struct cs4280_softc *) self; 568 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 569 pci_chipset_tag_t pc = pa->pa_pc; 570 char const *intrstr; 571 pci_intr_handle_t ih; 572 mixer_ctrl_t ctl; 573 u_int32_t mem; 574 575 /* Map I/O register */ 576 if (pci_mapreg_map(pa, CSCC_PCI_BA0, 577 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 578 &sc->ba0t, &sc->ba0h, NULL, NULL, 0)) { 579 printf(": can't map BA0 space\n"); 580 return; 581 } 582 if (pci_mapreg_map(pa, CSCC_PCI_BA1, 583 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 584 &sc->ba1t, &sc->ba1h, NULL, NULL, 0)) { 585 printf(": can't map BA1 space\n"); 586 return; 587 } 588 589 sc->sc_dmatag = pa->pa_dmat; 590 591 /* Enable the device (set bus master flag) */ 592 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 593 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 594 PCI_COMMAND_MASTER_ENABLE); 595 596 /* LATENCY_TIMER setting */ 597 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 598 if ( PCI_LATTIMER(mem) < 32 ) { 599 mem &= 0xffff00ff; 600 mem |= 0x00002000; 601 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 602 } 603 604 /* Map and establish the interrupt. */ 605 if (pci_intr_map(pa, &ih)) { 606 printf(": couldn't map interrupt\n"); 607 return; 608 } 609 intrstr = pci_intr_string(pc, ih); 610 611 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc, 612 sc->sc_dev.dv_xname); 613 if (sc->sc_ih == NULL) { 614 printf(": couldn't establish interrupt"); 615 if (intrstr != NULL) 616 printf(" at %s", intrstr); 617 printf("\n"); 618 return; 619 } 620 printf(" %s\n", intrstr); 621 622 /* Initialization */ 623 if(cs4280_init(sc, 1) != 0) 624 return; 625 626 /* AC 97 attachement */ 627 sc->host_if.arg = sc; 628 sc->host_if.attach = cs4280_attach_codec; 629 sc->host_if.read = cs4280_read_codec; 630 sc->host_if.write = cs4280_write_codec; 631 sc->host_if.reset = cs4280_reset_codec; 632 633 if (ac97_attach(&sc->host_if) != 0) { 634 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 635 return; 636 } 637 638 /* Turn mute off of DAC, CD and master volumes by default */ 639 ctl.type = AUDIO_MIXER_ENUM; 640 ctl.un.ord = 0; /* off */ 641 642 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 643 AudioNmaster, AudioNmute); 644 cs4280_mixer_set_port(sc, &ctl); 645 646 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 647 AudioNdac, AudioNmute); 648 cs4280_mixer_set_port(sc, &ctl); 649 650 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 651 AudioNcd, AudioNmute); 652 cs4280_mixer_set_port(sc, &ctl); 653 654 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 655 656 #if NMIDI > 0 657 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 658 #endif 659 sc->sc_suspend = PWR_RESUME; 660 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 661 } 662 663 int 664 cs4280_intr(p) 665 void *p; 666 { 667 /* 668 * XXX 669 * 670 * Since CS4280 has only 4kB dma buffer and 671 * interrupt occurs every 2kB block, I create dummy buffer 672 * which returns to audio driver and actual dma buffer 673 * using in DMA transfer. 674 * 675 * 676 * ring buffer in audio.c is pointed by BUFADDR 677 * <------ ring buffer size == 64kB ------> 678 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 679 * |= = = =|= = = =|= = = =|= = = =|= = = =| 680 * | | | | | | <- call audio_intp every 681 * sc->sc_[pr]_count time. 682 * 683 * actual dma buffer is pointed by KERNADDR 684 * <-> dma buffer size = 4kB 685 * |= =| 686 * 687 * 688 */ 689 struct cs4280_softc *sc = p; 690 u_int32_t intr, mem; 691 char * empty_dma; 692 int handled = 0; 693 694 /* grab interrupt register then clear it */ 695 intr = BA0READ4(sc, CS4280_HISR); 696 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 697 698 /* Playback Interrupt */ 699 if (intr & HISR_PINT) { 700 handled = 1; 701 mem = BA1READ4(sc, CS4280_PFIE); 702 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 703 if (sc->sc_pintr) { 704 if ((sc->sc_pi%sc->sc_pcount) == 0) 705 sc->sc_pintr(sc->sc_parg); 706 } else { 707 printf("unexpected play intr\n"); 708 } 709 /* copy buffer */ 710 ++sc->sc_pi; 711 empty_dma = sc->sc_pdma->addr; 712 if (sc->sc_pi&1) 713 empty_dma += CS4280_ICHUNK; 714 memcpy(empty_dma, sc->sc_pn, CS4280_ICHUNK); 715 sc->sc_pn += CS4280_ICHUNK; 716 if (sc->sc_pn >= sc->sc_pe) 717 sc->sc_pn = sc->sc_ps; 718 BA1WRITE4(sc, CS4280_PFIE, mem); 719 } 720 /* Capture Interrupt */ 721 if (intr & HISR_CINT) { 722 int i; 723 int16_t rdata; 724 725 handled = 1; 726 mem = BA1READ4(sc, CS4280_CIE); 727 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 728 ++sc->sc_ri; 729 empty_dma = sc->sc_rdma->addr; 730 if ((sc->sc_ri&1) == 0) 731 empty_dma += CS4280_ICHUNK; 732 733 /* 734 * XXX 735 * I think this audio data conversion should be 736 * happend in upper layer, but I put this here 737 * since there is no conversion function available. 738 */ 739 switch(sc->sc_rparam) { 740 case CF_16BIT_STEREO: 741 /* just copy it */ 742 memcpy(sc->sc_rn, empty_dma, CS4280_ICHUNK); 743 sc->sc_rn += CS4280_ICHUNK; 744 break; 745 case CF_16BIT_MONO: 746 for (i = 0; i < 512; i++) { 747 rdata = *((int16_t *)empty_dma)++>>1; 748 rdata += *((int16_t *)empty_dma)++>>1; 749 *((int16_t *)sc->sc_rn)++ = rdata; 750 } 751 break; 752 case CF_8BIT_STEREO: 753 for (i = 0; i < 512; i++) { 754 rdata = *((int16_t*)empty_dma)++; 755 *sc->sc_rn++ = rdata >> 8; 756 rdata = *((int16_t*)empty_dma)++; 757 *sc->sc_rn++ = rdata >> 8; 758 } 759 break; 760 case CF_8BIT_MONO: 761 for (i = 0; i < 512; i++) { 762 rdata = *((int16_t*)empty_dma)++ >>1; 763 rdata += *((int16_t*)empty_dma)++ >>1; 764 *sc->sc_rn++ = rdata >>8; 765 } 766 break; 767 default: 768 /* Should not reach here */ 769 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 770 } 771 if (sc->sc_rn >= sc->sc_re) 772 sc->sc_rn = sc->sc_rs; 773 BA1WRITE4(sc, CS4280_CIE, mem); 774 if (sc->sc_rintr) { 775 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 776 sc->sc_rintr(sc->sc_rarg); 777 } else { 778 printf("unexpected record intr\n"); 779 } 780 } 781 782 #if NMIDI > 0 783 /* Midi port Interrupt */ 784 if (intr & HISR_MIDI) { 785 int data; 786 787 handled = 1; 788 DPRINTF(("i: %d: ", 789 BA0READ4(sc, CS4280_MIDSR))); 790 /* Read the received data */ 791 while ((sc->sc_iintr != NULL) && 792 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 793 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 794 DPRINTF(("r:%x\n",data)); 795 sc->sc_iintr(sc->sc_arg, data); 796 } 797 798 /* Write the data */ 799 #if 1 800 /* XXX: 801 * It seems "Transmit Buffer Full" never activate until EOI 802 * is deliverd. Shall I throw EOI top of this routine ? 803 */ 804 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 805 DPRINTF(("w: ")); 806 if (sc->sc_ointr != NULL) 807 sc->sc_ointr(sc->sc_arg); 808 } 809 #else 810 while ((sc->sc_ointr != NULL) && 811 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 812 DPRINTF(("w: ")); 813 sc->sc_ointr(sc->sc_arg); 814 } 815 #endif 816 DPRINTF(("\n")); 817 } 818 #endif 819 820 return handled; 821 } 822 823 824 /* Download Proceessor Code and Data image */ 825 826 int 827 cs4280_download(sc, src, offset, len) 828 struct cs4280_softc *sc; 829 const u_int32_t *src; 830 u_int32_t offset, len; 831 { 832 u_int32_t ctr; 833 834 #ifdef CS4280_DEBUG 835 u_int32_t con, data; 836 u_int8_t c0,c1,c2,c3; 837 #endif 838 if ((offset&3) || (len&3)) 839 return (-1); 840 841 len /= sizeof(u_int32_t); 842 for (ctr = 0; ctr < len; ctr++) { 843 /* XXX: 844 * I cannot confirm this is the right thing or not 845 * on BIG-ENDIAN machines. 846 */ 847 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 848 #ifdef CS4280_DEBUG 849 data = htole32(*(src+ctr)); 850 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 851 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 852 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 853 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 854 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 855 if (data != con ) { 856 printf("0x%06x: write=0x%08x read=0x%08x\n", 857 offset+ctr*4, data, con); 858 return (-1); 859 } 860 #endif 861 } 862 return (0); 863 } 864 865 int 866 cs4280_download_image(sc) 867 struct cs4280_softc *sc; 868 { 869 int idx, err; 870 u_int32_t offset = 0; 871 872 err = 0; 873 874 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 875 err = cs4280_download(sc, &BA1Struct.map[offset], 876 BA1Struct.memory[idx].offset, 877 BA1Struct.memory[idx].size); 878 if (err != 0) { 879 printf("%s: load_image failed at %d\n", 880 sc->sc_dev.dv_xname, idx); 881 return (-1); 882 } 883 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 884 } 885 return (err); 886 } 887 888 #ifdef CS4280_DEBUG 889 int 890 cs4280_checkimage(sc, src, offset, len) 891 struct cs4280_softc *sc; 892 u_int32_t *src; 893 u_int32_t offset, len; 894 { 895 u_int32_t ctr, data; 896 int err = 0; 897 898 if ((offset&3) || (len&3)) 899 return -1; 900 901 len /= sizeof(u_int32_t); 902 for (ctr = 0; ctr < len; ctr++) { 903 /* I cannot confirm this is the right thing 904 * on BIG-ENDIAN machines 905 */ 906 data = BA1READ4(sc, offset+ctr*4); 907 if (data != htole32(*(src+ctr))) { 908 printf("0x%06x: 0x%08x(0x%08x)\n", 909 offset+ctr*4, data, *(src+ctr)); 910 *(src+ctr) = data; 911 ++err; 912 } 913 } 914 return (err); 915 } 916 917 int 918 cs4280_check_images(sc) 919 struct cs4280_softc *sc; 920 { 921 int idx, err; 922 u_int32_t offset = 0; 923 924 err = 0; 925 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 926 for (idx = 0; idx < 1; ++idx) { 927 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 928 BA1Struct.memory[idx].offset, 929 BA1Struct.memory[idx].size); 930 if (err != 0) { 931 printf("%s: check_image failed at %d\n", 932 sc->sc_dev.dv_xname, idx); 933 } 934 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 935 } 936 return (err); 937 } 938 939 #endif 940 941 int 942 cs4280_attach_codec(sc_, codec_if) 943 void *sc_; 944 struct ac97_codec_if *codec_if; 945 { 946 struct cs4280_softc *sc = sc_; 947 948 sc->codec_if = codec_if; 949 return (0); 950 } 951 952 void 953 cs4280_reset_codec(sc_) 954 void *sc_; 955 { 956 struct cs4280_softc *sc = sc_; 957 int n; 958 959 /* Reset codec */ 960 BA0WRITE4(sc, CS4280_ACCTL, 0); 961 delay(100); /* delay 100us */ 962 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 963 964 /* 965 * It looks like we do the following procedure, too 966 */ 967 968 /* Enable AC-link sync generation */ 969 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 970 delay(50*1000); /* XXX delay 50ms */ 971 972 /* Assert valid frame signal */ 973 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 974 975 /* Wait for valid AC97 input slot */ 976 n = 0; 977 while (BA0READ4(sc, CS4280_ACISV) != (ACISV_ISV3 | ACISV_ISV4)) { 978 delay(1000); 979 if (++n > 1000) { 980 printf("reset_codec: AC97 inputs slot ready timeout\n"); 981 return; 982 } 983 } 984 } 985 986 987 /* Processor Soft Reset */ 988 void 989 cs4280_reset(sc_) 990 void *sc_; 991 { 992 struct cs4280_softc *sc = sc_; 993 994 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 995 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 996 delay(100); 997 /* Clear RSTSP bit in SPCR */ 998 BA1WRITE4(sc, CS4280_SPCR, 0); 999 /* enable DMA reqest */ 1000 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1001 } 1002 1003 int 1004 cs4280_open(addr, flags) 1005 void *addr; 1006 int flags; 1007 { 1008 return (0); 1009 } 1010 1011 void 1012 cs4280_close(addr) 1013 void *addr; 1014 { 1015 struct cs4280_softc *sc = addr; 1016 1017 cs4280_halt_output(sc); 1018 cs4280_halt_input(sc); 1019 1020 sc->sc_pintr = 0; 1021 sc->sc_rintr = 0; 1022 } 1023 1024 int 1025 cs4280_query_encoding(addr, fp) 1026 void *addr; 1027 struct audio_encoding *fp; 1028 { 1029 switch (fp->index) { 1030 case 0: 1031 strcpy(fp->name, AudioEulinear); 1032 fp->encoding = AUDIO_ENCODING_ULINEAR; 1033 fp->precision = 8; 1034 fp->flags = 0; 1035 break; 1036 case 1: 1037 strcpy(fp->name, AudioEmulaw); 1038 fp->encoding = AUDIO_ENCODING_ULAW; 1039 fp->precision = 8; 1040 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1041 break; 1042 case 2: 1043 strcpy(fp->name, AudioEalaw); 1044 fp->encoding = AUDIO_ENCODING_ALAW; 1045 fp->precision = 8; 1046 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1047 break; 1048 case 3: 1049 strcpy(fp->name, AudioEslinear); 1050 fp->encoding = AUDIO_ENCODING_SLINEAR; 1051 fp->precision = 8; 1052 fp->flags = 0; 1053 break; 1054 case 4: 1055 strcpy(fp->name, AudioEslinear_le); 1056 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 1057 fp->precision = 16; 1058 fp->flags = 0; 1059 break; 1060 case 5: 1061 strcpy(fp->name, AudioEulinear_le); 1062 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 1063 fp->precision = 16; 1064 fp->flags = 0; 1065 break; 1066 case 6: 1067 strcpy(fp->name, AudioEslinear_be); 1068 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 1069 fp->precision = 16; 1070 fp->flags = 0; 1071 break; 1072 case 7: 1073 strcpy(fp->name, AudioEulinear_be); 1074 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 1075 fp->precision = 16; 1076 fp->flags = 0; 1077 break; 1078 default: 1079 return (EINVAL); 1080 } 1081 return (0); 1082 } 1083 1084 int 1085 cs4280_set_params(addr, setmode, usemode, play, rec) 1086 void *addr; 1087 int setmode, usemode; 1088 struct audio_params *play, *rec; 1089 { 1090 struct cs4280_softc *sc = addr; 1091 struct audio_params *p; 1092 int mode; 1093 1094 for (mode = AUMODE_RECORD; mode != -1; 1095 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 1096 if ((setmode & mode) == 0) 1097 continue; 1098 1099 p = mode == AUMODE_PLAY ? play : rec; 1100 1101 if (p == play) { 1102 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 1103 p->sample_rate, p->precision, p->channels)); 1104 /* play back data format may be 8- or 16-bit and 1105 * either stereo or mono. 1106 * playback rate may range from 8000Hz to 48000Hz 1107 */ 1108 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1109 (p->precision != 8 && p->precision != 16) || 1110 (p->channels != 1 && p->channels != 2) ) { 1111 return (EINVAL); 1112 } 1113 } else { 1114 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 1115 p->sample_rate, p->precision, p->channels)); 1116 /* capture data format must be 16bit stereo 1117 * and sample rate range from 11025Hz to 48000Hz. 1118 * 1119 * XXX: it looks like to work with 8000Hz, 1120 * although data sheets say lower limit is 1121 * 11025 Hz. 1122 */ 1123 1124 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1125 (p->precision != 8 && p->precision != 16) || 1126 (p->channels != 1 && p->channels != 2) ) { 1127 return (EINVAL); 1128 } 1129 } 1130 p->factor = 1; 1131 p->sw_code = 0; 1132 1133 /* capturing data is slinear */ 1134 switch (p->encoding) { 1135 case AUDIO_ENCODING_SLINEAR_BE: 1136 if (mode == AUMODE_RECORD) { 1137 if (p->precision == 16) 1138 p->sw_code = swap_bytes; 1139 } 1140 break; 1141 case AUDIO_ENCODING_SLINEAR_LE: 1142 break; 1143 case AUDIO_ENCODING_ULINEAR_BE: 1144 if (mode == AUMODE_RECORD) { 1145 if (p->precision == 16) 1146 p->sw_code = change_sign16_swap_bytes; 1147 else 1148 p->sw_code = change_sign8; 1149 } 1150 break; 1151 case AUDIO_ENCODING_ULINEAR_LE: 1152 if (mode == AUMODE_RECORD) { 1153 if (p->precision == 16) 1154 p->sw_code = change_sign16; 1155 else 1156 p->sw_code = change_sign8; 1157 } 1158 break; 1159 case AUDIO_ENCODING_ULAW: 1160 if (mode == AUMODE_PLAY) { 1161 p->factor = 2; 1162 p->sw_code = mulaw_to_slinear16; 1163 } else { 1164 p->sw_code = slinear8_to_mulaw; 1165 } 1166 break; 1167 case AUDIO_ENCODING_ALAW: 1168 if (mode == AUMODE_PLAY) { 1169 p->factor = 2; 1170 p->sw_code = alaw_to_slinear16; 1171 } else { 1172 p->sw_code = slinear8_to_alaw; 1173 } 1174 break; 1175 default: 1176 return (EINVAL); 1177 } 1178 } 1179 1180 /* set sample rate */ 1181 cs4280_set_dac_rate(sc, play->sample_rate); 1182 cs4280_set_adc_rate(sc, rec->sample_rate); 1183 return (0); 1184 } 1185 1186 int 1187 cs4280_round_blocksize(hdl, blk) 1188 void *hdl; 1189 int blk; 1190 { 1191 return (blk < CS4280_ICHUNK ? CS4280_ICHUNK : blk & -CS4280_ICHUNK); 1192 } 1193 1194 u_long 1195 cs4280_round_buffersize(addr, size) 1196 void *addr; 1197 u_long size; 1198 { 1199 /* although real dma buffer size is 4KB, 1200 * let the audio.c driver use a larger buffer. 1201 * ( suggested by Lennart Augustsson. ) 1202 */ 1203 return (size); 1204 } 1205 1206 int 1207 cs4280_get_props(hdl) 1208 void *hdl; 1209 { 1210 return (AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX); 1211 #ifdef notyet 1212 /* XXX 1213 * How can I mmap ? 1214 */ 1215 AUDIO_PROP_MMAP 1216 #endif 1217 1218 } 1219 1220 int 1221 cs4280_mixer_get_port(addr, cp) 1222 void *addr; 1223 mixer_ctrl_t *cp; 1224 { 1225 struct cs4280_softc *sc = addr; 1226 1227 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 1228 } 1229 1230 paddr_t 1231 cs4280_mappage(addr, mem, off, prot) 1232 void *addr; 1233 void *mem; 1234 off_t off; 1235 int prot; 1236 { 1237 struct cs4280_softc *sc = addr; 1238 struct cs4280_dma *p; 1239 1240 if (off < 0) 1241 return (-1); 1242 for (p = sc->sc_dmas; p && BUFADDR(p) != mem; p = p->next) 1243 ; 1244 if (!p) { 1245 DPRINTF(("cs4280_mappage: bad buffer address\n")); 1246 return (-1); 1247 } 1248 return (bus_dmamem_mmap(sc->sc_dmatag, p->segs, p->nsegs, 1249 off, prot, BUS_DMA_WAITOK)); 1250 } 1251 1252 1253 int 1254 cs4280_query_devinfo(addr, dip) 1255 void *addr; 1256 mixer_devinfo_t *dip; 1257 { 1258 struct cs4280_softc *sc = addr; 1259 1260 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dip)); 1261 } 1262 1263 int 1264 cs4280_get_portnum_by_name(sc, class, device, qualifier) 1265 struct cs4280_softc *sc; 1266 char *class, *device, *qualifier; 1267 { 1268 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1269 device, qualifier)); 1270 } 1271 1272 int 1273 cs4280_halt_output(addr) 1274 void *addr; 1275 { 1276 struct cs4280_softc *sc = addr; 1277 u_int32_t mem; 1278 1279 mem = BA1READ4(sc, CS4280_PCTL); 1280 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1281 #ifdef DIAGNOSTIC 1282 sc->sc_prun = 0; 1283 #endif 1284 return (0); 1285 } 1286 1287 int 1288 cs4280_halt_input(addr) 1289 void *addr; 1290 { 1291 struct cs4280_softc *sc = addr; 1292 u_int32_t mem; 1293 1294 mem = BA1READ4(sc, CS4280_CCTL); 1295 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1296 #ifdef DIAGNOSTIC 1297 sc->sc_rrun = 0; 1298 #endif 1299 return (0); 1300 } 1301 1302 int 1303 cs4280_getdev(addr, retp) 1304 void *addr; 1305 struct audio_device *retp; 1306 { 1307 *retp = cs4280_device; 1308 return (0); 1309 } 1310 1311 int 1312 cs4280_mixer_set_port(addr, cp) 1313 void *addr; 1314 mixer_ctrl_t *cp; 1315 { 1316 struct cs4280_softc *sc = addr; 1317 int val; 1318 1319 val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1320 DPRINTFN(3,("mixer_set_port: val=%d\n", val)); 1321 return (val); 1322 } 1323 1324 1325 int 1326 cs4280_freemem(sc, p) 1327 struct cs4280_softc *sc; 1328 struct cs4280_dma *p; 1329 { 1330 bus_dmamap_unload(sc->sc_dmatag, p->map); 1331 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1332 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1333 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1334 return (0); 1335 } 1336 1337 int 1338 cs4280_allocmem(sc, size, align, p) 1339 struct cs4280_softc *sc; 1340 size_t size; 1341 size_t align; 1342 struct cs4280_dma *p; 1343 { 1344 int error; 1345 1346 /* XXX */ 1347 p->size = size; 1348 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 1349 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1350 &p->nsegs, BUS_DMA_NOWAIT); 1351 if (error) { 1352 printf("%s: unable to allocate dma, error=%d\n", 1353 sc->sc_dev.dv_xname, error); 1354 return (error); 1355 } 1356 1357 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 1358 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1359 if (error) { 1360 printf("%s: unable to map dma, error=%d\n", 1361 sc->sc_dev.dv_xname, error); 1362 goto free; 1363 } 1364 1365 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 1366 0, BUS_DMA_NOWAIT, &p->map); 1367 if (error) { 1368 printf("%s: unable to create dma map, error=%d\n", 1369 sc->sc_dev.dv_xname, error); 1370 goto unmap; 1371 } 1372 1373 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, 1374 BUS_DMA_NOWAIT); 1375 if (error) { 1376 printf("%s: unable to load dma map, error=%d\n", 1377 sc->sc_dev.dv_xname, error); 1378 goto destroy; 1379 } 1380 return (0); 1381 1382 destroy: 1383 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1384 unmap: 1385 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1386 free: 1387 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1388 return (error); 1389 } 1390 1391 1392 void * 1393 cs4280_malloc(addr, size, pool, flags) 1394 void *addr; 1395 u_long size; 1396 int pool, flags; 1397 { 1398 struct cs4280_softc *sc = addr; 1399 struct cs4280_dma *p; 1400 caddr_t q; 1401 int error; 1402 1403 DPRINTFN(5,("cs4280_malloc: size=%d pool=%d flags=%d\n", size, pool, flags)); 1404 q = malloc(size, pool, flags); 1405 if (!q) 1406 return (0); 1407 p = malloc(sizeof(*p), pool, flags); 1408 if (!p) { 1409 free(q,pool); 1410 return (0); 1411 } 1412 /* 1413 * cs4280 has fixed 4kB buffer 1414 */ 1415 error = cs4280_allocmem(sc, CS4280_DCHUNK, CS4280_DALIGN, p); 1416 1417 if (error) { 1418 free(q, pool); 1419 free(p, pool); 1420 return (0); 1421 } 1422 1423 p->next = sc->sc_dmas; 1424 sc->sc_dmas = p; 1425 p->dum = q; /* return to audio driver */ 1426 1427 return (p->dum); 1428 } 1429 1430 void 1431 cs4280_free(addr, ptr, pool) 1432 void *addr; 1433 void *ptr; 1434 int pool; 1435 { 1436 struct cs4280_softc *sc = addr; 1437 struct cs4280_dma **pp, *p; 1438 1439 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1440 if (BUFADDR(p) == ptr) { 1441 cs4280_freemem(sc, p); 1442 *pp = p->next; 1443 free(p->dum, pool); 1444 free(p, pool); 1445 return; 1446 } 1447 } 1448 } 1449 1450 int 1451 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 1452 void *addr; 1453 void *start, *end; 1454 int blksize; 1455 void (*intr) __P((void *)); 1456 void *arg; 1457 struct audio_params *param; 1458 { 1459 struct cs4280_softc *sc = addr; 1460 u_int32_t pfie, pctl, mem, pdtc; 1461 struct cs4280_dma *p; 1462 1463 #ifdef DIAGNOSTIC 1464 if (sc->sc_prun) 1465 printf("cs4280_trigger_output: already running\n"); 1466 sc->sc_prun = 1; 1467 #endif 1468 1469 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 1470 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1471 sc->sc_pintr = intr; 1472 sc->sc_parg = arg; 1473 1474 /* stop playback DMA */ 1475 mem = BA1READ4(sc, CS4280_PCTL); 1476 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1477 1478 /* setup PDTC */ 1479 pdtc = BA1READ4(sc, CS4280_PDTC); 1480 pdtc &= ~PDTC_MASK; 1481 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 1482 BA1WRITE4(sc, CS4280_PDTC, pdtc); 1483 1484 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 1485 param->precision, param->factor, param->channels, 1486 param->encoding)); 1487 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 1488 ; 1489 if (p == NULL) { 1490 printf("cs4280_trigger_output: bad addr %p\n", start); 1491 return (EINVAL); 1492 } 1493 if (DMAADDR(p) % CS4280_DALIGN != 0 ) { 1494 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 1495 "4kB align\n", DMAADDR(p)); 1496 return (EINVAL); 1497 } 1498 1499 sc->sc_pcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1500 sc->sc_ps = (char *)start; 1501 sc->sc_pe = (char *)end; 1502 sc->sc_pdma = p; 1503 sc->sc_pbuf = KERNADDR(p); 1504 sc->sc_pi = 0; 1505 sc->sc_pn = sc->sc_ps; 1506 if (blksize >= CS4280_DCHUNK) { 1507 sc->sc_pn = sc->sc_ps + CS4280_DCHUNK; 1508 memcpy(sc->sc_pbuf, start, CS4280_DCHUNK); 1509 ++sc->sc_pi; 1510 } else { 1511 sc->sc_pn = sc->sc_ps + CS4280_ICHUNK; 1512 memcpy(sc->sc_pbuf, start, CS4280_ICHUNK); 1513 } 1514 1515 /* initiate playback dma */ 1516 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 1517 1518 /* set PFIE */ 1519 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 1520 1521 if (param->precision * param->factor == 8) 1522 pfie |= PFIE_8BIT; 1523 if (param->channels == 1) 1524 pfie |= PFIE_MONO; 1525 1526 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1527 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 1528 pfie |= PFIE_SWAPPED; 1529 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1530 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 1531 pfie |= PFIE_UNSIGNED; 1532 1533 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 1534 1535 cs4280_set_dac_rate(sc, param->sample_rate); 1536 1537 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 1538 pctl |= sc->pctl; 1539 BA1WRITE4(sc, CS4280_PCTL, pctl); 1540 return (0); 1541 } 1542 1543 int 1544 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 1545 void *addr; 1546 void *start, *end; 1547 int blksize; 1548 void (*intr) __P((void *)); 1549 void *arg; 1550 struct audio_params *param; 1551 { 1552 struct cs4280_softc *sc = addr; 1553 u_int32_t cctl, cie; 1554 struct cs4280_dma *p; 1555 1556 #ifdef DIAGNOSTIC 1557 if (sc->sc_rrun) 1558 printf("cs4280_trigger_input: already running\n"); 1559 sc->sc_rrun = 1; 1560 #endif 1561 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 1562 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1563 sc->sc_rintr = intr; 1564 sc->sc_rarg = arg; 1565 1566 sc->sc_ri = 0; 1567 sc->sc_rcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1568 sc->sc_rs = (char *)start; 1569 sc->sc_re = (char *)end; 1570 sc->sc_rn = sc->sc_rs; 1571 1572 /* setup format information for internal converter */ 1573 sc->sc_rparam = 0; 1574 if (param->precision == 8) { 1575 sc->sc_rparam += CF_8BIT; 1576 sc->sc_rcount <<= 1; 1577 } 1578 if (param->channels == 1) { 1579 sc->sc_rparam += CF_MONO; 1580 sc->sc_rcount <<= 1; 1581 } 1582 1583 /* stop capture DMA */ 1584 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1585 BA1WRITE4(sc, CS4280_CCTL, cctl); 1586 1587 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 1588 ; 1589 if (!p) { 1590 printf("cs4280_trigger_input: bad addr %p\n", start); 1591 return (EINVAL); 1592 } 1593 if (DMAADDR(p) % CS4280_DALIGN != 0) { 1594 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 1595 "4kB align\n", DMAADDR(p)); 1596 return (EINVAL); 1597 } 1598 sc->sc_rdma = p; 1599 sc->sc_rbuf = KERNADDR(p); 1600 1601 /* initiate capture dma */ 1602 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 1603 1604 /* set CIE */ 1605 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1606 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 1607 1608 cs4280_set_adc_rate(sc, param->sample_rate); 1609 1610 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1611 cctl |= sc->cctl; 1612 BA1WRITE4(sc, CS4280_CCTL, cctl); 1613 return (0); 1614 } 1615 1616 1617 int 1618 cs4280_init(sc, init) 1619 struct cs4280_softc *sc; 1620 int init; 1621 { 1622 int n; 1623 u_int32_t mem; 1624 1625 /* Start PLL out in known state */ 1626 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1627 /* Start serial ports out in known state */ 1628 BA0WRITE4(sc, CS4280_SERMC1, 0); 1629 1630 /* Specify type of CODEC */ 1631 /* XXX should no be here */ 1632 #define SERACC_CODEC_TYPE_1_03 1633 #ifdef SERACC_CODEC_TYPE_1_03 1634 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1635 #else 1636 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1637 #endif 1638 1639 /* Reset codec */ 1640 BA0WRITE4(sc, CS4280_ACCTL, 0); 1641 delay(100); /* delay 100us */ 1642 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 1643 1644 /* Enable AC-link sync generation */ 1645 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1646 delay(50*1000); /* delay 50ms */ 1647 1648 /* Set the serial port timing configuration */ 1649 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1650 1651 /* Setup clock control */ 1652 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1653 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1654 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1655 1656 /* Power up the PLL */ 1657 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1658 delay(50*1000); /* delay 50ms */ 1659 1660 /* Turn on clock */ 1661 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1662 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1663 1664 /* Set the serial port FIFO pointer to the 1665 * first sample in FIFO. (not documented) */ 1666 cs4280_clear_fifos(sc); 1667 1668 #if 0 1669 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1670 BA0WRITE4(sc, CS4280_SERBSP, 0); 1671 #endif 1672 1673 /* Configure the serial port */ 1674 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1675 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1676 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1677 1678 /* Wait for CODEC ready */ 1679 n = 0; 1680 while ((BA0READ4(sc, CS4280_ACSTS) & ACSTS_CRDY) == 0) { 1681 delay(125); 1682 if (++n > 1000) { 1683 printf("%s: codec ready timeout\n", 1684 sc->sc_dev.dv_xname); 1685 return(1); 1686 } 1687 } 1688 1689 /* Assert valid frame signal */ 1690 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1691 1692 /* Wait for valid AC97 input slot */ 1693 n = 0; 1694 while ((BA0READ4(sc, CS4280_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1695 (ACISV_ISV3 | ACISV_ISV4)) { 1696 delay(1000); 1697 if (++n > 1000) { 1698 printf("AC97 inputs slot ready timeout\n"); 1699 return(1); 1700 } 1701 } 1702 1703 /* Set AC97 output slot valid signals */ 1704 BA0WRITE4(sc, CS4280_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1705 1706 /* reset the processor */ 1707 cs4280_reset(sc); 1708 1709 /* Download the image to the processor */ 1710 if (cs4280_download_image(sc) != 0) { 1711 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1712 return(1); 1713 } 1714 1715 /* Save playback parameter and then write zero. 1716 * this ensures that DMA doesn't immediately occur upon 1717 * starting the processor core 1718 */ 1719 mem = BA1READ4(sc, CS4280_PCTL); 1720 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1721 cs4280_halt_output(sc); 1722 1723 /* Save capture parameter and then write zero. 1724 * this ensures that DMA doesn't immediately occur upon 1725 * starting the processor core 1726 */ 1727 mem = BA1READ4(sc, CS4280_CCTL); 1728 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1729 cs4280_halt_input(sc); 1730 1731 /* MSH: need to power up ADC and DAC? */ 1732 1733 /* Processor Startup Procedure */ 1734 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1735 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1736 1737 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1738 n = 0; 1739 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1740 delay(10); 1741 if (++n > 1000) { 1742 printf("SPCR 1->0 transition timeout\n"); 1743 return(1); 1744 } 1745 } 1746 1747 n = 0; 1748 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1749 delay(10); 1750 if (++n > 1000) { 1751 printf("SPCS 0->1 transition timeout\n"); 1752 return(1); 1753 } 1754 } 1755 /* Processor is now running !!! */ 1756 1757 /* Setup volume */ 1758 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1759 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1760 1761 /* Interrupt enable */ 1762 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1763 1764 /* playback interrupt enable */ 1765 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1766 mem |= PFIE_PI_ENABLE; 1767 BA1WRITE4(sc, CS4280_PFIE, mem); 1768 /* capture interrupt enable */ 1769 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1770 mem |= CIE_CI_ENABLE; 1771 BA1WRITE4(sc, CS4280_CIE, mem); 1772 1773 #if NMIDI > 0 1774 /* Reset midi port */ 1775 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1776 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1777 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1778 /* midi interrupt enable */ 1779 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1780 BA0WRITE4(sc, CS4280_MIDCR, mem); 1781 #endif 1782 return(0); 1783 } 1784 1785 void 1786 cs4280_power(why, v) 1787 int why; 1788 void *v; 1789 { 1790 struct cs4280_softc *sc = (struct cs4280_softc *)v; 1791 int i; 1792 1793 DPRINTF(("%s: cs4280_power why=%d\n", 1794 sc->sc_dev.dv_xname, why)); 1795 if (why != PWR_RESUME) { 1796 sc->sc_suspend = why; 1797 1798 cs4280_halt_output(sc); 1799 cs4280_halt_input(sc); 1800 /* Save AC97 registers */ 1801 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1802 if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1803 continue; 1804 cs4280_read_codec(sc, 2*i, &sc->ac97_reg[i]); 1805 } 1806 /* should I powerdown here ? */ 1807 cs4280_write_codec(sc, AC97_REG_POWER, CS4280_POWER_DOWN_ALL); 1808 } else { 1809 if (sc->sc_suspend == PWR_RESUME) { 1810 printf("cs4280_power: odd, resume without suspend.\n"); 1811 sc->sc_suspend = why; 1812 return; 1813 } 1814 sc->sc_suspend = why; 1815 cs4280_init(sc, 0); 1816 cs4280_reset_codec(sc); 1817 1818 /* restore ac97 registers */ 1819 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1820 if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1821 continue; 1822 cs4280_write_codec(sc, 2*i, sc->ac97_reg[i]); 1823 } 1824 } 1825 } 1826 1827 void 1828 cs4280_clear_fifos(sc) 1829 struct cs4280_softc *sc; 1830 { 1831 int pd = 0, cnt, n; 1832 u_int32_t mem; 1833 1834 /* 1835 * If device power down, power up the device and keep power down 1836 * state. 1837 */ 1838 mem = BA0READ4(sc, CS4280_CLKCR1); 1839 if (!(mem & CLKCR1_SWCE)) { 1840 printf("cs4280_clear_fifo: power down found.\n"); 1841 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1842 pd = 1; 1843 } 1844 BA0WRITE4(sc, CS4280_SERBWP, 0); 1845 for (cnt = 0; cnt < 256; cnt++) { 1846 n = 0; 1847 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1848 delay(1000); 1849 if (++n > 1000) { 1850 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1851 break; 1852 } 1853 } 1854 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1855 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1856 } 1857 if (pd) 1858 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1859 } 1860 1861 #if NMIDI > 0 1862 int 1863 cs4280_midi_open(addr, flags, iintr, ointr, arg) 1864 void *addr; 1865 int flags; 1866 void (*iintr)__P((void *, int)); 1867 void (*ointr)__P((void *)); 1868 void *arg; 1869 { 1870 struct cs4280_softc *sc = addr; 1871 u_int32_t mem; 1872 1873 DPRINTF(("midi_open\n")); 1874 sc->sc_iintr = iintr; 1875 sc->sc_ointr = ointr; 1876 sc->sc_arg = arg; 1877 1878 /* midi interrupt enable */ 1879 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1880 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1881 BA0WRITE4(sc, CS4280_MIDCR, mem); 1882 #ifdef CS4280_DEBUG 1883 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1884 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1885 return(EINVAL); 1886 } 1887 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1888 #endif 1889 return (0); 1890 } 1891 1892 void 1893 cs4280_midi_close(addr) 1894 void *addr; 1895 { 1896 struct cs4280_softc *sc = addr; 1897 u_int32_t mem; 1898 1899 DPRINTF(("midi_close\n")); 1900 mem = BA0READ4(sc, CS4280_MIDCR); 1901 mem &= ~MIDCR_MASK; 1902 BA0WRITE4(sc, CS4280_MIDCR, mem); 1903 1904 sc->sc_iintr = 0; 1905 sc->sc_ointr = 0; 1906 } 1907 1908 int 1909 cs4280_midi_output(addr, d) 1910 void *addr; 1911 int d; 1912 { 1913 struct cs4280_softc *sc = addr; 1914 u_int32_t mem; 1915 int x; 1916 1917 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1918 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1919 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1920 mem |= d & MIDWP_MASK; 1921 DPRINTFN(5,("midi_output d=0x%08x",d)); 1922 BA0WRITE4(sc, CS4280_MIDWP, mem); 1923 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1924 DPRINTF(("Bad write data: %d %d", 1925 mem, BA0READ4(sc, CS4280_MIDWP))); 1926 return(EIO); 1927 } 1928 return (0); 1929 } 1930 delay(MIDI_BUSY_DELAY); 1931 } 1932 return (EIO); 1933 } 1934 1935 void 1936 cs4280_midi_getinfo(addr, mi) 1937 void *addr; 1938 struct midi_info *mi; 1939 { 1940 mi->name = "CS4280 MIDI UART"; 1941 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1942 } 1943 1944 #endif 1945