1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include "amdgpu_ctx.h" 32 33 #include <linux/atomic.h> 34 #include <linux/wait.h> 35 #include <linux/list.h> 36 #include <linux/kref.h> 37 #include <linux/rbtree.h> 38 #include <linux/hashtable.h> 39 #include <linux/dma-fence.h> 40 41 #include <drm/ttm/ttm_bo_api.h> 42 #include <drm/ttm/ttm_bo_driver.h> 43 #include <drm/ttm/ttm_placement.h> 44 #include <drm/ttm/ttm_module.h> 45 #include <drm/ttm/ttm_execbuf_util.h> 46 47 #include <drm/amdgpu_drm.h> 48 #include <drm/drm_gem.h> 49 #include <drm/drm_ioctl.h> 50 #include <drm/gpu_scheduler.h> 51 52 #include <dev/wscons/wsconsio.h> 53 #include <dev/wscons/wsdisplayvar.h> 54 #include <dev/rasops/rasops.h> 55 56 #include <kgd_kfd_interface.h> 57 #include "dm_pp_interface.h" 58 #include "kgd_pp_interface.h" 59 60 #include "amd_shared.h" 61 #include "amdgpu_mode.h" 62 #include "amdgpu_ih.h" 63 #include "amdgpu_irq.h" 64 #include "amdgpu_ucode.h" 65 #include "amdgpu_ttm.h" 66 #include "amdgpu_psp.h" 67 #include "amdgpu_gds.h" 68 #include "amdgpu_sync.h" 69 #include "amdgpu_ring.h" 70 #include "amdgpu_vm.h" 71 #include "amdgpu_dpm.h" 72 #include "amdgpu_acp.h" 73 #include "amdgpu_uvd.h" 74 #include "amdgpu_vce.h" 75 #include "amdgpu_vcn.h" 76 #include "amdgpu_jpeg.h" 77 #include "amdgpu_mn.h" 78 #include "amdgpu_gmc.h" 79 #include "amdgpu_gfx.h" 80 #include "amdgpu_sdma.h" 81 #include "amdgpu_nbio.h" 82 #include "amdgpu_dm.h" 83 #include "amdgpu_virt.h" 84 #include "amdgpu_csa.h" 85 #include "amdgpu_gart.h" 86 #include "amdgpu_debugfs.h" 87 #include "amdgpu_job.h" 88 #include "amdgpu_bo_list.h" 89 #include "amdgpu_gem.h" 90 #include "amdgpu_doorbell.h" 91 #include "amdgpu_amdkfd.h" 92 #include "amdgpu_smu.h" 93 #include "amdgpu_discovery.h" 94 #include "amdgpu_mes.h" 95 #include "amdgpu_umc.h" 96 #include "amdgpu_mmhub.h" 97 #include "amdgpu_df.h" 98 99 #define MAX_GPU_INSTANCE 16 100 101 struct amdgpu_gpu_instance 102 { 103 struct amdgpu_device *adev; 104 int mgpu_fan_enabled; 105 }; 106 107 struct amdgpu_mgpu_info 108 { 109 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 110 struct rwlock mutex; 111 uint32_t num_gpu; 112 uint32_t num_dgpu; 113 uint32_t num_apu; 114 }; 115 116 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 117 118 /* 119 * Modules parameters. 120 */ 121 extern int amdgpu_modeset; 122 extern int amdgpu_vram_limit; 123 extern int amdgpu_vis_vram_limit; 124 extern int amdgpu_gart_size; 125 extern int amdgpu_gtt_size; 126 extern int amdgpu_moverate; 127 extern int amdgpu_benchmarking; 128 extern int amdgpu_testing; 129 extern int amdgpu_audio; 130 extern int amdgpu_disp_priority; 131 extern int amdgpu_hw_i2c; 132 extern int amdgpu_pcie_gen2; 133 extern int amdgpu_msi; 134 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 135 extern int amdgpu_dpm; 136 extern int amdgpu_fw_load_type; 137 extern int amdgpu_aspm; 138 extern int amdgpu_runtime_pm; 139 extern uint amdgpu_ip_block_mask; 140 extern int amdgpu_bapm; 141 extern int amdgpu_deep_color; 142 extern int amdgpu_vm_size; 143 extern int amdgpu_vm_block_size; 144 extern int amdgpu_vm_fragment_size; 145 extern int amdgpu_vm_fault_stop; 146 extern int amdgpu_vm_debug; 147 extern int amdgpu_vm_update_mode; 148 extern int amdgpu_exp_hw_support; 149 extern int amdgpu_dc; 150 extern int amdgpu_sched_jobs; 151 extern int amdgpu_sched_hw_submission; 152 extern uint amdgpu_pcie_gen_cap; 153 extern uint amdgpu_pcie_lane_cap; 154 extern uint amdgpu_cg_mask; 155 extern uint amdgpu_pg_mask; 156 extern uint amdgpu_sdma_phase_quantum; 157 extern char *amdgpu_disable_cu; 158 extern char *amdgpu_virtual_display; 159 extern uint amdgpu_pp_feature_mask; 160 extern uint amdgpu_force_long_training; 161 extern int amdgpu_job_hang_limit; 162 extern int amdgpu_lbpw; 163 extern int amdgpu_compute_multipipe; 164 extern int amdgpu_gpu_recovery; 165 extern int amdgpu_emu_mode; 166 extern uint amdgpu_smu_memory_pool_size; 167 extern uint amdgpu_dc_feature_mask; 168 extern uint amdgpu_dm_abm_level; 169 extern struct amdgpu_mgpu_info mgpu_info; 170 extern int amdgpu_ras_enable; 171 extern uint amdgpu_ras_mask; 172 extern int amdgpu_async_gfx_ring; 173 extern int amdgpu_mcbp; 174 extern int amdgpu_discovery; 175 extern int amdgpu_mes; 176 extern int amdgpu_noretry; 177 extern int amdgpu_force_asic_type; 178 #ifdef CONFIG_HSA_AMD 179 extern int sched_policy; 180 #else 181 static const int sched_policy = KFD_SCHED_POLICY_HWS; 182 #endif 183 184 #ifdef CONFIG_DRM_AMDGPU_SI 185 extern int amdgpu_si_support; 186 #endif 187 #ifdef CONFIG_DRM_AMDGPU_CIK 188 extern int amdgpu_cik_support; 189 #endif 190 191 #define AMDGPU_VM_MAX_NUM_CTX 4096 192 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 193 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 194 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 195 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 196 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 197 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 198 #define AMDGPU_IB_POOL_SIZE 16 199 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 200 #define AMDGPUFB_CONN_LIMIT 4 201 #define AMDGPU_BIOS_NUM_SCRATCH 16 202 203 /* hard reset data */ 204 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 205 206 /* reset flags */ 207 #define AMDGPU_RESET_GFX (1 << 0) 208 #define AMDGPU_RESET_COMPUTE (1 << 1) 209 #define AMDGPU_RESET_DMA (1 << 2) 210 #define AMDGPU_RESET_CP (1 << 3) 211 #define AMDGPU_RESET_GRBM (1 << 4) 212 #define AMDGPU_RESET_DMA1 (1 << 5) 213 #define AMDGPU_RESET_RLC (1 << 6) 214 #define AMDGPU_RESET_SEM (1 << 7) 215 #define AMDGPU_RESET_IH (1 << 8) 216 #define AMDGPU_RESET_VMC (1 << 9) 217 #define AMDGPU_RESET_MC (1 << 10) 218 #define AMDGPU_RESET_DISPLAY (1 << 11) 219 #define AMDGPU_RESET_UVD (1 << 12) 220 #define AMDGPU_RESET_VCE (1 << 13) 221 #define AMDGPU_RESET_VCE1 (1 << 14) 222 223 /* max cursor sizes (in pixels) */ 224 #define CIK_CURSOR_WIDTH 128 225 #define CIK_CURSOR_HEIGHT 128 226 227 struct amdgpu_device; 228 struct amdgpu_ib; 229 struct amdgpu_cs_parser; 230 struct amdgpu_job; 231 struct amdgpu_irq_src; 232 struct amdgpu_fpriv; 233 struct amdgpu_bo_va_mapping; 234 struct amdgpu_atif; 235 struct kfd_vm_fault_info; 236 237 enum amdgpu_cp_irq { 238 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 239 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 240 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 241 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 242 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 243 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 244 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 245 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 246 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 247 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 248 249 AMDGPU_CP_IRQ_LAST 250 }; 251 252 enum amdgpu_thermal_irq { 253 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 254 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 255 256 AMDGPU_THERMAL_IRQ_LAST 257 }; 258 259 enum amdgpu_kiq_irq { 260 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 261 AMDGPU_CP_KIQ_IRQ_LAST 262 }; 263 264 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 265 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 266 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 267 268 int amdgpu_device_ip_set_clockgating_state(void *dev, 269 enum amd_ip_block_type block_type, 270 enum amd_clockgating_state state); 271 int amdgpu_device_ip_set_powergating_state(void *dev, 272 enum amd_ip_block_type block_type, 273 enum amd_powergating_state state); 274 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 275 u32 *flags); 276 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 277 enum amd_ip_block_type block_type); 278 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 279 enum amd_ip_block_type block_type); 280 281 #define AMDGPU_MAX_IP_NUM 16 282 283 struct amdgpu_ip_block_status { 284 bool valid; 285 bool sw; 286 bool hw; 287 bool late_initialized; 288 bool hang; 289 }; 290 291 struct amdgpu_ip_block_version { 292 const enum amd_ip_block_type type; 293 const u32 major; 294 const u32 minor; 295 const u32 rev; 296 const struct amd_ip_funcs *funcs; 297 }; 298 299 #define HW_REV(_Major, _Minor, _Rev) \ 300 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 301 302 struct amdgpu_ip_block { 303 struct amdgpu_ip_block_status status; 304 const struct amdgpu_ip_block_version *version; 305 }; 306 307 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 308 enum amd_ip_block_type type, 309 u32 major, u32 minor); 310 311 struct amdgpu_ip_block * 312 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 313 enum amd_ip_block_type type); 314 315 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 316 const struct amdgpu_ip_block_version *ip_block_version); 317 318 /* 319 * BIOS. 320 */ 321 bool amdgpu_get_bios(struct amdgpu_device *adev); 322 bool amdgpu_read_bios(struct amdgpu_device *adev); 323 324 /* 325 * Clocks 326 */ 327 328 #define AMDGPU_MAX_PPLL 3 329 330 struct amdgpu_clock { 331 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 332 struct amdgpu_pll spll; 333 struct amdgpu_pll mpll; 334 /* 10 Khz units */ 335 uint32_t default_mclk; 336 uint32_t default_sclk; 337 uint32_t default_dispclk; 338 uint32_t current_dispclk; 339 uint32_t dp_extclk; 340 uint32_t max_pixel_clock; 341 }; 342 343 /* sub-allocation manager, it has to be protected by another lock. 344 * By conception this is an helper for other part of the driver 345 * like the indirect buffer or semaphore, which both have their 346 * locking. 347 * 348 * Principe is simple, we keep a list of sub allocation in offset 349 * order (first entry has offset == 0, last entry has the highest 350 * offset). 351 * 352 * When allocating new object we first check if there is room at 353 * the end total_size - (last_object_offset + last_object_size) >= 354 * alloc_size. If so we allocate new object there. 355 * 356 * When there is not enough room at the end, we start waiting for 357 * each sub object until we reach object_offset+object_size >= 358 * alloc_size, this object then become the sub object we return. 359 * 360 * Alignment can't be bigger than page size. 361 * 362 * Hole are not considered for allocation to keep things simple. 363 * Assumption is that there won't be hole (all object on same 364 * alignment). 365 */ 366 367 #define AMDGPU_SA_NUM_FENCE_LISTS 32 368 369 struct amdgpu_sa_manager { 370 wait_queue_head_t wq; 371 struct amdgpu_bo *bo; 372 struct list_head *hole; 373 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 374 struct list_head olist; 375 unsigned size; 376 uint64_t gpu_addr; 377 void *cpu_ptr; 378 uint32_t domain; 379 uint32_t align; 380 }; 381 382 /* sub-allocation buffer */ 383 struct amdgpu_sa_bo { 384 struct list_head olist; 385 struct list_head flist; 386 struct amdgpu_sa_manager *manager; 387 unsigned soffset; 388 unsigned eoffset; 389 struct dma_fence *fence; 390 }; 391 392 int amdgpu_fence_slab_init(void); 393 void amdgpu_fence_slab_fini(void); 394 395 /* 396 * IRQS. 397 */ 398 399 struct amdgpu_flip_work { 400 struct delayed_work flip_work; 401 struct work_struct unpin_work; 402 struct amdgpu_device *adev; 403 int crtc_id; 404 u32 target_vblank; 405 uint64_t base; 406 struct drm_pending_vblank_event *event; 407 struct amdgpu_bo *old_abo; 408 struct dma_fence *excl; 409 unsigned shared_count; 410 struct dma_fence **shared; 411 struct dma_fence_cb cb; 412 bool async; 413 }; 414 415 416 /* 417 * CP & rings. 418 */ 419 420 struct amdgpu_ib { 421 struct amdgpu_sa_bo *sa_bo; 422 uint32_t length_dw; 423 uint64_t gpu_addr; 424 uint32_t *ptr; 425 uint32_t flags; 426 }; 427 428 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 429 430 /* 431 * file private structure 432 */ 433 434 struct amdgpu_fpriv { 435 struct amdgpu_vm vm; 436 struct amdgpu_bo_va *prt_va; 437 struct amdgpu_bo_va *csa_va; 438 struct rwlock bo_list_lock; 439 struct idr bo_list_handles; 440 struct amdgpu_ctx_mgr ctx_mgr; 441 }; 442 443 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 444 445 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 446 unsigned size, struct amdgpu_ib *ib); 447 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 448 struct dma_fence *f); 449 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 450 struct amdgpu_ib *ibs, struct amdgpu_job *job, 451 struct dma_fence **f); 452 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 453 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 454 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 455 456 /* 457 * CS. 458 */ 459 struct amdgpu_cs_chunk { 460 uint32_t chunk_id; 461 uint32_t length_dw; 462 void *kdata; 463 }; 464 465 struct amdgpu_cs_post_dep { 466 struct drm_syncobj *syncobj; 467 struct dma_fence_chain *chain; 468 u64 point; 469 }; 470 471 struct amdgpu_cs_parser { 472 struct amdgpu_device *adev; 473 struct drm_file *filp; 474 struct amdgpu_ctx *ctx; 475 476 /* chunks */ 477 unsigned nchunks; 478 struct amdgpu_cs_chunk *chunks; 479 480 /* scheduler job object */ 481 struct amdgpu_job *job; 482 struct drm_sched_entity *entity; 483 484 /* buffer objects */ 485 struct ww_acquire_ctx ticket; 486 struct amdgpu_bo_list *bo_list; 487 struct amdgpu_mn *mn; 488 struct amdgpu_bo_list_entry vm_pd; 489 struct list_head validated; 490 struct dma_fence *fence; 491 uint64_t bytes_moved_threshold; 492 uint64_t bytes_moved_vis_threshold; 493 uint64_t bytes_moved; 494 uint64_t bytes_moved_vis; 495 496 /* user fence */ 497 struct amdgpu_bo_list_entry uf_entry; 498 499 unsigned num_post_deps; 500 struct amdgpu_cs_post_dep *post_deps; 501 }; 502 503 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 504 uint32_t ib_idx, int idx) 505 { 506 return p->job->ibs[ib_idx].ptr[idx]; 507 } 508 509 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 510 uint32_t ib_idx, int idx, 511 uint32_t value) 512 { 513 p->job->ibs[ib_idx].ptr[idx] = value; 514 } 515 516 /* 517 * Writeback 518 */ 519 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ 520 521 struct amdgpu_wb { 522 struct amdgpu_bo *wb_obj; 523 volatile uint32_t *wb; 524 uint64_t gpu_addr; 525 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 526 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 527 }; 528 529 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 530 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 531 532 /* 533 * Benchmarking 534 */ 535 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 536 537 538 /* 539 * Testing 540 */ 541 void amdgpu_test_moves(struct amdgpu_device *adev); 542 543 /* 544 * ASIC specific register table accessible by UMD 545 */ 546 struct amdgpu_allowed_register_entry { 547 uint32_t reg_offset; 548 bool grbm_indexed; 549 }; 550 551 enum amd_reset_method { 552 AMD_RESET_METHOD_LEGACY = 0, 553 AMD_RESET_METHOD_MODE0, 554 AMD_RESET_METHOD_MODE1, 555 AMD_RESET_METHOD_MODE2, 556 AMD_RESET_METHOD_BACO 557 }; 558 559 /* 560 * ASIC specific functions. 561 */ 562 struct amdgpu_asic_funcs { 563 bool (*read_disabled_bios)(struct amdgpu_device *adev); 564 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 565 u8 *bios, u32 length_bytes); 566 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 567 u32 sh_num, u32 reg_offset, u32 *value); 568 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 569 int (*reset)(struct amdgpu_device *adev); 570 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 571 /* get the reference clock */ 572 u32 (*get_xclk)(struct amdgpu_device *adev); 573 /* MM block clocks */ 574 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 575 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 576 /* static power management */ 577 int (*get_pcie_lanes)(struct amdgpu_device *adev); 578 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 579 /* get config memsize register */ 580 u32 (*get_config_memsize)(struct amdgpu_device *adev); 581 /* flush hdp write queue */ 582 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 583 /* invalidate hdp read cache */ 584 void (*invalidate_hdp)(struct amdgpu_device *adev, 585 struct amdgpu_ring *ring); 586 void (*reset_hdp_ras_error_count)(struct amdgpu_device *adev); 587 /* check if the asic needs a full reset of if soft reset will work */ 588 bool (*need_full_reset)(struct amdgpu_device *adev); 589 /* initialize doorbell layout for specific asic*/ 590 void (*init_doorbell_index)(struct amdgpu_device *adev); 591 /* PCIe bandwidth usage */ 592 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 593 uint64_t *count1); 594 /* do we need to reset the asic at init time (e.g., kexec) */ 595 bool (*need_reset_on_init)(struct amdgpu_device *adev); 596 /* PCIe replay counter */ 597 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 598 /* device supports BACO */ 599 bool (*supports_baco)(struct amdgpu_device *adev); 600 }; 601 602 /* 603 * IOCTL. 604 */ 605 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 606 struct drm_file *filp); 607 608 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 609 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 610 struct drm_file *filp); 611 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 612 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 613 struct drm_file *filp); 614 615 /* VRAM scratch page for HDP bug, default vram page */ 616 struct amdgpu_vram_scratch { 617 struct amdgpu_bo *robj; 618 volatile uint32_t *ptr; 619 u64 gpu_addr; 620 }; 621 622 /* 623 * ACPI 624 */ 625 struct amdgpu_atcs_functions { 626 bool get_ext_state; 627 bool pcie_perf_req; 628 bool pcie_dev_rdy; 629 bool pcie_bus_width; 630 }; 631 632 struct amdgpu_atcs { 633 struct amdgpu_atcs_functions functions; 634 }; 635 636 /* 637 * Firmware VRAM reservation 638 */ 639 struct amdgpu_fw_vram_usage { 640 u64 start_offset; 641 u64 size; 642 struct amdgpu_bo *reserved_bo; 643 void *va; 644 645 /* GDDR6 training support flag. 646 */ 647 bool mem_train_support; 648 }; 649 650 /* 651 * CGS 652 */ 653 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 654 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 655 656 /* 657 * Core structure, functions and helpers. 658 */ 659 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 660 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 661 662 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 663 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 664 665 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 666 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 667 668 struct amdgpu_mmio_remap { 669 u32 reg_offset; 670 resource_size_t bus_addr; 671 }; 672 673 /* Define the HW IP blocks will be used in driver , add more if necessary */ 674 enum amd_hw_ip_block_type { 675 GC_HWIP = 1, 676 HDP_HWIP, 677 SDMA0_HWIP, 678 SDMA1_HWIP, 679 SDMA2_HWIP, 680 SDMA3_HWIP, 681 SDMA4_HWIP, 682 SDMA5_HWIP, 683 SDMA6_HWIP, 684 SDMA7_HWIP, 685 MMHUB_HWIP, 686 ATHUB_HWIP, 687 NBIO_HWIP, 688 MP0_HWIP, 689 MP1_HWIP, 690 UVD_HWIP, 691 VCN_HWIP = UVD_HWIP, 692 JPEG_HWIP = VCN_HWIP, 693 VCE_HWIP, 694 DF_HWIP, 695 DCE_HWIP, 696 OSSSYS_HWIP, 697 SMUIO_HWIP, 698 PWR_HWIP, 699 NBIF_HWIP, 700 THM_HWIP, 701 CLK_HWIP, 702 UMC_HWIP, 703 RSMU_HWIP, 704 MAX_HWIP 705 }; 706 707 #define HWIP_MAX_INSTANCE 8 708 709 struct amd_powerplay { 710 void *pp_handle; 711 const struct amd_pm_funcs *pp_funcs; 712 }; 713 714 #define AMDGPU_RESET_MAGIC_NUM 64 715 #define AMDGPU_MAX_DF_PERFMONS 4 716 struct amdgpu_device { 717 struct device self; 718 struct device *dev; 719 struct drm_device *ddev; 720 struct pci_dev *pdev; 721 722 #ifdef CONFIG_DRM_AMD_ACP 723 struct amdgpu_acp acp; 724 #endif 725 726 pci_chipset_tag_t pc; 727 pcitag_t pa_tag; 728 pci_intr_handle_t intrh; 729 bus_space_tag_t iot; 730 bus_space_tag_t memt; 731 bus_dma_tag_t dmat; 732 void *irqh; 733 734 void (*switchcb)(void *, int, int); 735 void *switchcbarg; 736 void *switchcookie; 737 struct task switchtask; 738 struct rasops_info ro; 739 int console; 740 int primary; 741 742 struct task burner_task; 743 int burner_fblank; 744 745 unsigned long fb_aper_offset; 746 unsigned long fb_aper_size; 747 748 /* ASIC */ 749 enum amd_asic_type asic_type; 750 uint32_t family; 751 uint32_t rev_id; 752 uint32_t external_rev_id; 753 unsigned long flags; 754 int usec_timeout; 755 const struct amdgpu_asic_funcs *asic_funcs; 756 bool shutdown; 757 bool need_swiotlb; 758 bool accel_working; 759 struct notifier_block acpi_nb; 760 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 761 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 762 unsigned debugfs_count; 763 #if defined(CONFIG_DEBUG_FS) 764 struct dentry *debugfs_preempt; 765 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 766 #endif 767 struct amdgpu_atif *atif; 768 struct amdgpu_atcs atcs; 769 struct rwlock srbm_mutex; 770 /* GRBM index mutex. Protects concurrent access to GRBM index */ 771 struct rwlock grbm_idx_mutex; 772 struct dev_pm_domain vga_pm_domain; 773 bool have_disp_power_ref; 774 bool have_atomics_support; 775 776 /* BIOS */ 777 bool is_atom_fw; 778 uint8_t *bios; 779 uint32_t bios_size; 780 struct amdgpu_bo *stolen_vga_memory; 781 struct amdgpu_bo *discovery_memory; 782 uint32_t bios_scratch_reg_offset; 783 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 784 785 /* Register/doorbell mmio */ 786 resource_size_t rmmio_base; 787 resource_size_t rmmio_size; 788 #ifdef __linux__ 789 void __iomem *rmmio; 790 #endif 791 bus_space_tag_t rmmio_bst; 792 bus_space_handle_t rmmio_bsh; 793 /* protects concurrent MM_INDEX/DATA based register access */ 794 spinlock_t mmio_idx_lock; 795 struct amdgpu_mmio_remap rmmio_remap; 796 /* protects concurrent SMC based register access */ 797 spinlock_t smc_idx_lock; 798 amdgpu_rreg_t smc_rreg; 799 amdgpu_wreg_t smc_wreg; 800 /* protects concurrent PCIE register access */ 801 spinlock_t pcie_idx_lock; 802 amdgpu_rreg_t pcie_rreg; 803 amdgpu_wreg_t pcie_wreg; 804 amdgpu_rreg_t pciep_rreg; 805 amdgpu_wreg_t pciep_wreg; 806 amdgpu_rreg64_t pcie_rreg64; 807 amdgpu_wreg64_t pcie_wreg64; 808 /* protects concurrent UVD register access */ 809 spinlock_t uvd_ctx_idx_lock; 810 amdgpu_rreg_t uvd_ctx_rreg; 811 amdgpu_wreg_t uvd_ctx_wreg; 812 /* protects concurrent DIDT register access */ 813 spinlock_t didt_idx_lock; 814 amdgpu_rreg_t didt_rreg; 815 amdgpu_wreg_t didt_wreg; 816 /* protects concurrent gc_cac register access */ 817 spinlock_t gc_cac_idx_lock; 818 amdgpu_rreg_t gc_cac_rreg; 819 amdgpu_wreg_t gc_cac_wreg; 820 /* protects concurrent se_cac register access */ 821 spinlock_t se_cac_idx_lock; 822 amdgpu_rreg_t se_cac_rreg; 823 amdgpu_wreg_t se_cac_wreg; 824 /* protects concurrent ENDPOINT (audio) register access */ 825 spinlock_t audio_endpt_idx_lock; 826 amdgpu_block_rreg_t audio_endpt_rreg; 827 amdgpu_block_wreg_t audio_endpt_wreg; 828 #ifdef notyet 829 void __iomem *rio_mem; 830 #endif 831 bus_space_tag_t rio_mem_bst; 832 bus_space_handle_t rio_mem_bsh; 833 resource_size_t rio_mem_size; 834 struct amdgpu_doorbell doorbell; 835 836 /* clock/pll info */ 837 struct amdgpu_clock clock; 838 839 /* MC */ 840 struct amdgpu_gmc gmc; 841 struct amdgpu_gart gart; 842 dma_addr_t dummy_page_addr; 843 struct amdgpu_vm_manager vm_manager; 844 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 845 unsigned num_vmhubs; 846 847 /* memory management */ 848 struct amdgpu_mman mman; 849 struct amdgpu_vram_scratch vram_scratch; 850 struct amdgpu_wb wb; 851 atomic64_t num_bytes_moved; 852 atomic64_t num_evictions; 853 atomic64_t num_vram_cpu_page_faults; 854 atomic_t gpu_reset_counter; 855 atomic_t vram_lost_counter; 856 857 /* data for buffer migration throttling */ 858 struct { 859 spinlock_t lock; 860 s64 last_update_us; 861 s64 accum_us; /* accumulated microseconds */ 862 s64 accum_us_vis; /* for visible VRAM */ 863 u32 log2_max_MBps; 864 } mm_stats; 865 866 /* display */ 867 bool enable_virtual_display; 868 struct amdgpu_mode_info mode_info; 869 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 870 struct work_struct hotplug_work; 871 struct amdgpu_irq_src crtc_irq; 872 struct amdgpu_irq_src vupdate_irq; 873 struct amdgpu_irq_src pageflip_irq; 874 struct amdgpu_irq_src hpd_irq; 875 876 /* rings */ 877 u64 fence_context; 878 unsigned num_rings; 879 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 880 bool ib_pool_ready; 881 struct amdgpu_sa_manager ring_tmp_bo; 882 883 /* interrupts */ 884 struct amdgpu_irq irq; 885 886 /* powerplay */ 887 struct amd_powerplay powerplay; 888 bool pp_force_state_enabled; 889 890 /* smu */ 891 struct smu_context smu; 892 893 /* dpm */ 894 struct amdgpu_pm pm; 895 u32 cg_flags; 896 u32 pg_flags; 897 898 /* nbio */ 899 struct amdgpu_nbio nbio; 900 901 /* mmhub */ 902 struct amdgpu_mmhub mmhub; 903 904 /* gfx */ 905 struct amdgpu_gfx gfx; 906 907 /* sdma */ 908 struct amdgpu_sdma sdma; 909 910 /* uvd */ 911 struct amdgpu_uvd uvd; 912 913 /* vce */ 914 struct amdgpu_vce vce; 915 916 /* vcn */ 917 struct amdgpu_vcn vcn; 918 919 /* jpeg */ 920 struct amdgpu_jpeg jpeg; 921 922 /* firmwares */ 923 struct amdgpu_firmware firmware; 924 925 /* PSP */ 926 struct psp_context psp; 927 928 /* GDS */ 929 struct amdgpu_gds gds; 930 931 /* KFD */ 932 struct amdgpu_kfd_dev kfd; 933 934 /* UMC */ 935 struct amdgpu_umc umc; 936 937 /* display related functionality */ 938 struct amdgpu_display_manager dm; 939 940 /* discovery */ 941 uint8_t *discovery; 942 943 /* mes */ 944 bool enable_mes; 945 struct amdgpu_mes mes; 946 947 /* df */ 948 struct amdgpu_df df; 949 950 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 951 int num_ip_blocks; 952 struct rwlock mn_lock; 953 DECLARE_HASHTABLE(mn_hash, 7); 954 955 /* tracking pinned memory */ 956 atomic64_t vram_pin_size; 957 atomic64_t visible_pin_size; 958 atomic64_t gart_pin_size; 959 960 /* soc15 register offset based on ip, instance and segment */ 961 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 962 963 /* delayed work_func for deferring clockgating during resume */ 964 struct delayed_work delayed_init_work; 965 966 struct amdgpu_virt virt; 967 /* firmware VRAM reservation */ 968 struct amdgpu_fw_vram_usage fw_vram_usage; 969 970 /* link all shadow bo */ 971 struct list_head shadow_list; 972 struct rwlock shadow_list_lock; 973 /* keep an lru list of rings by HW IP */ 974 struct list_head ring_lru_list; 975 spinlock_t ring_lru_list_lock; 976 977 /* record hw reset is performed */ 978 bool has_hw_reset; 979 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 980 981 /* s3/s4 mask */ 982 bool in_suspend; 983 bool in_hibernate; 984 985 /* record last mm index being written through WREG32*/ 986 unsigned long last_mm_index; 987 bool in_gpu_reset; 988 enum pp_mp1_state mp1_state; 989 struct rwlock lock_reset; 990 struct amdgpu_doorbell_index doorbell_index; 991 992 struct rwlock notifier_lock; 993 994 int asic_reset_res; 995 struct work_struct xgmi_reset_work; 996 997 long gfx_timeout; 998 long sdma_timeout; 999 long video_timeout; 1000 long compute_timeout; 1001 1002 uint64_t unique_id; 1003 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1004 1005 /* device pstate */ 1006 int pstate; 1007 /* enable runtime pm on the device */ 1008 bool runpm; 1009 bool in_runpm; 1010 1011 bool pm_sysfs_en; 1012 bool ucode_sysfs_en; 1013 }; 1014 1015 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1016 { 1017 return container_of(bdev, struct amdgpu_device, mman.bdev); 1018 } 1019 1020 int amdgpu_device_init(struct amdgpu_device *adev, 1021 struct drm_device *ddev, 1022 struct pci_dev *pdev, 1023 uint32_t flags); 1024 void amdgpu_device_fini(struct amdgpu_device *adev); 1025 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1026 1027 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1028 uint32_t *buf, size_t size, bool write); 1029 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 1030 uint32_t acc_flags); 1031 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1032 uint32_t acc_flags); 1033 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1034 uint32_t acc_flags); 1035 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1036 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1037 1038 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1039 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1040 1041 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1042 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1043 1044 int emu_soc_asic_init(struct amdgpu_device *adev); 1045 1046 /* 1047 * Registers read & write functions. 1048 */ 1049 1050 #define AMDGPU_REGS_IDX (1<<0) 1051 #define AMDGPU_REGS_NO_KIQ (1<<1) 1052 #define AMDGPU_REGS_KIQ (1<<2) 1053 1054 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1055 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1056 1057 #define RREG32_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_KIQ) 1058 #define WREG32_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_KIQ) 1059 1060 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1061 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1062 1063 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1064 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 1065 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1066 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1067 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 1068 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1069 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1070 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1071 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1072 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1073 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1074 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1075 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1076 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1077 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1078 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1079 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1080 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1081 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1082 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1083 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1084 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1085 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1086 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1087 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1088 #define WREG32_P(reg, val, mask) \ 1089 do { \ 1090 uint32_t tmp_ = RREG32(reg); \ 1091 tmp_ &= (mask); \ 1092 tmp_ |= ((val) & ~(mask)); \ 1093 WREG32(reg, tmp_); \ 1094 } while (0) 1095 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1096 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1097 #define WREG32_PLL_P(reg, val, mask) \ 1098 do { \ 1099 uint32_t tmp_ = RREG32_PLL(reg); \ 1100 tmp_ &= (mask); \ 1101 tmp_ |= ((val) & ~(mask)); \ 1102 WREG32_PLL(reg, tmp_); \ 1103 } while (0) 1104 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1105 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1106 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1107 1108 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1109 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1110 1111 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1112 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1113 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1114 1115 #define REG_GET_FIELD(value, reg, field) \ 1116 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1117 1118 #define WREG32_FIELD(reg, field, val) \ 1119 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1120 1121 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1122 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1123 1124 /* 1125 * BIOS helpers. 1126 */ 1127 #define RBIOS8(i) (adev->bios[i]) 1128 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1129 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1130 1131 /* 1132 * ASICs macro. 1133 */ 1134 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1135 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1136 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1137 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1138 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1139 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1140 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1141 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1142 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1143 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1144 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1145 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1146 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1147 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1148 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1149 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1150 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1151 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1152 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1153 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1154 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1155 1156 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1157 1158 /* Common functions */ 1159 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1160 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1161 struct amdgpu_job* job); 1162 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1163 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1164 1165 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1166 u64 num_vis_bytes); 1167 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1168 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1169 const u32 *registers, 1170 const u32 array_size); 1171 1172 bool amdgpu_device_supports_boco(struct drm_device *dev); 1173 bool amdgpu_device_supports_baco(struct drm_device *dev); 1174 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1175 struct amdgpu_device *peer_adev); 1176 int amdgpu_device_baco_enter(struct drm_device *dev); 1177 int amdgpu_device_baco_exit(struct drm_device *dev); 1178 1179 /* atpx handler */ 1180 #if defined(CONFIG_VGA_SWITCHEROO) 1181 void amdgpu_register_atpx_handler(void); 1182 void amdgpu_unregister_atpx_handler(void); 1183 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1184 bool amdgpu_is_atpx_hybrid(void); 1185 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1186 bool amdgpu_has_atpx(void); 1187 #else 1188 static inline void amdgpu_register_atpx_handler(void) {} 1189 static inline void amdgpu_unregister_atpx_handler(void) {} 1190 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1191 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1192 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1193 static inline bool amdgpu_has_atpx(void) { return false; } 1194 #endif 1195 1196 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1197 void *amdgpu_atpx_get_dhandle(void); 1198 #else 1199 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1200 #endif 1201 1202 /* 1203 * KMS 1204 */ 1205 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1206 extern const int amdgpu_max_kms_ioctl; 1207 1208 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1209 void amdgpu_driver_unload_kms(struct drm_device *dev); 1210 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1211 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1212 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1213 struct drm_file *file_priv); 1214 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1215 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1216 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1217 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1218 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1219 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1220 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1221 unsigned long arg); 1222 1223 /* 1224 * functions used by amdgpu_encoder.c 1225 */ 1226 struct amdgpu_afmt_acr { 1227 u32 clock; 1228 1229 int n_32khz; 1230 int cts_32khz; 1231 1232 int n_44_1khz; 1233 int cts_44_1khz; 1234 1235 int n_48khz; 1236 int cts_48khz; 1237 1238 }; 1239 1240 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1241 1242 /* amdgpu_acpi.c */ 1243 #if defined(CONFIG_ACPI) 1244 int amdgpu_acpi_init(struct amdgpu_device *adev); 1245 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1246 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1247 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1248 u8 perf_req, bool advertise); 1249 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1250 1251 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1252 struct amdgpu_dm_backlight_caps *caps); 1253 #else 1254 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1255 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1256 #endif 1257 1258 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1259 uint64_t addr, struct amdgpu_bo **bo, 1260 struct amdgpu_bo_va_mapping **mapping); 1261 1262 #if defined(CONFIG_DRM_AMD_DC) 1263 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1264 #else 1265 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1266 #endif 1267 1268 1269 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1270 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1271 1272 #include "amdgpu_object.h" 1273 1274 /* used by df_v3_6.c and amdgpu_pmu.c */ 1275 #define AMDGPU_PMU_ATTR(_name, _object) \ 1276 static ssize_t \ 1277 _name##_show(struct device *dev, \ 1278 struct device_attribute *attr, \ 1279 char *page) \ 1280 { \ 1281 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \ 1282 return sprintf(page, _object "\n"); \ 1283 } \ 1284 \ 1285 static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name) 1286 1287 #endif 1288 1289