11bb76ff1Sjsg /* 21bb76ff1Sjsg * Copyright 2022 Advanced Micro Devices, Inc. 31bb76ff1Sjsg * 41bb76ff1Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 51bb76ff1Sjsg * copy of this software and associated documentation files (the "Software"), 61bb76ff1Sjsg * to deal in the Software without restriction, including without limitation 71bb76ff1Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 81bb76ff1Sjsg * and/or sell copies of the Software, and to permit persons to whom the 91bb76ff1Sjsg * Software is furnished to do so, subject to the following conditions: 101bb76ff1Sjsg * 111bb76ff1Sjsg * The above copyright notice and this permission notice shall be included in 121bb76ff1Sjsg * all copies or substantial portions of the Software. 131bb76ff1Sjsg * 141bb76ff1Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 151bb76ff1Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 161bb76ff1Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 171bb76ff1Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 181bb76ff1Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 191bb76ff1Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 201bb76ff1Sjsg * OTHER DEALINGS IN THE SOFTWARE. 211bb76ff1Sjsg * 221bb76ff1Sjsg */ 231bb76ff1Sjsg #ifndef __AMDGPU_CS_H__ 241bb76ff1Sjsg #define __AMDGPU_CS_H__ 251bb76ff1Sjsg 26*f005ef32Sjsg #include <linux/ww_mutex.h> 27*f005ef32Sjsg #include <drm/drm_exec.h> 28*f005ef32Sjsg 291bb76ff1Sjsg #include "amdgpu_job.h" 301bb76ff1Sjsg #include "amdgpu_bo_list.h" 311bb76ff1Sjsg #include "amdgpu_ring.h" 321bb76ff1Sjsg 331bb76ff1Sjsg #define AMDGPU_CS_GANG_SIZE 4 341bb76ff1Sjsg 351bb76ff1Sjsg struct amdgpu_bo_va_mapping; 361bb76ff1Sjsg 371bb76ff1Sjsg struct amdgpu_cs_chunk { 381bb76ff1Sjsg uint32_t chunk_id; 391bb76ff1Sjsg uint32_t length_dw; 401bb76ff1Sjsg void *kdata; 411bb76ff1Sjsg }; 421bb76ff1Sjsg 431bb76ff1Sjsg struct amdgpu_cs_post_dep { 441bb76ff1Sjsg struct drm_syncobj *syncobj; 451bb76ff1Sjsg struct dma_fence_chain *chain; 461bb76ff1Sjsg u64 point; 471bb76ff1Sjsg }; 481bb76ff1Sjsg 491bb76ff1Sjsg struct amdgpu_cs_parser { 501bb76ff1Sjsg struct amdgpu_device *adev; 511bb76ff1Sjsg struct drm_file *filp; 521bb76ff1Sjsg struct amdgpu_ctx *ctx; 531bb76ff1Sjsg 541bb76ff1Sjsg /* chunks */ 551bb76ff1Sjsg unsigned nchunks; 561bb76ff1Sjsg struct amdgpu_cs_chunk *chunks; 571bb76ff1Sjsg 581bb76ff1Sjsg /* scheduler job objects */ 591bb76ff1Sjsg unsigned int gang_size; 601bb76ff1Sjsg unsigned int gang_leader_idx; 611bb76ff1Sjsg struct drm_sched_entity *entities[AMDGPU_CS_GANG_SIZE]; 621bb76ff1Sjsg struct amdgpu_job *jobs[AMDGPU_CS_GANG_SIZE]; 631bb76ff1Sjsg struct amdgpu_job *gang_leader; 641bb76ff1Sjsg 651bb76ff1Sjsg /* buffer objects */ 66*f005ef32Sjsg struct drm_exec exec; 671bb76ff1Sjsg struct amdgpu_bo_list *bo_list; 681bb76ff1Sjsg struct amdgpu_mn *mn; 691bb76ff1Sjsg struct dma_fence *fence; 701bb76ff1Sjsg uint64_t bytes_moved_threshold; 711bb76ff1Sjsg uint64_t bytes_moved_vis_threshold; 721bb76ff1Sjsg uint64_t bytes_moved; 731bb76ff1Sjsg uint64_t bytes_moved_vis; 741bb76ff1Sjsg 751bb76ff1Sjsg /* user fence */ 76*f005ef32Sjsg struct amdgpu_bo *uf_bo; 771bb76ff1Sjsg 781bb76ff1Sjsg unsigned num_post_deps; 791bb76ff1Sjsg struct amdgpu_cs_post_dep *post_deps; 80*f005ef32Sjsg 81*f005ef32Sjsg struct amdgpu_sync sync; 821bb76ff1Sjsg }; 831bb76ff1Sjsg 841bb76ff1Sjsg int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 851bb76ff1Sjsg uint64_t addr, struct amdgpu_bo **bo, 861bb76ff1Sjsg struct amdgpu_bo_va_mapping **mapping); 871bb76ff1Sjsg 881bb76ff1Sjsg #endif 89