1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 /* 25 * GPU doorbell structures, functions & helpers 26 */ 27 struct amdgpu_doorbell { 28 /* doorbell mmio */ 29 resource_size_t base; 30 resource_size_t size; 31 u32 __iomem *ptr; 32 bus_space_tag_t bst; 33 bus_space_handle_t bsh; 34 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 35 }; 36 37 /* Reserved doorbells for amdgpu (including multimedia). 38 * KFD can use all the rest in the 2M doorbell bar. 39 * For asic before vega10, doorbell is 32-bit, so the 40 * index/offset is in dword. For vega10 and after, doorbell 41 * can be 64-bit, so the index defined is in qword. 42 */ 43 struct amdgpu_doorbell_index { 44 uint32_t kiq; 45 uint32_t mec_ring0; 46 uint32_t mec_ring1; 47 uint32_t mec_ring2; 48 uint32_t mec_ring3; 49 uint32_t mec_ring4; 50 uint32_t mec_ring5; 51 uint32_t mec_ring6; 52 uint32_t mec_ring7; 53 uint32_t userqueue_start; 54 uint32_t userqueue_end; 55 uint32_t gfx_ring0; 56 uint32_t gfx_ring1; 57 uint32_t sdma_engine[8]; 58 uint32_t mes_ring; 59 uint32_t ih; 60 union { 61 struct { 62 uint32_t vcn_ring0_1; 63 uint32_t vcn_ring2_3; 64 uint32_t vcn_ring4_5; 65 uint32_t vcn_ring6_7; 66 } vcn; 67 struct { 68 uint32_t uvd_ring0_1; 69 uint32_t uvd_ring2_3; 70 uint32_t uvd_ring4_5; 71 uint32_t uvd_ring6_7; 72 uint32_t vce_ring0_1; 73 uint32_t vce_ring2_3; 74 uint32_t vce_ring4_5; 75 uint32_t vce_ring6_7; 76 } uvd_vce; 77 }; 78 uint32_t first_non_cp; 79 uint32_t last_non_cp; 80 uint32_t max_assignment; 81 /* Per engine SDMA doorbell size in dword */ 82 uint32_t sdma_doorbell_range; 83 }; 84 85 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 86 { 87 AMDGPU_DOORBELL_KIQ = 0x000, 88 AMDGPU_DOORBELL_HIQ = 0x001, 89 AMDGPU_DOORBELL_DIQ = 0x002, 90 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 91 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 92 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 93 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 94 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 95 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 96 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 97 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 98 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 99 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 100 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 101 AMDGPU_DOORBELL_IH = 0x1E8, 102 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 103 AMDGPU_DOORBELL_INVALID = 0xFFFF 104 } AMDGPU_DOORBELL_ASSIGNMENT; 105 106 typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT 107 { 108 /* Compute + GFX: 0~255 */ 109 AMDGPU_VEGA20_DOORBELL_KIQ = 0x000, 110 AMDGPU_VEGA20_DOORBELL_HIQ = 0x001, 111 AMDGPU_VEGA20_DOORBELL_DIQ = 0x002, 112 AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 0x003, 113 AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 0x004, 114 AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 0x005, 115 AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 0x006, 116 AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 0x007, 117 AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 0x008, 118 AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 0x009, 119 AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 0x00A, 120 AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 0x00B, 121 AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 0x08A, 122 AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 0x08B, 123 /* SDMA:256~335*/ 124 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 0x100, 125 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = 0x10A, 126 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 0x114, 127 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = 0x11E, 128 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = 0x128, 129 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 0x132, 130 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = 0x13C, 131 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = 0x146, 132 /* IH: 376~391 */ 133 AMDGPU_VEGA20_DOORBELL_IH = 0x178, 134 /* MMSCH: 392~407 135 * overlap the doorbell assignment with VCN as they are mutually exclusive 136 * VCN engine's doorbell is 32 bit and two VCN ring share one QWORD 137 */ 138 AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* VNC0 */ 139 AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 0x189, 140 AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 0x18A, 141 AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 0x18B, 142 143 AMDGPU_VEGA20_DOORBELL64_VCN8_9 = 0x18C, /* VNC1 */ 144 AMDGPU_VEGA20_DOORBELL64_VCNa_b = 0x18D, 145 AMDGPU_VEGA20_DOORBELL64_VCNc_d = 0x18E, 146 AMDGPU_VEGA20_DOORBELL64_VCNe_f = 0x18F, 147 148 AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 0x188, 149 AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 0x189, 150 AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 0x18A, 151 AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 0x18B, 152 153 AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 0x18C, 154 AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D, 155 AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E, 156 AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F, 157 158 AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0, 159 AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7, 160 161 AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x18F, 162 AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF 163 } AMDGPU_VEGA20_DOORBELL_ASSIGNMENT; 164 165 typedef enum _AMDGPU_NAVI10_DOORBELL_ASSIGNMENT 166 { 167 /* Compute + GFX: 0~255 */ 168 AMDGPU_NAVI10_DOORBELL_KIQ = 0x000, 169 AMDGPU_NAVI10_DOORBELL_HIQ = 0x001, 170 AMDGPU_NAVI10_DOORBELL_DIQ = 0x002, 171 AMDGPU_NAVI10_DOORBELL_MEC_RING0 = 0x003, 172 AMDGPU_NAVI10_DOORBELL_MEC_RING1 = 0x004, 173 AMDGPU_NAVI10_DOORBELL_MEC_RING2 = 0x005, 174 AMDGPU_NAVI10_DOORBELL_MEC_RING3 = 0x006, 175 AMDGPU_NAVI10_DOORBELL_MEC_RING4 = 0x007, 176 AMDGPU_NAVI10_DOORBELL_MEC_RING5 = 0x008, 177 AMDGPU_NAVI10_DOORBELL_MEC_RING6 = 0x009, 178 AMDGPU_NAVI10_DOORBELL_MEC_RING7 = 0x00A, 179 AMDGPU_NAVI10_DOORBELL_USERQUEUE_START = 0x00B, 180 AMDGPU_NAVI10_DOORBELL_USERQUEUE_END = 0x08A, 181 AMDGPU_NAVI10_DOORBELL_GFX_RING0 = 0x08B, 182 AMDGPU_NAVI10_DOORBELL_GFX_RING1 = 0x08C, 183 AMDGPU_NAVI10_DOORBELL_MES_RING = 0x090, 184 /* SDMA:256~335*/ 185 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0 = 0x100, 186 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1 = 0x10A, 187 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2 = 0x114, 188 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3 = 0x11E, 189 /* IH: 376~391 */ 190 AMDGPU_NAVI10_DOORBELL_IH = 0x178, 191 /* MMSCH: 392~407 192 * overlap the doorbell assignment with VCN as they are mutually exclusive 193 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 194 */ 195 AMDGPU_NAVI10_DOORBELL64_VCN0_1 = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 196 AMDGPU_NAVI10_DOORBELL64_VCN2_3 = 0x189, 197 AMDGPU_NAVI10_DOORBELL64_VCN4_5 = 0x18A, 198 AMDGPU_NAVI10_DOORBELL64_VCN6_7 = 0x18B, 199 200 AMDGPU_NAVI10_DOORBELL64_VCN8_9 = 0x18C, 201 AMDGPU_NAVI10_DOORBELL64_VCNa_b = 0x18D, 202 AMDGPU_NAVI10_DOORBELL64_VCNc_d = 0x18E, 203 AMDGPU_NAVI10_DOORBELL64_VCNe_f = 0x18F, 204 205 AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0, 206 AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP = AMDGPU_NAVI10_DOORBELL64_VCNe_f, 207 208 AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT = 0x18F, 209 AMDGPU_NAVI10_DOORBELL_INVALID = 0xFFFF 210 } AMDGPU_NAVI10_DOORBELL_ASSIGNMENT; 211 212 /* 213 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 214 */ 215 typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT 216 { 217 /* 218 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in 219 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. 220 * Compute related doorbells are allocated from 0x00 to 0x8a 221 */ 222 223 224 /* kernel scheduling */ 225 AMDGPU_DOORBELL64_KIQ = 0x00, 226 227 /* HSA interface queue and debug queue */ 228 AMDGPU_DOORBELL64_HIQ = 0x01, 229 AMDGPU_DOORBELL64_DIQ = 0x02, 230 231 /* Compute engines */ 232 AMDGPU_DOORBELL64_MEC_RING0 = 0x03, 233 AMDGPU_DOORBELL64_MEC_RING1 = 0x04, 234 AMDGPU_DOORBELL64_MEC_RING2 = 0x05, 235 AMDGPU_DOORBELL64_MEC_RING3 = 0x06, 236 AMDGPU_DOORBELL64_MEC_RING4 = 0x07, 237 AMDGPU_DOORBELL64_MEC_RING5 = 0x08, 238 AMDGPU_DOORBELL64_MEC_RING6 = 0x09, 239 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, 240 241 /* User queue doorbell range (128 doorbells) */ 242 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, 243 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, 244 245 /* Graphics engine */ 246 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 247 248 /* 249 * Other graphics doorbells can be allocated here: from 0x8c to 0xdf 250 * Graphics voltage island aperture 1 251 * default non-graphics QWORD index is 0xe0 - 0xFF inclusive 252 */ 253 254 /* For vega10 sriov, the sdma doorbell must be fixed as follow 255 * to keep the same setting with host driver, or it will 256 * happen conflicts 257 */ 258 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, 259 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 260 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, 261 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, 262 263 /* Interrupt handler */ 264 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 265 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 266 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 267 268 /* VCN engine use 32 bits doorbell */ 269 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 270 AMDGPU_DOORBELL64_VCN2_3 = 0xF9, 271 AMDGPU_DOORBELL64_VCN4_5 = 0xFA, 272 AMDGPU_DOORBELL64_VCN6_7 = 0xFB, 273 274 /* overlap the doorbell assignment with VCN as they are mutually exclusive 275 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 276 */ 277 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, 278 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, 279 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, 280 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, 281 282 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, 283 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, 284 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, 285 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, 286 287 AMDGPU_DOORBELL64_FIRST_NON_CP = AMDGPU_DOORBELL64_sDMA_ENGINE0, 288 AMDGPU_DOORBELL64_LAST_NON_CP = AMDGPU_DOORBELL64_VCE_RING6_7, 289 290 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, 291 AMDGPU_DOORBELL64_INVALID = 0xFFFF 292 } AMDGPU_DOORBELL64_ASSIGNMENT; 293 294 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 295 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 296 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); 297 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 298 299 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 300 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 301 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) 302 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) 303 304