1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 /* 25 * GPU doorbell structures, functions & helpers 26 */ 27 struct amdgpu_doorbell { 28 /* doorbell mmio */ 29 resource_size_t base; 30 resource_size_t size; 31 u32 __iomem *ptr; 32 bus_space_tag_t bst; 33 bus_space_handle_t bsh; 34 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 35 }; 36 37 /* Reserved doorbells for amdgpu (including multimedia). 38 * KFD can use all the rest in the 2M doorbell bar. 39 * For asic before vega10, doorbell is 32-bit, so the 40 * index/offset is in dword. For vega10 and after, doorbell 41 * can be 64-bit, so the index defined is in qword. 42 */ 43 struct amdgpu_doorbell_index { 44 uint32_t kiq; 45 uint32_t mec_ring0; 46 uint32_t mec_ring1; 47 uint32_t mec_ring2; 48 uint32_t mec_ring3; 49 uint32_t mec_ring4; 50 uint32_t mec_ring5; 51 uint32_t mec_ring6; 52 uint32_t mec_ring7; 53 uint32_t userqueue_start; 54 uint32_t userqueue_end; 55 uint32_t gfx_ring0; 56 uint32_t gfx_ring1; 57 uint32_t gfx_userqueue_start; 58 uint32_t gfx_userqueue_end; 59 uint32_t sdma_engine[8]; 60 uint32_t mes_ring0; 61 uint32_t mes_ring1; 62 uint32_t ih; 63 union { 64 struct { 65 uint32_t vcn_ring0_1; 66 uint32_t vcn_ring2_3; 67 uint32_t vcn_ring4_5; 68 uint32_t vcn_ring6_7; 69 } vcn; 70 struct { 71 uint32_t uvd_ring0_1; 72 uint32_t uvd_ring2_3; 73 uint32_t uvd_ring4_5; 74 uint32_t uvd_ring6_7; 75 uint32_t vce_ring0_1; 76 uint32_t vce_ring2_3; 77 uint32_t vce_ring4_5; 78 uint32_t vce_ring6_7; 79 } uvd_vce; 80 }; 81 uint32_t first_non_cp; 82 uint32_t last_non_cp; 83 uint32_t max_assignment; 84 /* Per engine SDMA doorbell size in dword */ 85 uint32_t sdma_doorbell_range; 86 }; 87 88 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 89 { 90 AMDGPU_DOORBELL_KIQ = 0x000, 91 AMDGPU_DOORBELL_HIQ = 0x001, 92 AMDGPU_DOORBELL_DIQ = 0x002, 93 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 94 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 95 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 96 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 97 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 98 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 99 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 100 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 101 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 102 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 103 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 104 AMDGPU_DOORBELL_IH = 0x1E8, 105 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 106 AMDGPU_DOORBELL_INVALID = 0xFFFF 107 } AMDGPU_DOORBELL_ASSIGNMENT; 108 109 typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT 110 { 111 /* Compute + GFX: 0~255 */ 112 AMDGPU_VEGA20_DOORBELL_KIQ = 0x000, 113 AMDGPU_VEGA20_DOORBELL_HIQ = 0x001, 114 AMDGPU_VEGA20_DOORBELL_DIQ = 0x002, 115 AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 0x003, 116 AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 0x004, 117 AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 0x005, 118 AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 0x006, 119 AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 0x007, 120 AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 0x008, 121 AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 0x009, 122 AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 0x00A, 123 AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 0x00B, 124 AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 0x08A, 125 AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 0x08B, 126 /* SDMA:256~335*/ 127 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 0x100, 128 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = 0x10A, 129 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 0x114, 130 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = 0x11E, 131 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = 0x128, 132 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 0x132, 133 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = 0x13C, 134 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = 0x146, 135 /* IH: 376~391 */ 136 AMDGPU_VEGA20_DOORBELL_IH = 0x178, 137 /* MMSCH: 392~407 138 * overlap the doorbell assignment with VCN as they are mutually exclusive 139 * VCN engine's doorbell is 32 bit and two VCN ring share one QWORD 140 */ 141 AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* VNC0 */ 142 AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 0x189, 143 AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 0x18A, 144 AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 0x18B, 145 146 AMDGPU_VEGA20_DOORBELL64_VCN8_9 = 0x18C, /* VNC1 */ 147 AMDGPU_VEGA20_DOORBELL64_VCNa_b = 0x18D, 148 AMDGPU_VEGA20_DOORBELL64_VCNc_d = 0x18E, 149 AMDGPU_VEGA20_DOORBELL64_VCNe_f = 0x18F, 150 151 AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 0x188, 152 AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 0x189, 153 AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 0x18A, 154 AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 0x18B, 155 156 AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 0x18C, 157 AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D, 158 AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E, 159 AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F, 160 161 AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0, 162 AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7, 163 164 AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x18F, 165 AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF 166 } AMDGPU_VEGA20_DOORBELL_ASSIGNMENT; 167 168 typedef enum _AMDGPU_NAVI10_DOORBELL_ASSIGNMENT 169 { 170 /* Compute + GFX: 0~255 */ 171 AMDGPU_NAVI10_DOORBELL_KIQ = 0x000, 172 AMDGPU_NAVI10_DOORBELL_HIQ = 0x001, 173 AMDGPU_NAVI10_DOORBELL_DIQ = 0x002, 174 AMDGPU_NAVI10_DOORBELL_MEC_RING0 = 0x003, 175 AMDGPU_NAVI10_DOORBELL_MEC_RING1 = 0x004, 176 AMDGPU_NAVI10_DOORBELL_MEC_RING2 = 0x005, 177 AMDGPU_NAVI10_DOORBELL_MEC_RING3 = 0x006, 178 AMDGPU_NAVI10_DOORBELL_MEC_RING4 = 0x007, 179 AMDGPU_NAVI10_DOORBELL_MEC_RING5 = 0x008, 180 AMDGPU_NAVI10_DOORBELL_MEC_RING6 = 0x009, 181 AMDGPU_NAVI10_DOORBELL_MEC_RING7 = 0x00A, 182 AMDGPU_NAVI10_DOORBELL_MES_RING0 = 0x00B, 183 AMDGPU_NAVI10_DOORBELL_MES_RING1 = 0x00C, 184 AMDGPU_NAVI10_DOORBELL_USERQUEUE_START = 0x00D, 185 AMDGPU_NAVI10_DOORBELL_USERQUEUE_END = 0x08A, 186 AMDGPU_NAVI10_DOORBELL_GFX_RING0 = 0x08B, 187 AMDGPU_NAVI10_DOORBELL_GFX_RING1 = 0x08C, 188 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START = 0x08D, 189 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END = 0x0FF, 190 191 /* SDMA:256~335*/ 192 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0 = 0x100, 193 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1 = 0x10A, 194 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2 = 0x114, 195 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3 = 0x11E, 196 /* IH: 376~391 */ 197 AMDGPU_NAVI10_DOORBELL_IH = 0x178, 198 /* MMSCH: 392~407 199 * overlap the doorbell assignment with VCN as they are mutually exclusive 200 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 201 */ 202 AMDGPU_NAVI10_DOORBELL64_VCN0_1 = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 203 AMDGPU_NAVI10_DOORBELL64_VCN2_3 = 0x189, 204 AMDGPU_NAVI10_DOORBELL64_VCN4_5 = 0x18A, 205 AMDGPU_NAVI10_DOORBELL64_VCN6_7 = 0x18B, 206 207 AMDGPU_NAVI10_DOORBELL64_VCN8_9 = 0x18C, 208 AMDGPU_NAVI10_DOORBELL64_VCNa_b = 0x18D, 209 AMDGPU_NAVI10_DOORBELL64_VCNc_d = 0x18E, 210 AMDGPU_NAVI10_DOORBELL64_VCNe_f = 0x18F, 211 212 AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0, 213 AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP = AMDGPU_NAVI10_DOORBELL64_VCNe_f, 214 215 AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT = 0x18F, 216 AMDGPU_NAVI10_DOORBELL_INVALID = 0xFFFF 217 } AMDGPU_NAVI10_DOORBELL_ASSIGNMENT; 218 219 /* 220 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 221 */ 222 typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT 223 { 224 /* 225 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in 226 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. 227 * Compute related doorbells are allocated from 0x00 to 0x8a 228 */ 229 230 231 /* kernel scheduling */ 232 AMDGPU_DOORBELL64_KIQ = 0x00, 233 234 /* HSA interface queue and debug queue */ 235 AMDGPU_DOORBELL64_HIQ = 0x01, 236 AMDGPU_DOORBELL64_DIQ = 0x02, 237 238 /* Compute engines */ 239 AMDGPU_DOORBELL64_MEC_RING0 = 0x03, 240 AMDGPU_DOORBELL64_MEC_RING1 = 0x04, 241 AMDGPU_DOORBELL64_MEC_RING2 = 0x05, 242 AMDGPU_DOORBELL64_MEC_RING3 = 0x06, 243 AMDGPU_DOORBELL64_MEC_RING4 = 0x07, 244 AMDGPU_DOORBELL64_MEC_RING5 = 0x08, 245 AMDGPU_DOORBELL64_MEC_RING6 = 0x09, 246 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, 247 248 /* User queue doorbell range (128 doorbells) */ 249 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, 250 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, 251 252 /* Graphics engine */ 253 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 254 255 /* 256 * Other graphics doorbells can be allocated here: from 0x8c to 0xdf 257 * Graphics voltage island aperture 1 258 * default non-graphics QWORD index is 0xe0 - 0xFF inclusive 259 */ 260 261 /* For vega10 sriov, the sdma doorbell must be fixed as follow 262 * to keep the same setting with host driver, or it will 263 * happen conflicts 264 */ 265 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, 266 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 267 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, 268 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, 269 270 /* Interrupt handler */ 271 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 272 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 273 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 274 275 /* VCN engine use 32 bits doorbell */ 276 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 277 AMDGPU_DOORBELL64_VCN2_3 = 0xF9, 278 AMDGPU_DOORBELL64_VCN4_5 = 0xFA, 279 AMDGPU_DOORBELL64_VCN6_7 = 0xFB, 280 281 /* overlap the doorbell assignment with VCN as they are mutually exclusive 282 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 283 */ 284 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, 285 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, 286 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, 287 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, 288 289 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, 290 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, 291 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, 292 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, 293 294 AMDGPU_DOORBELL64_FIRST_NON_CP = AMDGPU_DOORBELL64_sDMA_ENGINE0, 295 AMDGPU_DOORBELL64_LAST_NON_CP = AMDGPU_DOORBELL64_VCE_RING6_7, 296 297 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, 298 AMDGPU_DOORBELL64_INVALID = 0xFFFF 299 } AMDGPU_DOORBELL64_ASSIGNMENT; 300 301 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 302 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 303 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); 304 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 305 306 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 307 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 308 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) 309 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) 310 311