1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/ktime.h> 29 #include <linux/module.h> 30 #include <linux/pagemap.h> 31 #include <linux/pci.h> 32 33 #include <drm/amdgpu_drm.h> 34 #include <drm/drm_debugfs.h> 35 36 #include "amdgpu.h" 37 #include "amdgpu_display.h" 38 #include "amdgpu_xgmi.h" 39 40 void amdgpu_gem_object_free(struct drm_gem_object *gobj) 41 { 42 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); 43 44 if (robj) { 45 amdgpu_mn_unregister(robj); 46 amdgpu_bo_unref(&robj); 47 } 48 } 49 50 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 51 int alignment, u32 initial_domain, 52 u64 flags, enum ttm_bo_type type, 53 struct dma_resv *resv, 54 struct drm_gem_object **obj) 55 { 56 struct amdgpu_bo *bo; 57 struct amdgpu_bo_param bp; 58 int r; 59 60 memset(&bp, 0, sizeof(bp)); 61 *obj = NULL; 62 63 bp.size = size; 64 bp.byte_align = alignment; 65 bp.type = type; 66 bp.resv = resv; 67 bp.preferred_domain = initial_domain; 68 retry: 69 bp.flags = flags; 70 bp.domain = initial_domain; 71 r = amdgpu_bo_create(adev, &bp, &bo); 72 if (r) { 73 if (r != -ERESTARTSYS) { 74 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { 75 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 76 goto retry; 77 } 78 79 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 80 initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 81 goto retry; 82 } 83 DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n", 84 size, initial_domain, alignment, r); 85 } 86 return r; 87 } 88 *obj = &bo->tbo.base; 89 90 return 0; 91 } 92 93 void amdgpu_gem_force_release(struct amdgpu_device *adev) 94 { 95 STUB(); 96 #ifdef notyet 97 struct drm_device *ddev = adev->ddev; 98 struct drm_file *file; 99 100 mutex_lock(&ddev->filelist_mutex); 101 102 list_for_each_entry(file, &ddev->filelist, lhead) { 103 struct drm_gem_object *gobj; 104 int handle; 105 106 WARN_ONCE(1, "Still active user space clients!\n"); 107 spin_lock(&file->table_lock); 108 idr_for_each_entry(&file->object_idr, gobj, handle) { 109 WARN_ONCE(1, "And also active allocations!\n"); 110 drm_gem_object_put_unlocked(gobj); 111 } 112 idr_destroy(&file->object_idr); 113 spin_unlock(&file->table_lock); 114 } 115 116 mutex_unlock(&ddev->filelist_mutex); 117 #endif 118 } 119 120 /* 121 * Call from drm_gem_handle_create which appear in both new and open ioctl 122 * case. 123 */ 124 int amdgpu_gem_object_open(struct drm_gem_object *obj, 125 struct drm_file *file_priv) 126 { 127 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); 128 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 129 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 130 struct amdgpu_vm *vm = &fpriv->vm; 131 struct amdgpu_bo_va *bo_va; 132 #ifdef notyet 133 struct mm_struct *mm; 134 #endif 135 int r; 136 137 #ifdef notyet 138 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); 139 if (mm && mm != current->mm) 140 return -EPERM; 141 #endif 142 143 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && 144 abo->tbo.base.resv != vm->root.base.bo->tbo.base.resv) 145 return -EPERM; 146 147 r = amdgpu_bo_reserve(abo, false); 148 if (r) 149 return r; 150 151 bo_va = amdgpu_vm_bo_find(vm, abo); 152 if (!bo_va) { 153 bo_va = amdgpu_vm_bo_add(adev, vm, abo); 154 } else { 155 ++bo_va->ref_count; 156 } 157 amdgpu_bo_unreserve(abo); 158 return 0; 159 } 160 161 void amdgpu_gem_object_close(struct drm_gem_object *obj, 162 struct drm_file *file_priv) 163 { 164 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 165 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 166 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 167 struct amdgpu_vm *vm = &fpriv->vm; 168 169 struct amdgpu_bo_list_entry vm_pd; 170 struct list_head list, duplicates; 171 struct dma_fence *fence = NULL; 172 struct ttm_validate_buffer tv; 173 struct ww_acquire_ctx ticket; 174 struct amdgpu_bo_va *bo_va; 175 long r; 176 177 INIT_LIST_HEAD(&list); 178 INIT_LIST_HEAD(&duplicates); 179 180 tv.bo = &bo->tbo; 181 tv.num_shared = 2; 182 list_add(&tv.head, &list); 183 184 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); 185 186 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); 187 if (r) { 188 dev_err(adev->dev, "leaking bo va because " 189 "we fail to reserve bo (%ld)\n", r); 190 return; 191 } 192 bo_va = amdgpu_vm_bo_find(vm, bo); 193 if (!bo_va || --bo_va->ref_count) 194 goto out_unlock; 195 196 amdgpu_vm_bo_rmv(adev, bo_va); 197 if (!amdgpu_vm_ready(vm)) 198 goto out_unlock; 199 200 fence = dma_resv_get_excl(bo->tbo.base.resv); 201 if (fence) { 202 amdgpu_bo_fence(bo, fence, true); 203 fence = NULL; 204 } 205 206 r = amdgpu_vm_clear_freed(adev, vm, &fence); 207 if (r || !fence) 208 goto out_unlock; 209 210 amdgpu_bo_fence(bo, fence, true); 211 dma_fence_put(fence); 212 213 out_unlock: 214 if (unlikely(r < 0)) 215 dev_err(adev->dev, "failed to clear page " 216 "tables on GEM object close (%ld)\n", r); 217 ttm_eu_backoff_reservation(&ticket, &list); 218 } 219 220 /* 221 * GEM ioctls. 222 */ 223 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 224 struct drm_file *filp) 225 { 226 struct amdgpu_device *adev = dev->dev_private; 227 struct amdgpu_fpriv *fpriv = filp->driver_priv; 228 struct amdgpu_vm *vm = &fpriv->vm; 229 union drm_amdgpu_gem_create *args = data; 230 uint64_t flags = args->in.domain_flags; 231 uint64_t size = args->in.bo_size; 232 struct dma_resv *resv = NULL; 233 struct drm_gem_object *gobj; 234 uint32_t handle; 235 int r; 236 237 /* reject invalid gem flags */ 238 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 239 AMDGPU_GEM_CREATE_NO_CPU_ACCESS | 240 AMDGPU_GEM_CREATE_CPU_GTT_USWC | 241 AMDGPU_GEM_CREATE_VRAM_CLEARED | 242 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | 243 AMDGPU_GEM_CREATE_EXPLICIT_SYNC)) 244 245 return -EINVAL; 246 247 /* reject invalid gem domains */ 248 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK) 249 return -EINVAL; 250 251 /* create a gem object to contain this object in */ 252 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 253 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 254 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 255 /* if gds bo is created from user space, it must be 256 * passed to bo list 257 */ 258 DRM_ERROR("GDS bo cannot be per-vm-bo\n"); 259 return -EINVAL; 260 } 261 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 262 } 263 264 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 265 r = amdgpu_bo_reserve(vm->root.base.bo, false); 266 if (r) 267 return r; 268 269 resv = vm->root.base.bo->tbo.base.resv; 270 } 271 272 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 273 (u32)(0xffffffff & args->in.domains), 274 flags, ttm_bo_type_device, resv, &gobj); 275 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 276 if (!r) { 277 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); 278 279 abo->parent = amdgpu_bo_ref(vm->root.base.bo); 280 } 281 amdgpu_bo_unreserve(vm->root.base.bo); 282 } 283 if (r) 284 return r; 285 286 r = drm_gem_handle_create(filp, gobj, &handle); 287 /* drop reference from allocate - handle holds it now */ 288 drm_gem_object_put_unlocked(gobj); 289 if (r) 290 return r; 291 292 memset(args, 0, sizeof(*args)); 293 args->out.handle = handle; 294 return 0; 295 } 296 297 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 298 struct drm_file *filp) 299 { 300 return -ENOSYS; 301 #ifdef notyet 302 struct ttm_operation_ctx ctx = { true, false }; 303 struct amdgpu_device *adev = dev->dev_private; 304 struct drm_amdgpu_gem_userptr *args = data; 305 struct drm_gem_object *gobj; 306 struct amdgpu_bo *bo; 307 uint32_t handle; 308 int r; 309 310 args->addr = untagged_addr(args->addr); 311 312 if (offset_in_page(args->addr | args->size)) 313 return -EINVAL; 314 315 /* reject unknown flag values */ 316 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | 317 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | 318 AMDGPU_GEM_USERPTR_REGISTER)) 319 return -EINVAL; 320 321 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && 322 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { 323 324 /* if we want to write to it we must install a MMU notifier */ 325 return -EACCES; 326 } 327 328 /* create a gem object to contain this object in */ 329 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, 330 0, ttm_bo_type_device, NULL, &gobj); 331 if (r) 332 return r; 333 334 bo = gem_to_amdgpu_bo(gobj); 335 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 336 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 337 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); 338 if (r) 339 goto release_object; 340 341 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { 342 r = amdgpu_mn_register(bo, args->addr); 343 if (r) 344 goto release_object; 345 } 346 347 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { 348 r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages); 349 if (r) 350 goto release_object; 351 352 r = amdgpu_bo_reserve(bo, true); 353 if (r) 354 goto user_pages_done; 355 356 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 357 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 358 amdgpu_bo_unreserve(bo); 359 if (r) 360 goto user_pages_done; 361 } 362 363 r = drm_gem_handle_create(filp, gobj, &handle); 364 if (r) 365 goto user_pages_done; 366 367 args->handle = handle; 368 369 user_pages_done: 370 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) 371 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm); 372 373 release_object: 374 drm_gem_object_put_unlocked(gobj); 375 376 return r; 377 #endif 378 } 379 380 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 381 struct drm_device *dev, 382 uint32_t handle, uint64_t *offset_p) 383 { 384 struct drm_gem_object *gobj; 385 struct amdgpu_bo *robj; 386 387 gobj = drm_gem_object_lookup(filp, handle); 388 if (gobj == NULL) { 389 return -ENOENT; 390 } 391 robj = gem_to_amdgpu_bo(gobj); 392 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || 393 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { 394 drm_gem_object_put_unlocked(gobj); 395 return -EPERM; 396 } 397 *offset_p = amdgpu_bo_mmap_offset(robj); 398 drm_gem_object_put_unlocked(gobj); 399 return 0; 400 } 401 402 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 403 struct drm_file *filp) 404 { 405 union drm_amdgpu_gem_mmap *args = data; 406 uint32_t handle = args->in.handle; 407 memset(args, 0, sizeof(*args)); 408 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); 409 } 410 411 /** 412 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value 413 * 414 * @timeout_ns: timeout in ns 415 * 416 * Calculate the timeout in jiffies from an absolute timeout in ns. 417 */ 418 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) 419 { 420 unsigned long timeout_jiffies; 421 ktime_t timeout; 422 423 /* clamp timeout if it's to large */ 424 if (((int64_t)timeout_ns) < 0) 425 return MAX_SCHEDULE_TIMEOUT; 426 427 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); 428 if (ktime_to_ns(timeout) < 0) 429 return 0; 430 431 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); 432 /* clamp timeout to avoid unsigned-> signed overflow */ 433 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) 434 return MAX_SCHEDULE_TIMEOUT - 1; 435 436 return timeout_jiffies; 437 } 438 439 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 440 struct drm_file *filp) 441 { 442 union drm_amdgpu_gem_wait_idle *args = data; 443 struct drm_gem_object *gobj; 444 struct amdgpu_bo *robj; 445 uint32_t handle = args->in.handle; 446 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); 447 int r = 0; 448 long ret; 449 450 gobj = drm_gem_object_lookup(filp, handle); 451 if (gobj == NULL) { 452 return -ENOENT; 453 } 454 robj = gem_to_amdgpu_bo(gobj); 455 ret = dma_resv_wait_timeout_rcu(robj->tbo.base.resv, true, true, 456 timeout); 457 458 /* ret == 0 means not signaled, 459 * ret > 0 means signaled 460 * ret < 0 means interrupted before timeout 461 */ 462 if (ret >= 0) { 463 memset(args, 0, sizeof(*args)); 464 args->out.status = (ret == 0); 465 } else 466 r = ret; 467 468 drm_gem_object_put_unlocked(gobj); 469 return r; 470 } 471 472 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 473 struct drm_file *filp) 474 { 475 struct drm_amdgpu_gem_metadata *args = data; 476 struct drm_gem_object *gobj; 477 struct amdgpu_bo *robj; 478 int r = -1; 479 480 DRM_DEBUG("%d \n", args->handle); 481 gobj = drm_gem_object_lookup(filp, args->handle); 482 if (gobj == NULL) 483 return -ENOENT; 484 robj = gem_to_amdgpu_bo(gobj); 485 486 r = amdgpu_bo_reserve(robj, false); 487 if (unlikely(r != 0)) 488 goto out; 489 490 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { 491 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); 492 r = amdgpu_bo_get_metadata(robj, args->data.data, 493 sizeof(args->data.data), 494 &args->data.data_size_bytes, 495 &args->data.flags); 496 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { 497 if (args->data.data_size_bytes > sizeof(args->data.data)) { 498 r = -EINVAL; 499 goto unreserve; 500 } 501 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); 502 if (!r) 503 r = amdgpu_bo_set_metadata(robj, args->data.data, 504 args->data.data_size_bytes, 505 args->data.flags); 506 } 507 508 unreserve: 509 amdgpu_bo_unreserve(robj); 510 out: 511 drm_gem_object_put_unlocked(gobj); 512 return r; 513 } 514 515 /** 516 * amdgpu_gem_va_update_vm -update the bo_va in its VM 517 * 518 * @adev: amdgpu_device pointer 519 * @vm: vm to update 520 * @bo_va: bo_va to update 521 * @operation: map, unmap or clear 522 * 523 * Update the bo_va directly after setting its address. Errors are not 524 * vital here, so they are not reported back to userspace. 525 */ 526 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 527 struct amdgpu_vm *vm, 528 struct amdgpu_bo_va *bo_va, 529 uint32_t operation) 530 { 531 int r; 532 533 if (!amdgpu_vm_ready(vm)) 534 return; 535 536 r = amdgpu_vm_clear_freed(adev, vm, NULL); 537 if (r) 538 goto error; 539 540 if (operation == AMDGPU_VA_OP_MAP || 541 operation == AMDGPU_VA_OP_REPLACE) { 542 r = amdgpu_vm_bo_update(adev, bo_va, false); 543 if (r) 544 goto error; 545 } 546 547 r = amdgpu_vm_update_pdes(adev, vm, false); 548 549 error: 550 if (r && r != -ERESTARTSYS) 551 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 552 } 553 554 /** 555 * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags 556 * 557 * @adev: amdgpu_device pointer 558 * @flags: GEM UAPI flags 559 * 560 * Returns the GEM UAPI flags mapped into hardware for the ASIC. 561 */ 562 uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags) 563 { 564 uint64_t pte_flag = 0; 565 566 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 567 pte_flag |= AMDGPU_PTE_EXECUTABLE; 568 if (flags & AMDGPU_VM_PAGE_READABLE) 569 pte_flag |= AMDGPU_PTE_READABLE; 570 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 571 pte_flag |= AMDGPU_PTE_WRITEABLE; 572 if (flags & AMDGPU_VM_PAGE_PRT) 573 pte_flag |= AMDGPU_PTE_PRT; 574 575 if (adev->gmc.gmc_funcs->map_mtype) 576 pte_flag |= amdgpu_gmc_map_mtype(adev, 577 flags & AMDGPU_VM_MTYPE_MASK); 578 579 return pte_flag; 580 } 581 582 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 583 struct drm_file *filp) 584 { 585 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | 586 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | 587 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK; 588 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | 589 AMDGPU_VM_PAGE_PRT; 590 591 struct drm_amdgpu_gem_va *args = data; 592 struct drm_gem_object *gobj; 593 struct amdgpu_device *adev = dev->dev_private; 594 struct amdgpu_fpriv *fpriv = filp->driver_priv; 595 struct amdgpu_bo *abo; 596 struct amdgpu_bo_va *bo_va; 597 struct amdgpu_bo_list_entry vm_pd; 598 struct ttm_validate_buffer tv; 599 struct ww_acquire_ctx ticket; 600 struct list_head list, duplicates; 601 uint64_t va_flags; 602 int r = 0; 603 604 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { 605 dev_dbg(&dev->pdev->dev, 606 "va_address 0x%LX is in reserved area 0x%LX\n", 607 args->va_address, AMDGPU_VA_RESERVED_SIZE); 608 return -EINVAL; 609 } 610 611 if (args->va_address >= AMDGPU_GMC_HOLE_START && 612 args->va_address < AMDGPU_GMC_HOLE_END) { 613 dev_dbg(&dev->pdev->dev, 614 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n", 615 args->va_address, AMDGPU_GMC_HOLE_START, 616 AMDGPU_GMC_HOLE_END); 617 return -EINVAL; 618 } 619 620 args->va_address &= AMDGPU_GMC_HOLE_MASK; 621 622 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { 623 dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n", 624 args->flags); 625 return -EINVAL; 626 } 627 628 switch (args->operation) { 629 case AMDGPU_VA_OP_MAP: 630 case AMDGPU_VA_OP_UNMAP: 631 case AMDGPU_VA_OP_CLEAR: 632 case AMDGPU_VA_OP_REPLACE: 633 break; 634 default: 635 dev_dbg(&dev->pdev->dev, "unsupported operation %d\n", 636 args->operation); 637 return -EINVAL; 638 } 639 640 INIT_LIST_HEAD(&list); 641 INIT_LIST_HEAD(&duplicates); 642 if ((args->operation != AMDGPU_VA_OP_CLEAR) && 643 !(args->flags & AMDGPU_VM_PAGE_PRT)) { 644 gobj = drm_gem_object_lookup(filp, args->handle); 645 if (gobj == NULL) 646 return -ENOENT; 647 abo = gem_to_amdgpu_bo(gobj); 648 tv.bo = &abo->tbo; 649 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 650 tv.num_shared = 1; 651 else 652 tv.num_shared = 0; 653 list_add(&tv.head, &list); 654 } else { 655 gobj = NULL; 656 abo = NULL; 657 } 658 659 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); 660 661 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 662 if (r) 663 goto error_unref; 664 665 if (abo) { 666 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); 667 if (!bo_va) { 668 r = -ENOENT; 669 goto error_backoff; 670 } 671 } else if (args->operation != AMDGPU_VA_OP_CLEAR) { 672 bo_va = fpriv->prt_va; 673 } else { 674 bo_va = NULL; 675 } 676 677 switch (args->operation) { 678 case AMDGPU_VA_OP_MAP: 679 va_flags = amdgpu_gem_va_map_flags(adev, args->flags); 680 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, 681 args->offset_in_bo, args->map_size, 682 va_flags); 683 break; 684 case AMDGPU_VA_OP_UNMAP: 685 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); 686 break; 687 688 case AMDGPU_VA_OP_CLEAR: 689 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, 690 args->va_address, 691 args->map_size); 692 break; 693 case AMDGPU_VA_OP_REPLACE: 694 va_flags = amdgpu_gem_va_map_flags(adev, args->flags); 695 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, 696 args->offset_in_bo, args->map_size, 697 va_flags); 698 break; 699 default: 700 break; 701 } 702 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) 703 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, 704 args->operation); 705 706 error_backoff: 707 ttm_eu_backoff_reservation(&ticket, &list); 708 709 error_unref: 710 drm_gem_object_put_unlocked(gobj); 711 return r; 712 } 713 714 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 715 struct drm_file *filp) 716 { 717 struct amdgpu_device *adev = dev->dev_private; 718 struct drm_amdgpu_gem_op *args = data; 719 struct drm_gem_object *gobj; 720 struct amdgpu_vm_bo_base *base; 721 struct amdgpu_bo *robj; 722 int r; 723 724 gobj = drm_gem_object_lookup(filp, args->handle); 725 if (gobj == NULL) { 726 return -ENOENT; 727 } 728 robj = gem_to_amdgpu_bo(gobj); 729 730 r = amdgpu_bo_reserve(robj, false); 731 if (unlikely(r)) 732 goto out; 733 734 switch (args->op) { 735 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { 736 struct drm_amdgpu_gem_create_in info; 737 void __user *out = u64_to_user_ptr(args->value); 738 739 info.bo_size = robj->tbo.base.size; 740 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; 741 info.domains = robj->preferred_domains; 742 info.domain_flags = robj->flags; 743 amdgpu_bo_unreserve(robj); 744 if (copy_to_user(out, &info, sizeof(info))) 745 r = -EFAULT; 746 break; 747 } 748 case AMDGPU_GEM_OP_SET_PLACEMENT: 749 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) { 750 r = -EINVAL; 751 amdgpu_bo_unreserve(robj); 752 break; 753 } 754 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { 755 r = -EPERM; 756 amdgpu_bo_unreserve(robj); 757 break; 758 } 759 for (base = robj->vm_bo; base; base = base->next) 760 if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev), 761 amdgpu_ttm_adev(base->vm->root.base.bo->tbo.bdev))) { 762 r = -EINVAL; 763 amdgpu_bo_unreserve(robj); 764 goto out; 765 } 766 767 768 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | 769 AMDGPU_GEM_DOMAIN_GTT | 770 AMDGPU_GEM_DOMAIN_CPU); 771 robj->allowed_domains = robj->preferred_domains; 772 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 773 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 774 775 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 776 amdgpu_vm_bo_invalidate(adev, robj, true); 777 778 amdgpu_bo_unreserve(robj); 779 break; 780 default: 781 amdgpu_bo_unreserve(robj); 782 r = -EINVAL; 783 } 784 785 out: 786 drm_gem_object_put_unlocked(gobj); 787 return r; 788 } 789 790 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 791 struct drm_device *dev, 792 struct drm_mode_create_dumb *args) 793 { 794 struct amdgpu_device *adev = dev->dev_private; 795 struct drm_gem_object *gobj; 796 uint32_t handle; 797 u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 798 AMDGPU_GEM_CREATE_CPU_GTT_USWC; 799 u32 domain; 800 int r; 801 802 /* 803 * The buffer returned from this function should be cleared, but 804 * it can only be done if the ring is enabled or we'll fail to 805 * create the buffer. 806 */ 807 if (adev->mman.buffer_funcs_enabled) 808 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; 809 810 args->pitch = amdgpu_align_pitch(adev, args->width, 811 DIV_ROUND_UP(args->bpp, 8), 0); 812 args->size = (u64)args->pitch * args->height; 813 args->size = roundup2(args->size, PAGE_SIZE); 814 domain = amdgpu_bo_get_preferred_pin_domain(adev, 815 amdgpu_display_supported_domains(adev, flags)); 816 r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags, 817 ttm_bo_type_device, NULL, &gobj); 818 if (r) 819 return -ENOMEM; 820 821 r = drm_gem_handle_create(file_priv, gobj, &handle); 822 /* drop reference from allocate - handle holds it now */ 823 drm_gem_object_put_unlocked(gobj); 824 if (r) { 825 return r; 826 } 827 args->handle = handle; 828 return 0; 829 } 830 831 #if defined(CONFIG_DEBUG_FS) 832 833 #define amdgpu_debugfs_gem_bo_print_flag(m, bo, flag) \ 834 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \ 835 seq_printf((m), " " #flag); \ 836 } 837 838 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data) 839 { 840 struct drm_gem_object *gobj = ptr; 841 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 842 struct seq_file *m = data; 843 844 struct dma_buf_attachment *attachment; 845 struct dma_buf *dma_buf; 846 unsigned domain; 847 const char *placement; 848 unsigned pin_count; 849 850 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 851 switch (domain) { 852 case AMDGPU_GEM_DOMAIN_VRAM: 853 placement = "VRAM"; 854 break; 855 case AMDGPU_GEM_DOMAIN_GTT: 856 placement = " GTT"; 857 break; 858 case AMDGPU_GEM_DOMAIN_CPU: 859 default: 860 placement = " CPU"; 861 break; 862 } 863 seq_printf(m, "\t0x%08x: %12ld byte %s", 864 id, amdgpu_bo_size(bo), placement); 865 866 pin_count = READ_ONCE(bo->pin_count); 867 if (pin_count) 868 seq_printf(m, " pin count %d", pin_count); 869 870 dma_buf = READ_ONCE(bo->tbo.base.dma_buf); 871 attachment = READ_ONCE(bo->tbo.base.import_attach); 872 873 if (attachment) 874 seq_printf(m, " imported from %p", dma_buf); 875 else if (dma_buf) 876 seq_printf(m, " exported as %p", dma_buf); 877 878 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED); 879 amdgpu_debugfs_gem_bo_print_flag(m, bo, NO_CPU_ACCESS); 880 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_GTT_USWC); 881 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CLEARED); 882 amdgpu_debugfs_gem_bo_print_flag(m, bo, SHADOW); 883 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CONTIGUOUS); 884 amdgpu_debugfs_gem_bo_print_flag(m, bo, VM_ALWAYS_VALID); 885 amdgpu_debugfs_gem_bo_print_flag(m, bo, EXPLICIT_SYNC); 886 887 seq_printf(m, "\n"); 888 889 return 0; 890 } 891 892 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) 893 { 894 struct drm_info_node *node = (struct drm_info_node *)m->private; 895 struct drm_device *dev = node->minor->dev; 896 struct drm_file *file; 897 int r; 898 899 r = mutex_lock_interruptible(&dev->filelist_mutex); 900 if (r) 901 return r; 902 903 list_for_each_entry(file, &dev->filelist, lhead) { 904 struct task_struct *task; 905 906 /* 907 * Although we have a valid reference on file->pid, that does 908 * not guarantee that the task_struct who called get_pid() is 909 * still alive (e.g. get_pid(current) => fork() => exit()). 910 * Therefore, we need to protect this ->comm access using RCU. 911 */ 912 rcu_read_lock(); 913 task = pid_task(file->pid, PIDTYPE_PID); 914 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), 915 task ? task->comm : "<unknown>"); 916 rcu_read_unlock(); 917 918 spin_lock(&file->table_lock); 919 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m); 920 spin_unlock(&file->table_lock); 921 } 922 923 mutex_unlock(&dev->filelist_mutex); 924 return 0; 925 } 926 927 static const struct drm_info_list amdgpu_debugfs_gem_list[] = { 928 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, 929 }; 930 #endif 931 932 int amdgpu_debugfs_gem_init(struct amdgpu_device *adev) 933 { 934 #if defined(CONFIG_DEBUG_FS) 935 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1); 936 #endif 937 return 0; 938 } 939