1fb4d8502Sjsg /*
2fb4d8502Sjsg * Copyright 2007-8 Advanced Micro Devices, Inc.
3fb4d8502Sjsg * Copyright 2008 Red Hat Inc.
4fb4d8502Sjsg *
5fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a
6fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"),
7fb4d8502Sjsg * to deal in the Software without restriction, including without limitation
8fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the
10fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions:
11fb4d8502Sjsg *
12fb4d8502Sjsg * The above copyright notice and this permission notice shall be included in
13fb4d8502Sjsg * all copies or substantial portions of the Software.
14fb4d8502Sjsg *
15fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16fb4d8502Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19fb4d8502Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20fb4d8502Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21fb4d8502Sjsg * OTHER DEALINGS IN THE SOFTWARE.
22fb4d8502Sjsg *
23fb4d8502Sjsg * Authors: Dave Airlie
24fb4d8502Sjsg * Alex Deucher
25fb4d8502Sjsg */
26fb4d8502Sjsg
27c349dbc7Sjsg #include <linux/export.h>
28c349dbc7Sjsg #include <linux/pci.h>
29c349dbc7Sjsg
30fb4d8502Sjsg #include <drm/drm_edid.h>
31fb4d8502Sjsg #include <drm/amdgpu_drm.h>
32fb4d8502Sjsg #include "amdgpu.h"
33fb4d8502Sjsg #include "amdgpu_i2c.h"
34fb4d8502Sjsg #include "amdgpu_atombios.h"
35fb4d8502Sjsg #include "atom.h"
36fb4d8502Sjsg #include "atombios_dp.h"
37fb4d8502Sjsg #include "atombios_i2c.h"
38fb4d8502Sjsg
39fb4d8502Sjsg #include <dev/i2c/i2cvar.h>
40fb4d8502Sjsg #include <dev/i2c/i2c_bitbang.h>
41fb4d8502Sjsg
42fb4d8502Sjsg /* bit banging i2c */
amdgpu_i2c_pre_xfer(struct i2c_adapter * i2c_adap)43fb4d8502Sjsg static int amdgpu_i2c_pre_xfer(struct i2c_adapter *i2c_adap)
44fb4d8502Sjsg {
45fb4d8502Sjsg struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
46ad8b1aafSjsg struct amdgpu_device *adev = drm_to_adev(i2c->dev);
47fb4d8502Sjsg struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
48fb4d8502Sjsg uint32_t temp;
49fb4d8502Sjsg
50fb4d8502Sjsg mutex_lock(&i2c->mutex);
51fb4d8502Sjsg
52fb4d8502Sjsg /* switch the pads to ddc mode */
53fb4d8502Sjsg if (rec->hw_capable) {
54fb4d8502Sjsg temp = RREG32(rec->mask_clk_reg);
55fb4d8502Sjsg temp &= ~(1 << 16);
56fb4d8502Sjsg WREG32(rec->mask_clk_reg, temp);
57fb4d8502Sjsg }
58fb4d8502Sjsg
59fb4d8502Sjsg /* clear the output pin values */
60fb4d8502Sjsg temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
61fb4d8502Sjsg WREG32(rec->a_clk_reg, temp);
62fb4d8502Sjsg
63fb4d8502Sjsg temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
64fb4d8502Sjsg WREG32(rec->a_data_reg, temp);
65fb4d8502Sjsg
66fb4d8502Sjsg /* set the pins to input */
67fb4d8502Sjsg temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
68fb4d8502Sjsg WREG32(rec->en_clk_reg, temp);
69fb4d8502Sjsg
70fb4d8502Sjsg temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
71fb4d8502Sjsg WREG32(rec->en_data_reg, temp);
72fb4d8502Sjsg
73fb4d8502Sjsg /* mask the gpio pins for software use */
74fb4d8502Sjsg temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
75fb4d8502Sjsg WREG32(rec->mask_clk_reg, temp);
76fb4d8502Sjsg temp = RREG32(rec->mask_clk_reg);
77fb4d8502Sjsg
78fb4d8502Sjsg temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
79fb4d8502Sjsg WREG32(rec->mask_data_reg, temp);
80fb4d8502Sjsg temp = RREG32(rec->mask_data_reg);
81fb4d8502Sjsg
82fb4d8502Sjsg return 0;
83fb4d8502Sjsg }
84fb4d8502Sjsg
amdgpu_i2c_post_xfer(struct i2c_adapter * i2c_adap)85fb4d8502Sjsg static void amdgpu_i2c_post_xfer(struct i2c_adapter *i2c_adap)
86fb4d8502Sjsg {
87fb4d8502Sjsg struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
88ad8b1aafSjsg struct amdgpu_device *adev = drm_to_adev(i2c->dev);
89fb4d8502Sjsg struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
90fb4d8502Sjsg uint32_t temp;
91fb4d8502Sjsg
92fb4d8502Sjsg /* unmask the gpio pins for software use */
93fb4d8502Sjsg temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
94fb4d8502Sjsg WREG32(rec->mask_clk_reg, temp);
95fb4d8502Sjsg temp = RREG32(rec->mask_clk_reg);
96fb4d8502Sjsg
97fb4d8502Sjsg temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
98fb4d8502Sjsg WREG32(rec->mask_data_reg, temp);
99fb4d8502Sjsg temp = RREG32(rec->mask_data_reg);
100fb4d8502Sjsg
101fb4d8502Sjsg mutex_unlock(&i2c->mutex);
102fb4d8502Sjsg }
103fb4d8502Sjsg
amdgpu_i2c_get_clock(void * i2c_priv)104fb4d8502Sjsg static int amdgpu_i2c_get_clock(void *i2c_priv)
105fb4d8502Sjsg {
106fb4d8502Sjsg struct amdgpu_i2c_chan *i2c = i2c_priv;
107ad8b1aafSjsg struct amdgpu_device *adev = drm_to_adev(i2c->dev);
108fb4d8502Sjsg struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
109fb4d8502Sjsg uint32_t val;
110fb4d8502Sjsg
111fb4d8502Sjsg /* read the value off the pin */
112fb4d8502Sjsg val = RREG32(rec->y_clk_reg);
113fb4d8502Sjsg val &= rec->y_clk_mask;
114fb4d8502Sjsg
115fb4d8502Sjsg return (val != 0);
116fb4d8502Sjsg }
117fb4d8502Sjsg
118fb4d8502Sjsg
amdgpu_i2c_get_data(void * i2c_priv)119fb4d8502Sjsg static int amdgpu_i2c_get_data(void *i2c_priv)
120fb4d8502Sjsg {
121fb4d8502Sjsg struct amdgpu_i2c_chan *i2c = i2c_priv;
122ad8b1aafSjsg struct amdgpu_device *adev = drm_to_adev(i2c->dev);
123fb4d8502Sjsg struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
124fb4d8502Sjsg uint32_t val;
125fb4d8502Sjsg
126fb4d8502Sjsg /* read the value off the pin */
127fb4d8502Sjsg val = RREG32(rec->y_data_reg);
128fb4d8502Sjsg val &= rec->y_data_mask;
129fb4d8502Sjsg
130fb4d8502Sjsg return (val != 0);
131fb4d8502Sjsg }
132fb4d8502Sjsg
amdgpu_i2c_set_clock(void * i2c_priv,int clock)133fb4d8502Sjsg static void amdgpu_i2c_set_clock(void *i2c_priv, int clock)
134fb4d8502Sjsg {
135fb4d8502Sjsg struct amdgpu_i2c_chan *i2c = i2c_priv;
136ad8b1aafSjsg struct amdgpu_device *adev = drm_to_adev(i2c->dev);
137fb4d8502Sjsg struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
138fb4d8502Sjsg uint32_t val;
139fb4d8502Sjsg
140fb4d8502Sjsg /* set pin direction */
141fb4d8502Sjsg val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
142fb4d8502Sjsg val |= clock ? 0 : rec->en_clk_mask;
143fb4d8502Sjsg WREG32(rec->en_clk_reg, val);
144fb4d8502Sjsg }
145fb4d8502Sjsg
amdgpu_i2c_set_data(void * i2c_priv,int data)146fb4d8502Sjsg static void amdgpu_i2c_set_data(void *i2c_priv, int data)
147fb4d8502Sjsg {
148fb4d8502Sjsg struct amdgpu_i2c_chan *i2c = i2c_priv;
149ad8b1aafSjsg struct amdgpu_device *adev = drm_to_adev(i2c->dev);
150fb4d8502Sjsg struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
151fb4d8502Sjsg uint32_t val;
152fb4d8502Sjsg
153fb4d8502Sjsg /* set pin direction */
154fb4d8502Sjsg val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
155fb4d8502Sjsg val |= data ? 0 : rec->en_data_mask;
156fb4d8502Sjsg WREG32(rec->en_data_reg, val);
157fb4d8502Sjsg }
158fb4d8502Sjsg
159fb4d8502Sjsg void amdgpu_bb_set_bits(void *, uint32_t);
160fb4d8502Sjsg void amdgpu_bb_set_dir(void *, uint32_t);
161fb4d8502Sjsg uint32_t amdgpu_bb_read_bits(void *);
162fb4d8502Sjsg
163fb4d8502Sjsg int amdgpu_acquire_bus(void *, int);
164fb4d8502Sjsg void amdgpu_release_bus(void *, int);
165fb4d8502Sjsg int amdgpu_send_start(void *, int);
166fb4d8502Sjsg int amdgpu_send_stop(void *, int);
167fb4d8502Sjsg int amdgpu_initiate_xfer(void *, i2c_addr_t, int);
168fb4d8502Sjsg int amdgpu_read_byte(void *, u_int8_t *, int);
169fb4d8502Sjsg int amdgpu_write_byte(void *, u_int8_t, int);
170fb4d8502Sjsg
171fb4d8502Sjsg #define AMDGPU_BB_SDA (1 << I2C_BIT_SDA)
172fb4d8502Sjsg #define AMDGPU_BB_SCL (1 << I2C_BIT_SCL)
173fb4d8502Sjsg
174fb4d8502Sjsg struct i2c_bitbang_ops amdgpu_bbops = {
175fb4d8502Sjsg amdgpu_bb_set_bits,
176fb4d8502Sjsg amdgpu_bb_set_dir,
177fb4d8502Sjsg amdgpu_bb_read_bits,
178fb4d8502Sjsg { AMDGPU_BB_SDA, AMDGPU_BB_SCL, 0, 0 }
179fb4d8502Sjsg };
180fb4d8502Sjsg
181fb4d8502Sjsg void
amdgpu_bb_set_bits(void * cookie,uint32_t bits)182fb4d8502Sjsg amdgpu_bb_set_bits(void *cookie, uint32_t bits)
183fb4d8502Sjsg {
184fb4d8502Sjsg amdgpu_i2c_set_clock(cookie, bits & AMDGPU_BB_SCL);
185fb4d8502Sjsg amdgpu_i2c_set_data(cookie, bits & AMDGPU_BB_SDA);
186fb4d8502Sjsg }
187fb4d8502Sjsg
188fb4d8502Sjsg void
amdgpu_bb_set_dir(void * cookie,uint32_t bits)189fb4d8502Sjsg amdgpu_bb_set_dir(void *cookie, uint32_t bits)
190fb4d8502Sjsg {
191fb4d8502Sjsg }
192fb4d8502Sjsg
193fb4d8502Sjsg uint32_t
amdgpu_bb_read_bits(void * cookie)194fb4d8502Sjsg amdgpu_bb_read_bits(void *cookie)
195fb4d8502Sjsg {
196fb4d8502Sjsg uint32_t bits = 0;
197fb4d8502Sjsg
198fb4d8502Sjsg if (amdgpu_i2c_get_clock(cookie))
199fb4d8502Sjsg bits |= AMDGPU_BB_SCL;
200fb4d8502Sjsg if (amdgpu_i2c_get_data(cookie))
201fb4d8502Sjsg bits |= AMDGPU_BB_SDA;
202fb4d8502Sjsg
203fb4d8502Sjsg return bits;
204fb4d8502Sjsg }
205fb4d8502Sjsg
206fb4d8502Sjsg int
amdgpu_acquire_bus(void * cookie,int flags)207fb4d8502Sjsg amdgpu_acquire_bus(void *cookie, int flags)
208fb4d8502Sjsg {
209fb4d8502Sjsg struct amdgpu_i2c_chan *i2c = cookie;
210fb4d8502Sjsg amdgpu_i2c_pre_xfer(&i2c->adapter);
211fb4d8502Sjsg return (0);
212fb4d8502Sjsg }
213fb4d8502Sjsg
214fb4d8502Sjsg void
amdgpu_release_bus(void * cookie,int flags)215fb4d8502Sjsg amdgpu_release_bus(void *cookie, int flags)
216fb4d8502Sjsg {
217fb4d8502Sjsg struct amdgpu_i2c_chan *i2c = cookie;
218fb4d8502Sjsg amdgpu_i2c_post_xfer(&i2c->adapter);
219fb4d8502Sjsg }
220fb4d8502Sjsg
221fb4d8502Sjsg int
amdgpu_send_start(void * cookie,int flags)222fb4d8502Sjsg amdgpu_send_start(void *cookie, int flags)
223fb4d8502Sjsg {
224fb4d8502Sjsg return (i2c_bitbang_send_start(cookie, flags, &amdgpu_bbops));
225fb4d8502Sjsg }
226fb4d8502Sjsg
227fb4d8502Sjsg int
amdgpu_send_stop(void * cookie,int flags)228fb4d8502Sjsg amdgpu_send_stop(void *cookie, int flags)
229fb4d8502Sjsg {
230fb4d8502Sjsg return (i2c_bitbang_send_stop(cookie, flags, &amdgpu_bbops));
231fb4d8502Sjsg }
232fb4d8502Sjsg
233fb4d8502Sjsg int
amdgpu_initiate_xfer(void * cookie,i2c_addr_t addr,int flags)234fb4d8502Sjsg amdgpu_initiate_xfer(void *cookie, i2c_addr_t addr, int flags)
235fb4d8502Sjsg {
236fb4d8502Sjsg return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &amdgpu_bbops));
237fb4d8502Sjsg }
238fb4d8502Sjsg
239fb4d8502Sjsg int
amdgpu_read_byte(void * cookie,u_int8_t * bytep,int flags)240fb4d8502Sjsg amdgpu_read_byte(void *cookie, u_int8_t *bytep, int flags)
241fb4d8502Sjsg {
242fb4d8502Sjsg return (i2c_bitbang_read_byte(cookie, bytep, flags, &amdgpu_bbops));
243fb4d8502Sjsg }
244fb4d8502Sjsg
245fb4d8502Sjsg int
amdgpu_write_byte(void * cookie,u_int8_t byte,int flags)246fb4d8502Sjsg amdgpu_write_byte(void *cookie, u_int8_t byte, int flags)
247fb4d8502Sjsg {
248fb4d8502Sjsg return (i2c_bitbang_write_byte(cookie, byte, flags, &amdgpu_bbops));
249fb4d8502Sjsg }
250fb4d8502Sjsg
251fb4d8502Sjsg static const struct i2c_algorithm amdgpu_atombios_i2c_algo = {
252fb4d8502Sjsg .master_xfer = amdgpu_atombios_i2c_xfer,
253fb4d8502Sjsg .functionality = amdgpu_atombios_i2c_func,
254fb4d8502Sjsg };
255fb4d8502Sjsg
amdgpu_i2c_create(struct drm_device * dev,const struct amdgpu_i2c_bus_rec * rec,const char * name)256fb4d8502Sjsg struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev,
257fb4d8502Sjsg const struct amdgpu_i2c_bus_rec *rec,
258fb4d8502Sjsg const char *name)
259fb4d8502Sjsg {
260fb4d8502Sjsg struct amdgpu_i2c_chan *i2c;
261fb4d8502Sjsg int ret;
262fb4d8502Sjsg
263fb4d8502Sjsg /* don't add the mm_i2c bus unless hw_i2c is enabled */
264fb4d8502Sjsg if (rec->mm_i2c && (amdgpu_hw_i2c == 0))
265fb4d8502Sjsg return NULL;
266fb4d8502Sjsg
267fb4d8502Sjsg i2c = kzalloc(sizeof(struct amdgpu_i2c_chan), GFP_KERNEL);
268fb4d8502Sjsg if (i2c == NULL)
269fb4d8502Sjsg return NULL;
270fb4d8502Sjsg
271fb4d8502Sjsg i2c->rec = *rec;
272fb4d8502Sjsg #ifdef __linux__
273fb4d8502Sjsg i2c->adapter.owner = THIS_MODULE;
274fb4d8502Sjsg i2c->adapter.class = I2C_CLASS_DDC;
275*5ca02815Sjsg i2c->adapter.dev.parent = dev->dev;
276fb4d8502Sjsg #endif
277fb4d8502Sjsg i2c->dev = dev;
278fb4d8502Sjsg i2c_set_adapdata(&i2c->adapter, i2c);
279fb4d8502Sjsg rw_init(&i2c->mutex, "agiic");
280fb4d8502Sjsg if (rec->hw_capable &&
281fb4d8502Sjsg amdgpu_hw_i2c) {
282fb4d8502Sjsg /* hw i2c using atom */
283fb4d8502Sjsg snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
284fb4d8502Sjsg "AMDGPU i2c hw bus %s", name);
285fb4d8502Sjsg i2c->adapter.algo = &amdgpu_atombios_i2c_algo;
286fb4d8502Sjsg ret = i2c_add_adapter(&i2c->adapter);
287fb4d8502Sjsg if (ret)
288fb4d8502Sjsg goto out_free;
289fb4d8502Sjsg } else {
290fb4d8502Sjsg /* set the amdgpu bit adapter */
291fb4d8502Sjsg snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
292fb4d8502Sjsg "AMDGPU i2c bit bus %s", name);
293fb4d8502Sjsg i2c->adapter.algo_data = &i2c->bit;
294fb4d8502Sjsg #ifdef notyet
295fb4d8502Sjsg i2c->bit.pre_xfer = amdgpu_i2c_pre_xfer;
296fb4d8502Sjsg i2c->bit.post_xfer = amdgpu_i2c_post_xfer;
297fb4d8502Sjsg i2c->bit.setsda = amdgpu_i2c_set_data;
298fb4d8502Sjsg i2c->bit.setscl = amdgpu_i2c_set_clock;
299fb4d8502Sjsg i2c->bit.getsda = amdgpu_i2c_get_data;
300fb4d8502Sjsg i2c->bit.getscl = amdgpu_i2c_get_clock;
301fb4d8502Sjsg i2c->bit.udelay = 10;
302fb4d8502Sjsg i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */
303fb4d8502Sjsg i2c->bit.data = i2c;
304fb4d8502Sjsg #else
305fb4d8502Sjsg i2c->bit.ic.ic_cookie = i2c;
306fb4d8502Sjsg i2c->bit.ic.ic_acquire_bus = amdgpu_acquire_bus;
307fb4d8502Sjsg i2c->bit.ic.ic_release_bus = amdgpu_release_bus;
308fb4d8502Sjsg i2c->bit.ic.ic_send_start = amdgpu_send_start;
309fb4d8502Sjsg i2c->bit.ic.ic_send_stop = amdgpu_send_stop;
310fb4d8502Sjsg i2c->bit.ic.ic_initiate_xfer = amdgpu_initiate_xfer;
311fb4d8502Sjsg i2c->bit.ic.ic_read_byte = amdgpu_read_byte;
312fb4d8502Sjsg i2c->bit.ic.ic_write_byte = amdgpu_write_byte;
313fb4d8502Sjsg #endif
314fb4d8502Sjsg ret = i2c_bit_add_bus(&i2c->adapter);
315fb4d8502Sjsg if (ret) {
316fb4d8502Sjsg DRM_ERROR("Failed to register bit i2c %s\n", name);
317fb4d8502Sjsg goto out_free;
318fb4d8502Sjsg }
319fb4d8502Sjsg }
320fb4d8502Sjsg
321fb4d8502Sjsg return i2c;
322fb4d8502Sjsg out_free:
323fb4d8502Sjsg kfree(i2c);
324fb4d8502Sjsg return NULL;
325fb4d8502Sjsg
326fb4d8502Sjsg }
327fb4d8502Sjsg
amdgpu_i2c_destroy(struct amdgpu_i2c_chan * i2c)328fb4d8502Sjsg void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c)
329fb4d8502Sjsg {
330fb4d8502Sjsg if (!i2c)
331fb4d8502Sjsg return;
332fb4d8502Sjsg WARN_ON(i2c->has_aux);
333fb4d8502Sjsg i2c_del_adapter(&i2c->adapter);
334fb4d8502Sjsg kfree(i2c);
335fb4d8502Sjsg }
336fb4d8502Sjsg
337fb4d8502Sjsg /* Add the default buses */
amdgpu_i2c_init(struct amdgpu_device * adev)338fb4d8502Sjsg void amdgpu_i2c_init(struct amdgpu_device *adev)
339fb4d8502Sjsg {
340fb4d8502Sjsg if (amdgpu_hw_i2c)
341fb4d8502Sjsg DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n");
342fb4d8502Sjsg
343fb4d8502Sjsg amdgpu_atombios_i2c_init(adev);
344fb4d8502Sjsg }
345fb4d8502Sjsg
346fb4d8502Sjsg /* remove all the buses */
amdgpu_i2c_fini(struct amdgpu_device * adev)347fb4d8502Sjsg void amdgpu_i2c_fini(struct amdgpu_device *adev)
348fb4d8502Sjsg {
349fb4d8502Sjsg int i;
350fb4d8502Sjsg
351fb4d8502Sjsg for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
352fb4d8502Sjsg if (adev->i2c_bus[i]) {
353fb4d8502Sjsg amdgpu_i2c_destroy(adev->i2c_bus[i]);
354fb4d8502Sjsg adev->i2c_bus[i] = NULL;
355fb4d8502Sjsg }
356fb4d8502Sjsg }
357fb4d8502Sjsg }
358fb4d8502Sjsg
359fb4d8502Sjsg /* Add additional buses */
amdgpu_i2c_add(struct amdgpu_device * adev,const struct amdgpu_i2c_bus_rec * rec,const char * name)360fb4d8502Sjsg void amdgpu_i2c_add(struct amdgpu_device *adev,
361fb4d8502Sjsg const struct amdgpu_i2c_bus_rec *rec,
362fb4d8502Sjsg const char *name)
363fb4d8502Sjsg {
364ad8b1aafSjsg struct drm_device *dev = adev_to_drm(adev);
365fb4d8502Sjsg int i;
366fb4d8502Sjsg
367fb4d8502Sjsg for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
368fb4d8502Sjsg if (!adev->i2c_bus[i]) {
369fb4d8502Sjsg adev->i2c_bus[i] = amdgpu_i2c_create(dev, rec, name);
370fb4d8502Sjsg return;
371fb4d8502Sjsg }
372fb4d8502Sjsg }
373fb4d8502Sjsg }
374fb4d8502Sjsg
375fb4d8502Sjsg /* looks up bus based on id */
376fb4d8502Sjsg struct amdgpu_i2c_chan *
amdgpu_i2c_lookup(struct amdgpu_device * adev,const struct amdgpu_i2c_bus_rec * i2c_bus)377fb4d8502Sjsg amdgpu_i2c_lookup(struct amdgpu_device *adev,
378fb4d8502Sjsg const struct amdgpu_i2c_bus_rec *i2c_bus)
379fb4d8502Sjsg {
380fb4d8502Sjsg int i;
381fb4d8502Sjsg
382fb4d8502Sjsg for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
383fb4d8502Sjsg if (adev->i2c_bus[i] &&
384fb4d8502Sjsg (adev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
385fb4d8502Sjsg return adev->i2c_bus[i];
386fb4d8502Sjsg }
387fb4d8502Sjsg }
388fb4d8502Sjsg return NULL;
389fb4d8502Sjsg }
390fb4d8502Sjsg
amdgpu_i2c_get_byte(struct amdgpu_i2c_chan * i2c_bus,u8 slave_addr,u8 addr,u8 * val)391fb4d8502Sjsg static void amdgpu_i2c_get_byte(struct amdgpu_i2c_chan *i2c_bus,
392fb4d8502Sjsg u8 slave_addr,
393fb4d8502Sjsg u8 addr,
394fb4d8502Sjsg u8 *val)
395fb4d8502Sjsg {
396fb4d8502Sjsg u8 out_buf[2];
397fb4d8502Sjsg u8 in_buf[2];
398fb4d8502Sjsg struct i2c_msg msgs[] = {
399fb4d8502Sjsg {
400fb4d8502Sjsg .addr = slave_addr,
401fb4d8502Sjsg .flags = 0,
402fb4d8502Sjsg .len = 1,
403fb4d8502Sjsg .buf = out_buf,
404fb4d8502Sjsg },
405fb4d8502Sjsg {
406fb4d8502Sjsg .addr = slave_addr,
407fb4d8502Sjsg .flags = I2C_M_RD,
408fb4d8502Sjsg .len = 1,
409fb4d8502Sjsg .buf = in_buf,
410fb4d8502Sjsg }
411fb4d8502Sjsg };
412fb4d8502Sjsg
413fb4d8502Sjsg out_buf[0] = addr;
414fb4d8502Sjsg out_buf[1] = 0;
415fb4d8502Sjsg
416fb4d8502Sjsg if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
417fb4d8502Sjsg *val = in_buf[0];
418fb4d8502Sjsg DRM_DEBUG("val = 0x%02x\n", *val);
419fb4d8502Sjsg } else {
420fb4d8502Sjsg DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
421fb4d8502Sjsg addr, *val);
422fb4d8502Sjsg }
423fb4d8502Sjsg }
424fb4d8502Sjsg
amdgpu_i2c_put_byte(struct amdgpu_i2c_chan * i2c_bus,u8 slave_addr,u8 addr,u8 val)425fb4d8502Sjsg static void amdgpu_i2c_put_byte(struct amdgpu_i2c_chan *i2c_bus,
426fb4d8502Sjsg u8 slave_addr,
427fb4d8502Sjsg u8 addr,
428fb4d8502Sjsg u8 val)
429fb4d8502Sjsg {
430fb4d8502Sjsg uint8_t out_buf[2];
431fb4d8502Sjsg struct i2c_msg msg = {
432fb4d8502Sjsg .addr = slave_addr,
433fb4d8502Sjsg .flags = 0,
434fb4d8502Sjsg .len = 2,
435fb4d8502Sjsg .buf = out_buf,
436fb4d8502Sjsg };
437fb4d8502Sjsg
438fb4d8502Sjsg out_buf[0] = addr;
439fb4d8502Sjsg out_buf[1] = val;
440fb4d8502Sjsg
441fb4d8502Sjsg if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
442fb4d8502Sjsg DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
443fb4d8502Sjsg addr, val);
444fb4d8502Sjsg }
445fb4d8502Sjsg
446fb4d8502Sjsg /* ddc router switching */
447fb4d8502Sjsg void
amdgpu_i2c_router_select_ddc_port(const struct amdgpu_connector * amdgpu_connector)448fb4d8502Sjsg amdgpu_i2c_router_select_ddc_port(const struct amdgpu_connector *amdgpu_connector)
449fb4d8502Sjsg {
4506f5f80bcSjsg u8 val = 0;
451fb4d8502Sjsg
452fb4d8502Sjsg if (!amdgpu_connector->router.ddc_valid)
453fb4d8502Sjsg return;
454fb4d8502Sjsg
455fb4d8502Sjsg if (!amdgpu_connector->router_bus)
456fb4d8502Sjsg return;
457fb4d8502Sjsg
458fb4d8502Sjsg amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
459fb4d8502Sjsg amdgpu_connector->router.i2c_addr,
460fb4d8502Sjsg 0x3, &val);
461fb4d8502Sjsg val &= ~amdgpu_connector->router.ddc_mux_control_pin;
462fb4d8502Sjsg amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
463fb4d8502Sjsg amdgpu_connector->router.i2c_addr,
464fb4d8502Sjsg 0x3, val);
465fb4d8502Sjsg amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
466fb4d8502Sjsg amdgpu_connector->router.i2c_addr,
467fb4d8502Sjsg 0x1, &val);
468fb4d8502Sjsg val &= ~amdgpu_connector->router.ddc_mux_control_pin;
469fb4d8502Sjsg val |= amdgpu_connector->router.ddc_mux_state;
470fb4d8502Sjsg amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
471fb4d8502Sjsg amdgpu_connector->router.i2c_addr,
472fb4d8502Sjsg 0x1, val);
473fb4d8502Sjsg }
474fb4d8502Sjsg
475fb4d8502Sjsg /* clock/data router switching */
476fb4d8502Sjsg void
amdgpu_i2c_router_select_cd_port(const struct amdgpu_connector * amdgpu_connector)477fb4d8502Sjsg amdgpu_i2c_router_select_cd_port(const struct amdgpu_connector *amdgpu_connector)
478fb4d8502Sjsg {
479fb4d8502Sjsg u8 val;
480fb4d8502Sjsg
481fb4d8502Sjsg if (!amdgpu_connector->router.cd_valid)
482fb4d8502Sjsg return;
483fb4d8502Sjsg
484fb4d8502Sjsg if (!amdgpu_connector->router_bus)
485fb4d8502Sjsg return;
486fb4d8502Sjsg
487fb4d8502Sjsg amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
488fb4d8502Sjsg amdgpu_connector->router.i2c_addr,
489fb4d8502Sjsg 0x3, &val);
490fb4d8502Sjsg val &= ~amdgpu_connector->router.cd_mux_control_pin;
491fb4d8502Sjsg amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
492fb4d8502Sjsg amdgpu_connector->router.i2c_addr,
493fb4d8502Sjsg 0x3, val);
494fb4d8502Sjsg amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
495fb4d8502Sjsg amdgpu_connector->router.i2c_addr,
496fb4d8502Sjsg 0x1, &val);
497fb4d8502Sjsg val &= ~amdgpu_connector->router.cd_mux_control_pin;
498fb4d8502Sjsg val |= amdgpu_connector->router.cd_mux_state;
499fb4d8502Sjsg amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
500fb4d8502Sjsg amdgpu_connector->router.i2c_addr,
501fb4d8502Sjsg 0x1, val);
502fb4d8502Sjsg }
503