1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/dma-mapping.h> 25 26 #include <drm/drm_legacy.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_ih.h" 30 31 /** 32 * amdgpu_ih_ring_init - initialize the IH state 33 * 34 * @adev: amdgpu_device pointer 35 * @ih: ih ring to initialize 36 * @ring_size: ring size to allocate 37 * @use_bus_addr: true when we can use dma_alloc_coherent 38 * 39 * Initializes the IH state and allocates a buffer 40 * for the IH ring buffer. 41 * Returns 0 for success, errors for failure. 42 */ 43 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, 44 unsigned ring_size, bool use_bus_addr) 45 { 46 u32 rb_bufsz; 47 int r; 48 struct drm_dmamem *dmah; 49 int flags = 0; 50 51 /* Align ring size */ 52 rb_bufsz = order_base_2(ring_size / 4); 53 ring_size = (1 << rb_bufsz) * 4; 54 ih->ring_size = ring_size; 55 ih->ptr_mask = ih->ring_size - 1; 56 ih->rptr = 0; 57 ih->use_bus_addr = use_bus_addr; 58 59 if (use_bus_addr) { 60 dma_addr_t dma_addr; 61 62 if (ih->ring) 63 return 0; 64 65 /* add 8 bytes for the rptr/wptr shadows and 66 * add them to the end of the ring allocation. 67 */ 68 #ifdef __linux__ 69 ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8, 70 &dma_addr, GFP_KERNEL); 71 if (ih->ring == NULL) 72 return -ENOMEM; 73 #else 74 dmah = drm_dmamem_alloc(adev->dmat, 75 ih->ring_size + 8, 76 PAGE_SIZE, 1, 77 ih->ring_size + 8, flags, 0); 78 if (dmah == NULL) 79 return -ENOMEM; 80 ih->dmah = dmah; 81 dma_addr = dmah->map->dm_segs[0].ds_addr; 82 ih->ring = (volatile uint32_t *)dmah->kva; 83 #endif 84 85 ih->gpu_addr = dma_addr; 86 ih->wptr_addr = dma_addr + ih->ring_size; 87 ih->wptr_cpu = &ih->ring[ih->ring_size / 4]; 88 ih->rptr_addr = dma_addr + ih->ring_size + 4; 89 ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1]; 90 } else { 91 unsigned wptr_offs, rptr_offs; 92 93 r = amdgpu_device_wb_get(adev, &wptr_offs); 94 if (r) 95 return r; 96 97 r = amdgpu_device_wb_get(adev, &rptr_offs); 98 if (r) { 99 amdgpu_device_wb_free(adev, wptr_offs); 100 return r; 101 } 102 103 r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE, 104 AMDGPU_GEM_DOMAIN_GTT, 105 &ih->ring_obj, &ih->gpu_addr, 106 (void **)&ih->ring); 107 if (r) { 108 amdgpu_device_wb_free(adev, rptr_offs); 109 amdgpu_device_wb_free(adev, wptr_offs); 110 return r; 111 } 112 113 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4; 114 ih->wptr_cpu = &adev->wb.wb[wptr_offs]; 115 ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4; 116 ih->rptr_cpu = &adev->wb.wb[rptr_offs]; 117 } 118 return 0; 119 } 120 121 /** 122 * amdgpu_ih_ring_fini - tear down the IH state 123 * 124 * @adev: amdgpu_device pointer 125 * @ih: ih ring to tear down 126 * 127 * Tears down the IH state and frees buffer 128 * used for the IH ring buffer. 129 */ 130 void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) 131 { 132 if (ih->use_bus_addr) { 133 if (!ih->ring) 134 return; 135 136 /* add 8 bytes for the rptr/wptr shadows and 137 * add them to the end of the ring allocation. 138 */ 139 #ifdef __linux__ 140 dma_free_coherent(adev->dev, ih->ring_size + 8, 141 (void *)ih->ring, ih->gpu_addr); 142 #else 143 drm_dmamem_free(adev->dmat, ih->dmah); 144 #endif 145 ih->ring = NULL; 146 } else { 147 amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr, 148 (void **)&ih->ring); 149 amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4); 150 amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4); 151 } 152 } 153 154 /** 155 * amdgpu_ih_process - interrupt handler 156 * 157 * @adev: amdgpu_device pointer 158 * @ih: ih ring to process 159 * 160 * Interrupt hander (VI), walk the IH ring. 161 * Returns irq process return code. 162 */ 163 int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) 164 { 165 unsigned int count = AMDGPU_IH_MAX_NUM_IVS; 166 u32 wptr; 167 168 if (!ih->enabled || adev->shutdown) 169 return IRQ_NONE; 170 171 wptr = amdgpu_ih_get_wptr(adev, ih); 172 173 restart_ih: 174 /* is somebody else already processing irqs? */ 175 if (atomic_xchg(&ih->lock, 1)) 176 return IRQ_NONE; 177 178 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr); 179 180 /* Order reading of wptr vs. reading of IH ring data */ 181 rmb(); 182 183 while (ih->rptr != wptr && --count) { 184 amdgpu_irq_dispatch(adev, ih); 185 ih->rptr &= ih->ptr_mask; 186 } 187 188 amdgpu_ih_set_rptr(adev, ih); 189 atomic_set(&ih->lock, 0); 190 191 /* make sure wptr hasn't changed while processing */ 192 wptr = amdgpu_ih_get_wptr(adev, ih); 193 if (wptr != ih->rptr) 194 goto restart_ih; 195 196 return IRQ_HANDLED; 197 } 198 199