1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include <drm/drm_drv.h> 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 #include "atom.h" 35 36 #include <linux/vga_switcheroo.h> 37 #include <linux/slab.h> 38 #include <linux/uaccess.h> 39 #include <linux/pci.h> 40 #include <linux/pm_runtime.h> 41 #include "amdgpu_amdkfd.h" 42 #include "amdgpu_gem.h" 43 #include "amdgpu_display.h" 44 #include "amdgpu_ras.h" 45 46 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 47 { 48 struct amdgpu_gpu_instance *gpu_instance; 49 int i; 50 51 mutex_lock(&mgpu_info.mutex); 52 53 for (i = 0; i < mgpu_info.num_gpu; i++) { 54 gpu_instance = &(mgpu_info.gpu_ins[i]); 55 if (gpu_instance->adev == adev) { 56 mgpu_info.gpu_ins[i] = 57 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 58 mgpu_info.num_gpu--; 59 if (adev->flags & AMD_IS_APU) 60 mgpu_info.num_apu--; 61 else 62 mgpu_info.num_dgpu--; 63 break; 64 } 65 } 66 67 mutex_unlock(&mgpu_info.mutex); 68 } 69 70 #ifdef __linux__ 71 /** 72 * amdgpu_driver_unload_kms - Main unload function for KMS. 73 * 74 * @dev: drm dev pointer 75 * 76 * This is the main unload function for KMS (all asics). 77 * Returns 0 on success. 78 */ 79 void amdgpu_driver_unload_kms(struct drm_device *dev) 80 { 81 struct amdgpu_device *adev = drm_to_adev(dev); 82 83 if (adev == NULL) 84 return; 85 86 amdgpu_unregister_gpu_instance(adev); 87 88 if (adev->rmmio == NULL) 89 return; 90 91 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD)) 92 DRM_WARN("smart shift update failed\n"); 93 94 amdgpu_acpi_fini(adev); 95 amdgpu_device_fini_hw(adev); 96 } 97 #endif /* __linux__ */ 98 99 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 100 { 101 struct amdgpu_gpu_instance *gpu_instance; 102 103 mutex_lock(&mgpu_info.mutex); 104 105 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 106 DRM_ERROR("Cannot register more gpu instance\n"); 107 mutex_unlock(&mgpu_info.mutex); 108 return; 109 } 110 111 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 112 gpu_instance->adev = adev; 113 gpu_instance->mgpu_fan_enabled = 0; 114 115 mgpu_info.num_gpu++; 116 if (adev->flags & AMD_IS_APU) 117 mgpu_info.num_apu++; 118 else 119 mgpu_info.num_dgpu++; 120 121 mutex_unlock(&mgpu_info.mutex); 122 } 123 124 #ifdef __linux__ 125 /** 126 * amdgpu_driver_load_kms - Main load function for KMS. 127 * 128 * @adev: pointer to struct amdgpu_device 129 * @flags: device flags 130 * 131 * This is the main load function for KMS (all asics). 132 * Returns 0 on success, error on failure. 133 */ 134 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 135 { 136 struct drm_device *dev; 137 int r, acpi_status; 138 139 dev = adev_to_drm(adev); 140 141 /* amdgpu_device_init should report only fatal error 142 * like memory allocation failure or iomapping failure, 143 * or memory manager initialization failure, it must 144 * properly initialize the GPU MC controller and permit 145 * VRAM allocation 146 */ 147 r = amdgpu_device_init(adev, flags); 148 if (r) { 149 dev_err(dev->dev, "Fatal error during GPU init\n"); 150 goto out; 151 } 152 153 adev->pm.rpm_mode = AMDGPU_RUNPM_NONE; 154 if (amdgpu_device_supports_px(dev) && 155 (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */ 156 adev->pm.rpm_mode = AMDGPU_RUNPM_PX; 157 dev_info(adev->dev, "Using ATPX for runtime pm\n"); 158 } else if (amdgpu_device_supports_boco(dev) && 159 (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */ 160 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO; 161 dev_info(adev->dev, "Using BOCO for runtime pm\n"); 162 } else if (amdgpu_device_supports_baco(dev) && 163 (amdgpu_runtime_pm != 0)) { 164 switch (adev->asic_type) { 165 case CHIP_VEGA20: 166 case CHIP_ARCTURUS: 167 /* enable BACO as runpm mode if runpm=1 */ 168 if (amdgpu_runtime_pm > 0) 169 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 170 break; 171 case CHIP_VEGA10: 172 /* enable BACO as runpm mode if noretry=0 */ 173 if (!adev->gmc.noretry) 174 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 175 break; 176 default: 177 /* enable BACO as runpm mode on CI+ */ 178 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 179 break; 180 } 181 182 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) 183 dev_info(adev->dev, "Using BACO for runtime pm\n"); 184 } 185 186 /* Call ACPI methods: require modeset init 187 * but failure is not fatal 188 */ 189 190 acpi_status = amdgpu_acpi_init(adev); 191 if (acpi_status) 192 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 193 194 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD)) 195 DRM_WARN("smart shift update failed\n"); 196 197 out: 198 if (r) 199 amdgpu_driver_unload_kms(dev); 200 201 return r; 202 } 203 #endif /* __linux__ */ 204 205 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 206 struct drm_amdgpu_query_fw *query_fw, 207 struct amdgpu_device *adev) 208 { 209 switch (query_fw->fw_type) { 210 case AMDGPU_INFO_FW_VCE: 211 fw_info->ver = adev->vce.fw_version; 212 fw_info->feature = adev->vce.fb_version; 213 break; 214 case AMDGPU_INFO_FW_UVD: 215 fw_info->ver = adev->uvd.fw_version; 216 fw_info->feature = 0; 217 break; 218 case AMDGPU_INFO_FW_VCN: 219 fw_info->ver = adev->vcn.fw_version; 220 fw_info->feature = 0; 221 break; 222 case AMDGPU_INFO_FW_GMC: 223 fw_info->ver = adev->gmc.fw_version; 224 fw_info->feature = 0; 225 break; 226 case AMDGPU_INFO_FW_GFX_ME: 227 fw_info->ver = adev->gfx.me_fw_version; 228 fw_info->feature = adev->gfx.me_feature_version; 229 break; 230 case AMDGPU_INFO_FW_GFX_PFP: 231 fw_info->ver = adev->gfx.pfp_fw_version; 232 fw_info->feature = adev->gfx.pfp_feature_version; 233 break; 234 case AMDGPU_INFO_FW_GFX_CE: 235 fw_info->ver = adev->gfx.ce_fw_version; 236 fw_info->feature = adev->gfx.ce_feature_version; 237 break; 238 case AMDGPU_INFO_FW_GFX_RLC: 239 fw_info->ver = adev->gfx.rlc_fw_version; 240 fw_info->feature = adev->gfx.rlc_feature_version; 241 break; 242 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 243 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 244 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 245 break; 246 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 247 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 248 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 249 break; 250 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 251 fw_info->ver = adev->gfx.rlc_srls_fw_version; 252 fw_info->feature = adev->gfx.rlc_srls_feature_version; 253 break; 254 case AMDGPU_INFO_FW_GFX_RLCP: 255 fw_info->ver = adev->gfx.rlcp_ucode_version; 256 fw_info->feature = adev->gfx.rlcp_ucode_feature_version; 257 break; 258 case AMDGPU_INFO_FW_GFX_RLCV: 259 fw_info->ver = adev->gfx.rlcv_ucode_version; 260 fw_info->feature = adev->gfx.rlcv_ucode_feature_version; 261 break; 262 case AMDGPU_INFO_FW_GFX_MEC: 263 if (query_fw->index == 0) { 264 fw_info->ver = adev->gfx.mec_fw_version; 265 fw_info->feature = adev->gfx.mec_feature_version; 266 } else if (query_fw->index == 1) { 267 fw_info->ver = adev->gfx.mec2_fw_version; 268 fw_info->feature = adev->gfx.mec2_feature_version; 269 } else 270 return -EINVAL; 271 break; 272 case AMDGPU_INFO_FW_SMC: 273 fw_info->ver = adev->pm.fw_version; 274 fw_info->feature = 0; 275 break; 276 case AMDGPU_INFO_FW_TA: 277 switch (query_fw->index) { 278 case TA_FW_TYPE_PSP_XGMI: 279 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; 280 fw_info->feature = adev->psp.xgmi_context.context 281 .bin_desc.feature_version; 282 break; 283 case TA_FW_TYPE_PSP_RAS: 284 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; 285 fw_info->feature = adev->psp.ras_context.context 286 .bin_desc.feature_version; 287 break; 288 case TA_FW_TYPE_PSP_HDCP: 289 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; 290 fw_info->feature = adev->psp.hdcp_context.context 291 .bin_desc.feature_version; 292 break; 293 case TA_FW_TYPE_PSP_DTM: 294 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; 295 fw_info->feature = adev->psp.dtm_context.context 296 .bin_desc.feature_version; 297 break; 298 case TA_FW_TYPE_PSP_RAP: 299 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; 300 fw_info->feature = adev->psp.rap_context.context 301 .bin_desc.feature_version; 302 break; 303 case TA_FW_TYPE_PSP_SECUREDISPLAY: 304 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; 305 fw_info->feature = 306 adev->psp.securedisplay_context.context.bin_desc 307 .feature_version; 308 break; 309 default: 310 return -EINVAL; 311 } 312 break; 313 case AMDGPU_INFO_FW_SDMA: 314 if (query_fw->index >= adev->sdma.num_instances) 315 return -EINVAL; 316 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 317 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 318 break; 319 case AMDGPU_INFO_FW_SOS: 320 fw_info->ver = adev->psp.sos.fw_version; 321 fw_info->feature = adev->psp.sos.feature_version; 322 break; 323 case AMDGPU_INFO_FW_ASD: 324 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; 325 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; 326 break; 327 case AMDGPU_INFO_FW_DMCU: 328 fw_info->ver = adev->dm.dmcu_fw_version; 329 fw_info->feature = 0; 330 break; 331 case AMDGPU_INFO_FW_DMCUB: 332 fw_info->ver = adev->dm.dmcub_fw_version; 333 fw_info->feature = 0; 334 break; 335 case AMDGPU_INFO_FW_TOC: 336 fw_info->ver = adev->psp.toc.fw_version; 337 fw_info->feature = adev->psp.toc.feature_version; 338 break; 339 case AMDGPU_INFO_FW_CAP: 340 fw_info->ver = adev->psp.cap_fw_version; 341 fw_info->feature = adev->psp.cap_feature_version; 342 break; 343 case AMDGPU_INFO_FW_MES_KIQ: 344 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK; 345 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK) 346 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 347 break; 348 case AMDGPU_INFO_FW_MES: 349 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 350 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK) 351 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 352 break; 353 case AMDGPU_INFO_FW_IMU: 354 fw_info->ver = adev->gfx.imu_fw_version; 355 fw_info->feature = 0; 356 break; 357 default: 358 return -EINVAL; 359 } 360 return 0; 361 } 362 363 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 364 struct drm_amdgpu_info *info, 365 struct drm_amdgpu_info_hw_ip *result) 366 { 367 uint32_t ib_start_alignment = 0; 368 uint32_t ib_size_alignment = 0; 369 enum amd_ip_block_type type; 370 unsigned int num_rings = 0; 371 unsigned int i, j; 372 373 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 374 return -EINVAL; 375 376 switch (info->query_hw_ip.type) { 377 case AMDGPU_HW_IP_GFX: 378 type = AMD_IP_BLOCK_TYPE_GFX; 379 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 380 if (adev->gfx.gfx_ring[i].sched.ready) 381 ++num_rings; 382 ib_start_alignment = 32; 383 ib_size_alignment = 32; 384 break; 385 case AMDGPU_HW_IP_COMPUTE: 386 type = AMD_IP_BLOCK_TYPE_GFX; 387 for (i = 0; i < adev->gfx.num_compute_rings; i++) 388 if (adev->gfx.compute_ring[i].sched.ready) 389 ++num_rings; 390 ib_start_alignment = 32; 391 ib_size_alignment = 32; 392 break; 393 case AMDGPU_HW_IP_DMA: 394 type = AMD_IP_BLOCK_TYPE_SDMA; 395 for (i = 0; i < adev->sdma.num_instances; i++) 396 if (adev->sdma.instance[i].ring.sched.ready) 397 ++num_rings; 398 ib_start_alignment = 256; 399 ib_size_alignment = 4; 400 break; 401 case AMDGPU_HW_IP_UVD: 402 type = AMD_IP_BLOCK_TYPE_UVD; 403 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 404 if (adev->uvd.harvest_config & (1 << i)) 405 continue; 406 407 if (adev->uvd.inst[i].ring.sched.ready) 408 ++num_rings; 409 } 410 ib_start_alignment = 64; 411 ib_size_alignment = 64; 412 break; 413 case AMDGPU_HW_IP_VCE: 414 type = AMD_IP_BLOCK_TYPE_VCE; 415 for (i = 0; i < adev->vce.num_rings; i++) 416 if (adev->vce.ring[i].sched.ready) 417 ++num_rings; 418 ib_start_alignment = 4; 419 ib_size_alignment = 1; 420 break; 421 case AMDGPU_HW_IP_UVD_ENC: 422 type = AMD_IP_BLOCK_TYPE_UVD; 423 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 424 if (adev->uvd.harvest_config & (1 << i)) 425 continue; 426 427 for (j = 0; j < adev->uvd.num_enc_rings; j++) 428 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 429 ++num_rings; 430 } 431 ib_start_alignment = 64; 432 ib_size_alignment = 64; 433 break; 434 case AMDGPU_HW_IP_VCN_DEC: 435 type = AMD_IP_BLOCK_TYPE_VCN; 436 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 437 if (adev->uvd.harvest_config & (1 << i)) 438 continue; 439 440 if (adev->vcn.inst[i].ring_dec.sched.ready) 441 ++num_rings; 442 } 443 ib_start_alignment = 16; 444 ib_size_alignment = 16; 445 break; 446 case AMDGPU_HW_IP_VCN_ENC: 447 type = AMD_IP_BLOCK_TYPE_VCN; 448 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 449 if (adev->uvd.harvest_config & (1 << i)) 450 continue; 451 452 for (j = 0; j < adev->vcn.num_enc_rings; j++) 453 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 454 ++num_rings; 455 } 456 ib_start_alignment = 64; 457 ib_size_alignment = 1; 458 break; 459 case AMDGPU_HW_IP_VCN_JPEG: 460 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 461 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 462 463 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 464 if (adev->jpeg.harvest_config & (1 << i)) 465 continue; 466 467 if (adev->jpeg.inst[i].ring_dec.sched.ready) 468 ++num_rings; 469 } 470 ib_start_alignment = 16; 471 ib_size_alignment = 16; 472 break; 473 default: 474 return -EINVAL; 475 } 476 477 for (i = 0; i < adev->num_ip_blocks; i++) 478 if (adev->ip_blocks[i].version->type == type && 479 adev->ip_blocks[i].status.valid) 480 break; 481 482 if (i == adev->num_ip_blocks) 483 return 0; 484 485 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 486 num_rings); 487 488 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 489 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 490 491 if (adev->asic_type >= CHIP_VEGA10) { 492 switch (type) { 493 case AMD_IP_BLOCK_TYPE_GFX: 494 result->ip_discovery_version = adev->ip_versions[GC_HWIP][0]; 495 break; 496 case AMD_IP_BLOCK_TYPE_SDMA: 497 result->ip_discovery_version = adev->ip_versions[SDMA0_HWIP][0]; 498 break; 499 case AMD_IP_BLOCK_TYPE_UVD: 500 case AMD_IP_BLOCK_TYPE_VCN: 501 case AMD_IP_BLOCK_TYPE_JPEG: 502 result->ip_discovery_version = adev->ip_versions[UVD_HWIP][0]; 503 break; 504 case AMD_IP_BLOCK_TYPE_VCE: 505 result->ip_discovery_version = adev->ip_versions[VCE_HWIP][0]; 506 break; 507 default: 508 result->ip_discovery_version = 0; 509 break; 510 } 511 } else { 512 result->ip_discovery_version = 0; 513 } 514 result->capabilities_flags = 0; 515 result->available_rings = (1 << num_rings) - 1; 516 result->ib_start_alignment = ib_start_alignment; 517 result->ib_size_alignment = ib_size_alignment; 518 return 0; 519 } 520 521 /* 522 * Userspace get information ioctl 523 */ 524 /** 525 * amdgpu_info_ioctl - answer a device specific request. 526 * 527 * @dev: drm device pointer 528 * @data: request object 529 * @filp: drm filp 530 * 531 * This function is used to pass device specific parameters to the userspace 532 * drivers. Examples include: pci device id, pipeline parms, tiling params, 533 * etc. (all asics). 534 * Returns 0 on success, -EINVAL on failure. 535 */ 536 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 537 { 538 struct amdgpu_device *adev = drm_to_adev(dev); 539 struct drm_amdgpu_info *info = data; 540 struct amdgpu_mode_info *minfo = &adev->mode_info; 541 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 542 uint32_t size = info->return_size; 543 struct drm_crtc *crtc; 544 uint32_t ui32 = 0; 545 uint64_t ui64 = 0; 546 int i, found; 547 int ui32_size = sizeof(ui32); 548 549 if (!info->return_size || !info->return_pointer) 550 return -EINVAL; 551 552 switch (info->query) { 553 case AMDGPU_INFO_ACCEL_WORKING: 554 ui32 = adev->accel_working; 555 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 556 case AMDGPU_INFO_CRTC_FROM_ID: 557 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 558 crtc = (struct drm_crtc *)minfo->crtcs[i]; 559 if (crtc && crtc->base.id == info->mode_crtc.id) { 560 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 561 562 ui32 = amdgpu_crtc->crtc_id; 563 found = 1; 564 break; 565 } 566 } 567 if (!found) { 568 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 569 return -EINVAL; 570 } 571 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 572 case AMDGPU_INFO_HW_IP_INFO: { 573 struct drm_amdgpu_info_hw_ip ip = {}; 574 int ret; 575 576 ret = amdgpu_hw_ip_info(adev, info, &ip); 577 if (ret) 578 return ret; 579 580 ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip))); 581 return ret ? -EFAULT : 0; 582 } 583 case AMDGPU_INFO_HW_IP_COUNT: { 584 enum amd_ip_block_type type; 585 uint32_t count = 0; 586 587 switch (info->query_hw_ip.type) { 588 case AMDGPU_HW_IP_GFX: 589 type = AMD_IP_BLOCK_TYPE_GFX; 590 break; 591 case AMDGPU_HW_IP_COMPUTE: 592 type = AMD_IP_BLOCK_TYPE_GFX; 593 break; 594 case AMDGPU_HW_IP_DMA: 595 type = AMD_IP_BLOCK_TYPE_SDMA; 596 break; 597 case AMDGPU_HW_IP_UVD: 598 type = AMD_IP_BLOCK_TYPE_UVD; 599 break; 600 case AMDGPU_HW_IP_VCE: 601 type = AMD_IP_BLOCK_TYPE_VCE; 602 break; 603 case AMDGPU_HW_IP_UVD_ENC: 604 type = AMD_IP_BLOCK_TYPE_UVD; 605 break; 606 case AMDGPU_HW_IP_VCN_DEC: 607 case AMDGPU_HW_IP_VCN_ENC: 608 type = AMD_IP_BLOCK_TYPE_VCN; 609 break; 610 case AMDGPU_HW_IP_VCN_JPEG: 611 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 612 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 613 break; 614 default: 615 return -EINVAL; 616 } 617 618 for (i = 0; i < adev->num_ip_blocks; i++) 619 if (adev->ip_blocks[i].version->type == type && 620 adev->ip_blocks[i].status.valid && 621 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 622 count++; 623 624 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 625 } 626 case AMDGPU_INFO_TIMESTAMP: 627 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 628 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 629 case AMDGPU_INFO_FW_VERSION: { 630 struct drm_amdgpu_info_firmware fw_info; 631 int ret; 632 633 /* We only support one instance of each IP block right now. */ 634 if (info->query_fw.ip_instance != 0) 635 return -EINVAL; 636 637 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 638 if (ret) 639 return ret; 640 641 return copy_to_user(out, &fw_info, 642 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 643 } 644 case AMDGPU_INFO_NUM_BYTES_MOVED: 645 ui64 = atomic64_read(&adev->num_bytes_moved); 646 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 647 case AMDGPU_INFO_NUM_EVICTIONS: 648 ui64 = atomic64_read(&adev->num_evictions); 649 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 650 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 651 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 652 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 653 case AMDGPU_INFO_VRAM_USAGE: 654 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager); 655 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 656 case AMDGPU_INFO_VIS_VRAM_USAGE: 657 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 658 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 659 case AMDGPU_INFO_GTT_USAGE: 660 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager); 661 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 662 case AMDGPU_INFO_GDS_CONFIG: { 663 struct drm_amdgpu_info_gds gds_info; 664 665 memset(&gds_info, 0, sizeof(gds_info)); 666 gds_info.compute_partition_size = adev->gds.gds_size; 667 gds_info.gds_total_size = adev->gds.gds_size; 668 gds_info.gws_per_compute_partition = adev->gds.gws_size; 669 gds_info.oa_per_compute_partition = adev->gds.oa_size; 670 return copy_to_user(out, &gds_info, 671 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 672 } 673 case AMDGPU_INFO_VRAM_GTT: { 674 struct drm_amdgpu_info_vram_gtt vram_gtt; 675 676 vram_gtt.vram_size = adev->gmc.real_vram_size - 677 atomic64_read(&adev->vram_pin_size) - 678 AMDGPU_VM_RESERVED_VRAM; 679 vram_gtt.vram_cpu_accessible_size = 680 min(adev->gmc.visible_vram_size - 681 atomic64_read(&adev->visible_pin_size), 682 vram_gtt.vram_size); 683 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 684 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 685 return copy_to_user(out, &vram_gtt, 686 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 687 } 688 case AMDGPU_INFO_MEMORY: { 689 struct drm_amdgpu_memory_info mem; 690 struct ttm_resource_manager *gtt_man = 691 &adev->mman.gtt_mgr.manager; 692 struct ttm_resource_manager *vram_man = 693 &adev->mman.vram_mgr.manager; 694 695 memset(&mem, 0, sizeof(mem)); 696 mem.vram.total_heap_size = adev->gmc.real_vram_size; 697 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 698 atomic64_read(&adev->vram_pin_size) - 699 AMDGPU_VM_RESERVED_VRAM; 700 mem.vram.heap_usage = 701 ttm_resource_manager_usage(vram_man); 702 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 703 704 mem.cpu_accessible_vram.total_heap_size = 705 adev->gmc.visible_vram_size; 706 mem.cpu_accessible_vram.usable_heap_size = 707 min(adev->gmc.visible_vram_size - 708 atomic64_read(&adev->visible_pin_size), 709 mem.vram.usable_heap_size); 710 mem.cpu_accessible_vram.heap_usage = 711 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 712 mem.cpu_accessible_vram.max_allocation = 713 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 714 715 mem.gtt.total_heap_size = gtt_man->size; 716 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 717 atomic64_read(&adev->gart_pin_size); 718 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man); 719 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 720 721 return copy_to_user(out, &mem, 722 min((size_t)size, sizeof(mem))) 723 ? -EFAULT : 0; 724 } 725 case AMDGPU_INFO_READ_MMR_REG: { 726 unsigned int n, alloc_size; 727 uint32_t *regs; 728 unsigned int se_num = (info->read_mmr_reg.instance >> 729 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 730 AMDGPU_INFO_MMR_SE_INDEX_MASK; 731 unsigned int sh_num = (info->read_mmr_reg.instance >> 732 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 733 AMDGPU_INFO_MMR_SH_INDEX_MASK; 734 735 /* set full masks if the userspace set all bits 736 * in the bitfields 737 */ 738 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 739 se_num = 0xffffffff; 740 else if (se_num >= AMDGPU_GFX_MAX_SE) 741 return -EINVAL; 742 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 743 sh_num = 0xffffffff; 744 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 745 return -EINVAL; 746 747 if (info->read_mmr_reg.count > 128) 748 return -EINVAL; 749 750 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 751 if (!regs) 752 return -ENOMEM; 753 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 754 755 amdgpu_gfx_off_ctrl(adev, false); 756 for (i = 0; i < info->read_mmr_reg.count; i++) { 757 if (amdgpu_asic_read_register(adev, se_num, sh_num, 758 info->read_mmr_reg.dword_offset + i, 759 ®s[i])) { 760 DRM_DEBUG_KMS("unallowed offset %#x\n", 761 info->read_mmr_reg.dword_offset + i); 762 kfree(regs); 763 amdgpu_gfx_off_ctrl(adev, true); 764 return -EFAULT; 765 } 766 } 767 amdgpu_gfx_off_ctrl(adev, true); 768 n = copy_to_user(out, regs, min(size, alloc_size)); 769 kfree(regs); 770 return n ? -EFAULT : 0; 771 } 772 case AMDGPU_INFO_DEV_INFO: { 773 struct drm_amdgpu_info_device *dev_info; 774 uint64_t vm_size; 775 int ret; 776 777 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); 778 if (!dev_info) 779 return -ENOMEM; 780 781 dev_info->device_id = adev->pdev->device; 782 dev_info->chip_rev = adev->rev_id; 783 dev_info->external_rev = adev->external_rev_id; 784 dev_info->pci_rev = adev->pdev->revision; 785 dev_info->family = adev->family; 786 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 787 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 788 /* return all clocks in KHz */ 789 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 790 if (adev->pm.dpm_enabled) { 791 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 792 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 793 } else { 794 dev_info->max_engine_clock = adev->clock.default_sclk * 10; 795 dev_info->max_memory_clock = adev->clock.default_mclk * 10; 796 } 797 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 798 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 799 adev->gfx.config.max_shader_engines; 800 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 801 dev_info->_pad = 0; 802 dev_info->ids_flags = 0; 803 if (adev->flags & AMD_IS_APU) 804 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 805 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 806 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 807 if (amdgpu_is_tmz(adev)) 808 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 809 810 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 811 vm_size -= AMDGPU_VA_RESERVED_SIZE; 812 813 /* Older VCE FW versions are buggy and can handle only 40bits */ 814 if (adev->vce.fw_version && 815 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 816 vm_size = min(vm_size, 1ULL << 40); 817 818 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 819 dev_info->virtual_address_max = 820 min(vm_size, AMDGPU_GMC_HOLE_START); 821 822 if (vm_size > AMDGPU_GMC_HOLE_START) { 823 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 824 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 825 } 826 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 827 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 828 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 829 dev_info->cu_active_number = adev->gfx.cu_info.number; 830 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 831 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 832 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 833 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 834 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 835 sizeof(adev->gfx.cu_info.bitmap)); 836 dev_info->vram_type = adev->gmc.vram_type; 837 dev_info->vram_bit_width = adev->gmc.vram_width; 838 dev_info->vce_harvest_config = adev->vce.harvest_config; 839 dev_info->gc_double_offchip_lds_buf = 840 adev->gfx.config.double_offchip_lds_buf; 841 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 842 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 843 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 844 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 845 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 846 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 847 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 848 849 if (adev->family >= AMDGPU_FAMILY_NV) 850 dev_info->pa_sc_tile_steering_override = 851 adev->gfx.config.pa_sc_tile_steering_override; 852 853 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 854 855 ret = copy_to_user(out, dev_info, 856 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 857 kfree(dev_info); 858 return ret; 859 } 860 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 861 unsigned int i; 862 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 863 struct amd_vce_state *vce_state; 864 865 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 866 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 867 if (vce_state) { 868 vce_clk_table.entries[i].sclk = vce_state->sclk; 869 vce_clk_table.entries[i].mclk = vce_state->mclk; 870 vce_clk_table.entries[i].eclk = vce_state->evclk; 871 vce_clk_table.num_valid_entries++; 872 } 873 } 874 875 return copy_to_user(out, &vce_clk_table, 876 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 877 } 878 case AMDGPU_INFO_VBIOS: { 879 uint32_t bios_size = adev->bios_size; 880 881 switch (info->vbios_info.type) { 882 case AMDGPU_INFO_VBIOS_SIZE: 883 return copy_to_user(out, &bios_size, 884 min((size_t)size, sizeof(bios_size))) 885 ? -EFAULT : 0; 886 case AMDGPU_INFO_VBIOS_IMAGE: { 887 uint8_t *bios; 888 uint32_t bios_offset = info->vbios_info.offset; 889 890 if (bios_offset >= bios_size) 891 return -EINVAL; 892 893 bios = adev->bios + bios_offset; 894 return copy_to_user(out, bios, 895 min((size_t)size, (size_t)(bios_size - bios_offset))) 896 ? -EFAULT : 0; 897 } 898 case AMDGPU_INFO_VBIOS_INFO: { 899 struct drm_amdgpu_info_vbios vbios_info = {}; 900 struct atom_context *atom_context; 901 902 atom_context = adev->mode_info.atom_context; 903 if (atom_context) { 904 memcpy(vbios_info.name, atom_context->name, 905 sizeof(atom_context->name)); 906 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, 907 sizeof(atom_context->vbios_pn)); 908 vbios_info.version = atom_context->version; 909 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, 910 sizeof(atom_context->vbios_ver_str)); 911 memcpy(vbios_info.date, atom_context->date, 912 sizeof(atom_context->date)); 913 } 914 915 return copy_to_user(out, &vbios_info, 916 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; 917 } 918 default: 919 DRM_DEBUG_KMS("Invalid request %d\n", 920 info->vbios_info.type); 921 return -EINVAL; 922 } 923 } 924 case AMDGPU_INFO_NUM_HANDLES: { 925 struct drm_amdgpu_info_num_handles handle; 926 927 switch (info->query_hw_ip.type) { 928 case AMDGPU_HW_IP_UVD: 929 /* Starting Polaris, we support unlimited UVD handles */ 930 if (adev->asic_type < CHIP_POLARIS10) { 931 handle.uvd_max_handles = adev->uvd.max_handles; 932 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 933 934 return copy_to_user(out, &handle, 935 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 936 } else { 937 return -ENODATA; 938 } 939 940 break; 941 default: 942 return -EINVAL; 943 } 944 } 945 case AMDGPU_INFO_SENSOR: { 946 if (!adev->pm.dpm_enabled) 947 return -ENOENT; 948 949 switch (info->sensor_info.type) { 950 case AMDGPU_INFO_SENSOR_GFX_SCLK: 951 /* get sclk in Mhz */ 952 if (amdgpu_dpm_read_sensor(adev, 953 AMDGPU_PP_SENSOR_GFX_SCLK, 954 (void *)&ui32, &ui32_size)) { 955 return -EINVAL; 956 } 957 ui32 /= 100; 958 break; 959 case AMDGPU_INFO_SENSOR_GFX_MCLK: 960 /* get mclk in Mhz */ 961 if (amdgpu_dpm_read_sensor(adev, 962 AMDGPU_PP_SENSOR_GFX_MCLK, 963 (void *)&ui32, &ui32_size)) { 964 return -EINVAL; 965 } 966 ui32 /= 100; 967 break; 968 case AMDGPU_INFO_SENSOR_GPU_TEMP: 969 /* get temperature in millidegrees C */ 970 if (amdgpu_dpm_read_sensor(adev, 971 AMDGPU_PP_SENSOR_GPU_TEMP, 972 (void *)&ui32, &ui32_size)) { 973 return -EINVAL; 974 } 975 break; 976 case AMDGPU_INFO_SENSOR_GPU_LOAD: 977 /* get GPU load */ 978 if (amdgpu_dpm_read_sensor(adev, 979 AMDGPU_PP_SENSOR_GPU_LOAD, 980 (void *)&ui32, &ui32_size)) { 981 return -EINVAL; 982 } 983 break; 984 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 985 /* get average GPU power */ 986 if (amdgpu_dpm_read_sensor(adev, 987 AMDGPU_PP_SENSOR_GPU_POWER, 988 (void *)&ui32, &ui32_size)) { 989 return -EINVAL; 990 } 991 ui32 >>= 8; 992 break; 993 case AMDGPU_INFO_SENSOR_VDDNB: 994 /* get VDDNB in millivolts */ 995 if (amdgpu_dpm_read_sensor(adev, 996 AMDGPU_PP_SENSOR_VDDNB, 997 (void *)&ui32, &ui32_size)) { 998 return -EINVAL; 999 } 1000 break; 1001 case AMDGPU_INFO_SENSOR_VDDGFX: 1002 /* get VDDGFX in millivolts */ 1003 if (amdgpu_dpm_read_sensor(adev, 1004 AMDGPU_PP_SENSOR_VDDGFX, 1005 (void *)&ui32, &ui32_size)) { 1006 return -EINVAL; 1007 } 1008 break; 1009 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 1010 /* get stable pstate sclk in Mhz */ 1011 if (amdgpu_dpm_read_sensor(adev, 1012 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 1013 (void *)&ui32, &ui32_size)) { 1014 return -EINVAL; 1015 } 1016 ui32 /= 100; 1017 break; 1018 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 1019 /* get stable pstate mclk in Mhz */ 1020 if (amdgpu_dpm_read_sensor(adev, 1021 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 1022 (void *)&ui32, &ui32_size)) { 1023 return -EINVAL; 1024 } 1025 ui32 /= 100; 1026 break; 1027 default: 1028 DRM_DEBUG_KMS("Invalid request %d\n", 1029 info->sensor_info.type); 1030 return -EINVAL; 1031 } 1032 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1033 } 1034 case AMDGPU_INFO_VRAM_LOST_COUNTER: 1035 ui32 = atomic_read(&adev->vram_lost_counter); 1036 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1037 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 1038 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1039 uint64_t ras_mask; 1040 1041 if (!ras) 1042 return -EINVAL; 1043 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; 1044 1045 return copy_to_user(out, &ras_mask, 1046 min_t(u64, size, sizeof(ras_mask))) ? 1047 -EFAULT : 0; 1048 } 1049 case AMDGPU_INFO_VIDEO_CAPS: { 1050 const struct amdgpu_video_codecs *codecs; 1051 struct drm_amdgpu_info_video_caps *caps; 1052 int r; 1053 1054 switch (info->video_cap.type) { 1055 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 1056 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 1057 if (r) 1058 return -EINVAL; 1059 break; 1060 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1061 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1062 if (r) 1063 return -EINVAL; 1064 break; 1065 default: 1066 DRM_DEBUG_KMS("Invalid request %d\n", 1067 info->video_cap.type); 1068 return -EINVAL; 1069 } 1070 1071 caps = kzalloc(sizeof(*caps), GFP_KERNEL); 1072 if (!caps) 1073 return -ENOMEM; 1074 1075 for (i = 0; i < codecs->codec_count; i++) { 1076 int idx = codecs->codec_array[i].codec_type; 1077 1078 switch (idx) { 1079 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1080 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1081 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1082 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1083 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1084 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1085 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1086 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1087 caps->codec_info[idx].valid = 1; 1088 caps->codec_info[idx].max_width = 1089 codecs->codec_array[i].max_width; 1090 caps->codec_info[idx].max_height = 1091 codecs->codec_array[i].max_height; 1092 caps->codec_info[idx].max_pixels_per_frame = 1093 codecs->codec_array[i].max_pixels_per_frame; 1094 caps->codec_info[idx].max_level = 1095 codecs->codec_array[i].max_level; 1096 break; 1097 default: 1098 break; 1099 } 1100 } 1101 r = copy_to_user(out, caps, 1102 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1103 kfree(caps); 1104 return r; 1105 } 1106 default: 1107 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1108 return -EINVAL; 1109 } 1110 return 0; 1111 } 1112 1113 1114 /* 1115 * Outdated mess for old drm with Xorg being in charge (void function now). 1116 */ 1117 /** 1118 * amdgpu_driver_lastclose_kms - drm callback for last close 1119 * 1120 * @dev: drm dev pointer 1121 * 1122 * Switch vga_switcheroo state after last close (all asics). 1123 */ 1124 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 1125 { 1126 drm_fb_helper_lastclose(dev); 1127 vga_switcheroo_process_delayed_switch(); 1128 } 1129 1130 /** 1131 * amdgpu_driver_open_kms - drm callback for open 1132 * 1133 * @dev: drm dev pointer 1134 * @file_priv: drm file 1135 * 1136 * On device open, init vm on cayman+ (all asics). 1137 * Returns 0 on success, error on failure. 1138 */ 1139 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1140 { 1141 struct amdgpu_device *adev = drm_to_adev(dev); 1142 struct amdgpu_fpriv *fpriv; 1143 int r, pasid; 1144 1145 /* Ensure IB tests are run on ring */ 1146 flush_delayed_work(&adev->delayed_init_work); 1147 1148 1149 if (amdgpu_ras_intr_triggered()) { 1150 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1151 return -EHWPOISON; 1152 } 1153 1154 file_priv->driver_priv = NULL; 1155 1156 r = pm_runtime_get_sync(dev->dev); 1157 if (r < 0) 1158 goto pm_put; 1159 1160 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1161 if (unlikely(!fpriv)) { 1162 r = -ENOMEM; 1163 goto out_suspend; 1164 } 1165 1166 pasid = amdgpu_pasid_alloc(16); 1167 if (pasid < 0) { 1168 dev_warn(adev->dev, "No more PASIDs available!"); 1169 pasid = 0; 1170 } 1171 1172 r = amdgpu_vm_init(adev, &fpriv->vm); 1173 if (r) 1174 goto error_pasid; 1175 1176 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid); 1177 if (r) 1178 goto error_vm; 1179 1180 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1181 if (!fpriv->prt_va) { 1182 r = -ENOMEM; 1183 goto error_vm; 1184 } 1185 1186 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1187 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1188 1189 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1190 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1191 if (r) 1192 goto error_vm; 1193 } 1194 1195 rw_init(&fpriv->bo_list_lock, "agbo"); 1196 idr_init_base(&fpriv->bo_list_handles, 1); 1197 1198 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); 1199 1200 file_priv->driver_priv = fpriv; 1201 goto out_suspend; 1202 1203 error_vm: 1204 amdgpu_vm_fini(adev, &fpriv->vm); 1205 1206 error_pasid: 1207 if (pasid) { 1208 amdgpu_pasid_free(pasid); 1209 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0); 1210 } 1211 1212 kfree(fpriv); 1213 1214 out_suspend: 1215 pm_runtime_mark_last_busy(dev->dev); 1216 pm_put: 1217 pm_runtime_put_autosuspend(dev->dev); 1218 1219 return r; 1220 } 1221 1222 /** 1223 * amdgpu_driver_postclose_kms - drm callback for post close 1224 * 1225 * @dev: drm dev pointer 1226 * @file_priv: drm file 1227 * 1228 * On device post close, tear down vm on cayman+ (all asics). 1229 */ 1230 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1231 struct drm_file *file_priv) 1232 { 1233 struct amdgpu_device *adev = drm_to_adev(dev); 1234 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1235 struct amdgpu_bo_list *list; 1236 struct amdgpu_bo *pd; 1237 u32 pasid; 1238 int handle; 1239 1240 if (!fpriv) 1241 return; 1242 1243 pm_runtime_get_sync(dev->dev); 1244 1245 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1246 amdgpu_uvd_free_handles(adev, file_priv); 1247 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1248 amdgpu_vce_free_handles(adev, file_priv); 1249 1250 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1251 /* TODO: how to handle reserve failure */ 1252 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1253 amdgpu_vm_bo_del(adev, fpriv->csa_va); 1254 fpriv->csa_va = NULL; 1255 amdgpu_bo_unreserve(adev->virt.csa_obj); 1256 } 1257 1258 pasid = fpriv->vm.pasid; 1259 pd = amdgpu_bo_ref(fpriv->vm.root.bo); 1260 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) { 1261 amdgpu_vm_bo_del(adev, fpriv->prt_va); 1262 amdgpu_bo_unreserve(pd); 1263 } 1264 1265 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1266 amdgpu_vm_fini(adev, &fpriv->vm); 1267 1268 if (pasid) 1269 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1270 amdgpu_bo_unref(&pd); 1271 1272 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1273 amdgpu_bo_list_put(list); 1274 1275 idr_destroy(&fpriv->bo_list_handles); 1276 mutex_destroy(&fpriv->bo_list_lock); 1277 1278 kfree(fpriv); 1279 file_priv->driver_priv = NULL; 1280 1281 pm_runtime_mark_last_busy(dev->dev); 1282 pm_runtime_put_autosuspend(dev->dev); 1283 } 1284 1285 1286 void amdgpu_driver_release_kms(struct drm_device *dev) 1287 { 1288 struct amdgpu_device *adev = drm_to_adev(dev); 1289 1290 amdgpu_device_fini_sw(adev); 1291 pci_set_drvdata(adev->pdev, NULL); 1292 } 1293 1294 /* 1295 * VBlank related functions. 1296 */ 1297 /** 1298 * amdgpu_get_vblank_counter_kms - get frame count 1299 * 1300 * @crtc: crtc to get the frame count from 1301 * 1302 * Gets the frame count on the requested crtc (all asics). 1303 * Returns frame count on success, -EINVAL on failure. 1304 */ 1305 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1306 { 1307 struct drm_device *dev = crtc->dev; 1308 unsigned int pipe = crtc->index; 1309 struct amdgpu_device *adev = drm_to_adev(dev); 1310 int vpos, hpos, stat; 1311 u32 count; 1312 1313 if (pipe >= adev->mode_info.num_crtc) { 1314 DRM_ERROR("Invalid crtc %u\n", pipe); 1315 return -EINVAL; 1316 } 1317 1318 /* The hw increments its frame counter at start of vsync, not at start 1319 * of vblank, as is required by DRM core vblank counter handling. 1320 * Cook the hw count here to make it appear to the caller as if it 1321 * incremented at start of vblank. We measure distance to start of 1322 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1323 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1324 * result by 1 to give the proper appearance to caller. 1325 */ 1326 if (adev->mode_info.crtcs[pipe]) { 1327 /* Repeat readout if needed to provide stable result if 1328 * we cross start of vsync during the queries. 1329 */ 1330 do { 1331 count = amdgpu_display_vblank_get_counter(adev, pipe); 1332 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1333 * vpos as distance to start of vblank, instead of 1334 * regular vertical scanout pos. 1335 */ 1336 stat = amdgpu_display_get_crtc_scanoutpos( 1337 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1338 &vpos, &hpos, NULL, NULL, 1339 &adev->mode_info.crtcs[pipe]->base.hwmode); 1340 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1341 1342 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1343 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1344 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1345 } else { 1346 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1347 pipe, vpos); 1348 1349 /* Bump counter if we are at >= leading edge of vblank, 1350 * but before vsync where vpos would turn negative and 1351 * the hw counter really increments. 1352 */ 1353 if (vpos >= 0) 1354 count++; 1355 } 1356 } else { 1357 /* Fallback to use value as is. */ 1358 count = amdgpu_display_vblank_get_counter(adev, pipe); 1359 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1360 } 1361 1362 return count; 1363 } 1364 1365 /** 1366 * amdgpu_enable_vblank_kms - enable vblank interrupt 1367 * 1368 * @crtc: crtc to enable vblank interrupt for 1369 * 1370 * Enable the interrupt on the requested crtc (all asics). 1371 * Returns 0 on success, -EINVAL on failure. 1372 */ 1373 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1374 { 1375 struct drm_device *dev = crtc->dev; 1376 unsigned int pipe = crtc->index; 1377 struct amdgpu_device *adev = drm_to_adev(dev); 1378 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1379 1380 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1381 } 1382 1383 /** 1384 * amdgpu_disable_vblank_kms - disable vblank interrupt 1385 * 1386 * @crtc: crtc to disable vblank interrupt for 1387 * 1388 * Disable the interrupt on the requested crtc (all asics). 1389 */ 1390 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1391 { 1392 struct drm_device *dev = crtc->dev; 1393 unsigned int pipe = crtc->index; 1394 struct amdgpu_device *adev = drm_to_adev(dev); 1395 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1396 1397 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1398 } 1399 1400 /* 1401 * Debugfs info 1402 */ 1403 #if defined(CONFIG_DEBUG_FS) 1404 1405 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1406 { 1407 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 1408 struct drm_amdgpu_info_firmware fw_info; 1409 struct drm_amdgpu_query_fw query_fw; 1410 struct atom_context *ctx = adev->mode_info.atom_context; 1411 uint8_t smu_program, smu_major, smu_minor, smu_debug; 1412 int ret, i; 1413 1414 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { 1415 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type 1416 TA_FW_NAME(XGMI), 1417 TA_FW_NAME(RAS), 1418 TA_FW_NAME(HDCP), 1419 TA_FW_NAME(DTM), 1420 TA_FW_NAME(RAP), 1421 TA_FW_NAME(SECUREDISPLAY), 1422 #undef TA_FW_NAME 1423 }; 1424 1425 /* VCE */ 1426 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1427 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1428 if (ret) 1429 return ret; 1430 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1431 fw_info.feature, fw_info.ver); 1432 1433 /* UVD */ 1434 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1435 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1436 if (ret) 1437 return ret; 1438 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1439 fw_info.feature, fw_info.ver); 1440 1441 /* GMC */ 1442 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1443 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1444 if (ret) 1445 return ret; 1446 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1447 fw_info.feature, fw_info.ver); 1448 1449 /* ME */ 1450 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1451 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1452 if (ret) 1453 return ret; 1454 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1455 fw_info.feature, fw_info.ver); 1456 1457 /* PFP */ 1458 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1459 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1460 if (ret) 1461 return ret; 1462 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1463 fw_info.feature, fw_info.ver); 1464 1465 /* CE */ 1466 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1467 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1468 if (ret) 1469 return ret; 1470 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1471 fw_info.feature, fw_info.ver); 1472 1473 /* RLC */ 1474 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1475 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1476 if (ret) 1477 return ret; 1478 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1479 fw_info.feature, fw_info.ver); 1480 1481 /* RLC SAVE RESTORE LIST CNTL */ 1482 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1483 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1484 if (ret) 1485 return ret; 1486 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1487 fw_info.feature, fw_info.ver); 1488 1489 /* RLC SAVE RESTORE LIST GPM MEM */ 1490 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1491 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1492 if (ret) 1493 return ret; 1494 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1495 fw_info.feature, fw_info.ver); 1496 1497 /* RLC SAVE RESTORE LIST SRM MEM */ 1498 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1499 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1500 if (ret) 1501 return ret; 1502 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1503 fw_info.feature, fw_info.ver); 1504 1505 /* RLCP */ 1506 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP; 1507 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1508 if (ret) 1509 return ret; 1510 seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n", 1511 fw_info.feature, fw_info.ver); 1512 1513 /* RLCV */ 1514 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV; 1515 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1516 if (ret) 1517 return ret; 1518 seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n", 1519 fw_info.feature, fw_info.ver); 1520 1521 /* MEC */ 1522 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1523 query_fw.index = 0; 1524 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1525 if (ret) 1526 return ret; 1527 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1528 fw_info.feature, fw_info.ver); 1529 1530 /* MEC2 */ 1531 if (adev->gfx.mec2_fw) { 1532 query_fw.index = 1; 1533 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1534 if (ret) 1535 return ret; 1536 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1537 fw_info.feature, fw_info.ver); 1538 } 1539 1540 /* IMU */ 1541 query_fw.fw_type = AMDGPU_INFO_FW_IMU; 1542 query_fw.index = 0; 1543 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1544 if (ret) 1545 return ret; 1546 seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n", 1547 fw_info.feature, fw_info.ver); 1548 1549 /* PSP SOS */ 1550 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1551 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1552 if (ret) 1553 return ret; 1554 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1555 fw_info.feature, fw_info.ver); 1556 1557 1558 /* PSP ASD */ 1559 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1560 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1561 if (ret) 1562 return ret; 1563 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1564 fw_info.feature, fw_info.ver); 1565 1566 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1567 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { 1568 query_fw.index = i; 1569 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1570 if (ret) 1571 continue; 1572 1573 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1574 ta_fw_name[i], fw_info.feature, fw_info.ver); 1575 } 1576 1577 /* SMC */ 1578 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1579 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1580 if (ret) 1581 return ret; 1582 smu_program = (fw_info.ver >> 24) & 0xff; 1583 smu_major = (fw_info.ver >> 16) & 0xff; 1584 smu_minor = (fw_info.ver >> 8) & 0xff; 1585 smu_debug = (fw_info.ver >> 0) & 0xff; 1586 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n", 1587 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug); 1588 1589 /* SDMA */ 1590 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1591 for (i = 0; i < adev->sdma.num_instances; i++) { 1592 query_fw.index = i; 1593 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1594 if (ret) 1595 return ret; 1596 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1597 i, fw_info.feature, fw_info.ver); 1598 } 1599 1600 /* VCN */ 1601 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1602 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1603 if (ret) 1604 return ret; 1605 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1606 fw_info.feature, fw_info.ver); 1607 1608 /* DMCU */ 1609 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1610 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1611 if (ret) 1612 return ret; 1613 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1614 fw_info.feature, fw_info.ver); 1615 1616 /* DMCUB */ 1617 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1618 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1619 if (ret) 1620 return ret; 1621 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1622 fw_info.feature, fw_info.ver); 1623 1624 /* TOC */ 1625 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1626 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1627 if (ret) 1628 return ret; 1629 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1630 fw_info.feature, fw_info.ver); 1631 1632 /* CAP */ 1633 if (adev->psp.cap_fw) { 1634 query_fw.fw_type = AMDGPU_INFO_FW_CAP; 1635 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1636 if (ret) 1637 return ret; 1638 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n", 1639 fw_info.feature, fw_info.ver); 1640 } 1641 1642 /* MES_KIQ */ 1643 query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ; 1644 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1645 if (ret) 1646 return ret; 1647 seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n", 1648 fw_info.feature, fw_info.ver); 1649 1650 /* MES */ 1651 query_fw.fw_type = AMDGPU_INFO_FW_MES; 1652 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1653 if (ret) 1654 return ret; 1655 seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n", 1656 fw_info.feature, fw_info.ver); 1657 1658 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1659 1660 return 0; 1661 } 1662 1663 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 1664 1665 #endif 1666 1667 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1668 { 1669 #if defined(CONFIG_DEBUG_FS) 1670 struct drm_minor *minor = adev_to_drm(adev)->primary; 1671 struct dentry *root = minor->debugfs_root; 1672 1673 debugfs_create_file("amdgpu_firmware_info", 0444, root, 1674 adev, &amdgpu_debugfs_firmware_info_fops); 1675 1676 #endif 1677 } 1678