1fb4d8502Sjsg /* 2fb4d8502Sjsg * Copyright 2012 Advanced Micro Devices, Inc. 3fb4d8502Sjsg * 4fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"), 6fb4d8502Sjsg * to deal in the Software without restriction, including without limitation 7fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions: 10fb4d8502Sjsg * 11fb4d8502Sjsg * The above copyright notice and this permission notice shall be included in 12fb4d8502Sjsg * all copies or substantial portions of the Software. 13fb4d8502Sjsg * 14fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15fb4d8502Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18fb4d8502Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19fb4d8502Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20fb4d8502Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21fb4d8502Sjsg * 22fb4d8502Sjsg */ 23fb4d8502Sjsg #ifndef __AMDGPU_UCODE_H__ 24fb4d8502Sjsg #define __AMDGPU_UCODE_H__ 25fb4d8502Sjsg 26c349dbc7Sjsg #include "amdgpu_socbb.h" 27c349dbc7Sjsg 28fb4d8502Sjsg struct common_firmware_header { 29fb4d8502Sjsg uint32_t size_bytes; /* size of the entire header+image(s) in bytes */ 30fb4d8502Sjsg uint32_t header_size_bytes; /* size of just the header in bytes */ 31fb4d8502Sjsg uint16_t header_version_major; /* header version */ 32fb4d8502Sjsg uint16_t header_version_minor; /* header version */ 33fb4d8502Sjsg uint16_t ip_version_major; /* IP version */ 34fb4d8502Sjsg uint16_t ip_version_minor; /* IP version */ 35fb4d8502Sjsg uint32_t ucode_version; 36fb4d8502Sjsg uint32_t ucode_size_bytes; /* size of ucode in bytes */ 37fb4d8502Sjsg uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */ 38fb4d8502Sjsg uint32_t crc32; /* crc32 checksum of the payload */ 39fb4d8502Sjsg }; 40fb4d8502Sjsg 41fb4d8502Sjsg /* version_major=1, version_minor=0 */ 42fb4d8502Sjsg struct mc_firmware_header_v1_0 { 43fb4d8502Sjsg struct common_firmware_header header; 44fb4d8502Sjsg uint32_t io_debug_size_bytes; /* size of debug array in dwords */ 45fb4d8502Sjsg uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */ 46fb4d8502Sjsg }; 47fb4d8502Sjsg 48fb4d8502Sjsg /* version_major=1, version_minor=0 */ 49fb4d8502Sjsg struct smc_firmware_header_v1_0 { 50fb4d8502Sjsg struct common_firmware_header header; 51fb4d8502Sjsg uint32_t ucode_start_addr; 52fb4d8502Sjsg }; 53fb4d8502Sjsg 54c349dbc7Sjsg /* version_major=2, version_minor=0 */ 55c349dbc7Sjsg struct smc_firmware_header_v2_0 { 56c349dbc7Sjsg struct smc_firmware_header_v1_0 v1_0; 57c349dbc7Sjsg uint32_t ppt_offset_bytes; /* soft pptable offset */ 58c349dbc7Sjsg uint32_t ppt_size_bytes; /* soft pptable size */ 59c349dbc7Sjsg }; 60c349dbc7Sjsg 61c349dbc7Sjsg struct smc_soft_pptable_entry { 62c349dbc7Sjsg uint32_t id; 63c349dbc7Sjsg uint32_t ppt_offset_bytes; 64c349dbc7Sjsg uint32_t ppt_size_bytes; 65c349dbc7Sjsg }; 66c349dbc7Sjsg 67c349dbc7Sjsg /* version_major=2, version_minor=1 */ 68c349dbc7Sjsg struct smc_firmware_header_v2_1 { 69c349dbc7Sjsg struct smc_firmware_header_v1_0 v1_0; 70c349dbc7Sjsg uint32_t pptable_count; 71c349dbc7Sjsg uint32_t pptable_entry_offset; 72c349dbc7Sjsg }; 73c349dbc7Sjsg 745ca02815Sjsg struct psp_fw_legacy_bin_desc { 755ca02815Sjsg uint32_t fw_version; 765ca02815Sjsg uint32_t offset_bytes; 775ca02815Sjsg uint32_t size_bytes; 785ca02815Sjsg }; 795ca02815Sjsg 80fb4d8502Sjsg /* version_major=1, version_minor=0 */ 81fb4d8502Sjsg struct psp_firmware_header_v1_0 { 82fb4d8502Sjsg struct common_firmware_header header; 835ca02815Sjsg struct psp_fw_legacy_bin_desc sos; 84fb4d8502Sjsg }; 85fb4d8502Sjsg 86c349dbc7Sjsg /* version_major=1, version_minor=1 */ 87c349dbc7Sjsg struct psp_firmware_header_v1_1 { 88c349dbc7Sjsg struct psp_firmware_header_v1_0 v1_0; 895ca02815Sjsg struct psp_fw_legacy_bin_desc toc; 905ca02815Sjsg struct psp_fw_legacy_bin_desc kdb; 91c349dbc7Sjsg }; 92c349dbc7Sjsg 93c349dbc7Sjsg /* version_major=1, version_minor=2 */ 94c349dbc7Sjsg struct psp_firmware_header_v1_2 { 95c349dbc7Sjsg struct psp_firmware_header_v1_0 v1_0; 965ca02815Sjsg struct psp_fw_legacy_bin_desc res; 975ca02815Sjsg struct psp_fw_legacy_bin_desc kdb; 98c349dbc7Sjsg }; 99c349dbc7Sjsg 100ad8b1aafSjsg /* version_major=1, version_minor=3 */ 101ad8b1aafSjsg struct psp_firmware_header_v1_3 { 102ad8b1aafSjsg struct psp_firmware_header_v1_1 v1_1; 1035ca02815Sjsg struct psp_fw_legacy_bin_desc spl; 1045ca02815Sjsg struct psp_fw_legacy_bin_desc rl; 1055ca02815Sjsg struct psp_fw_legacy_bin_desc sys_drv_aux; 1065ca02815Sjsg struct psp_fw_legacy_bin_desc sos_aux; 1075ca02815Sjsg }; 1085ca02815Sjsg 1095ca02815Sjsg struct psp_fw_bin_desc { 1105ca02815Sjsg uint32_t fw_type; 1115ca02815Sjsg uint32_t fw_version; 1125ca02815Sjsg uint32_t offset_bytes; 1135ca02815Sjsg uint32_t size_bytes; 1145ca02815Sjsg }; 1155ca02815Sjsg 1165ca02815Sjsg enum psp_fw_type { 1175ca02815Sjsg PSP_FW_TYPE_UNKOWN, 1185ca02815Sjsg PSP_FW_TYPE_PSP_SOS, 1195ca02815Sjsg PSP_FW_TYPE_PSP_SYS_DRV, 1205ca02815Sjsg PSP_FW_TYPE_PSP_KDB, 1215ca02815Sjsg PSP_FW_TYPE_PSP_TOC, 1225ca02815Sjsg PSP_FW_TYPE_PSP_SPL, 1235ca02815Sjsg PSP_FW_TYPE_PSP_RL, 1245ca02815Sjsg PSP_FW_TYPE_PSP_SOC_DRV, 1255ca02815Sjsg PSP_FW_TYPE_PSP_INTF_DRV, 1265ca02815Sjsg PSP_FW_TYPE_PSP_DBG_DRV, 1271bb76ff1Sjsg PSP_FW_TYPE_PSP_RAS_DRV, 128*f005ef32Sjsg PSP_FW_TYPE_MAX_INDEX, 1295ca02815Sjsg }; 1305ca02815Sjsg 1315ca02815Sjsg /* version_major=2, version_minor=0 */ 1325ca02815Sjsg struct psp_firmware_header_v2_0 { 1335ca02815Sjsg struct common_firmware_header header; 1345ca02815Sjsg uint32_t psp_fw_bin_count; 1355ca02815Sjsg struct psp_fw_bin_desc psp_fw_bin[]; 136ad8b1aafSjsg }; 137ad8b1aafSjsg 138c349dbc7Sjsg /* version_major=1, version_minor=0 */ 139c349dbc7Sjsg struct ta_firmware_header_v1_0 { 140c349dbc7Sjsg struct common_firmware_header header; 1415ca02815Sjsg struct psp_fw_legacy_bin_desc xgmi; 1425ca02815Sjsg struct psp_fw_legacy_bin_desc ras; 1435ca02815Sjsg struct psp_fw_legacy_bin_desc hdcp; 1445ca02815Sjsg struct psp_fw_legacy_bin_desc dtm; 1455ca02815Sjsg struct psp_fw_legacy_bin_desc securedisplay; 146c349dbc7Sjsg }; 147c349dbc7Sjsg 148ad8b1aafSjsg enum ta_fw_type { 149ad8b1aafSjsg TA_FW_TYPE_UNKOWN, 150ad8b1aafSjsg TA_FW_TYPE_PSP_ASD, 151ad8b1aafSjsg TA_FW_TYPE_PSP_XGMI, 152ad8b1aafSjsg TA_FW_TYPE_PSP_RAS, 153ad8b1aafSjsg TA_FW_TYPE_PSP_HDCP, 154ad8b1aafSjsg TA_FW_TYPE_PSP_DTM, 155ad8b1aafSjsg TA_FW_TYPE_PSP_RAP, 1565ca02815Sjsg TA_FW_TYPE_PSP_SECUREDISPLAY, 1575ca02815Sjsg TA_FW_TYPE_MAX_INDEX, 158ad8b1aafSjsg }; 159ad8b1aafSjsg 160ad8b1aafSjsg /* version_major=2, version_minor=0 */ 161ad8b1aafSjsg struct ta_firmware_header_v2_0 { 162ad8b1aafSjsg struct common_firmware_header header; 163ad8b1aafSjsg uint32_t ta_fw_bin_count; 1645ca02815Sjsg struct psp_fw_bin_desc ta_fw_bin[]; 165ad8b1aafSjsg }; 166ad8b1aafSjsg 167fb4d8502Sjsg /* version_major=1, version_minor=0 */ 168fb4d8502Sjsg struct gfx_firmware_header_v1_0 { 169fb4d8502Sjsg struct common_firmware_header header; 170fb4d8502Sjsg uint32_t ucode_feature_version; 171fb4d8502Sjsg uint32_t jt_offset; /* jt location */ 172fb4d8502Sjsg uint32_t jt_size; /* size of jt */ 173fb4d8502Sjsg }; 174fb4d8502Sjsg 1751bb76ff1Sjsg /* version_major=2, version_minor=0 */ 1761bb76ff1Sjsg struct gfx_firmware_header_v2_0 { 1771bb76ff1Sjsg struct common_firmware_header header; 1781bb76ff1Sjsg uint32_t ucode_feature_version; 1791bb76ff1Sjsg uint32_t ucode_size_bytes; 1801bb76ff1Sjsg uint32_t ucode_offset_bytes; 1811bb76ff1Sjsg uint32_t data_size_bytes; 1821bb76ff1Sjsg uint32_t data_offset_bytes; 1831bb76ff1Sjsg uint32_t ucode_start_addr_lo; 1841bb76ff1Sjsg uint32_t ucode_start_addr_hi; 1851bb76ff1Sjsg }; 1861bb76ff1Sjsg 187fb4d8502Sjsg /* version_major=1, version_minor=0 */ 188c349dbc7Sjsg struct mes_firmware_header_v1_0 { 189c349dbc7Sjsg struct common_firmware_header header; 190c349dbc7Sjsg uint32_t mes_ucode_version; 191c349dbc7Sjsg uint32_t mes_ucode_size_bytes; 192c349dbc7Sjsg uint32_t mes_ucode_offset_bytes; 193c349dbc7Sjsg uint32_t mes_ucode_data_version; 194c349dbc7Sjsg uint32_t mes_ucode_data_size_bytes; 195c349dbc7Sjsg uint32_t mes_ucode_data_offset_bytes; 196c349dbc7Sjsg uint32_t mes_uc_start_addr_lo; 197c349dbc7Sjsg uint32_t mes_uc_start_addr_hi; 198c349dbc7Sjsg uint32_t mes_data_start_addr_lo; 199c349dbc7Sjsg uint32_t mes_data_start_addr_hi; 200c349dbc7Sjsg }; 201c349dbc7Sjsg 202c349dbc7Sjsg /* version_major=1, version_minor=0 */ 203fb4d8502Sjsg struct rlc_firmware_header_v1_0 { 204fb4d8502Sjsg struct common_firmware_header header; 205fb4d8502Sjsg uint32_t ucode_feature_version; 206fb4d8502Sjsg uint32_t save_and_restore_offset; 207fb4d8502Sjsg uint32_t clear_state_descriptor_offset; 208fb4d8502Sjsg uint32_t avail_scratch_ram_locations; 209fb4d8502Sjsg uint32_t master_pkt_description_offset; 210fb4d8502Sjsg }; 211fb4d8502Sjsg 212fb4d8502Sjsg /* version_major=2, version_minor=0 */ 213fb4d8502Sjsg struct rlc_firmware_header_v2_0 { 214fb4d8502Sjsg struct common_firmware_header header; 215fb4d8502Sjsg uint32_t ucode_feature_version; 216fb4d8502Sjsg uint32_t jt_offset; /* jt location */ 217fb4d8502Sjsg uint32_t jt_size; /* size of jt */ 218fb4d8502Sjsg uint32_t save_and_restore_offset; 219fb4d8502Sjsg uint32_t clear_state_descriptor_offset; 220fb4d8502Sjsg uint32_t avail_scratch_ram_locations; 221fb4d8502Sjsg uint32_t reg_restore_list_size; 222fb4d8502Sjsg uint32_t reg_list_format_start; 223fb4d8502Sjsg uint32_t reg_list_format_separate_start; 224fb4d8502Sjsg uint32_t starting_offsets_start; 225fb4d8502Sjsg uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */ 226fb4d8502Sjsg uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */ 227fb4d8502Sjsg uint32_t reg_list_size_bytes; /* size of reg list array in bytes */ 228fb4d8502Sjsg uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */ 229fb4d8502Sjsg uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */ 230fb4d8502Sjsg uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */ 231fb4d8502Sjsg uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */ 232fb4d8502Sjsg uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */ 233fb4d8502Sjsg }; 234fb4d8502Sjsg 235fb4d8502Sjsg /* version_major=2, version_minor=1 */ 236fb4d8502Sjsg struct rlc_firmware_header_v2_1 { 237fb4d8502Sjsg struct rlc_firmware_header_v2_0 v2_0; 238fb4d8502Sjsg uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */ 239fb4d8502Sjsg uint32_t save_restore_list_cntl_ucode_ver; 240fb4d8502Sjsg uint32_t save_restore_list_cntl_feature_ver; 241fb4d8502Sjsg uint32_t save_restore_list_cntl_size_bytes; 242fb4d8502Sjsg uint32_t save_restore_list_cntl_offset_bytes; 243fb4d8502Sjsg uint32_t save_restore_list_gpm_ucode_ver; 244fb4d8502Sjsg uint32_t save_restore_list_gpm_feature_ver; 245fb4d8502Sjsg uint32_t save_restore_list_gpm_size_bytes; 246fb4d8502Sjsg uint32_t save_restore_list_gpm_offset_bytes; 247fb4d8502Sjsg uint32_t save_restore_list_srm_ucode_ver; 248fb4d8502Sjsg uint32_t save_restore_list_srm_feature_ver; 249fb4d8502Sjsg uint32_t save_restore_list_srm_size_bytes; 250fb4d8502Sjsg uint32_t save_restore_list_srm_offset_bytes; 251fb4d8502Sjsg }; 252fb4d8502Sjsg 2531bb76ff1Sjsg /* version_major=2, version_minor=2 */ 254ad8b1aafSjsg struct rlc_firmware_header_v2_2 { 255ad8b1aafSjsg struct rlc_firmware_header_v2_1 v2_1; 256ad8b1aafSjsg uint32_t rlc_iram_ucode_size_bytes; 257ad8b1aafSjsg uint32_t rlc_iram_ucode_offset_bytes; 258ad8b1aafSjsg uint32_t rlc_dram_ucode_size_bytes; 259ad8b1aafSjsg uint32_t rlc_dram_ucode_offset_bytes; 260ad8b1aafSjsg }; 261ad8b1aafSjsg 2621bb76ff1Sjsg /* version_major=2, version_minor=3 */ 2631bb76ff1Sjsg struct rlc_firmware_header_v2_3 { 2641bb76ff1Sjsg struct rlc_firmware_header_v2_2 v2_2; 2651bb76ff1Sjsg uint32_t rlcp_ucode_version; 2661bb76ff1Sjsg uint32_t rlcp_ucode_feature_version; 2671bb76ff1Sjsg uint32_t rlcp_ucode_size_bytes; 2681bb76ff1Sjsg uint32_t rlcp_ucode_offset_bytes; 2691bb76ff1Sjsg uint32_t rlcv_ucode_version; 2701bb76ff1Sjsg uint32_t rlcv_ucode_feature_version; 2711bb76ff1Sjsg uint32_t rlcv_ucode_size_bytes; 2721bb76ff1Sjsg uint32_t rlcv_ucode_offset_bytes; 2731bb76ff1Sjsg }; 2741bb76ff1Sjsg 2751bb76ff1Sjsg /* version_major=2, version_minor=4 */ 2761bb76ff1Sjsg struct rlc_firmware_header_v2_4 { 2771bb76ff1Sjsg struct rlc_firmware_header_v2_3 v2_3; 2781bb76ff1Sjsg uint32_t global_tap_delays_ucode_size_bytes; 2791bb76ff1Sjsg uint32_t global_tap_delays_ucode_offset_bytes; 2801bb76ff1Sjsg uint32_t se0_tap_delays_ucode_size_bytes; 2811bb76ff1Sjsg uint32_t se0_tap_delays_ucode_offset_bytes; 2821bb76ff1Sjsg uint32_t se1_tap_delays_ucode_size_bytes; 2831bb76ff1Sjsg uint32_t se1_tap_delays_ucode_offset_bytes; 2841bb76ff1Sjsg uint32_t se2_tap_delays_ucode_size_bytes; 2851bb76ff1Sjsg uint32_t se2_tap_delays_ucode_offset_bytes; 2861bb76ff1Sjsg uint32_t se3_tap_delays_ucode_size_bytes; 2871bb76ff1Sjsg uint32_t se3_tap_delays_ucode_offset_bytes; 2881bb76ff1Sjsg }; 2891bb76ff1Sjsg 290fb4d8502Sjsg /* version_major=1, version_minor=0 */ 291fb4d8502Sjsg struct sdma_firmware_header_v1_0 { 292fb4d8502Sjsg struct common_firmware_header header; 293fb4d8502Sjsg uint32_t ucode_feature_version; 294fb4d8502Sjsg uint32_t ucode_change_version; 295fb4d8502Sjsg uint32_t jt_offset; /* jt location */ 296fb4d8502Sjsg uint32_t jt_size; /* size of jt */ 297fb4d8502Sjsg }; 298fb4d8502Sjsg 299fb4d8502Sjsg /* version_major=1, version_minor=1 */ 300fb4d8502Sjsg struct sdma_firmware_header_v1_1 { 301fb4d8502Sjsg struct sdma_firmware_header_v1_0 v1_0; 302fb4d8502Sjsg uint32_t digest_size; 303fb4d8502Sjsg }; 304fb4d8502Sjsg 3051bb76ff1Sjsg /* version_major=2, version_minor=0 */ 3061bb76ff1Sjsg struct sdma_firmware_header_v2_0 { 3071bb76ff1Sjsg struct common_firmware_header header; 3081bb76ff1Sjsg uint32_t ucode_feature_version; 3091bb76ff1Sjsg uint32_t ctx_ucode_size_bytes; /* context thread ucode size */ 3101bb76ff1Sjsg uint32_t ctx_jt_offset; /* context thread jt location */ 3111bb76ff1Sjsg uint32_t ctx_jt_size; /* context thread size of jt */ 3121bb76ff1Sjsg uint32_t ctl_ucode_offset; 3131bb76ff1Sjsg uint32_t ctl_ucode_size_bytes; /* control thread ucode size */ 3141bb76ff1Sjsg uint32_t ctl_jt_offset; /* control thread jt location */ 3151bb76ff1Sjsg uint32_t ctl_jt_size; /* control thread size of jt */ 3161bb76ff1Sjsg }; 3171bb76ff1Sjsg 318fb4d8502Sjsg /* gpu info payload */ 319fb4d8502Sjsg struct gpu_info_firmware_v1_0 { 320fb4d8502Sjsg uint32_t gc_num_se; 321fb4d8502Sjsg uint32_t gc_num_cu_per_sh; 322fb4d8502Sjsg uint32_t gc_num_sh_per_se; 323fb4d8502Sjsg uint32_t gc_num_rb_per_se; 324fb4d8502Sjsg uint32_t gc_num_tccs; 325fb4d8502Sjsg uint32_t gc_num_gprs; 326fb4d8502Sjsg uint32_t gc_num_max_gs_thds; 327fb4d8502Sjsg uint32_t gc_gs_table_depth; 328fb4d8502Sjsg uint32_t gc_gsprim_buff_depth; 329fb4d8502Sjsg uint32_t gc_parameter_cache_depth; 330fb4d8502Sjsg uint32_t gc_double_offchip_lds_buffer; 331fb4d8502Sjsg uint32_t gc_wave_size; 332fb4d8502Sjsg uint32_t gc_max_waves_per_simd; 333fb4d8502Sjsg uint32_t gc_max_scratch_slots_per_cu; 334fb4d8502Sjsg uint32_t gc_lds_size; 335fb4d8502Sjsg }; 336fb4d8502Sjsg 337c349dbc7Sjsg struct gpu_info_firmware_v1_1 { 338c349dbc7Sjsg struct gpu_info_firmware_v1_0 v1_0; 339c349dbc7Sjsg uint32_t num_sc_per_sh; 340c349dbc7Sjsg uint32_t num_packer_per_sc; 341c349dbc7Sjsg }; 342c349dbc7Sjsg 343c349dbc7Sjsg /* gpu info payload 344c349dbc7Sjsg * version_major=1, version_minor=1 */ 345c349dbc7Sjsg struct gpu_info_firmware_v1_2 { 346c349dbc7Sjsg struct gpu_info_firmware_v1_1 v1_1; 347c349dbc7Sjsg struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box; 348c349dbc7Sjsg }; 349c349dbc7Sjsg 350fb4d8502Sjsg /* version_major=1, version_minor=0 */ 351fb4d8502Sjsg struct gpu_info_firmware_header_v1_0 { 352fb4d8502Sjsg struct common_firmware_header header; 353fb4d8502Sjsg uint16_t version_major; /* version */ 354fb4d8502Sjsg uint16_t version_minor; /* version */ 355fb4d8502Sjsg }; 356fb4d8502Sjsg 3572c4a196eSkettenis /* version_major=1, version_minor=0 */ 3582c4a196eSkettenis struct dmcu_firmware_header_v1_0 { 3592c4a196eSkettenis struct common_firmware_header header; 3602c4a196eSkettenis uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */ 3612c4a196eSkettenis uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */ 3622c4a196eSkettenis }; 3632c4a196eSkettenis 364c349dbc7Sjsg /* version_major=1, version_minor=0 */ 365c349dbc7Sjsg struct dmcub_firmware_header_v1_0 { 366c349dbc7Sjsg struct common_firmware_header header; 367c349dbc7Sjsg uint32_t inst_const_bytes; /* size of instruction region, in bytes */ 368c349dbc7Sjsg uint32_t bss_data_bytes; /* size of bss/data region, in bytes */ 369c349dbc7Sjsg }; 370c349dbc7Sjsg 3711bb76ff1Sjsg /* version_major=1, version_minor=0 */ 3721bb76ff1Sjsg struct imu_firmware_header_v1_0 { 3731bb76ff1Sjsg struct common_firmware_header header; 3741bb76ff1Sjsg uint32_t imu_iram_ucode_size_bytes; 3751bb76ff1Sjsg uint32_t imu_iram_ucode_offset_bytes; 3761bb76ff1Sjsg uint32_t imu_dram_ucode_size_bytes; 3771bb76ff1Sjsg uint32_t imu_dram_ucode_offset_bytes; 3781bb76ff1Sjsg }; 3791bb76ff1Sjsg 380fb4d8502Sjsg /* header is fixed size */ 381fb4d8502Sjsg union amdgpu_firmware_header { 382fb4d8502Sjsg struct common_firmware_header common; 383fb4d8502Sjsg struct mc_firmware_header_v1_0 mc; 384fb4d8502Sjsg struct smc_firmware_header_v1_0 smc; 385c349dbc7Sjsg struct smc_firmware_header_v2_0 smc_v2_0; 386fb4d8502Sjsg struct psp_firmware_header_v1_0 psp; 387c349dbc7Sjsg struct psp_firmware_header_v1_1 psp_v1_1; 388ad8b1aafSjsg struct psp_firmware_header_v1_3 psp_v1_3; 3895ca02815Sjsg struct psp_firmware_header_v2_0 psp_v2_0; 390c349dbc7Sjsg struct ta_firmware_header_v1_0 ta; 391ad8b1aafSjsg struct ta_firmware_header_v2_0 ta_v2_0; 392fb4d8502Sjsg struct gfx_firmware_header_v1_0 gfx; 3931bb76ff1Sjsg struct gfx_firmware_header_v2_0 gfx_v2_0; 394fb4d8502Sjsg struct rlc_firmware_header_v1_0 rlc; 395fb4d8502Sjsg struct rlc_firmware_header_v2_0 rlc_v2_0; 396fb4d8502Sjsg struct rlc_firmware_header_v2_1 rlc_v2_1; 3971bb76ff1Sjsg struct rlc_firmware_header_v2_2 rlc_v2_2; 3981bb76ff1Sjsg struct rlc_firmware_header_v2_3 rlc_v2_3; 3991bb76ff1Sjsg struct rlc_firmware_header_v2_4 rlc_v2_4; 400fb4d8502Sjsg struct sdma_firmware_header_v1_0 sdma; 401fb4d8502Sjsg struct sdma_firmware_header_v1_1 sdma_v1_1; 4021bb76ff1Sjsg struct sdma_firmware_header_v2_0 sdma_v2_0; 403fb4d8502Sjsg struct gpu_info_firmware_header_v1_0 gpu_info; 4042c4a196eSkettenis struct dmcu_firmware_header_v1_0 dmcu; 405c349dbc7Sjsg struct dmcub_firmware_header_v1_0 dmcub; 4061bb76ff1Sjsg struct imu_firmware_header_v1_0 imu; 407fb4d8502Sjsg uint8_t raw[0x100]; 408fb4d8502Sjsg }; 409fb4d8502Sjsg 4105ca02815Sjsg #define UCODE_MAX_PSP_PACKAGING ((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc)) 411ad8b1aafSjsg 412fb4d8502Sjsg /* 413fb4d8502Sjsg * fw loading support 414fb4d8502Sjsg */ 415fb4d8502Sjsg enum AMDGPU_UCODE_ID { 4161bb76ff1Sjsg AMDGPU_UCODE_ID_CAP = 0, 4171bb76ff1Sjsg AMDGPU_UCODE_ID_SDMA0, 418fb4d8502Sjsg AMDGPU_UCODE_ID_SDMA1, 419c349dbc7Sjsg AMDGPU_UCODE_ID_SDMA2, 420c349dbc7Sjsg AMDGPU_UCODE_ID_SDMA3, 421c349dbc7Sjsg AMDGPU_UCODE_ID_SDMA4, 422c349dbc7Sjsg AMDGPU_UCODE_ID_SDMA5, 423c349dbc7Sjsg AMDGPU_UCODE_ID_SDMA6, 424c349dbc7Sjsg AMDGPU_UCODE_ID_SDMA7, 4251bb76ff1Sjsg AMDGPU_UCODE_ID_SDMA_UCODE_TH0, 4261bb76ff1Sjsg AMDGPU_UCODE_ID_SDMA_UCODE_TH1, 427fb4d8502Sjsg AMDGPU_UCODE_ID_CP_CE, 428fb4d8502Sjsg AMDGPU_UCODE_ID_CP_PFP, 429fb4d8502Sjsg AMDGPU_UCODE_ID_CP_ME, 4301bb76ff1Sjsg AMDGPU_UCODE_ID_CP_RS64_PFP, 4311bb76ff1Sjsg AMDGPU_UCODE_ID_CP_RS64_ME, 4321bb76ff1Sjsg AMDGPU_UCODE_ID_CP_RS64_MEC, 4331bb76ff1Sjsg AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK, 4341bb76ff1Sjsg AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK, 4351bb76ff1Sjsg AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK, 4361bb76ff1Sjsg AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK, 4371bb76ff1Sjsg AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK, 4381bb76ff1Sjsg AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK, 4391bb76ff1Sjsg AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK, 4401bb76ff1Sjsg AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK, 441fb4d8502Sjsg AMDGPU_UCODE_ID_CP_MEC1, 442fb4d8502Sjsg AMDGPU_UCODE_ID_CP_MEC1_JT, 443fb4d8502Sjsg AMDGPU_UCODE_ID_CP_MEC2, 444fb4d8502Sjsg AMDGPU_UCODE_ID_CP_MEC2_JT, 445c349dbc7Sjsg AMDGPU_UCODE_ID_CP_MES, 446c349dbc7Sjsg AMDGPU_UCODE_ID_CP_MES_DATA, 4471bb76ff1Sjsg AMDGPU_UCODE_ID_CP_MES1, 4481bb76ff1Sjsg AMDGPU_UCODE_ID_CP_MES1_DATA, 4491bb76ff1Sjsg AMDGPU_UCODE_ID_IMU_I, 4501bb76ff1Sjsg AMDGPU_UCODE_ID_IMU_D, 4511bb76ff1Sjsg AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS, 4521bb76ff1Sjsg AMDGPU_UCODE_ID_SE0_TAP_DELAYS, 4531bb76ff1Sjsg AMDGPU_UCODE_ID_SE1_TAP_DELAYS, 4541bb76ff1Sjsg AMDGPU_UCODE_ID_SE2_TAP_DELAYS, 4551bb76ff1Sjsg AMDGPU_UCODE_ID_SE3_TAP_DELAYS, 456fb4d8502Sjsg AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL, 457fb4d8502Sjsg AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM, 458fb4d8502Sjsg AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM, 459ad8b1aafSjsg AMDGPU_UCODE_ID_RLC_IRAM, 460ad8b1aafSjsg AMDGPU_UCODE_ID_RLC_DRAM, 4611bb76ff1Sjsg AMDGPU_UCODE_ID_RLC_P, 4621bb76ff1Sjsg AMDGPU_UCODE_ID_RLC_V, 463c349dbc7Sjsg AMDGPU_UCODE_ID_RLC_G, 464fb4d8502Sjsg AMDGPU_UCODE_ID_STORAGE, 465fb4d8502Sjsg AMDGPU_UCODE_ID_SMC, 4661bb76ff1Sjsg AMDGPU_UCODE_ID_PPTABLE, 467fb4d8502Sjsg AMDGPU_UCODE_ID_UVD, 468c349dbc7Sjsg AMDGPU_UCODE_ID_UVD1, 469fb4d8502Sjsg AMDGPU_UCODE_ID_VCE, 470fb4d8502Sjsg AMDGPU_UCODE_ID_VCN, 471c349dbc7Sjsg AMDGPU_UCODE_ID_VCN1, 4722c4a196eSkettenis AMDGPU_UCODE_ID_DMCU_ERAM, 4732c4a196eSkettenis AMDGPU_UCODE_ID_DMCU_INTV, 474c349dbc7Sjsg AMDGPU_UCODE_ID_VCN0_RAM, 475c349dbc7Sjsg AMDGPU_UCODE_ID_VCN1_RAM, 476c349dbc7Sjsg AMDGPU_UCODE_ID_DMCUB, 477fb4d8502Sjsg AMDGPU_UCODE_ID_MAXIMUM, 478fb4d8502Sjsg }; 479fb4d8502Sjsg 480fb4d8502Sjsg /* engine firmware status */ 481fb4d8502Sjsg enum AMDGPU_UCODE_STATUS { 482fb4d8502Sjsg AMDGPU_UCODE_STATUS_INVALID, 483fb4d8502Sjsg AMDGPU_UCODE_STATUS_NOT_LOADED, 484fb4d8502Sjsg AMDGPU_UCODE_STATUS_LOADED, 485fb4d8502Sjsg }; 486fb4d8502Sjsg 487c349dbc7Sjsg enum amdgpu_firmware_load_type { 488c349dbc7Sjsg AMDGPU_FW_LOAD_DIRECT = 0, 489c349dbc7Sjsg AMDGPU_FW_LOAD_PSP, 4901bb76ff1Sjsg AMDGPU_FW_LOAD_SMU, 491c349dbc7Sjsg AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO, 492c349dbc7Sjsg }; 493c349dbc7Sjsg 494fb4d8502Sjsg /* conform to smu_ucode_xfer_cz.h */ 495fb4d8502Sjsg #define AMDGPU_SDMA0_UCODE_LOADED 0x00000001 496fb4d8502Sjsg #define AMDGPU_SDMA1_UCODE_LOADED 0x00000002 497fb4d8502Sjsg #define AMDGPU_CPCE_UCODE_LOADED 0x00000004 498fb4d8502Sjsg #define AMDGPU_CPPFP_UCODE_LOADED 0x00000008 499fb4d8502Sjsg #define AMDGPU_CPME_UCODE_LOADED 0x00000010 500fb4d8502Sjsg #define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020 501fb4d8502Sjsg #define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040 502fb4d8502Sjsg #define AMDGPU_CPRLC_UCODE_LOADED 0x00000100 503fb4d8502Sjsg 504fb4d8502Sjsg /* amdgpu firmware info */ 505fb4d8502Sjsg struct amdgpu_firmware_info { 506fb4d8502Sjsg /* ucode ID */ 507fb4d8502Sjsg enum AMDGPU_UCODE_ID ucode_id; 508fb4d8502Sjsg /* request_firmware */ 509fb4d8502Sjsg const struct firmware *fw; 510fb4d8502Sjsg /* starting mc address */ 511fb4d8502Sjsg uint64_t mc_addr; 512fb4d8502Sjsg /* kernel linear address */ 513fb4d8502Sjsg void *kaddr; 514fb4d8502Sjsg /* ucode_size_bytes */ 515fb4d8502Sjsg uint32_t ucode_size; 516fb4d8502Sjsg /* starting tmr mc address */ 517fb4d8502Sjsg uint32_t tmr_mc_addr_lo; 518fb4d8502Sjsg uint32_t tmr_mc_addr_hi; 519fb4d8502Sjsg }; 520fb4d8502Sjsg 521c349dbc7Sjsg struct amdgpu_firmware { 522c349dbc7Sjsg struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 523c349dbc7Sjsg enum amdgpu_firmware_load_type load_type; 524c349dbc7Sjsg struct amdgpu_bo *fw_buf; 525c349dbc7Sjsg unsigned int fw_size; 526c349dbc7Sjsg unsigned int max_ucodes; 527c349dbc7Sjsg /* firmwares are loaded by psp instead of smu from vega10 */ 528c349dbc7Sjsg const struct amdgpu_psp_funcs *funcs; 529c349dbc7Sjsg struct amdgpu_bo *rbuf; 530c349dbc7Sjsg struct rwlock mutex; 531c349dbc7Sjsg 532c349dbc7Sjsg /* gpu info firmware data pointer */ 533c349dbc7Sjsg const struct firmware *gpu_info_fw; 534c349dbc7Sjsg 535c349dbc7Sjsg void *fw_buf_ptr; 536c349dbc7Sjsg uint64_t fw_buf_mc; 537c349dbc7Sjsg }; 538c349dbc7Sjsg 539fb4d8502Sjsg void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr); 540fb4d8502Sjsg void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr); 541*f005ef32Sjsg void amdgpu_ucode_print_imu_hdr(const struct common_firmware_header *hdr); 542fb4d8502Sjsg void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr); 543fb4d8502Sjsg void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr); 544fb4d8502Sjsg void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); 545c349dbc7Sjsg void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr); 546fb4d8502Sjsg void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr); 54736022db4Sjsg int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw, 54836022db4Sjsg const char *fw_name); 54936022db4Sjsg void amdgpu_ucode_release(const struct firmware **fw); 550fb4d8502Sjsg bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 551fb4d8502Sjsg uint16_t hdr_major, uint16_t hdr_minor); 552c349dbc7Sjsg 553fb4d8502Sjsg int amdgpu_ucode_init_bo(struct amdgpu_device *adev); 554c349dbc7Sjsg int amdgpu_ucode_create_bo(struct amdgpu_device *adev); 555c349dbc7Sjsg int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev); 556c349dbc7Sjsg void amdgpu_ucode_free_bo(struct amdgpu_device *adev); 557c349dbc7Sjsg void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev); 558fb4d8502Sjsg 559fb4d8502Sjsg enum amdgpu_firmware_load_type 560fb4d8502Sjsg amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type); 561fb4d8502Sjsg 5625ca02815Sjsg const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id); 5635ca02815Sjsg 5641bb76ff1Sjsg void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len); 5651bb76ff1Sjsg 566fb4d8502Sjsg #endif 567