1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "df_v3_6.h" 25 26 #include "df/df_3_6_default.h" 27 #include "df/df_3_6_offset.h" 28 #include "df/df_3_6_sh_mask.h" 29 30 #define DF_3_6_SMN_REG_INST_DIST 0x8 31 #define DF_3_6_INST_CNT 8 32 33 static u32 df_v3_6_channel_number[] = {1, 2, 0, 4, 0, 8, 0, 34 16, 32, 0, 0, 0, 2, 4, 8}; 35 36 #ifdef __linux__ 37 /* init df format attrs */ 38 AMDGPU_PMU_ATTR(event, "config:0-7"); 39 AMDGPU_PMU_ATTR(instance, "config:8-15"); 40 AMDGPU_PMU_ATTR(umask, "config:16-23"); 41 42 /* df format attributes */ 43 static struct attribute *df_v3_6_format_attrs[] = { 44 &pmu_attr_event.attr, 45 &pmu_attr_instance.attr, 46 &pmu_attr_umask.attr, 47 NULL 48 }; 49 50 /* df format attribute group */ 51 static struct attribute_group df_v3_6_format_attr_group = { 52 .name = "format", 53 .attrs = df_v3_6_format_attrs, 54 }; 55 56 /* df event attrs */ 57 AMDGPU_PMU_ATTR(cake0_pcsout_txdata, 58 "event=0x7,instance=0x46,umask=0x2"); 59 AMDGPU_PMU_ATTR(cake1_pcsout_txdata, 60 "event=0x7,instance=0x47,umask=0x2"); 61 AMDGPU_PMU_ATTR(cake0_pcsout_txmeta, 62 "event=0x7,instance=0x46,umask=0x4"); 63 AMDGPU_PMU_ATTR(cake1_pcsout_txmeta, 64 "event=0x7,instance=0x47,umask=0x4"); 65 AMDGPU_PMU_ATTR(cake0_ftiinstat_reqalloc, 66 "event=0xb,instance=0x46,umask=0x4"); 67 AMDGPU_PMU_ATTR(cake1_ftiinstat_reqalloc, 68 "event=0xb,instance=0x47,umask=0x4"); 69 AMDGPU_PMU_ATTR(cake0_ftiinstat_rspalloc, 70 "event=0xb,instance=0x46,umask=0x8"); 71 AMDGPU_PMU_ATTR(cake1_ftiinstat_rspalloc, 72 "event=0xb,instance=0x47,umask=0x8"); 73 74 /* df event attributes */ 75 static struct attribute *df_v3_6_event_attrs[] = { 76 &pmu_attr_cake0_pcsout_txdata.attr, 77 &pmu_attr_cake1_pcsout_txdata.attr, 78 &pmu_attr_cake0_pcsout_txmeta.attr, 79 &pmu_attr_cake1_pcsout_txmeta.attr, 80 &pmu_attr_cake0_ftiinstat_reqalloc.attr, 81 &pmu_attr_cake1_ftiinstat_reqalloc.attr, 82 &pmu_attr_cake0_ftiinstat_rspalloc.attr, 83 &pmu_attr_cake1_ftiinstat_rspalloc.attr, 84 NULL 85 }; 86 87 /* df event attribute group */ 88 static struct attribute_group df_v3_6_event_attr_group = { 89 .name = "events", 90 .attrs = df_v3_6_event_attrs 91 }; 92 93 /* df event attr groups */ 94 const struct attribute_group *df_v3_6_attr_groups[] = { 95 &df_v3_6_format_attr_group, 96 &df_v3_6_event_attr_group, 97 NULL 98 }; 99 100 #endif /* __linux__ */ 101 102 static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev, 103 uint32_t ficaa_val) 104 { 105 unsigned long flags, address, data; 106 uint32_t ficadl_val, ficadh_val; 107 108 address = adev->nbio.funcs->get_pcie_index_offset(adev); 109 data = adev->nbio.funcs->get_pcie_data_offset(adev); 110 111 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 112 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3); 113 WREG32(data, ficaa_val); 114 115 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3); 116 ficadl_val = RREG32(data); 117 118 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3); 119 ficadh_val = RREG32(data); 120 121 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 122 123 return (((ficadh_val & 0xFFFFFFFFFFFFFFFF) << 32) | ficadl_val); 124 } 125 126 static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val, 127 uint32_t ficadl_val, uint32_t ficadh_val) 128 { 129 unsigned long flags, address, data; 130 131 address = adev->nbio.funcs->get_pcie_index_offset(adev); 132 data = adev->nbio.funcs->get_pcie_data_offset(adev); 133 134 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 135 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3); 136 WREG32(data, ficaa_val); 137 138 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3); 139 WREG32(data, ficadl_val); 140 141 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3); 142 WREG32(data, ficadh_val); 143 144 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 145 } 146 147 /* 148 * df_v3_6_perfmon_rreg - read perfmon lo and hi 149 * 150 * required to be atomic. no mmio method provided so subsequent reads for lo 151 * and hi require to preserve df finite state machine 152 */ 153 static void df_v3_6_perfmon_rreg(struct amdgpu_device *adev, 154 uint32_t lo_addr, uint32_t *lo_val, 155 uint32_t hi_addr, uint32_t *hi_val) 156 { 157 unsigned long flags, address, data; 158 159 address = adev->nbio.funcs->get_pcie_index_offset(adev); 160 data = adev->nbio.funcs->get_pcie_data_offset(adev); 161 162 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 163 WREG32(address, lo_addr); 164 *lo_val = RREG32(data); 165 WREG32(address, hi_addr); 166 *hi_val = RREG32(data); 167 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 168 } 169 170 /* 171 * df_v3_6_perfmon_wreg - write to perfmon lo and hi 172 * 173 * required to be atomic. no mmio method provided so subsequent reads after 174 * data writes cannot occur to preserve data fabrics finite state machine. 175 */ 176 static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr, 177 uint32_t lo_val, uint32_t hi_addr, uint32_t hi_val) 178 { 179 unsigned long flags, address, data; 180 181 address = adev->nbio.funcs->get_pcie_index_offset(adev); 182 data = adev->nbio.funcs->get_pcie_data_offset(adev); 183 184 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 185 WREG32(address, lo_addr); 186 WREG32(data, lo_val); 187 WREG32(address, hi_addr); 188 WREG32(data, hi_val); 189 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 190 } 191 192 /* same as perfmon_wreg but return status on write value check */ 193 static int df_v3_6_perfmon_arm_with_status(struct amdgpu_device *adev, 194 uint32_t lo_addr, uint32_t lo_val, 195 uint32_t hi_addr, uint32_t hi_val) 196 { 197 unsigned long flags, address, data; 198 uint32_t lo_val_rb, hi_val_rb; 199 200 address = adev->nbio.funcs->get_pcie_index_offset(adev); 201 data = adev->nbio.funcs->get_pcie_data_offset(adev); 202 203 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 204 WREG32(address, lo_addr); 205 WREG32(data, lo_val); 206 WREG32(address, hi_addr); 207 WREG32(data, hi_val); 208 209 WREG32(address, lo_addr); 210 lo_val_rb = RREG32(data); 211 WREG32(address, hi_addr); 212 hi_val_rb = RREG32(data); 213 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 214 215 if (!(lo_val == lo_val_rb && hi_val == hi_val_rb)) 216 return -EBUSY; 217 218 return 0; 219 } 220 221 222 /* 223 * retry arming counters every 100 usecs within 1 millisecond interval. 224 * if retry fails after time out, return error. 225 */ 226 #define ARM_RETRY_USEC_TIMEOUT 1000 227 #define ARM_RETRY_USEC_INTERVAL 100 228 static int df_v3_6_perfmon_arm_with_retry(struct amdgpu_device *adev, 229 uint32_t lo_addr, uint32_t lo_val, 230 uint32_t hi_addr, uint32_t hi_val) 231 { 232 int countdown = ARM_RETRY_USEC_TIMEOUT; 233 234 while (countdown) { 235 236 if (!df_v3_6_perfmon_arm_with_status(adev, lo_addr, lo_val, 237 hi_addr, hi_val)) 238 break; 239 240 countdown -= ARM_RETRY_USEC_INTERVAL; 241 udelay(ARM_RETRY_USEC_INTERVAL); 242 } 243 244 return countdown > 0 ? 0 : -ETIME; 245 } 246 247 /* get the number of df counters available */ 248 static ssize_t df_v3_6_get_df_cntr_avail(struct device *dev, 249 struct device_attribute *attr, 250 char *buf) 251 { 252 struct amdgpu_device *adev; 253 struct drm_device *ddev; 254 int i, count; 255 256 ddev = dev_get_drvdata(dev); 257 adev = ddev->dev_private; 258 count = 0; 259 260 for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) { 261 if (adev->df_perfmon_config_assign_mask[i] == 0) 262 count++; 263 } 264 265 return snprintf(buf, PAGE_SIZE, "%i\n", count); 266 } 267 268 /* device attr for available perfmon counters */ 269 static DEVICE_ATTR(df_cntr_avail, S_IRUGO, df_v3_6_get_df_cntr_avail, NULL); 270 271 static void df_v3_6_query_hashes(struct amdgpu_device *adev) 272 { 273 u32 tmp; 274 275 adev->df.hash_status.hash_64k = false; 276 adev->df.hash_status.hash_2m = false; 277 adev->df.hash_status.hash_1g = false; 278 279 if (adev->asic_type != CHIP_ARCTURUS) 280 return; 281 282 /* encoding for hash-enabled on Arcturus */ 283 if (adev->df.funcs->get_fb_channel_number(adev) == 0xe) { 284 tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DfGlobalCtrl); 285 adev->df.hash_status.hash_64k = REG_GET_FIELD(tmp, 286 DF_CS_UMC_AON0_DfGlobalCtrl, 287 GlbHashIntlvCtl64K); 288 adev->df.hash_status.hash_2m = REG_GET_FIELD(tmp, 289 DF_CS_UMC_AON0_DfGlobalCtrl, 290 GlbHashIntlvCtl2M); 291 adev->df.hash_status.hash_1g = REG_GET_FIELD(tmp, 292 DF_CS_UMC_AON0_DfGlobalCtrl, 293 GlbHashIntlvCtl1G); 294 } 295 } 296 297 /* init perfmons */ 298 static void df_v3_6_sw_init(struct amdgpu_device *adev) 299 { 300 int i, ret; 301 302 ret = device_create_file(adev->dev, &dev_attr_df_cntr_avail); 303 if (ret) 304 DRM_ERROR("failed to create file for available df counters\n"); 305 306 for (i = 0; i < AMDGPU_MAX_DF_PERFMONS; i++) 307 adev->df_perfmon_config_assign_mask[i] = 0; 308 309 df_v3_6_query_hashes(adev); 310 } 311 312 static void df_v3_6_sw_fini(struct amdgpu_device *adev) 313 { 314 315 device_remove_file(adev->dev, &dev_attr_df_cntr_avail); 316 317 } 318 319 static void df_v3_6_enable_broadcast_mode(struct amdgpu_device *adev, 320 bool enable) 321 { 322 u32 tmp; 323 324 if (enable) { 325 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl); 326 tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK; 327 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp); 328 } else 329 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, 330 mmFabricConfigAccessControl_DEFAULT); 331 } 332 333 static u32 df_v3_6_get_fb_channel_number(struct amdgpu_device *adev) 334 { 335 u32 tmp; 336 337 tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0); 338 tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK; 339 tmp >>= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; 340 341 return tmp; 342 } 343 344 static u32 df_v3_6_get_hbm_channel_number(struct amdgpu_device *adev) 345 { 346 int fb_channel_number; 347 348 fb_channel_number = adev->df.funcs->get_fb_channel_number(adev); 349 if (fb_channel_number >= ARRAY_SIZE(df_v3_6_channel_number)) 350 fb_channel_number = 0; 351 352 return df_v3_6_channel_number[fb_channel_number]; 353 } 354 355 static void df_v3_6_update_medium_grain_clock_gating(struct amdgpu_device *adev, 356 bool enable) 357 { 358 u32 tmp; 359 360 if (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG) { 361 /* Put DF on broadcast mode */ 362 adev->df.funcs->enable_broadcast_mode(adev, true); 363 364 if (enable) { 365 tmp = RREG32_SOC15(DF, 0, 366 mmDF_PIE_AON0_DfGlobalClkGater); 367 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK; 368 tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY; 369 WREG32_SOC15(DF, 0, 370 mmDF_PIE_AON0_DfGlobalClkGater, tmp); 371 } else { 372 tmp = RREG32_SOC15(DF, 0, 373 mmDF_PIE_AON0_DfGlobalClkGater); 374 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK; 375 tmp |= DF_V3_6_MGCG_DISABLE; 376 WREG32_SOC15(DF, 0, 377 mmDF_PIE_AON0_DfGlobalClkGater, tmp); 378 } 379 380 /* Exit broadcast mode */ 381 adev->df.funcs->enable_broadcast_mode(adev, false); 382 } 383 } 384 385 static void df_v3_6_get_clockgating_state(struct amdgpu_device *adev, 386 u32 *flags) 387 { 388 u32 tmp; 389 390 /* AMD_CG_SUPPORT_DF_MGCG */ 391 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); 392 if (tmp & DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY) 393 *flags |= AMD_CG_SUPPORT_DF_MGCG; 394 } 395 396 /* get assigned df perfmon ctr as int */ 397 static int df_v3_6_pmc_config_2_cntr(struct amdgpu_device *adev, 398 uint64_t config) 399 { 400 int i; 401 402 for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) { 403 if ((config & 0x0FFFFFFUL) == 404 adev->df_perfmon_config_assign_mask[i]) 405 return i; 406 } 407 408 return -EINVAL; 409 } 410 411 /* get address based on counter assignment */ 412 static void df_v3_6_pmc_get_addr(struct amdgpu_device *adev, 413 uint64_t config, 414 int is_ctrl, 415 uint32_t *lo_base_addr, 416 uint32_t *hi_base_addr) 417 { 418 int target_cntr = df_v3_6_pmc_config_2_cntr(adev, config); 419 420 if (target_cntr < 0) 421 return; 422 423 switch (target_cntr) { 424 425 case 0: 426 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo4 : smnPerfMonCtrLo4; 427 *hi_base_addr = is_ctrl ? smnPerfMonCtlHi4 : smnPerfMonCtrHi4; 428 break; 429 case 1: 430 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo5 : smnPerfMonCtrLo5; 431 *hi_base_addr = is_ctrl ? smnPerfMonCtlHi5 : smnPerfMonCtrHi5; 432 break; 433 case 2: 434 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo6 : smnPerfMonCtrLo6; 435 *hi_base_addr = is_ctrl ? smnPerfMonCtlHi6 : smnPerfMonCtrHi6; 436 break; 437 case 3: 438 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo7 : smnPerfMonCtrLo7; 439 *hi_base_addr = is_ctrl ? smnPerfMonCtlHi7 : smnPerfMonCtrHi7; 440 break; 441 442 } 443 444 } 445 446 /* get read counter address */ 447 static void df_v3_6_pmc_get_read_settings(struct amdgpu_device *adev, 448 uint64_t config, 449 uint32_t *lo_base_addr, 450 uint32_t *hi_base_addr) 451 { 452 df_v3_6_pmc_get_addr(adev, config, 0, lo_base_addr, hi_base_addr); 453 } 454 455 /* get control counter settings i.e. address and values to set */ 456 static int df_v3_6_pmc_get_ctrl_settings(struct amdgpu_device *adev, 457 uint64_t config, 458 uint32_t *lo_base_addr, 459 uint32_t *hi_base_addr, 460 uint32_t *lo_val, 461 uint32_t *hi_val) 462 { 463 464 uint32_t eventsel, instance, unitmask; 465 uint32_t instance_10, instance_5432, instance_76; 466 467 df_v3_6_pmc_get_addr(adev, config, 1, lo_base_addr, hi_base_addr); 468 469 if ((*lo_base_addr == 0) || (*hi_base_addr == 0)) { 470 DRM_ERROR("[DF PMC] addressing not retrieved! Lo: %x, Hi: %x", 471 *lo_base_addr, *hi_base_addr); 472 return -ENXIO; 473 } 474 475 eventsel = DF_V3_6_GET_EVENT(config) & 0x3f; 476 unitmask = DF_V3_6_GET_UNITMASK(config) & 0xf; 477 instance = DF_V3_6_GET_INSTANCE(config); 478 479 instance_10 = instance & 0x3; 480 instance_5432 = (instance >> 2) & 0xf; 481 instance_76 = (instance >> 6) & 0x3; 482 483 *lo_val = (unitmask << 8) | (instance_10 << 6) | eventsel | (1 << 22); 484 *hi_val = (instance_76 << 29) | instance_5432; 485 486 DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x", 487 config, *lo_base_addr, *hi_base_addr, *lo_val, *hi_val); 488 489 return 0; 490 } 491 492 /* add df performance counters for read */ 493 static int df_v3_6_pmc_add_cntr(struct amdgpu_device *adev, 494 uint64_t config) 495 { 496 int i, target_cntr; 497 498 target_cntr = df_v3_6_pmc_config_2_cntr(adev, config); 499 500 if (target_cntr >= 0) 501 return 0; 502 503 for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) { 504 if (adev->df_perfmon_config_assign_mask[i] == 0U) { 505 adev->df_perfmon_config_assign_mask[i] = 506 config & 0x0FFFFFFUL; 507 return 0; 508 } 509 } 510 511 return -ENOSPC; 512 } 513 514 #define DEFERRED_ARM_MASK (1 << 31) 515 static int df_v3_6_pmc_set_deferred(struct amdgpu_device *adev, 516 uint64_t config, bool is_deferred) 517 { 518 int target_cntr; 519 520 target_cntr = df_v3_6_pmc_config_2_cntr(adev, config); 521 522 if (target_cntr < 0) 523 return -EINVAL; 524 525 if (is_deferred) 526 adev->df_perfmon_config_assign_mask[target_cntr] |= 527 DEFERRED_ARM_MASK; 528 else 529 adev->df_perfmon_config_assign_mask[target_cntr] &= 530 ~DEFERRED_ARM_MASK; 531 532 return 0; 533 } 534 535 static bool df_v3_6_pmc_is_deferred(struct amdgpu_device *adev, 536 uint64_t config) 537 { 538 int target_cntr; 539 540 target_cntr = df_v3_6_pmc_config_2_cntr(adev, config); 541 542 /* 543 * we never get target_cntr < 0 since this funciton is only called in 544 * pmc_count for now but we should check anyways. 545 */ 546 return (target_cntr >= 0 && 547 (adev->df_perfmon_config_assign_mask[target_cntr] 548 & DEFERRED_ARM_MASK)); 549 550 } 551 552 /* release performance counter */ 553 static void df_v3_6_pmc_release_cntr(struct amdgpu_device *adev, 554 uint64_t config) 555 { 556 int target_cntr = df_v3_6_pmc_config_2_cntr(adev, config); 557 558 if (target_cntr >= 0) 559 adev->df_perfmon_config_assign_mask[target_cntr] = 0ULL; 560 } 561 562 563 static void df_v3_6_reset_perfmon_cntr(struct amdgpu_device *adev, 564 uint64_t config) 565 { 566 uint32_t lo_base_addr, hi_base_addr; 567 568 df_v3_6_pmc_get_read_settings(adev, config, &lo_base_addr, 569 &hi_base_addr); 570 571 if ((lo_base_addr == 0) || (hi_base_addr == 0)) 572 return; 573 574 df_v3_6_perfmon_wreg(adev, lo_base_addr, 0, hi_base_addr, 0); 575 } 576 577 static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config, 578 int is_enable) 579 { 580 uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val; 581 int err = 0, ret = 0; 582 583 switch (adev->asic_type) { 584 case CHIP_VEGA20: 585 if (is_enable) 586 return df_v3_6_pmc_add_cntr(adev, config); 587 588 df_v3_6_reset_perfmon_cntr(adev, config); 589 590 ret = df_v3_6_pmc_get_ctrl_settings(adev, 591 config, 592 &lo_base_addr, 593 &hi_base_addr, 594 &lo_val, 595 &hi_val); 596 597 if (ret) 598 return ret; 599 600 err = df_v3_6_perfmon_arm_with_retry(adev, 601 lo_base_addr, 602 lo_val, 603 hi_base_addr, 604 hi_val); 605 606 if (err) 607 ret = df_v3_6_pmc_set_deferred(adev, config, true); 608 609 break; 610 default: 611 break; 612 } 613 614 return ret; 615 } 616 617 static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config, 618 int is_disable) 619 { 620 uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val; 621 int ret = 0; 622 623 switch (adev->asic_type) { 624 case CHIP_VEGA20: 625 ret = df_v3_6_pmc_get_ctrl_settings(adev, 626 config, 627 &lo_base_addr, 628 &hi_base_addr, 629 &lo_val, 630 &hi_val); 631 632 if (ret) 633 return ret; 634 635 df_v3_6_reset_perfmon_cntr(adev, config); 636 637 if (is_disable) 638 df_v3_6_pmc_release_cntr(adev, config); 639 640 break; 641 default: 642 break; 643 } 644 645 return ret; 646 } 647 648 static void df_v3_6_pmc_get_count(struct amdgpu_device *adev, 649 uint64_t config, 650 uint64_t *count) 651 { 652 uint32_t lo_base_addr, hi_base_addr, lo_val = 0, hi_val = 0; 653 *count = 0; 654 655 switch (adev->asic_type) { 656 case CHIP_VEGA20: 657 df_v3_6_pmc_get_read_settings(adev, config, &lo_base_addr, 658 &hi_base_addr); 659 660 if ((lo_base_addr == 0) || (hi_base_addr == 0)) 661 return; 662 663 /* rearm the counter or throw away count value on failure */ 664 if (df_v3_6_pmc_is_deferred(adev, config)) { 665 int rearm_err = df_v3_6_perfmon_arm_with_status(adev, 666 lo_base_addr, lo_val, 667 hi_base_addr, hi_val); 668 669 if (rearm_err) 670 return; 671 672 df_v3_6_pmc_set_deferred(adev, config, false); 673 } 674 675 df_v3_6_perfmon_rreg(adev, lo_base_addr, &lo_val, 676 hi_base_addr, &hi_val); 677 678 *count = ((hi_val | 0ULL) << 32) | (lo_val | 0ULL); 679 680 if (*count >= DF_V3_6_PERFMON_OVERFLOW) 681 *count = 0; 682 683 DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x", 684 config, lo_base_addr, hi_base_addr, lo_val, hi_val); 685 686 break; 687 default: 688 break; 689 } 690 } 691 692 static uint64_t df_v3_6_get_dram_base_addr(struct amdgpu_device *adev, 693 uint32_t df_inst) 694 { 695 uint32_t base_addr_reg_val = 0; 696 uint64_t base_addr = 0; 697 698 base_addr_reg_val = RREG32_PCIE(smnDF_CS_UMC_AON0_DramBaseAddress0 + 699 df_inst * DF_3_6_SMN_REG_INST_DIST); 700 701 if (REG_GET_FIELD(base_addr_reg_val, 702 DF_CS_UMC_AON0_DramBaseAddress0, 703 AddrRngVal) == 0) { 704 DRM_WARN("address range not valid"); 705 return 0; 706 } 707 708 base_addr = REG_GET_FIELD(base_addr_reg_val, 709 DF_CS_UMC_AON0_DramBaseAddress0, 710 DramBaseAddr); 711 712 return base_addr << 28; 713 } 714 715 static uint32_t df_v3_6_get_df_inst_id(struct amdgpu_device *adev) 716 { 717 uint32_t xgmi_node_id = 0; 718 uint32_t df_inst_id = 0; 719 720 /* Walk through DF dst nodes to find current XGMI node */ 721 for (df_inst_id = 0; df_inst_id < DF_3_6_INST_CNT; df_inst_id++) { 722 723 xgmi_node_id = RREG32_PCIE(smnDF_CS_UMC_AON0_DramLimitAddress0 + 724 df_inst_id * DF_3_6_SMN_REG_INST_DIST); 725 xgmi_node_id = REG_GET_FIELD(xgmi_node_id, 726 DF_CS_UMC_AON0_DramLimitAddress0, 727 DstFabricID); 728 729 /* TODO: establish reason dest fabric id is offset by 7 */ 730 xgmi_node_id = xgmi_node_id >> 7; 731 732 if (adev->gmc.xgmi.physical_node_id == xgmi_node_id) 733 break; 734 } 735 736 if (df_inst_id == DF_3_6_INST_CNT) { 737 DRM_WARN("cant match df dst id with gpu node"); 738 return 0; 739 } 740 741 return df_inst_id; 742 } 743 744 const struct amdgpu_df_funcs df_v3_6_funcs = { 745 .sw_init = df_v3_6_sw_init, 746 .sw_fini = df_v3_6_sw_fini, 747 .enable_broadcast_mode = df_v3_6_enable_broadcast_mode, 748 .get_fb_channel_number = df_v3_6_get_fb_channel_number, 749 .get_hbm_channel_number = df_v3_6_get_hbm_channel_number, 750 .update_medium_grain_clock_gating = 751 df_v3_6_update_medium_grain_clock_gating, 752 .get_clockgating_state = df_v3_6_get_clockgating_state, 753 .pmc_start = df_v3_6_pmc_start, 754 .pmc_stop = df_v3_6_pmc_stop, 755 .pmc_get_count = df_v3_6_pmc_get_count, 756 .get_fica = df_v3_6_get_fica, 757 .set_fica = df_v3_6_set_fica, 758 .get_dram_base_addr = df_v3_6_get_dram_base_addr, 759 .get_df_inst_id = df_v3_6_get_df_inst_id 760 }; 761