1c349dbc7Sjsg /*
2c349dbc7Sjsg * Copyright 2019 Advanced Micro Devices, Inc.
3c349dbc7Sjsg *
4c349dbc7Sjsg * Permission is hereby granted, free of charge, to any person obtaining a
5c349dbc7Sjsg * copy of this software and associated documentation files (the "Software"),
6c349dbc7Sjsg * to deal in the Software without restriction, including without limitation
7c349dbc7Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8c349dbc7Sjsg * and/or sell copies of the Software, and to permit persons to whom the
9c349dbc7Sjsg * Software is furnished to do so, subject to the following conditions:
10c349dbc7Sjsg *
11c349dbc7Sjsg * The above copyright notice and this permission notice shall be included in
12c349dbc7Sjsg * all copies or substantial portions of the Software.
13c349dbc7Sjsg *
14c349dbc7Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15c349dbc7Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16c349dbc7Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17c349dbc7Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18c349dbc7Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19c349dbc7Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20c349dbc7Sjsg * OTHER DEALINGS IN THE SOFTWARE.
21c349dbc7Sjsg *
22c349dbc7Sjsg */
23c349dbc7Sjsg
24c349dbc7Sjsg #include <linux/delay.h>
25c349dbc7Sjsg #include <linux/kernel.h>
26c349dbc7Sjsg #include <linux/firmware.h>
27c349dbc7Sjsg #include <linux/module.h>
28c349dbc7Sjsg #include <linux/pci.h>
29c349dbc7Sjsg #include "amdgpu.h"
30c349dbc7Sjsg #include "amdgpu_gfx.h"
31c349dbc7Sjsg #include "amdgpu_psp.h"
32c349dbc7Sjsg #include "nv.h"
33c349dbc7Sjsg #include "nvd.h"
34c349dbc7Sjsg
35c349dbc7Sjsg #include "gc/gc_10_1_0_offset.h"
36c349dbc7Sjsg #include "gc/gc_10_1_0_sh_mask.h"
37c349dbc7Sjsg #include "smuio/smuio_11_0_0_offset.h"
38c349dbc7Sjsg #include "smuio/smuio_11_0_0_sh_mask.h"
39c349dbc7Sjsg #include "navi10_enum.h"
40c349dbc7Sjsg #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
41c349dbc7Sjsg
42c349dbc7Sjsg #include "soc15.h"
43c349dbc7Sjsg #include "soc15d.h"
44c349dbc7Sjsg #include "soc15_common.h"
45c349dbc7Sjsg #include "clearstate_gfx10.h"
46c349dbc7Sjsg #include "v10_structs.h"
47c349dbc7Sjsg #include "gfx_v10_0.h"
48c349dbc7Sjsg #include "nbio_v2_3.h"
49c349dbc7Sjsg
505ca02815Sjsg /*
51c349dbc7Sjsg * Navi10 has two graphic rings to share each graphic pipe.
52c349dbc7Sjsg * 1. Primary ring
53c349dbc7Sjsg * 2. Async ring
54c349dbc7Sjsg */
55c349dbc7Sjsg #define GFX10_NUM_GFX_RINGS_NV1X 1
561bb76ff1Sjsg #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2
57c349dbc7Sjsg #define GFX10_MEC_HPD_SIZE 2048
58c349dbc7Sjsg
59c349dbc7Sjsg #define F32_CE_PROGRAM_RAM_SIZE 65536
60c349dbc7Sjsg #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
61c349dbc7Sjsg
62c349dbc7Sjsg #define mmCGTT_GS_NGG_CLK_CTRL 0x5087
63c349dbc7Sjsg #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
64ad8b1aafSjsg #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
65ad8b1aafSjsg #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
66ad8b1aafSjsg #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
67ad8b1aafSjsg #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
68ad8b1aafSjsg
69ad8b1aafSjsg #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8
70ad8b1aafSjsg #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L
71ad8b1aafSjsg
725ca02815Sjsg #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006
735ca02815Sjsg #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1
745ca02815Sjsg #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007
755ca02815Sjsg #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1
765ca02815Sjsg
77ad8b1aafSjsg #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55
78ad8b1aafSjsg #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0
79ad8b1aafSjsg #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0
80ad8b1aafSjsg #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1
81ad8b1aafSjsg #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1
82ad8b1aafSjsg #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1
83ad8b1aafSjsg #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec
84ad8b1aafSjsg #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0
85ad8b1aafSjsg #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1
86ad8b1aafSjsg #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
87ad8b1aafSjsg #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2
88ad8b1aafSjsg #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
89ad8b1aafSjsg #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3
90ad8b1aafSjsg #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
91ad8b1aafSjsg #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4
92ad8b1aafSjsg #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0
93ad8b1aafSjsg #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5
94ad8b1aafSjsg #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0
95ad8b1aafSjsg #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6
96ad8b1aafSjsg #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
97ad8b1aafSjsg #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a
98ad8b1aafSjsg #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L
99ad8b1aafSjsg #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL
100ad8b1aafSjsg #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2
101ad8b1aafSjsg #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL
102ad8b1aafSjsg #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580
103ad8b1aafSjsg #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0
104ad8b1aafSjsg
1055ca02815Sjsg #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025
1065ca02815Sjsg #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1
1075ca02815Sjsg #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026
1085ca02815Sjsg #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1
1091bb76ff1Sjsg
1101bb76ff1Sjsg #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d
1111bb76ff1Sjsg #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1
1121bb76ff1Sjsg #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e
1131bb76ff1Sjsg #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1
1141bb76ff1Sjsg
1155ca02815Sjsg #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441
1165ca02815Sjsg #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1
1175ca02815Sjsg #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261
1185ca02815Sjsg #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
1195ca02815Sjsg #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f
1205ca02815Sjsg #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1
1215ca02815Sjsg #define mmVGT_TF_RING_SIZE_Vangogh 0x224e
1225ca02815Sjsg #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1
1235ca02815Sjsg #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241
1245ca02815Sjsg #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1
1255ca02815Sjsg #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250
1265ca02815Sjsg #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1
1275ca02815Sjsg #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240
1285ca02815Sjsg #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1
1295ca02815Sjsg #define mmSPI_CONFIG_CNTL_Vangogh 0x2440
1305ca02815Sjsg #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1
1315ca02815Sjsg #define mmGCR_GENERAL_CNTL_Vangogh 0x1580
1325ca02815Sjsg #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0
1335ca02815Sjsg #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL
1345ca02815Sjsg
135ad8b1aafSjsg #define mmCP_HYP_PFP_UCODE_ADDR 0x5814
136ad8b1aafSjsg #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1
137ad8b1aafSjsg #define mmCP_HYP_PFP_UCODE_DATA 0x5815
138ad8b1aafSjsg #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1
139ad8b1aafSjsg #define mmCP_HYP_CE_UCODE_ADDR 0x5818
140ad8b1aafSjsg #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1
141ad8b1aafSjsg #define mmCP_HYP_CE_UCODE_DATA 0x5819
142ad8b1aafSjsg #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1
143ad8b1aafSjsg #define mmCP_HYP_ME_UCODE_ADDR 0x5816
144ad8b1aafSjsg #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1
145ad8b1aafSjsg #define mmCP_HYP_ME_UCODE_DATA 0x5817
146ad8b1aafSjsg #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1
147ad8b1aafSjsg
1485ca02815Sjsg #define mmCPG_PSP_DEBUG 0x5c10
1495ca02815Sjsg #define mmCPG_PSP_DEBUG_BASE_IDX 1
1505ca02815Sjsg #define mmCPC_PSP_DEBUG 0x5c11
1515ca02815Sjsg #define mmCPC_PSP_DEBUG_BASE_IDX 1
1525ca02815Sjsg #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L
1535ca02815Sjsg #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L
1545ca02815Sjsg
155ad8b1aafSjsg //CC_GC_SA_UNIT_DISABLE
156ad8b1aafSjsg #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9
157ad8b1aafSjsg #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0
158ad8b1aafSjsg #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8
159ad8b1aafSjsg #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L
160ad8b1aafSjsg //GC_USER_SA_UNIT_DISABLE
161ad8b1aafSjsg #define mmGC_USER_SA_UNIT_DISABLE 0x0fea
162ad8b1aafSjsg #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0
163ad8b1aafSjsg #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8
164ad8b1aafSjsg #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L
165ad8b1aafSjsg //PA_SC_ENHANCE_3
166ad8b1aafSjsg #define mmPA_SC_ENHANCE_3 0x1085
167ad8b1aafSjsg #define mmPA_SC_ENHANCE_3_BASE_IDX 0
168ad8b1aafSjsg #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
169ad8b1aafSjsg #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L
170ad8b1aafSjsg
171ad8b1aafSjsg #define mmCGTT_SPI_CS_CLK_CTRL 0x507c
172ad8b1aafSjsg #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1
173c349dbc7Sjsg
1745ca02815Sjsg #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3
1755ca02815Sjsg #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
1765ca02815Sjsg #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db
1775ca02815Sjsg #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
1785ca02815Sjsg
1795ca02815Sjsg #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030
1805ca02815Sjsg #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0
1815ca02815Sjsg
1825ca02815Sjsg #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5
1835ca02815Sjsg #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1
1845ca02815Sjsg
185c349dbc7Sjsg MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
186c349dbc7Sjsg MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
187c349dbc7Sjsg MODULE_FIRMWARE("amdgpu/navi10_me.bin");
188c349dbc7Sjsg MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
189c349dbc7Sjsg MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
190c349dbc7Sjsg MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
191c349dbc7Sjsg
192c349dbc7Sjsg MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
193c349dbc7Sjsg MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
194c349dbc7Sjsg MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
195c349dbc7Sjsg MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
196c349dbc7Sjsg MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
197c349dbc7Sjsg MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
198c349dbc7Sjsg MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
199c349dbc7Sjsg MODULE_FIRMWARE("amdgpu/navi14_me.bin");
200c349dbc7Sjsg MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
201c349dbc7Sjsg MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
202c349dbc7Sjsg MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
203c349dbc7Sjsg
204c349dbc7Sjsg MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
205c349dbc7Sjsg MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
206c349dbc7Sjsg MODULE_FIRMWARE("amdgpu/navi12_me.bin");
207c349dbc7Sjsg MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
208c349dbc7Sjsg MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
209c349dbc7Sjsg MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
210c349dbc7Sjsg
211ad8b1aafSjsg MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
212ad8b1aafSjsg MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
213ad8b1aafSjsg MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
214ad8b1aafSjsg MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
215ad8b1aafSjsg MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
216ad8b1aafSjsg MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
217ad8b1aafSjsg
218ad8b1aafSjsg MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
219ad8b1aafSjsg MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
220ad8b1aafSjsg MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
221ad8b1aafSjsg MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
222ad8b1aafSjsg MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
223ad8b1aafSjsg MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
224ad8b1aafSjsg
2255ca02815Sjsg MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
2265ca02815Sjsg MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
2275ca02815Sjsg MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
2285ca02815Sjsg MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
2295ca02815Sjsg MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
2305ca02815Sjsg MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
2315ca02815Sjsg
2325ca02815Sjsg MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
2335ca02815Sjsg MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
2345ca02815Sjsg MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
2355ca02815Sjsg MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
2365ca02815Sjsg MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
2375ca02815Sjsg MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
2385ca02815Sjsg
2395ca02815Sjsg MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
2405ca02815Sjsg MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
2415ca02815Sjsg MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
2425ca02815Sjsg MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
2435ca02815Sjsg MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
2445ca02815Sjsg MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
2455ca02815Sjsg
2465ca02815Sjsg MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
2475ca02815Sjsg MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
2485ca02815Sjsg MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
2495ca02815Sjsg MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
2505ca02815Sjsg MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
2515ca02815Sjsg MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
2525ca02815Sjsg
2535ca02815Sjsg MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");
2545ca02815Sjsg MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");
2555ca02815Sjsg MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");
2565ca02815Sjsg MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
2575ca02815Sjsg MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
2585ca02815Sjsg MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
2595ca02815Sjsg
2601bb76ff1Sjsg MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
2611bb76ff1Sjsg MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
2621bb76ff1Sjsg MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
2631bb76ff1Sjsg MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
2641bb76ff1Sjsg MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
2651bb76ff1Sjsg MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
2661bb76ff1Sjsg
2671bb76ff1Sjsg MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
2681bb76ff1Sjsg MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
2691bb76ff1Sjsg MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
2701bb76ff1Sjsg MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
2711bb76ff1Sjsg MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
2721bb76ff1Sjsg MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
2735ca02815Sjsg
274f005ef32Sjsg static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
275c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
276c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
277c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
278c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
279c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
280c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
281c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
282c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
283c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
284c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
285c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
286c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
287c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
288c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
289c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
290c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
291c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
292c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
293c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
294c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
295c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
296c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
297c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
298c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
299c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
300c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
301c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
302c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
303c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
304c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
305c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
306c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
307c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
308c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
309c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
310c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
311c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
312c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
313c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
314c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
315c349dbc7Sjsg };
316c349dbc7Sjsg
317f005ef32Sjsg static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = {
318c349dbc7Sjsg /* Pending on emulation bring up */
319c349dbc7Sjsg };
320c349dbc7Sjsg
321f005ef32Sjsg static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = {
322ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
323ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
324ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
325ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
326ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
327ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
328ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
329ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
330ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
331ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
332ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
333ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
334ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
335ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
336ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
337ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
338ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
339ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
340ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
341ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
342ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
343ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
344ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
345ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
346ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
347ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
348ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
349ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
350ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
351ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
352ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
353ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
354ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
355ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
356ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
357ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
358ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
359ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
360ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
361ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
362ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
363ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
364ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
365ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
366ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
367ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
368ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
369ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
370ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
371ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
372ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
373ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
374ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
375ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
376ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
377ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
378ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
379ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
380ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
381ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
382ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
383ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
384ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
385ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
386ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
387ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
388ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
389ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
390ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
391ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
392ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
393ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
394ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
395ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
396ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
397ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
398ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
399ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
400ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
401ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
402ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
403ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
404ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
405ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
406ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
407ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
408ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
409ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
410ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
411ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
412ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
413ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
414ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
415ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
416ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
417ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
418ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
419ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
420ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
421ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
422ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
423ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
424ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
425ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
426ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
427ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
428ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
429ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
430ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
431ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
432ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
433ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
434ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
435ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
436ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
437ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
438ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
439ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
440ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
441ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
442ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
443ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
444ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
445ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
446ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
447ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
448ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
449ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
450ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
451ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
452ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
453ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
454ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
455ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
456ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
457ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
458ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
459ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
460ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
461ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
462ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
463ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
464ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
465ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
466ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
467ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
468ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
469ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
470ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
471ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
472ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
473ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
474ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
475ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
476ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
477ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
478ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
479ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
480ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
481ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
482ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
483ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
484ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
485ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
486ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
487ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
488ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
489ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
490ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
491ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
492ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
493ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
494ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
495ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
496ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
497ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
498ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
499ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
500ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
501ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
502ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
503ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
504ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
505ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
506ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
507ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
508ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
509ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
510ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
511ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
512ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
513ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
514ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
515ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
516ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
517ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
518ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
519ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
520ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
521ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
522ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
523ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
524ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
525ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
526ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
527ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
528ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
529ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
530ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
531ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
532ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
533ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
534ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
535ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
536ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
537ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
538ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
539ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
540ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
541ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
542ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
543ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
544ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
545ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
546ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
547ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
548ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
549ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
550ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
551ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
552ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
553ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
554ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
555ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
556ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
557ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
558ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
559ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
560ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
561ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
562ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
563ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
564ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
565ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
566ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
567ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
568ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
569ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
570ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
571ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
572ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
573ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
574ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
575ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
576ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
577ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
578ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
579ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
580ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
581ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
582ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
583ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
584ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
585ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
586ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
587ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
588ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
589ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
590ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
591ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
592ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
593ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
594ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
595ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
596ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
597ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
598ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
599ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
600ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
601ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
602ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
603ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
604ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
605ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
606ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
607ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
608ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
609ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
610ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
611ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
612ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
613ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
614ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
615ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
616ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
617ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
618ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
619ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
620ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
621ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
622ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
623ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
624ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
625ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
626ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
627ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
628ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
629ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
630ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
631ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
632ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
633ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
634ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
635ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
636ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
637ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
638ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
639ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
640ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
641ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
642ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
643ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
644ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
645ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
646ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
647ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
648ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
649ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
650ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
651ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
652ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
653ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
654ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
655ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
656ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
657ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
658ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
659ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
660ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
661ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
662ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
663ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
664ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
665ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
666ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
667ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
668ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
669ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
670ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
671ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
672ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
673ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
674ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
675ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
676ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
677ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
678ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
679ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
680ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
681ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
682ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
683ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
684ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
685ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
686ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
687ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
688ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
689ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
690ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
691ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
692ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
693ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
694ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
695ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
696ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
697ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
698ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
699ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
700ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
701ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
702ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
703ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
704ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
705ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
706ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
707ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
708ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
709ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
710ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
711ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
712ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
713ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
714ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
715ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
716ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
717ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
718ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
719ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
720ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
721ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
722ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
723ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
724ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
725ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
726ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
727ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
728ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
729ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
730ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
731ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
732ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
733ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
734ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
735ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
736ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
737ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
738ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
739ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
740ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
741ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
742ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
743ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
744ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
745ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
746ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
747ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
748ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
749ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
750ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
751ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
752ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
753ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
754ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
755ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
756ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
757ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
758ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
759ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
760ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
761ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
762ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
763ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
764ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
765ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
766ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
767ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
768ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
769ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
770ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
771ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
772ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
773ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
774ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
775ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
776ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
777ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
778ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
779ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
780ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
781ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
782ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
783ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
784ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
785ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
786ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
787ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
788ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
789ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
790ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
791ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
792ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
793ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
794ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
795ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
796ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
797ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
798ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
799ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
800ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
801ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
802ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
803ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
804ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
805ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
806ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
807ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
808ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
809ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
810ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
811ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
812ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
813ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
814ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
815ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
816ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
817ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
818ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
819ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
820ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
821ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
822ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
823ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
824ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
825ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
826ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
827ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
828ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
829ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
830ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
831ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
832ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
833ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
834ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
835ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
836ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
837ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
838ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
839ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
840ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
841ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
842ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
843ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
844ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
845ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
846ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
847ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
848ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
849ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
850ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
851ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
852ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
853ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
854ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
855ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
856ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
857ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
858ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
859ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
860ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
861ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
862ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
863ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
864ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
865ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
866ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
867ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
868ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
869ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
870ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
871ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
872ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
873ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
874ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
875ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
876ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
877ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
878ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
879ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
880ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
881ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
882ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
883ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
884ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
885ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
886ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
887ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
888ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
889ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
890ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
891ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
892ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
893ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
894ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
895ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
896ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
897ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
898ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
899ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
900ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
901ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
902ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
903ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
904ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
905ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
906ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
907ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
908ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
909ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
910ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
911ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
912ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
913ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
914ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
915ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
916ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
917ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
918ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
919ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
920ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
921ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
922ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
923ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
924ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
925ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
926ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
927ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
928ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
929ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
930ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
931ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
932ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
933ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
934ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
935ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
936ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
937ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
938ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
939ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
940ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
941ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
942ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
943ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
944ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
945ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
946ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
947ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
948ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
949ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
950ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
951ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
952ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
953ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
954ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
955ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
956ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
957ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
958ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
959ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
960ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
961ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
962ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
963ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
964ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
965ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
966ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
967ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
968ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
969ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
970ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
971ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
972ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
973ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
974ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
975ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
976ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
977ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
978ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
979ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
980ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
981ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
982ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
983ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
984ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
985ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
986ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
987ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
988ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
989ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
990ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
991ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
992ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
993ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
994ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
995ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
996ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
997ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
998ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
999ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1000ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1001ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1002ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1003ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1004ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1005ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1006ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1007ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1008ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1009ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1010ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1011ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1012ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1013ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1014ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1015ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1016ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1017ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1018ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1019ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1020ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1021ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1022ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1023ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1024ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1025ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1026ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1027ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1028ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1029ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1030ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1031ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1032ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1033ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1034ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1035ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1036ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1037ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1038ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1039ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1040ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1041ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1042ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1043ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1044ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1045ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1046ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1047ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1048ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1049ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1050ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1051ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1052ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1053ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1054ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1055ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1056ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1057ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1058ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1059ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1060ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1061ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1062ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1063ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1064ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1065ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1066ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1067ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1068ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1069ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1070ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1071ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1072ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1073ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1074ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1075ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1076ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1077ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1078ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1079ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1080ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1081ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1082ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1083ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1084ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1085ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1086ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1087ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1088ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1089ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1090ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1091ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1092ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1093ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1094ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1095ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1096ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1097ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1098ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1099ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1100ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1101ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1102ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1103ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1104ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1105ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1106ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1107ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1108ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1109ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1110ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1111ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1112ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1113ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1114ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1115ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1116ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1117ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1118ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1119ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1120ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1121ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1122ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1123ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1124ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1125ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1126ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1127ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1128ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1129ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1130ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1131ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1132ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1133ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1134ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1135ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1136ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1137ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1138ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1139ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1140ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1141ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1142ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1143ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1144ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1145ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1146ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1147ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1148ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1149ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1150ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1151ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1152ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1153ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1154ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1155ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1156ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1157ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1158ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1159ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1160ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1161ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1162ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1163ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1164ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1165ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1166ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1167ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1168ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1169ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1170ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1171ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1172ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1173ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1174ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1175ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1176ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1177ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1178ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1179ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1180ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1181ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1182ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1183ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1184ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1185ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1186ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1187ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1188ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1189ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1190ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1191ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1192ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1193ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1194ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1195ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1196ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1197ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1198ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1199ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1200ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1201ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1202ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1203ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1204ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1205ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1206ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1207ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1208ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1209ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1210ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1211ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1212ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1213ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1214ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1215ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1216ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1217ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1218ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1219ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1220ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1221ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1222ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1223ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1224ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1225ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1226ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1227ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1228ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1229ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1230ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1231ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1232ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1233ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1234ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1235ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1236ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1237ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1238ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1239ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1240ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1241ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1242ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1243ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1244ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1245ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1246ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1247ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1248ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1249ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1250ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1251ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1252ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1253ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1254ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1255ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1256ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1257ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1258ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1259ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1260ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1261ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1262ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1263ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1264ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1265ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1266ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1267ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1268ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1269ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1270ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1271ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1272ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1273ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1274ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1275ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1276ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1277ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1278ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1279ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1280ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1281ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1282ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1283ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1284ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1285ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1286ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1287ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1288ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1289ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1290ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1291ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1292ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1293ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1294ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1295ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1296ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1297ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1298ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1299ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1300ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1301ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1302ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1303ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1304ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1305ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1306ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1307ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1308ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1309ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1310ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1311ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1312ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1313ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1314ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1315ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1316ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1317ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1318ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1319ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1320ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1321ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1322ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1323ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1324ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1325ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1326ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1327ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1328ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1329ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1330ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1331ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1332ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1333ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1334ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1335ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1336ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1337ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1338ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1339ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1340ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1341ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1342ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1343ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1344ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1345ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1346ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1347ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1348ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1349ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1350ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1351ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1352ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1353ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1354ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1355ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1356ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1357ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1358ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1359ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1360ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1361ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1362ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1363ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1364ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1365ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1366ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1367ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1368ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1369ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1370ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1371ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1372ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1373ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1374ad8b1aafSjsg };
1375ad8b1aafSjsg
1376f005ef32Sjsg static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = {
1377c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1378c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1379c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1380c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1381c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1382c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1383c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1384c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1385c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1386c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1387c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1388c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1389c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1390c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1391c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1392c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1393c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1394c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1395c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1396c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1397c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1398c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1399c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1400c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1401c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1402c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1403c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1404c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1405c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1406c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1407c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1408c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1409c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1410c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1411c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1412c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1413c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1414c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1415c349dbc7Sjsg };
1416c349dbc7Sjsg
1417f005ef32Sjsg static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = {
1418c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1419c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1420c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1421c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1422c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1423c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1424c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1425c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1426c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1427c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1428c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1429c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1430c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1431c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1432ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1433c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1434c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1435ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1436c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1437c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1438c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1439c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1440c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1441c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1442c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1443c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1444c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1445c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1446c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1447c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1448c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1449c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1450c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1451c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1452c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1453ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1454c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1455c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1456c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1457c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1458c349dbc7Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1459ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1460c349dbc7Sjsg };
1461c349dbc7Sjsg
1462f005ef32Sjsg static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = {
1463c349dbc7Sjsg /* Pending on emulation bring up */
1464c349dbc7Sjsg };
1465c349dbc7Sjsg
1466f005ef32Sjsg static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = {
1467ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1468ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1469ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1470ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1471ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1472ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1473ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1474ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1475ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1476ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1477ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1478ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1479ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1480ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1481ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1482ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1483ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1484ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1485ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1486ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1487ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1488ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1489ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1490ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1491ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1492ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1493ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1494ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1495ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1496ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1497ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1498ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1499ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1500ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1501ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1502ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1503ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1504ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1505ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1506ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1507ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1508ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1509ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1510ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1511ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1512ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1513ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1514ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1515ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1516ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1517ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1518ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1519ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1520ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1521ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1522ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1523ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1524ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1525ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1526ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1527ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1528ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1529ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1530ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1531ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1532ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1533ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1534ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1535ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1536ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1537ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1538ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1539ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1540ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1541ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1542ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1543ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1544ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1545ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1546ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1547ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1548ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1549ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1550ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1551ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1552ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1553ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1554ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1555ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1556ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1557ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1558ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1559ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1560ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1561ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1562ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1563ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1564ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1565ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1566ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1567ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1568ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1569ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1570ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1571ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1572ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1573ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1574ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1575ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1576ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1577ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1578ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1579ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1580ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1581ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1582ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1583ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1584ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1585ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1586ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1587ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1588ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1589ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1590ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1591ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1592ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1593ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1594ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1595ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1596ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1597ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1598ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1599ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1600ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1601ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1602ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1603ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1604ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1605ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1606ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1607ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1608ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1609ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1610ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1611ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1612ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1613ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1614ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1615ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1616ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1617ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1618ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1619ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1620ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1621ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1622ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1623ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1624ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1625ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1626ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1627ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1628ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1629ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1630ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1631ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1632ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1633ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1634ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1635ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1636ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1637ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1638ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1639ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1640ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1641ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1642ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1643ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1644ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1645ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1646ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1647ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1648ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1649ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1650ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1651ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1652ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1653ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1654ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1655ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1656ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1657ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1658ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1659ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1660ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1661ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1662ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1663ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1664ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1665ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1666ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1667ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1668ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1669ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1670ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1671ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1672ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1673ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1674ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1675ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1676ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1677ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1678ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1679ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1680ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1681ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1682ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1683ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1684ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1685ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1686ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1687ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1688ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1689ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1690ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1691ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1692ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1693ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1694ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1695ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1696ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1697ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1698ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1699ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1700ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1701ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1702ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1703ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1704ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1705ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1706ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1707ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1708ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1709ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1710ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1711ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1712ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1713ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1714ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1715ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1716ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1717ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1718ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1719ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1720ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1721ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1722ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1723ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1724ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1725ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1726ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1727ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1728ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1729ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1730ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1731ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1732ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1733ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1734ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1735ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1736ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1737ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1738ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1739ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1740ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1741ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1742ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1743ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1744ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1745ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1746ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1747ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1748ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1749ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1750ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1751ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1752ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1753ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1754ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1755ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1756ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1757ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1758ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1759ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1760ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1761ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1762ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1763ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1764ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1765ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1766ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1767ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1768ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1769ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1770ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1771ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1772ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1773ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1774ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1775ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1776ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1777ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1778ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1779ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1780ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1781ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1782ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1783ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1784ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1785ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1786ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1787ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1788ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1789ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1790ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1791ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1792ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1793ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1794ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1795ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1796ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1797ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1798ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1799ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1800ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1801ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1802ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1803ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1804ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1805ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1806ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1807ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1808ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1809ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1810ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1811ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1812ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1813ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1814ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1815ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1816ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1817ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1818ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1819ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1820ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1821ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1822ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1823ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1824ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1825ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1826ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1827ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1828ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1829ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1830ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1831ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1832ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1833ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1834ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1835ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1836ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1837ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1838ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1839ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1840ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1841ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1842ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1843ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1844ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1845ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1846ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1847ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1848ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1849ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1850ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1851ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1852ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1853ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1854ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1855ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1856ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1857ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1858ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1859ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1860ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1861ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1862ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1863ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1864ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1865ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1866ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1867ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1868ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1869ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1870ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1871ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1872ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1873ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1874ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1875ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1876ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1877ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1878ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1879ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1880ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1881ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1882ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1883ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1884ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1885ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1886ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1887ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1888ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1889ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1890ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1891ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1892ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1893ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1894ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1895ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1896ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1897ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1898ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1899ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1900ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1901ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1902ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1903ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1904ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1905ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1906ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1907ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1908ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1909ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1910ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1911ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1912ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1913ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1914ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1915ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1916ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1917ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1918ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1919ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1920ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1921ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1922ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1923ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1924ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1925ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1926ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1927ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1928ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1929ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1930ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1931ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1932ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1933ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1934ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1935ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1936ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1937ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1938ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1939ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1940ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1941ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1942ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1943ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1944ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1945ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1946ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1947ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1948ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1949ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1950ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1951ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1952ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1953ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1954ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1955ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1956ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1957ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1958ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1959ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1960ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1961ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1962ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1963ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1964ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1965ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1966ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1967ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1968ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1969ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1970ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1971ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1972ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1973ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1974ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1975ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1976ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1977ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1978ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1979ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1980ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1981ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1982ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1983ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1984ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1985ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1986ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1987ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1988ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1989ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1990ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1991ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1992ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1993ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1994ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1995ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1996ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1997ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1998ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1999ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2000ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2001ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2002ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2003ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2004ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2005ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2006ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2007ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2008ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2009ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2010ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2011ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2012ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2013ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2014ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2015ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2016ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2017ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2018ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2019ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2020ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2021ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2022ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2023ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2024ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2025ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2026ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2027ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2028ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2029ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2030ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2031ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2032ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2033ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2034ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2035ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2036ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2037ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2038ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2039ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2040ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2041ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2042ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2043ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2044ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2045ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2046ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2047ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2048ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2049ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2050ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2051ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2052ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2053ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2054ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2055ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2056ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2057ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2058ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2059ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2060ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2061ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2062ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2063ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2064ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2065ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2066ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2067ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2068ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2069ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2070ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2071ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2072ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2073ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2074ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2075ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2076ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2077ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2078ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2079ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2080ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2081ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2082ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2083ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2084ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2085ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2086ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2087ad8b1aafSjsg };
2088ad8b1aafSjsg
2089f005ef32Sjsg static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = {
2090c349dbc7Sjsg /* Pending on emulation bring up */
2091c349dbc7Sjsg };
2092c349dbc7Sjsg
2093f005ef32Sjsg static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = {
2094ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2095ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2096ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2097ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2098ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2099ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2100ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2101ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2102ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2103ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2104ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2105ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2106ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2107ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2108ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2109ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2110ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2111ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2112ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2113ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2114ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2115ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2116ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2117ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2118ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2119ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2120ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2121ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2122ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2123ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2124ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2125ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2126ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2127ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2128ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2129ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2130ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2131ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2132ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2133ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2134ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2135ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2136ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2137ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2138ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2139ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2140ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2141ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2142ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2143ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2144ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2145ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2146ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2147ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2148ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2149ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2150ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2151ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2152ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2153ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2154ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2155ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2156ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2157ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2158ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2159ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2160ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2161ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2162ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2163ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2164ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2165ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2166ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2167ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2168ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2169ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2170ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2171ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2172ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2173ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2174ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2175ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2176ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2177ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2178ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2179ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2180ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2181ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2182ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2183ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2184ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2185ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2186ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2187ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2188ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2189ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2190ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2191ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2192ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2193ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2194ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2195ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2196ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2197ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2198ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2199ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2200ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2201ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2202ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2203ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2204ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2205ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2206ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2207ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2208ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2209ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2210ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2211ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2212ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2213ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2214ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2215ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2216ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2217ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2218ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2219ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2220ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2221ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2222ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2223ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2224ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2225ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2226ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2227ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2228ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2229ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2230ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2231ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2232ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2233ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2234ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2235ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2236ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2237ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2238ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2239ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2240ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2241ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2242ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2243ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2244ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2245ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2246ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2247ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2248ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2249ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2250ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2251ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2252ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2253ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2254ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2255ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2256ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2257ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2258ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2259ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2260ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2261ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2262ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2263ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2264ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2265ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2266ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2267ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2268ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2269ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2270ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2271ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2272ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2273ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2274ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2275ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2276ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2277ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2278ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2279ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2280ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2281ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2282ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2283ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2284ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2285ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2286ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2287ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2288ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2289ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2290ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2291ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2292ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2293ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2294ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2295ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2296ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2297ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2298ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2299ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2300ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2301ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2302ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2303ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2304ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2305ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2306ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2307ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2308ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2309ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2310ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2311ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2312ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2313ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2314ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2315ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2316ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2317ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2318ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2319ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2320ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2321ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2322ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2323ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2324ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2325ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2326ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2327ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2328ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2329ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2330ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2331ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2332ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2333ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2334ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2335ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2336ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2337ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2338ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2339ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2340ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2341ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2342ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2343ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2344ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2345ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2346ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2347ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2348ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2349ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2350ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2351ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2352ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2353ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2354ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2355ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2356ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2357ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2358ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2359ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2360ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2361ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2362ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2363ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2364ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2365ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2366ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2367ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2368ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2369ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2370ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2371ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2372ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2373ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2374ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2375ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2376ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2377ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2378ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2379ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2380ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2381ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2382ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2383ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2384ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2385ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2386ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2387ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2388ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2389ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2390ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2391ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2392ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2393ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2394ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2395ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2396ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2397ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2398ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2399ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2400ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2401ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2402ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2403ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2404ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2405ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2406ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2407ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2408ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2409ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2410ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2411ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2412ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2413ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2414ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2415ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2416ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2417ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2418ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2419ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2420ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2421ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2422ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2423ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2424ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2425ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2426ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2427ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2428ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2429ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2430ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2431ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2432ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2433ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2434ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2435ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2436ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2437ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2438ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2439ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2440ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2441ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2442ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2443ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2444ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2445ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2446ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2447ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2448ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2449ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2450ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2451ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2452ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2453ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2454ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2455ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2456ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2457ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2458ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2459ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2460ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2461ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2462ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2463ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2464ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2465ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2466ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2467ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2468ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2469ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2470ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2471ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2472ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2473ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2474ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2475ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2476ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2477ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2478ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2479ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2480ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2481ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2482ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2483ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2484ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2485ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2486ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2487ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2488ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2489ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2490ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2491ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2492ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2493ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2494ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2495ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2496ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2497ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2498ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2499ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2500ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2501ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2502ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2503ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2504ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2505ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2506ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2507ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2508ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2509ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2510ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2511ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2512ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2513ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2514ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2515ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2516ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2517ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2518ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2519ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2520ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2521ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2522ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2523ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2524ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2525ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2526ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2527ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2528ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2529ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2530ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2531ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2532ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2533ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2534ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2535ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2536ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2537ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2538ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2539ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2540ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2541ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2542ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2543ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2544ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2545ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2546ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2547ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2548ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2549ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2550ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2551ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2552ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2553ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2554ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2555ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2556ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2557ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2558ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2559ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2560ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2561ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2562ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2563ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2564ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2565ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2566ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2567ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2568ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2569ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2570ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2571ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2572ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2573ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2574ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2575ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2576ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2577ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2578ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2579ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2580ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2581ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2582ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2583ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2584ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2585ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2586ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2587ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2588ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2589ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2590ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2591ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2592ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2593ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2594ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2595ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2596ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2597ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2598ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2599ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2600ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2601ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2602ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2603ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2604ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2605ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2606ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2607ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2608ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2609ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2610ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2611ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2612ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2613ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2614ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2615ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2616ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2617ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2618ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2619ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2620ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2621ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2622ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2623ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2624ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2625ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2626ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2627ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2628ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2629ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2630ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2631ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2632ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2633ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2634ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2635ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2636ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2637ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2638ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2639ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2640ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2641ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2642ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2643ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2644ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2645ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2646ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2647ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2648ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2649ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2650ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2651ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2652ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2653ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2654ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2655ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2656ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2657ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2658ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2659ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2660ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2661ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2662ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2663ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2664ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2665ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2666ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2667ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2668ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2669ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2670ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2671ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2672ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2673ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2674ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2675ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2676ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2677ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2678ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2679ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2680ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2681ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2682ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2683ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2684ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2685ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2686ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2687ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2688ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2689ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2690ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2691ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2692ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2693ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2694ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2695ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2696ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2697ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2698ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2699ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2700ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2701ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2702ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2703ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2704ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2705ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2706ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2707ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2708ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2709ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2710ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2711ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2712ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2713ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2714ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2715ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2716ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2717ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2718ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2719ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2720ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2721ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2722ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2723ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2724ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2725ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2726ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2727ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2728ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2729ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2730ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2731ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2732ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2733ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2734ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2735ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2736ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2737ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2738ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2739ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2740ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2741ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2742ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2743ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2744ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2745ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2746ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2747ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2748ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2749ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2750ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2751ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2752ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2753ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2754ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2755ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2756ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2757ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2758ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2759ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2760ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2761ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2762ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2763ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2764ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2765ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2766ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2767ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2768ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2769ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2770ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2771ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2772ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2773ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2774ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2775ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2776ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2777ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2778ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2779ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2780ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2781ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2782ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2783ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2784ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2785ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2786ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2787ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2788ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2789ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2790ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2791ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2792ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2793ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2794ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2795ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2796ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2797ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2798ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2799ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2800ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2801ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2802ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2803ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2804ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2805ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2806ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2807ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2808ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2809ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2810ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2811ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2812ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2813ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2814ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2815ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2816ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2817ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2818ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2819ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2820ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2821ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2822ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2823ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2824ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2825ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2826ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2827ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2828ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2829ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2830ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2831ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2832ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2833ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2834ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2835ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2836ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2837ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2838ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2839ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2840ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2841ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2842ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2843ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2844ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2845ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2846ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2847ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2848ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2849ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2850ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2851ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2852ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2853ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2854ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2855ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2856ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2857ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2858ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2859ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2860ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2861ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2862ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2863ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2864ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2865ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2866ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2867ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2868ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2869ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2870ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2871ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2872ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2873ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2874ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2875ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2876ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2877ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2878ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2879ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2880ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2881ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2882ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2883ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2884ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2885ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2886ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2887ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2888ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2889ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2890ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2891ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2892ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2893ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2894ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2895ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2896ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2897ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2898ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2899ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2900ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2901ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2902ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2903ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2904ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2905ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2906ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2907ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2908ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2909ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2910ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2911ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2912ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2913ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2914ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2915ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2916ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2917ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2918ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2919ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2920ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2921ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2922ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2923ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2924ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2925ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2926ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2927ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2928ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2929ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2930ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2931ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2932ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2933ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2934ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2935ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2936ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2937ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2938ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2939ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2940ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2941ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2942ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2943ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2944ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2945ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2946ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2947ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2948ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2949ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2950ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2951ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2952ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2953ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2954ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2955ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2956ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2957ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2958ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2959ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2960ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2961ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2962ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2963ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2964ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2965ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2966ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2967ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2968ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2969ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2970ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2971ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2972ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2973ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2974ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2975ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2976ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2977ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2978ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2979ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2980ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2981ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2982ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2983ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2984ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2985ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2986ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2987ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2988ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2989ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2990ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2991ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2992ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2993ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2994ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2995ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2996ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2997ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2998ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2999ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3000ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3001ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3002ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3003ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3004ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3005ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3006ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3007ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3008ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3009ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3010ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3011ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3012ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3013ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3014ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3015ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3016ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3017ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3018ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3019ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3020ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3021ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3022ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3023ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3024ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3025ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3026ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3027ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3028ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3029ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3030ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3031ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3032ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3033ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3034ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3035ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3036ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3037ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3038ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3039ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3040ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3041ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3042ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3043ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3044ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3045ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3046ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3047ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3048ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3049ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3050ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3051ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3052ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3053ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3054ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3055ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3056ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3057ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3058ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3059ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3060ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3061ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3062ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3063ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3064ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3065ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3066ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3067ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3068ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3069ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3070ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3071ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3072ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3073ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3074ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3075ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3076ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3077ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3078ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3079ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3080ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3081ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3082ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3083ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3084ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3085ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3086ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3087ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3088ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3089ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3090ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3091ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3092ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3093ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3094ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3095ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3096ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3097ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3098ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3099ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3100ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3101ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3102ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3103ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3104ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3105ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3106ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3107ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3108ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3109ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3110ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3111ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3112ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3113ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3114ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3115ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3116ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3117ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3118ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3119ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3120ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3121ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3122ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3123ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3124ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3125ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3126ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3127ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3128ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3129ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3130ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3131ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3132ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3133ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3134ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3135ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3136ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3137ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3138ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3139ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3140ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3141ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3142ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3143ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3144ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3145ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3146ad8b1aafSjsg };
3147ad8b1aafSjsg
3148f005ef32Sjsg static const struct soc15_reg_golden golden_settings_gc_10_3[] = {
3149ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3150ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3151ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3152ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3153ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3154ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3155ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3156ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3157ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3158ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3159ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
31605ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
31615ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3162ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3163ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3164ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3165ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3166ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3167ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
3168ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3169ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3170ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3171ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3172ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3173ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3174ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3175ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3176ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3177ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3178ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3179ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3180ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3181ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3182ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3183ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3184ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3185ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3186ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3187ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3188ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
318931324656Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3190ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3191ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3192ad8b1aafSjsg };
3193ad8b1aafSjsg
3194f005ef32Sjsg static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = {
3195ad8b1aafSjsg /* Pending on emulation bring up */
3196ad8b1aafSjsg };
3197ad8b1aafSjsg
3198f005ef32Sjsg static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = {
31995ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3200ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3201ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3202ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3203ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3204ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3205ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3206ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3207ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
32085ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
32095ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3210ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3211ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3212ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3213ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3214ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3215ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3216ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3217ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3218ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3219ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3220ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3221ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3222ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3223ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3224ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3225ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3226ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3227ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3228ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3229ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3230ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3231ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3232ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3233ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3234ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3235ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3236ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3237ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3238ad8b1aafSjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
32395ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
32405ca02815Sjsg
32415ca02815Sjsg /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
32425ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
32435ca02815Sjsg };
32445ca02815Sjsg
3245f005ef32Sjsg static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = {
32465ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
32475ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
32485ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
32495ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
32505ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
32515ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
32525ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
32535ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
32545ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
32555ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
32565ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
32575ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
32585ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
32595ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
32605ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
32615ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
32625ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
32635ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
32645ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
32655ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
32665ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
32675ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
32685ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
32695ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
32705ca02815Sjsg
32715ca02815Sjsg /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
32725ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
32735ca02815Sjsg };
32745ca02815Sjsg
3275f005ef32Sjsg static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = {
32765ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
32775ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
32785ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
32795ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
32805ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
32815ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
32821bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
32835ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
32845ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
32855ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
32865ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
32875ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
32885ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
32895ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
32905ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
32915ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
32925ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
32935ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
32945ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
32955ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
32965ca02815Sjsg };
32975ca02815Sjsg
3298f005ef32Sjsg static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = {
32995ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
33005ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
33015ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
33025ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
33035ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
33045ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
33055ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
33065ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
33075ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
33085ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
33095ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
33105ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
33115ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
33125ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
33135ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
33145ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
33155ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
33165ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
33175ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
33185ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
33195ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
33205ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
33215ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
33225ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
33235ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
33245ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
33255ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
33265ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
33275ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
33285ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
33295ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
33305ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
33315ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
33325ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
33335ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
33345ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020)
33355ca02815Sjsg };
33365ca02815Sjsg
33375ca02815Sjsg static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
33385ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
33395ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
33405ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
33415ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
33425ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
33435ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
33445ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
33455ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
33465ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
33475ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
33485ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
33495ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
33505ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
33515ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
33525ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
33535ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
33545ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
33555ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
33565ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
33575ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
33585ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
33595ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
33605ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
33615ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
33625ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
33635ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
33645ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
33655ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
33665ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
33675ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
33685ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
33695ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
33705ca02815Sjsg };
33715ca02815Sjsg
33725ca02815Sjsg static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
33735ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000),
33745ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e),
33755ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
33765ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100),
33775ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000),
33785ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014),
33795ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
33805ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8),
33815ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003),
33825ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
33835ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
33845ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
33855ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
33865ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210),
33875ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
33885ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500),
33895ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff),
33905ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
33915ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8),
33925ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130),
33935ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130),
33945ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
33955ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
33965ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
33975ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f),
33985ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188),
33995ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009),
34005ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02),
34015ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000),
34025ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101),
34035ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
34045ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
34055ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
34065ca02815Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
3407ad8b1aafSjsg };
3408ad8b1aafSjsg
3409f005ef32Sjsg static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = {
34101bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
34111bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),
34121bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
34131bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
34141bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
34151bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),
34161bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
34171bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),
34181bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
34191bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
34201bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
34211bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
34221bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
34231bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
34241bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
34251bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
34261bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
34271bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
34281bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
34291bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
34301bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
34311bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
34321bb76ff1Sjsg };
34331bb76ff1Sjsg
34341bb76ff1Sjsg static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
34351bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
34361bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
34371bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
34381bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
34391bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
34401bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),
34411bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
34421bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
34431bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
34441bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
34451bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
34461bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
34471bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
34481bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
34491bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
34501bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),
34511bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
34521bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
34531bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
34541bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
34551bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
34561bb76ff1Sjsg SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
34571bb76ff1Sjsg };
34581bb76ff1Sjsg
3459c349dbc7Sjsg #define DEFAULT_SH_MEM_CONFIG \
3460c349dbc7Sjsg ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3461c349dbc7Sjsg (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3462c349dbc7Sjsg (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3463c349dbc7Sjsg (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3464c349dbc7Sjsg
34655ca02815Sjsg /* TODO: pending on golden setting value of gb address config */
34665ca02815Sjsg #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044
3467c349dbc7Sjsg
3468c349dbc7Sjsg static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3469c349dbc7Sjsg static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3470c349dbc7Sjsg static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3471c349dbc7Sjsg static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
34721bb76ff1Sjsg static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev);
3473c349dbc7Sjsg static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3474c349dbc7Sjsg struct amdgpu_cu_info *cu_info);
3475c349dbc7Sjsg static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3476c349dbc7Sjsg static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3477f005ef32Sjsg u32 sh_num, u32 instance, int xcc_id);
3478c349dbc7Sjsg static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3479c349dbc7Sjsg
3480c349dbc7Sjsg static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3481c349dbc7Sjsg static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3482c349dbc7Sjsg static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3483c349dbc7Sjsg static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3484c349dbc7Sjsg static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3485c349dbc7Sjsg static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3486ad8b1aafSjsg static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3487ad8b1aafSjsg static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3488ad8b1aafSjsg static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
34895ca02815Sjsg static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
34901bb76ff1Sjsg static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
34911bb76ff1Sjsg uint16_t pasid, uint32_t flush_type,
34921bb76ff1Sjsg bool all_hub, uint8_t dst_sel);
3493f005ef32Sjsg static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
3494f005ef32Sjsg unsigned int vmid);
3495c349dbc7Sjsg
gfx10_kiq_set_resources(struct amdgpu_ring * kiq_ring,uint64_t queue_mask)3496c349dbc7Sjsg static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3497c349dbc7Sjsg {
3498c349dbc7Sjsg amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3499c349dbc7Sjsg amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3500c349dbc7Sjsg PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3501c349dbc7Sjsg amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3502c349dbc7Sjsg amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3503c349dbc7Sjsg amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3504c349dbc7Sjsg amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3505c349dbc7Sjsg amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3506c349dbc7Sjsg amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3507c349dbc7Sjsg }
3508c349dbc7Sjsg
gfx10_kiq_map_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring)3509c349dbc7Sjsg static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3510c349dbc7Sjsg struct amdgpu_ring *ring)
3511c349dbc7Sjsg {
3512c349dbc7Sjsg uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
35131bb76ff1Sjsg uint64_t wptr_addr = ring->wptr_gpu_addr;
35141bb76ff1Sjsg uint32_t eng_sel = 0;
35151bb76ff1Sjsg
35161bb76ff1Sjsg switch (ring->funcs->type) {
35171bb76ff1Sjsg case AMDGPU_RING_TYPE_COMPUTE:
35181bb76ff1Sjsg eng_sel = 0;
35191bb76ff1Sjsg break;
35201bb76ff1Sjsg case AMDGPU_RING_TYPE_GFX:
35211bb76ff1Sjsg eng_sel = 4;
35221bb76ff1Sjsg break;
35231bb76ff1Sjsg case AMDGPU_RING_TYPE_MES:
35241bb76ff1Sjsg eng_sel = 5;
35251bb76ff1Sjsg break;
35261bb76ff1Sjsg default:
35271bb76ff1Sjsg WARN_ON(1);
35281bb76ff1Sjsg }
3529c349dbc7Sjsg
3530c349dbc7Sjsg amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3531c349dbc7Sjsg /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3532c349dbc7Sjsg amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3533c349dbc7Sjsg PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3534c349dbc7Sjsg PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3535c349dbc7Sjsg PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3536c349dbc7Sjsg PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3537c349dbc7Sjsg PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3538c349dbc7Sjsg PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3539c349dbc7Sjsg PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3540c349dbc7Sjsg PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3541c349dbc7Sjsg PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3542c349dbc7Sjsg amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3543c349dbc7Sjsg amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3544c349dbc7Sjsg amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3545c349dbc7Sjsg amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3546c349dbc7Sjsg amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3547c349dbc7Sjsg }
3548c349dbc7Sjsg
gfx10_kiq_unmap_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,enum amdgpu_unmap_queues_action action,u64 gpu_addr,u64 seq)3549c349dbc7Sjsg static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3550c349dbc7Sjsg struct amdgpu_ring *ring,
3551c349dbc7Sjsg enum amdgpu_unmap_queues_action action,
3552c349dbc7Sjsg u64 gpu_addr, u64 seq)
3553c349dbc7Sjsg {
35541bb76ff1Sjsg struct amdgpu_device *adev = kiq_ring->adev;
3555c349dbc7Sjsg uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3556c349dbc7Sjsg
3557f005ef32Sjsg if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
35581bb76ff1Sjsg amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
35591bb76ff1Sjsg return;
35601bb76ff1Sjsg }
35611bb76ff1Sjsg
3562c349dbc7Sjsg amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3563c349dbc7Sjsg amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3564c349dbc7Sjsg PACKET3_UNMAP_QUEUES_ACTION(action) |
3565c349dbc7Sjsg PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3566c349dbc7Sjsg PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3567c349dbc7Sjsg PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3568c349dbc7Sjsg amdgpu_ring_write(kiq_ring,
3569c349dbc7Sjsg PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3570c349dbc7Sjsg
3571c349dbc7Sjsg if (action == PREEMPT_QUEUES_NO_UNMAP) {
3572c349dbc7Sjsg amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3573c349dbc7Sjsg amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3574c349dbc7Sjsg amdgpu_ring_write(kiq_ring, seq);
3575c349dbc7Sjsg } else {
3576c349dbc7Sjsg amdgpu_ring_write(kiq_ring, 0);
3577c349dbc7Sjsg amdgpu_ring_write(kiq_ring, 0);
3578c349dbc7Sjsg amdgpu_ring_write(kiq_ring, 0);
3579c349dbc7Sjsg }
3580c349dbc7Sjsg }
3581c349dbc7Sjsg
gfx10_kiq_query_status(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,u64 addr,u64 seq)3582c349dbc7Sjsg static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3583c349dbc7Sjsg struct amdgpu_ring *ring,
3584c349dbc7Sjsg u64 addr,
3585c349dbc7Sjsg u64 seq)
3586c349dbc7Sjsg {
3587c349dbc7Sjsg uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3588c349dbc7Sjsg
3589c349dbc7Sjsg amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3590c349dbc7Sjsg amdgpu_ring_write(kiq_ring,
3591c349dbc7Sjsg PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3592c349dbc7Sjsg PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3593c349dbc7Sjsg PACKET3_QUERY_STATUS_COMMAND(2));
3594c349dbc7Sjsg amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3595c349dbc7Sjsg PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3596c349dbc7Sjsg PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3597c349dbc7Sjsg amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3598c349dbc7Sjsg amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3599c349dbc7Sjsg amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3600c349dbc7Sjsg amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3601c349dbc7Sjsg }
3602c349dbc7Sjsg
gfx10_kiq_invalidate_tlbs(struct amdgpu_ring * kiq_ring,uint16_t pasid,uint32_t flush_type,bool all_hub)3603c349dbc7Sjsg static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3604c349dbc7Sjsg uint16_t pasid, uint32_t flush_type,
3605c349dbc7Sjsg bool all_hub)
3606c349dbc7Sjsg {
36071bb76ff1Sjsg gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
3608c349dbc7Sjsg }
3609c349dbc7Sjsg
3610c349dbc7Sjsg static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3611c349dbc7Sjsg .kiq_set_resources = gfx10_kiq_set_resources,
3612c349dbc7Sjsg .kiq_map_queues = gfx10_kiq_map_queues,
3613c349dbc7Sjsg .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3614c349dbc7Sjsg .kiq_query_status = gfx10_kiq_query_status,
3615c349dbc7Sjsg .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3616c349dbc7Sjsg .set_resources_size = 8,
3617c349dbc7Sjsg .map_queues_size = 7,
3618c349dbc7Sjsg .unmap_queues_size = 6,
3619c349dbc7Sjsg .query_status_size = 7,
3620c349dbc7Sjsg .invalidate_tlbs_size = 2,
3621c349dbc7Sjsg };
3622c349dbc7Sjsg
gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device * adev)3623c349dbc7Sjsg static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3624c349dbc7Sjsg {
3625f005ef32Sjsg adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs;
3626c349dbc7Sjsg }
3627c349dbc7Sjsg
gfx_v10_0_init_spm_golden_registers(struct amdgpu_device * adev)3628ad8b1aafSjsg static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3629ad8b1aafSjsg {
36301bb76ff1Sjsg switch (adev->ip_versions[GC_HWIP][0]) {
36311bb76ff1Sjsg case IP_VERSION(10, 1, 10):
3632ad8b1aafSjsg soc15_program_register_sequence(adev,
3633ad8b1aafSjsg golden_settings_gc_rlc_spm_10_0_nv10,
3634ad8b1aafSjsg (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3635ad8b1aafSjsg break;
36361bb76ff1Sjsg case IP_VERSION(10, 1, 1):
3637ad8b1aafSjsg soc15_program_register_sequence(adev,
3638ad8b1aafSjsg golden_settings_gc_rlc_spm_10_1_nv14,
3639ad8b1aafSjsg (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3640ad8b1aafSjsg break;
36411bb76ff1Sjsg case IP_VERSION(10, 1, 2):
3642ad8b1aafSjsg soc15_program_register_sequence(adev,
3643ad8b1aafSjsg golden_settings_gc_rlc_spm_10_1_2_nv12,
3644ad8b1aafSjsg (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3645ad8b1aafSjsg break;
3646ad8b1aafSjsg default:
3647ad8b1aafSjsg break;
3648ad8b1aafSjsg }
3649ad8b1aafSjsg }
3650ad8b1aafSjsg
gfx_v10_0_init_golden_registers(struct amdgpu_device * adev)3651c349dbc7Sjsg static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3652c349dbc7Sjsg {
36531bb76ff1Sjsg switch (adev->ip_versions[GC_HWIP][0]) {
36541bb76ff1Sjsg case IP_VERSION(10, 1, 10):
3655c349dbc7Sjsg soc15_program_register_sequence(adev,
3656c349dbc7Sjsg golden_settings_gc_10_1,
3657c349dbc7Sjsg (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3658c349dbc7Sjsg soc15_program_register_sequence(adev,
3659c349dbc7Sjsg golden_settings_gc_10_0_nv10,
3660c349dbc7Sjsg (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3661c349dbc7Sjsg break;
36621bb76ff1Sjsg case IP_VERSION(10, 1, 1):
3663c349dbc7Sjsg soc15_program_register_sequence(adev,
3664c349dbc7Sjsg golden_settings_gc_10_1_1,
3665c349dbc7Sjsg (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3666c349dbc7Sjsg soc15_program_register_sequence(adev,
3667c349dbc7Sjsg golden_settings_gc_10_1_nv14,
3668c349dbc7Sjsg (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3669c349dbc7Sjsg break;
36701bb76ff1Sjsg case IP_VERSION(10, 1, 2):
3671c349dbc7Sjsg soc15_program_register_sequence(adev,
3672c349dbc7Sjsg golden_settings_gc_10_1_2,
3673c349dbc7Sjsg (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3674c349dbc7Sjsg soc15_program_register_sequence(adev,
3675c349dbc7Sjsg golden_settings_gc_10_1_2_nv12,
3676c349dbc7Sjsg (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3677c349dbc7Sjsg break;
36781bb76ff1Sjsg case IP_VERSION(10, 3, 0):
3679ad8b1aafSjsg soc15_program_register_sequence(adev,
3680ad8b1aafSjsg golden_settings_gc_10_3,
3681ad8b1aafSjsg (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3682ad8b1aafSjsg soc15_program_register_sequence(adev,
3683ad8b1aafSjsg golden_settings_gc_10_3_sienna_cichlid,
3684ad8b1aafSjsg (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3685ad8b1aafSjsg break;
36861bb76ff1Sjsg case IP_VERSION(10, 3, 2):
3687ad8b1aafSjsg soc15_program_register_sequence(adev,
3688ad8b1aafSjsg golden_settings_gc_10_3_2,
3689ad8b1aafSjsg (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3690ad8b1aafSjsg break;
36911bb76ff1Sjsg case IP_VERSION(10, 3, 1):
36925ca02815Sjsg soc15_program_register_sequence(adev,
36935ca02815Sjsg golden_settings_gc_10_3_vangogh,
36945ca02815Sjsg (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
36955ca02815Sjsg break;
36961bb76ff1Sjsg case IP_VERSION(10, 3, 3):
36975ca02815Sjsg soc15_program_register_sequence(adev,
36985ca02815Sjsg golden_settings_gc_10_3_3,
36995ca02815Sjsg (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
37005ca02815Sjsg break;
37011bb76ff1Sjsg case IP_VERSION(10, 3, 4):
37025ca02815Sjsg soc15_program_register_sequence(adev,
37035ca02815Sjsg golden_settings_gc_10_3_4,
37045ca02815Sjsg (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
37055ca02815Sjsg break;
37061bb76ff1Sjsg case IP_VERSION(10, 3, 5):
37075ca02815Sjsg soc15_program_register_sequence(adev,
37085ca02815Sjsg golden_settings_gc_10_3_5,
37095ca02815Sjsg (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
37105ca02815Sjsg break;
37111bb76ff1Sjsg case IP_VERSION(10, 1, 3):
37121bb76ff1Sjsg case IP_VERSION(10, 1, 4):
37135ca02815Sjsg soc15_program_register_sequence(adev,
37145ca02815Sjsg golden_settings_gc_10_0_cyan_skillfish,
37155ca02815Sjsg (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
37165ca02815Sjsg break;
37171bb76ff1Sjsg case IP_VERSION(10, 3, 6):
37181bb76ff1Sjsg soc15_program_register_sequence(adev,
37191bb76ff1Sjsg golden_settings_gc_10_3_6,
37201bb76ff1Sjsg (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));
37211bb76ff1Sjsg break;
37221bb76ff1Sjsg case IP_VERSION(10, 3, 7):
37231bb76ff1Sjsg soc15_program_register_sequence(adev,
37241bb76ff1Sjsg golden_settings_gc_10_3_7,
37251bb76ff1Sjsg (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));
37261bb76ff1Sjsg break;
3727c349dbc7Sjsg default:
3728c349dbc7Sjsg break;
3729c349dbc7Sjsg }
3730ad8b1aafSjsg gfx_v10_0_init_spm_golden_registers(adev);
3731c349dbc7Sjsg }
3732c349dbc7Sjsg
gfx_v10_0_write_data_to_reg(struct amdgpu_ring * ring,int eng_sel,bool wc,uint32_t reg,uint32_t val)3733c349dbc7Sjsg static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3734c349dbc7Sjsg bool wc, uint32_t reg, uint32_t val)
3735c349dbc7Sjsg {
3736c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3737c349dbc7Sjsg amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3738c349dbc7Sjsg WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3739c349dbc7Sjsg amdgpu_ring_write(ring, reg);
3740c349dbc7Sjsg amdgpu_ring_write(ring, 0);
3741c349dbc7Sjsg amdgpu_ring_write(ring, val);
3742c349dbc7Sjsg }
3743c349dbc7Sjsg
gfx_v10_0_wait_reg_mem(struct amdgpu_ring * ring,int eng_sel,int mem_space,int opt,uint32_t addr0,uint32_t addr1,uint32_t ref,uint32_t mask,uint32_t inv)3744c349dbc7Sjsg static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3745c349dbc7Sjsg int mem_space, int opt, uint32_t addr0,
3746c349dbc7Sjsg uint32_t addr1, uint32_t ref, uint32_t mask,
3747c349dbc7Sjsg uint32_t inv)
3748c349dbc7Sjsg {
3749c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3750c349dbc7Sjsg amdgpu_ring_write(ring,
3751c349dbc7Sjsg /* memory (1) or register (0) */
3752c349dbc7Sjsg (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3753c349dbc7Sjsg WAIT_REG_MEM_OPERATION(opt) | /* wait */
3754c349dbc7Sjsg WAIT_REG_MEM_FUNCTION(3) | /* equal */
3755c349dbc7Sjsg WAIT_REG_MEM_ENGINE(eng_sel)));
3756c349dbc7Sjsg
3757c349dbc7Sjsg if (mem_space)
3758c349dbc7Sjsg BUG_ON(addr0 & 0x3); /* Dword align */
3759c349dbc7Sjsg amdgpu_ring_write(ring, addr0);
3760c349dbc7Sjsg amdgpu_ring_write(ring, addr1);
3761c349dbc7Sjsg amdgpu_ring_write(ring, ref);
3762c349dbc7Sjsg amdgpu_ring_write(ring, mask);
3763c349dbc7Sjsg amdgpu_ring_write(ring, inv); /* poll interval */
3764c349dbc7Sjsg }
3765c349dbc7Sjsg
gfx_v10_0_ring_test_ring(struct amdgpu_ring * ring)3766c349dbc7Sjsg static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3767c349dbc7Sjsg {
3768c349dbc7Sjsg struct amdgpu_device *adev = ring->adev;
37691bb76ff1Sjsg uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3770c349dbc7Sjsg uint32_t tmp = 0;
3771f005ef32Sjsg unsigned int i;
3772c349dbc7Sjsg int r;
3773c349dbc7Sjsg
3774c349dbc7Sjsg WREG32(scratch, 0xCAFEDEAD);
3775c349dbc7Sjsg r = amdgpu_ring_alloc(ring, 3);
3776c349dbc7Sjsg if (r) {
3777c349dbc7Sjsg DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3778c349dbc7Sjsg ring->idx, r);
3779c349dbc7Sjsg return r;
3780c349dbc7Sjsg }
3781c349dbc7Sjsg
3782c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
37831bb76ff1Sjsg amdgpu_ring_write(ring, scratch -
37841bb76ff1Sjsg PACKET3_SET_UCONFIG_REG_START);
3785c349dbc7Sjsg amdgpu_ring_write(ring, 0xDEADBEEF);
3786c349dbc7Sjsg amdgpu_ring_commit(ring);
3787c349dbc7Sjsg
3788c349dbc7Sjsg for (i = 0; i < adev->usec_timeout; i++) {
3789c349dbc7Sjsg tmp = RREG32(scratch);
3790c349dbc7Sjsg if (tmp == 0xDEADBEEF)
3791c349dbc7Sjsg break;
3792c349dbc7Sjsg if (amdgpu_emu_mode == 1)
3793c349dbc7Sjsg drm_msleep(1);
3794c349dbc7Sjsg else
3795c349dbc7Sjsg udelay(1);
3796c349dbc7Sjsg }
3797c349dbc7Sjsg
3798c349dbc7Sjsg if (i >= adev->usec_timeout)
3799c349dbc7Sjsg r = -ETIMEDOUT;
3800c349dbc7Sjsg
3801c349dbc7Sjsg return r;
3802c349dbc7Sjsg }
3803c349dbc7Sjsg
gfx_v10_0_ring_test_ib(struct amdgpu_ring * ring,long timeout)3804c349dbc7Sjsg static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3805c349dbc7Sjsg {
3806c349dbc7Sjsg struct amdgpu_device *adev = ring->adev;
3807c349dbc7Sjsg struct amdgpu_ib ib;
3808c349dbc7Sjsg struct dma_fence *f = NULL;
3809f005ef32Sjsg unsigned int index;
3810c349dbc7Sjsg uint64_t gpu_addr;
38111bb76ff1Sjsg volatile uint32_t *cpu_ptr;
3812c349dbc7Sjsg long r;
3813c349dbc7Sjsg
38141bb76ff1Sjsg memset(&ib, 0, sizeof(ib));
38151bb76ff1Sjsg
38161bb76ff1Sjsg if (ring->is_mes_queue) {
38171bb76ff1Sjsg uint32_t padding, offset;
38181bb76ff1Sjsg
38191bb76ff1Sjsg offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
38201bb76ff1Sjsg padding = amdgpu_mes_ctx_get_offs(ring,
38211bb76ff1Sjsg AMDGPU_MES_CTX_PADDING_OFFS);
38221bb76ff1Sjsg
38231bb76ff1Sjsg ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
38241bb76ff1Sjsg ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
38251bb76ff1Sjsg
38261bb76ff1Sjsg gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
38271bb76ff1Sjsg cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
38281bb76ff1Sjsg *cpu_ptr = cpu_to_le32(0xCAFEDEAD);
38291bb76ff1Sjsg } else {
3830c349dbc7Sjsg r = amdgpu_device_wb_get(adev, &index);
3831c349dbc7Sjsg if (r)
3832c349dbc7Sjsg return r;
3833c349dbc7Sjsg
3834c349dbc7Sjsg gpu_addr = adev->wb.gpu_addr + (index * 4);
3835c349dbc7Sjsg adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
38361bb76ff1Sjsg cpu_ptr = &adev->wb.wb[index];
38371bb76ff1Sjsg
38381bb76ff1Sjsg r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
38391bb76ff1Sjsg if (r) {
38401bb76ff1Sjsg DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
3841c349dbc7Sjsg goto err1;
38421bb76ff1Sjsg }
38431bb76ff1Sjsg }
3844c349dbc7Sjsg
3845c349dbc7Sjsg ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3846c349dbc7Sjsg ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3847c349dbc7Sjsg ib.ptr[2] = lower_32_bits(gpu_addr);
3848c349dbc7Sjsg ib.ptr[3] = upper_32_bits(gpu_addr);
3849c349dbc7Sjsg ib.ptr[4] = 0xDEADBEEF;
3850c349dbc7Sjsg ib.length_dw = 5;
3851c349dbc7Sjsg
3852c349dbc7Sjsg r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3853c349dbc7Sjsg if (r)
3854c349dbc7Sjsg goto err2;
3855c349dbc7Sjsg
3856c349dbc7Sjsg r = dma_fence_wait_timeout(f, false, timeout);
3857c349dbc7Sjsg if (r == 0) {
3858c349dbc7Sjsg r = -ETIMEDOUT;
3859c349dbc7Sjsg goto err2;
3860c349dbc7Sjsg } else if (r < 0) {
3861c349dbc7Sjsg goto err2;
3862c349dbc7Sjsg }
3863c349dbc7Sjsg
38641bb76ff1Sjsg if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
3865c349dbc7Sjsg r = 0;
3866c349dbc7Sjsg else
3867c349dbc7Sjsg r = -EINVAL;
3868c349dbc7Sjsg err2:
38691bb76ff1Sjsg if (!ring->is_mes_queue)
3870c349dbc7Sjsg amdgpu_ib_free(adev, &ib, NULL);
3871c349dbc7Sjsg dma_fence_put(f);
3872c349dbc7Sjsg err1:
38731bb76ff1Sjsg if (!ring->is_mes_queue)
3874c349dbc7Sjsg amdgpu_device_wb_free(adev, index);
3875c349dbc7Sjsg return r;
3876c349dbc7Sjsg }
3877c349dbc7Sjsg
gfx_v10_0_free_microcode(struct amdgpu_device * adev)3878c349dbc7Sjsg static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3879c349dbc7Sjsg {
3880f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.pfp_fw);
3881f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.me_fw);
3882f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.ce_fw);
3883f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.rlc_fw);
3884f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.mec_fw);
3885f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.mec2_fw);
3886c349dbc7Sjsg
3887c349dbc7Sjsg kfree(adev->gfx.rlc.register_list_format);
3888c349dbc7Sjsg }
3889c349dbc7Sjsg
gfx_v10_0_check_fw_write_wait(struct amdgpu_device * adev)3890c349dbc7Sjsg static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3891c349dbc7Sjsg {
3892c349dbc7Sjsg adev->gfx.cp_fw_write_wait = false;
3893c349dbc7Sjsg
38941bb76ff1Sjsg switch (adev->ip_versions[GC_HWIP][0]) {
38951bb76ff1Sjsg case IP_VERSION(10, 1, 10):
38961bb76ff1Sjsg case IP_VERSION(10, 1, 2):
38971bb76ff1Sjsg case IP_VERSION(10, 1, 1):
38981bb76ff1Sjsg case IP_VERSION(10, 1, 3):
38991bb76ff1Sjsg case IP_VERSION(10, 1, 4):
3900c349dbc7Sjsg if ((adev->gfx.me_fw_version >= 0x00000046) &&
3901c349dbc7Sjsg (adev->gfx.me_feature_version >= 27) &&
3902c349dbc7Sjsg (adev->gfx.pfp_fw_version >= 0x00000068) &&
3903c349dbc7Sjsg (adev->gfx.pfp_feature_version >= 27) &&
3904c349dbc7Sjsg (adev->gfx.mec_fw_version >= 0x0000005b) &&
3905c349dbc7Sjsg (adev->gfx.mec_feature_version >= 27))
3906c349dbc7Sjsg adev->gfx.cp_fw_write_wait = true;
3907c349dbc7Sjsg break;
39081bb76ff1Sjsg case IP_VERSION(10, 3, 0):
39091bb76ff1Sjsg case IP_VERSION(10, 3, 2):
39101bb76ff1Sjsg case IP_VERSION(10, 3, 1):
39111bb76ff1Sjsg case IP_VERSION(10, 3, 4):
39121bb76ff1Sjsg case IP_VERSION(10, 3, 5):
39131bb76ff1Sjsg case IP_VERSION(10, 3, 6):
39141bb76ff1Sjsg case IP_VERSION(10, 3, 3):
39151bb76ff1Sjsg case IP_VERSION(10, 3, 7):
3916ad8b1aafSjsg adev->gfx.cp_fw_write_wait = true;
3917ad8b1aafSjsg break;
3918c349dbc7Sjsg default:
3919c349dbc7Sjsg break;
3920c349dbc7Sjsg }
3921c349dbc7Sjsg
3922ad8b1aafSjsg if (!adev->gfx.cp_fw_write_wait)
3923c349dbc7Sjsg DRM_WARN_ONCE("CP firmware version too old, please update!");
3924c349dbc7Sjsg }
3925c349dbc7Sjsg
gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device * adev)3926c349dbc7Sjsg static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3927c349dbc7Sjsg {
3928c349dbc7Sjsg bool ret = false;
3929c349dbc7Sjsg
3930c349dbc7Sjsg switch (adev->pdev->revision) {
3931c349dbc7Sjsg case 0xc2:
3932c349dbc7Sjsg case 0xc3:
3933c349dbc7Sjsg ret = true;
3934c349dbc7Sjsg break;
3935c349dbc7Sjsg default:
3936c349dbc7Sjsg ret = false;
3937c349dbc7Sjsg break;
3938c349dbc7Sjsg }
3939c349dbc7Sjsg
3940c349dbc7Sjsg return ret;
3941c349dbc7Sjsg }
3942c349dbc7Sjsg
gfx_v10_0_check_gfxoff_flag(struct amdgpu_device * adev)3943c349dbc7Sjsg static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3944c349dbc7Sjsg {
39451bb76ff1Sjsg switch (adev->ip_versions[GC_HWIP][0]) {
39461bb76ff1Sjsg case IP_VERSION(10, 1, 10):
3947c349dbc7Sjsg if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3948c349dbc7Sjsg adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3949c349dbc7Sjsg break;
3950c349dbc7Sjsg default:
3951c349dbc7Sjsg break;
3952c349dbc7Sjsg }
3953c349dbc7Sjsg }
3954c349dbc7Sjsg
gfx_v10_0_init_microcode(struct amdgpu_device * adev)3955c349dbc7Sjsg static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3956c349dbc7Sjsg {
3957c349dbc7Sjsg char fw_name[40];
3958f005ef32Sjsg char ucode_prefix[30];
3959f005ef32Sjsg const char *wks = "";
3960c349dbc7Sjsg int err;
3961c349dbc7Sjsg const struct rlc_firmware_header_v2_0 *rlc_hdr;
3962c349dbc7Sjsg uint16_t version_major;
3963c349dbc7Sjsg uint16_t version_minor;
3964c349dbc7Sjsg
3965c349dbc7Sjsg DRM_DEBUG("\n");
3966c349dbc7Sjsg
3967f005ef32Sjsg if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) &&
3968f005ef32Sjsg (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00)))
39695ca02815Sjsg wks = "_wks";
3970f005ef32Sjsg amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
3971c349dbc7Sjsg
3972f005ef32Sjsg snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", ucode_prefix, wks);
3973f005ef32Sjsg err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
3974c349dbc7Sjsg if (err)
3975c349dbc7Sjsg goto out;
39761bb76ff1Sjsg amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
3977c349dbc7Sjsg
3978f005ef32Sjsg snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", ucode_prefix, wks);
3979f005ef32Sjsg err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
3980c349dbc7Sjsg if (err)
3981c349dbc7Sjsg goto out;
39821bb76ff1Sjsg amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
3983c349dbc7Sjsg
3984f005ef32Sjsg snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", ucode_prefix, wks);
3985f005ef32Sjsg err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name);
3986c349dbc7Sjsg if (err)
3987c349dbc7Sjsg goto out;
39881bb76ff1Sjsg amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE);
3989c349dbc7Sjsg
3990c349dbc7Sjsg if (!amdgpu_sriov_vf(adev)) {
3991f005ef32Sjsg snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);
399240763ddaSjsg err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
39931bb76ff1Sjsg if (err)
399440763ddaSjsg goto out;
399540763ddaSjsg
399640763ddaSjsg /* don't validate this firmware. There are apparently firmwares
399740763ddaSjsg * in the wild with incorrect size in the header
399840763ddaSjsg */
3999c349dbc7Sjsg rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4000c349dbc7Sjsg version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4001c349dbc7Sjsg version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
40021bb76ff1Sjsg err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
40031bb76ff1Sjsg if (err)
4004c349dbc7Sjsg goto out;
4005c349dbc7Sjsg }
4006c349dbc7Sjsg
4007f005ef32Sjsg snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", ucode_prefix, wks);
4008f005ef32Sjsg err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
4009c349dbc7Sjsg if (err)
4010c349dbc7Sjsg goto out;
40111bb76ff1Sjsg amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
40121bb76ff1Sjsg amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
4013c349dbc7Sjsg
4014f005ef32Sjsg snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", ucode_prefix, wks);
4015f005ef32Sjsg err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name);
4016c349dbc7Sjsg if (!err) {
40171bb76ff1Sjsg amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
40181bb76ff1Sjsg amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
4019c349dbc7Sjsg } else {
4020c349dbc7Sjsg err = 0;
4021c349dbc7Sjsg adev->gfx.mec2_fw = NULL;
4022c349dbc7Sjsg }
4023c349dbc7Sjsg
4024c349dbc7Sjsg gfx_v10_0_check_fw_write_wait(adev);
4025c349dbc7Sjsg out:
4026c349dbc7Sjsg if (err) {
4027f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.pfp_fw);
4028f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.me_fw);
4029f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.ce_fw);
4030f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.rlc_fw);
4031f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.mec_fw);
4032f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.mec2_fw);
4033c349dbc7Sjsg }
4034c349dbc7Sjsg
4035c349dbc7Sjsg gfx_v10_0_check_gfxoff_flag(adev);
4036c349dbc7Sjsg
4037c349dbc7Sjsg return err;
4038c349dbc7Sjsg }
4039c349dbc7Sjsg
gfx_v10_0_get_csb_size(struct amdgpu_device * adev)4040c349dbc7Sjsg static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4041c349dbc7Sjsg {
4042c349dbc7Sjsg u32 count = 0;
4043c349dbc7Sjsg const struct cs_section_def *sect = NULL;
4044c349dbc7Sjsg const struct cs_extent_def *ext = NULL;
4045c349dbc7Sjsg
4046c349dbc7Sjsg /* begin clear state */
4047c349dbc7Sjsg count += 2;
4048c349dbc7Sjsg /* context control state */
4049c349dbc7Sjsg count += 3;
4050c349dbc7Sjsg
4051c349dbc7Sjsg for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4052c349dbc7Sjsg for (ext = sect->section; ext->extent != NULL; ++ext) {
4053c349dbc7Sjsg if (sect->id == SECT_CONTEXT)
4054c349dbc7Sjsg count += 2 + ext->reg_count;
4055c349dbc7Sjsg else
4056c349dbc7Sjsg return 0;
4057c349dbc7Sjsg }
4058c349dbc7Sjsg }
4059c349dbc7Sjsg
4060c349dbc7Sjsg /* set PA_SC_TILE_STEERING_OVERRIDE */
4061c349dbc7Sjsg count += 3;
4062c349dbc7Sjsg /* end clear state */
4063c349dbc7Sjsg count += 2;
4064c349dbc7Sjsg /* clear state */
4065c349dbc7Sjsg count += 2;
4066c349dbc7Sjsg
4067c349dbc7Sjsg return count;
4068c349dbc7Sjsg }
4069c349dbc7Sjsg
gfx_v10_0_get_csb_buffer(struct amdgpu_device * adev,volatile u32 * buffer)4070c349dbc7Sjsg static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4071c349dbc7Sjsg volatile u32 *buffer)
4072c349dbc7Sjsg {
4073c349dbc7Sjsg u32 count = 0, i;
4074c349dbc7Sjsg const struct cs_section_def *sect = NULL;
4075c349dbc7Sjsg const struct cs_extent_def *ext = NULL;
4076c349dbc7Sjsg int ctx_reg_offset;
4077c349dbc7Sjsg
4078c349dbc7Sjsg if (adev->gfx.rlc.cs_data == NULL)
4079c349dbc7Sjsg return;
4080c349dbc7Sjsg if (buffer == NULL)
4081c349dbc7Sjsg return;
4082c349dbc7Sjsg
4083c349dbc7Sjsg buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4084c349dbc7Sjsg buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4085c349dbc7Sjsg
4086c349dbc7Sjsg buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4087c349dbc7Sjsg buffer[count++] = cpu_to_le32(0x80000000);
4088c349dbc7Sjsg buffer[count++] = cpu_to_le32(0x80000000);
4089c349dbc7Sjsg
4090c349dbc7Sjsg for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4091c349dbc7Sjsg for (ext = sect->section; ext->extent != NULL; ++ext) {
4092c349dbc7Sjsg if (sect->id == SECT_CONTEXT) {
4093c349dbc7Sjsg buffer[count++] =
4094c349dbc7Sjsg cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4095c349dbc7Sjsg buffer[count++] = cpu_to_le32(ext->reg_index -
4096c349dbc7Sjsg PACKET3_SET_CONTEXT_REG_START);
4097c349dbc7Sjsg for (i = 0; i < ext->reg_count; i++)
4098c349dbc7Sjsg buffer[count++] = cpu_to_le32(ext->extent[i]);
4099c349dbc7Sjsg } else {
4100c349dbc7Sjsg return;
4101c349dbc7Sjsg }
4102c349dbc7Sjsg }
4103c349dbc7Sjsg }
4104c349dbc7Sjsg
4105c349dbc7Sjsg ctx_reg_offset =
4106c349dbc7Sjsg SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4107c349dbc7Sjsg buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4108c349dbc7Sjsg buffer[count++] = cpu_to_le32(ctx_reg_offset);
4109c349dbc7Sjsg buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4110c349dbc7Sjsg
4111c349dbc7Sjsg buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4112c349dbc7Sjsg buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4113c349dbc7Sjsg
4114c349dbc7Sjsg buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4115c349dbc7Sjsg buffer[count++] = cpu_to_le32(0);
4116c349dbc7Sjsg }
4117c349dbc7Sjsg
gfx_v10_0_rlc_fini(struct amdgpu_device * adev)4118c349dbc7Sjsg static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4119c349dbc7Sjsg {
4120c349dbc7Sjsg /* clear state block */
4121c349dbc7Sjsg amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4122c349dbc7Sjsg &adev->gfx.rlc.clear_state_gpu_addr,
4123c349dbc7Sjsg (void **)&adev->gfx.rlc.cs_ptr);
4124c349dbc7Sjsg
4125c349dbc7Sjsg /* jump table block */
4126c349dbc7Sjsg amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4127c349dbc7Sjsg &adev->gfx.rlc.cp_table_gpu_addr,
4128c349dbc7Sjsg (void **)&adev->gfx.rlc.cp_table_ptr);
4129c349dbc7Sjsg }
4130c349dbc7Sjsg
gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device * adev)41311bb76ff1Sjsg static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
41321bb76ff1Sjsg {
41331bb76ff1Sjsg struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
41341bb76ff1Sjsg
4135f005ef32Sjsg reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
41361bb76ff1Sjsg reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
41371bb76ff1Sjsg reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
41381bb76ff1Sjsg reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
41391bb76ff1Sjsg reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
41401bb76ff1Sjsg reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
41411bb76ff1Sjsg reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
41421bb76ff1Sjsg switch (adev->ip_versions[GC_HWIP][0]) {
41431bb76ff1Sjsg case IP_VERSION(10, 3, 0):
41441bb76ff1Sjsg reg_access_ctrl->spare_int =
41451bb76ff1Sjsg SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);
41461bb76ff1Sjsg break;
41471bb76ff1Sjsg default:
41481bb76ff1Sjsg reg_access_ctrl->spare_int =
41491bb76ff1Sjsg SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
41501bb76ff1Sjsg break;
41511bb76ff1Sjsg }
41521bb76ff1Sjsg adev->gfx.rlc.rlcg_reg_access_supported = true;
41531bb76ff1Sjsg }
41541bb76ff1Sjsg
gfx_v10_0_rlc_init(struct amdgpu_device * adev)4155c349dbc7Sjsg static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4156c349dbc7Sjsg {
4157c349dbc7Sjsg const struct cs_section_def *cs_data;
4158c349dbc7Sjsg int r;
4159c349dbc7Sjsg
4160c349dbc7Sjsg adev->gfx.rlc.cs_data = gfx10_cs_data;
4161c349dbc7Sjsg
4162c349dbc7Sjsg cs_data = adev->gfx.rlc.cs_data;
4163c349dbc7Sjsg
4164c349dbc7Sjsg if (cs_data) {
4165c349dbc7Sjsg /* init clear state block */
4166c349dbc7Sjsg r = amdgpu_gfx_rlc_init_csb(adev);
4167c349dbc7Sjsg if (r)
4168c349dbc7Sjsg return r;
4169c349dbc7Sjsg }
4170c349dbc7Sjsg
4171c349dbc7Sjsg return 0;
4172c349dbc7Sjsg }
4173c349dbc7Sjsg
gfx_v10_0_mec_fini(struct amdgpu_device * adev)4174c349dbc7Sjsg static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4175c349dbc7Sjsg {
4176c349dbc7Sjsg amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4177c349dbc7Sjsg amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4178c349dbc7Sjsg }
4179c349dbc7Sjsg
gfx_v10_0_me_init(struct amdgpu_device * adev)4180f005ef32Sjsg static void gfx_v10_0_me_init(struct amdgpu_device *adev)
4181c349dbc7Sjsg {
4182c349dbc7Sjsg bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4183c349dbc7Sjsg
4184c349dbc7Sjsg amdgpu_gfx_graphics_queue_acquire(adev);
4185c349dbc7Sjsg }
4186c349dbc7Sjsg
gfx_v10_0_mec_init(struct amdgpu_device * adev)4187c349dbc7Sjsg static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4188c349dbc7Sjsg {
4189c349dbc7Sjsg int r;
4190c349dbc7Sjsg u32 *hpd;
4191c349dbc7Sjsg const __le32 *fw_data = NULL;
4192f005ef32Sjsg unsigned int fw_size;
4193c349dbc7Sjsg u32 *fw = NULL;
4194c349dbc7Sjsg size_t mec_hpd_size;
4195c349dbc7Sjsg
4196c349dbc7Sjsg const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4197c349dbc7Sjsg
4198f005ef32Sjsg bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4199c349dbc7Sjsg
4200c349dbc7Sjsg /* take ownership of the relevant compute queues */
4201c349dbc7Sjsg amdgpu_gfx_compute_queue_acquire(adev);
4202c349dbc7Sjsg mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4203c349dbc7Sjsg
4204ad8b1aafSjsg if (mec_hpd_size) {
4205c349dbc7Sjsg r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4206c349dbc7Sjsg AMDGPU_GEM_DOMAIN_GTT,
4207c349dbc7Sjsg &adev->gfx.mec.hpd_eop_obj,
4208c349dbc7Sjsg &adev->gfx.mec.hpd_eop_gpu_addr,
4209c349dbc7Sjsg (void **)&hpd);
4210c349dbc7Sjsg if (r) {
4211c349dbc7Sjsg dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4212c349dbc7Sjsg gfx_v10_0_mec_fini(adev);
4213c349dbc7Sjsg return r;
4214c349dbc7Sjsg }
4215c349dbc7Sjsg
4216c349dbc7Sjsg memset(hpd, 0, mec_hpd_size);
4217c349dbc7Sjsg
4218c349dbc7Sjsg amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4219c349dbc7Sjsg amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4220ad8b1aafSjsg }
4221c349dbc7Sjsg
4222c349dbc7Sjsg if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4223c349dbc7Sjsg mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4224c349dbc7Sjsg
4225c349dbc7Sjsg fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4226c349dbc7Sjsg le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4227c349dbc7Sjsg fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4228c349dbc7Sjsg
4229c349dbc7Sjsg r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4230c349dbc7Sjsg PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4231c349dbc7Sjsg &adev->gfx.mec.mec_fw_obj,
4232c349dbc7Sjsg &adev->gfx.mec.mec_fw_gpu_addr,
4233c349dbc7Sjsg (void **)&fw);
4234c349dbc7Sjsg if (r) {
4235c349dbc7Sjsg dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4236c349dbc7Sjsg gfx_v10_0_mec_fini(adev);
4237c349dbc7Sjsg return r;
4238c349dbc7Sjsg }
4239c349dbc7Sjsg
4240c349dbc7Sjsg memcpy(fw, fw_data, fw_size);
4241c349dbc7Sjsg
4242c349dbc7Sjsg amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4243c349dbc7Sjsg amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4244c349dbc7Sjsg }
4245c349dbc7Sjsg
4246c349dbc7Sjsg return 0;
4247c349dbc7Sjsg }
4248c349dbc7Sjsg
wave_read_ind(struct amdgpu_device * adev,uint32_t wave,uint32_t address)4249c349dbc7Sjsg static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4250c349dbc7Sjsg {
4251c349dbc7Sjsg WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4252c349dbc7Sjsg (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4253c349dbc7Sjsg (address << SQ_IND_INDEX__INDEX__SHIFT));
4254c349dbc7Sjsg return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4255c349dbc7Sjsg }
4256c349dbc7Sjsg
wave_read_regs(struct amdgpu_device * adev,uint32_t wave,uint32_t thread,uint32_t regno,uint32_t num,uint32_t * out)4257c349dbc7Sjsg static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4258c349dbc7Sjsg uint32_t thread, uint32_t regno,
4259c349dbc7Sjsg uint32_t num, uint32_t *out)
4260c349dbc7Sjsg {
4261c349dbc7Sjsg WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4262c349dbc7Sjsg (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4263c349dbc7Sjsg (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4264c349dbc7Sjsg (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4265c349dbc7Sjsg (SQ_IND_INDEX__AUTO_INCR_MASK));
4266c349dbc7Sjsg while (num--)
4267c349dbc7Sjsg *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4268c349dbc7Sjsg }
4269c349dbc7Sjsg
gfx_v10_0_read_wave_data(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t * dst,int * no_fields)4270f005ef32Sjsg static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4271c349dbc7Sjsg {
4272c349dbc7Sjsg /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4273c349dbc7Sjsg * field when performing a select_se_sh so it should be
4274f005ef32Sjsg * zero here
4275f005ef32Sjsg */
4276c349dbc7Sjsg WARN_ON(simd != 0);
4277c349dbc7Sjsg
4278c349dbc7Sjsg /* type 2 wave data */
4279c349dbc7Sjsg dst[(*no_fields)++] = 2;
4280c349dbc7Sjsg dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4281c349dbc7Sjsg dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4282c349dbc7Sjsg dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4283c349dbc7Sjsg dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4284c349dbc7Sjsg dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4285c349dbc7Sjsg dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4286c349dbc7Sjsg dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4287c349dbc7Sjsg dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4288c349dbc7Sjsg dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4289c349dbc7Sjsg dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4290c349dbc7Sjsg dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4291c349dbc7Sjsg dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4292c349dbc7Sjsg dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4293c349dbc7Sjsg dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4294c349dbc7Sjsg dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
42955ca02815Sjsg dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
4296c349dbc7Sjsg }
4297c349dbc7Sjsg
gfx_v10_0_read_wave_sgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t start,uint32_t size,uint32_t * dst)4298f005ef32Sjsg static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4299c349dbc7Sjsg uint32_t wave, uint32_t start,
4300c349dbc7Sjsg uint32_t size, uint32_t *dst)
4301c349dbc7Sjsg {
4302c349dbc7Sjsg WARN_ON(simd != 0);
4303c349dbc7Sjsg
4304c349dbc7Sjsg wave_read_regs(
4305c349dbc7Sjsg adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4306c349dbc7Sjsg dst);
4307c349dbc7Sjsg }
4308c349dbc7Sjsg
gfx_v10_0_read_wave_vgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t start,uint32_t size,uint32_t * dst)4309f005ef32Sjsg static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4310c349dbc7Sjsg uint32_t wave, uint32_t thread,
4311c349dbc7Sjsg uint32_t start, uint32_t size,
4312c349dbc7Sjsg uint32_t *dst)
4313c349dbc7Sjsg {
4314c349dbc7Sjsg wave_read_regs(
4315c349dbc7Sjsg adev, wave, thread,
4316c349dbc7Sjsg start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4317c349dbc7Sjsg }
4318c349dbc7Sjsg
gfx_v10_0_select_me_pipe_q(struct amdgpu_device * adev,u32 me,u32 pipe,u32 q,u32 vm,u32 xcc_id)4319c349dbc7Sjsg static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4320f005ef32Sjsg u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
4321c349dbc7Sjsg {
4322c349dbc7Sjsg nv_grbm_select(adev, me, pipe, q, vm);
4323c349dbc7Sjsg }
4324c349dbc7Sjsg
gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device * adev,bool enable)43255ca02815Sjsg static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
43265ca02815Sjsg bool enable)
43275ca02815Sjsg {
43285ca02815Sjsg uint32_t data, def;
43295ca02815Sjsg
43305ca02815Sjsg data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
43315ca02815Sjsg
43325ca02815Sjsg if (enable)
43335ca02815Sjsg data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
43345ca02815Sjsg else
43355ca02815Sjsg data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
43365ca02815Sjsg
43375ca02815Sjsg if (data != def)
43385ca02815Sjsg WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
43395ca02815Sjsg }
4340c349dbc7Sjsg
4341c349dbc7Sjsg static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4342c349dbc7Sjsg .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4343c349dbc7Sjsg .select_se_sh = &gfx_v10_0_select_se_sh,
4344c349dbc7Sjsg .read_wave_data = &gfx_v10_0_read_wave_data,
4345c349dbc7Sjsg .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4346c349dbc7Sjsg .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4347c349dbc7Sjsg .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4348ad8b1aafSjsg .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
43495ca02815Sjsg .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4350c349dbc7Sjsg };
4351c349dbc7Sjsg
gfx_v10_0_gpu_early_init(struct amdgpu_device * adev)4352c349dbc7Sjsg static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4353c349dbc7Sjsg {
4354c349dbc7Sjsg u32 gb_addr_config;
4355c349dbc7Sjsg
43561bb76ff1Sjsg switch (adev->ip_versions[GC_HWIP][0]) {
43571bb76ff1Sjsg case IP_VERSION(10, 1, 10):
43581bb76ff1Sjsg case IP_VERSION(10, 1, 1):
43591bb76ff1Sjsg case IP_VERSION(10, 1, 2):
4360c349dbc7Sjsg adev->gfx.config.max_hw_contexts = 8;
4361c349dbc7Sjsg adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4362c349dbc7Sjsg adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4363c349dbc7Sjsg adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4364c349dbc7Sjsg adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4365c349dbc7Sjsg gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4366c349dbc7Sjsg break;
43671bb76ff1Sjsg case IP_VERSION(10, 3, 0):
43681bb76ff1Sjsg case IP_VERSION(10, 3, 2):
43691bb76ff1Sjsg case IP_VERSION(10, 3, 1):
43701bb76ff1Sjsg case IP_VERSION(10, 3, 4):
43711bb76ff1Sjsg case IP_VERSION(10, 3, 5):
43721bb76ff1Sjsg case IP_VERSION(10, 3, 6):
43731bb76ff1Sjsg case IP_VERSION(10, 3, 3):
43741bb76ff1Sjsg case IP_VERSION(10, 3, 7):
4375ad8b1aafSjsg adev->gfx.config.max_hw_contexts = 8;
4376ad8b1aafSjsg adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4377ad8b1aafSjsg adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4378ad8b1aafSjsg adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4379ad8b1aafSjsg adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4380ad8b1aafSjsg gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4381ad8b1aafSjsg adev->gfx.config.gb_addr_config_fields.num_pkrs =
4382ad8b1aafSjsg 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4383ad8b1aafSjsg break;
43841bb76ff1Sjsg case IP_VERSION(10, 1, 3):
43851bb76ff1Sjsg case IP_VERSION(10, 1, 4):
43865ca02815Sjsg adev->gfx.config.max_hw_contexts = 8;
43875ca02815Sjsg adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
43885ca02815Sjsg adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
43895ca02815Sjsg adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
43905ca02815Sjsg adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
43915ca02815Sjsg gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;
43925ca02815Sjsg break;
4393c349dbc7Sjsg default:
4394c349dbc7Sjsg BUG();
4395c349dbc7Sjsg break;
4396c349dbc7Sjsg }
4397c349dbc7Sjsg
4398c349dbc7Sjsg adev->gfx.config.gb_addr_config = gb_addr_config;
4399c349dbc7Sjsg
4400c349dbc7Sjsg adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4401c349dbc7Sjsg REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4402c349dbc7Sjsg GB_ADDR_CONFIG, NUM_PIPES);
4403c349dbc7Sjsg
4404c349dbc7Sjsg adev->gfx.config.max_tile_pipes =
4405c349dbc7Sjsg adev->gfx.config.gb_addr_config_fields.num_pipes;
4406c349dbc7Sjsg
4407c349dbc7Sjsg adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4408c349dbc7Sjsg REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4409c349dbc7Sjsg GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4410c349dbc7Sjsg adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4411c349dbc7Sjsg REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4412c349dbc7Sjsg GB_ADDR_CONFIG, NUM_RB_PER_SE);
4413c349dbc7Sjsg adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4414c349dbc7Sjsg REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4415c349dbc7Sjsg GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4416c349dbc7Sjsg adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4417c349dbc7Sjsg REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4418c349dbc7Sjsg GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4419c349dbc7Sjsg }
4420c349dbc7Sjsg
gfx_v10_0_gfx_ring_init(struct amdgpu_device * adev,int ring_id,int me,int pipe,int queue)4421c349dbc7Sjsg static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4422c349dbc7Sjsg int me, int pipe, int queue)
4423c349dbc7Sjsg {
4424c349dbc7Sjsg struct amdgpu_ring *ring;
4425c349dbc7Sjsg unsigned int irq_type;
44261bb76ff1Sjsg unsigned int hw_prio;
4427c349dbc7Sjsg
4428c349dbc7Sjsg ring = &adev->gfx.gfx_ring[ring_id];
4429c349dbc7Sjsg
4430c349dbc7Sjsg ring->me = me;
4431c349dbc7Sjsg ring->pipe = pipe;
4432c349dbc7Sjsg ring->queue = queue;
4433c349dbc7Sjsg
4434c349dbc7Sjsg ring->ring_obj = NULL;
4435c349dbc7Sjsg ring->use_doorbell = true;
4436c349dbc7Sjsg
4437c349dbc7Sjsg if (!ring_id)
4438c349dbc7Sjsg ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4439c349dbc7Sjsg else
4440c349dbc7Sjsg ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4441f005ef32Sjsg ring->vm_hub = AMDGPU_GFXHUB(0);
4442c349dbc7Sjsg snprintf(ring->name, sizeof(ring->name), "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4443c349dbc7Sjsg
4444c349dbc7Sjsg irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
44451bb76ff1Sjsg hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
44461bb76ff1Sjsg AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
44471bb76ff1Sjsg return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
44481bb76ff1Sjsg hw_prio, NULL);
4449c349dbc7Sjsg }
4450c349dbc7Sjsg
gfx_v10_0_compute_ring_init(struct amdgpu_device * adev,int ring_id,int mec,int pipe,int queue)4451c349dbc7Sjsg static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4452c349dbc7Sjsg int mec, int pipe, int queue)
4453c349dbc7Sjsg {
4454f005ef32Sjsg unsigned int irq_type;
4455ad8b1aafSjsg struct amdgpu_ring *ring;
4456ad8b1aafSjsg unsigned int hw_prio;
4457c349dbc7Sjsg
4458c349dbc7Sjsg ring = &adev->gfx.compute_ring[ring_id];
4459c349dbc7Sjsg
4460c349dbc7Sjsg /* mec0 is me1 */
4461c349dbc7Sjsg ring->me = mec + 1;
4462c349dbc7Sjsg ring->pipe = pipe;
4463c349dbc7Sjsg ring->queue = queue;
4464c349dbc7Sjsg
4465c349dbc7Sjsg ring->ring_obj = NULL;
4466c349dbc7Sjsg ring->use_doorbell = true;
4467c349dbc7Sjsg ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4468c349dbc7Sjsg ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4469c349dbc7Sjsg + (ring_id * GFX10_MEC_HPD_SIZE);
4470f005ef32Sjsg ring->vm_hub = AMDGPU_GFXHUB(0);
4471c349dbc7Sjsg snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4472c349dbc7Sjsg
4473c349dbc7Sjsg irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4474c349dbc7Sjsg + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4475c349dbc7Sjsg + ring->pipe;
44765ca02815Sjsg hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
44771bb76ff1Sjsg AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
4478c349dbc7Sjsg /* type-2 packets are deprecated on MEC, use type-3 instead */
44791bb76ff1Sjsg return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
44805ca02815Sjsg hw_prio, NULL);
4481c349dbc7Sjsg }
4482c349dbc7Sjsg
gfx_v10_0_sw_init(void * handle)4483c349dbc7Sjsg static int gfx_v10_0_sw_init(void *handle)
4484c349dbc7Sjsg {
4485c349dbc7Sjsg int i, j, k, r, ring_id = 0;
4486c349dbc7Sjsg struct amdgpu_kiq *kiq;
4487c349dbc7Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4488c349dbc7Sjsg
44891bb76ff1Sjsg switch (adev->ip_versions[GC_HWIP][0]) {
44901bb76ff1Sjsg case IP_VERSION(10, 1, 10):
44911bb76ff1Sjsg case IP_VERSION(10, 1, 1):
44921bb76ff1Sjsg case IP_VERSION(10, 1, 2):
44931bb76ff1Sjsg case IP_VERSION(10, 1, 3):
44941bb76ff1Sjsg case IP_VERSION(10, 1, 4):
4495c349dbc7Sjsg adev->gfx.me.num_me = 1;
4496c349dbc7Sjsg adev->gfx.me.num_pipe_per_me = 1;
4497c349dbc7Sjsg adev->gfx.me.num_queue_per_pipe = 1;
4498c349dbc7Sjsg adev->gfx.mec.num_mec = 2;
4499c349dbc7Sjsg adev->gfx.mec.num_pipe_per_mec = 4;
4500c349dbc7Sjsg adev->gfx.mec.num_queue_per_pipe = 8;
4501c349dbc7Sjsg break;
45021bb76ff1Sjsg case IP_VERSION(10, 3, 0):
45031bb76ff1Sjsg case IP_VERSION(10, 3, 2):
45041bb76ff1Sjsg case IP_VERSION(10, 3, 1):
45051bb76ff1Sjsg case IP_VERSION(10, 3, 4):
45061bb76ff1Sjsg case IP_VERSION(10, 3, 5):
45071bb76ff1Sjsg case IP_VERSION(10, 3, 6):
45081bb76ff1Sjsg case IP_VERSION(10, 3, 3):
45091bb76ff1Sjsg case IP_VERSION(10, 3, 7):
4510ad8b1aafSjsg adev->gfx.me.num_me = 1;
4511ad8b1aafSjsg adev->gfx.me.num_pipe_per_me = 1;
4512ad8b1aafSjsg adev->gfx.me.num_queue_per_pipe = 1;
4513ad8b1aafSjsg adev->gfx.mec.num_mec = 2;
4514ad8b1aafSjsg adev->gfx.mec.num_pipe_per_mec = 4;
4515ad8b1aafSjsg adev->gfx.mec.num_queue_per_pipe = 4;
4516ad8b1aafSjsg break;
4517c349dbc7Sjsg default:
4518c349dbc7Sjsg adev->gfx.me.num_me = 1;
4519c349dbc7Sjsg adev->gfx.me.num_pipe_per_me = 1;
4520c349dbc7Sjsg adev->gfx.me.num_queue_per_pipe = 1;
4521c349dbc7Sjsg adev->gfx.mec.num_mec = 1;
4522c349dbc7Sjsg adev->gfx.mec.num_pipe_per_mec = 4;
4523c349dbc7Sjsg adev->gfx.mec.num_queue_per_pipe = 8;
4524c349dbc7Sjsg break;
4525c349dbc7Sjsg }
4526c349dbc7Sjsg
4527c349dbc7Sjsg /* KIQ event */
4528c349dbc7Sjsg r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4529c349dbc7Sjsg GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4530f005ef32Sjsg &adev->gfx.kiq[0].irq);
4531c349dbc7Sjsg if (r)
4532c349dbc7Sjsg return r;
4533c349dbc7Sjsg
4534c349dbc7Sjsg /* EOP Event */
4535c349dbc7Sjsg r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4536c349dbc7Sjsg GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4537c349dbc7Sjsg &adev->gfx.eop_irq);
4538c349dbc7Sjsg if (r)
4539c349dbc7Sjsg return r;
4540c349dbc7Sjsg
4541c349dbc7Sjsg /* Privileged reg */
4542c349dbc7Sjsg r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4543c349dbc7Sjsg &adev->gfx.priv_reg_irq);
4544c349dbc7Sjsg if (r)
4545c349dbc7Sjsg return r;
4546c349dbc7Sjsg
4547c349dbc7Sjsg /* Privileged inst */
4548c349dbc7Sjsg r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4549c349dbc7Sjsg &adev->gfx.priv_inst_irq);
4550c349dbc7Sjsg if (r)
4551c349dbc7Sjsg return r;
4552c349dbc7Sjsg
4553c349dbc7Sjsg adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4554c349dbc7Sjsg
4555f005ef32Sjsg gfx_v10_0_me_init(adev);
4556c349dbc7Sjsg
45571bb76ff1Sjsg if (adev->gfx.rlc.funcs) {
45581bb76ff1Sjsg if (adev->gfx.rlc.funcs->init) {
45591bb76ff1Sjsg r = adev->gfx.rlc.funcs->init(adev);
4560c349dbc7Sjsg if (r) {
45611bb76ff1Sjsg dev_err(adev->dev, "Failed to init rlc BOs!\n");
4562c349dbc7Sjsg return r;
4563c349dbc7Sjsg }
45641bb76ff1Sjsg }
45651bb76ff1Sjsg }
4566c349dbc7Sjsg
4567c349dbc7Sjsg r = gfx_v10_0_mec_init(adev);
4568c349dbc7Sjsg if (r) {
4569c349dbc7Sjsg DRM_ERROR("Failed to init MEC BOs!\n");
4570c349dbc7Sjsg return r;
4571c349dbc7Sjsg }
4572c349dbc7Sjsg
4573c349dbc7Sjsg /* set up the gfx ring */
4574c349dbc7Sjsg for (i = 0; i < adev->gfx.me.num_me; i++) {
4575c349dbc7Sjsg for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4576c349dbc7Sjsg for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4577c349dbc7Sjsg if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4578c349dbc7Sjsg continue;
4579c349dbc7Sjsg
4580c349dbc7Sjsg r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4581c349dbc7Sjsg i, k, j);
4582c349dbc7Sjsg if (r)
4583c349dbc7Sjsg return r;
4584c349dbc7Sjsg ring_id++;
4585c349dbc7Sjsg }
4586c349dbc7Sjsg }
4587c349dbc7Sjsg }
4588c349dbc7Sjsg
4589c349dbc7Sjsg ring_id = 0;
4590c349dbc7Sjsg /* set up the compute queues - allocate horizontally across pipes */
4591c349dbc7Sjsg for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4592c349dbc7Sjsg for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4593c349dbc7Sjsg for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4594f005ef32Sjsg if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
4595f005ef32Sjsg k, j))
4596c349dbc7Sjsg continue;
4597c349dbc7Sjsg
4598c349dbc7Sjsg r = gfx_v10_0_compute_ring_init(adev, ring_id,
4599c349dbc7Sjsg i, k, j);
4600c349dbc7Sjsg if (r)
4601c349dbc7Sjsg return r;
4602c349dbc7Sjsg
4603c349dbc7Sjsg ring_id++;
4604c349dbc7Sjsg }
4605c349dbc7Sjsg }
4606c349dbc7Sjsg }
4607c349dbc7Sjsg
46081bb76ff1Sjsg if (!adev->enable_mes_kiq) {
4609f005ef32Sjsg r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0);
4610c349dbc7Sjsg if (r) {
4611c349dbc7Sjsg DRM_ERROR("Failed to init KIQ BOs!\n");
4612c349dbc7Sjsg return r;
4613c349dbc7Sjsg }
4614c349dbc7Sjsg
4615f005ef32Sjsg kiq = &adev->gfx.kiq[0];
4616f005ef32Sjsg r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0);
4617c349dbc7Sjsg if (r)
4618c349dbc7Sjsg return r;
46191bb76ff1Sjsg }
4620c349dbc7Sjsg
4621f005ef32Sjsg r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0);
4622c349dbc7Sjsg if (r)
4623c349dbc7Sjsg return r;
4624c349dbc7Sjsg
4625c349dbc7Sjsg /* allocate visible FB for rlc auto-loading fw */
4626c349dbc7Sjsg if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4627c349dbc7Sjsg r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4628c349dbc7Sjsg if (r)
4629c349dbc7Sjsg return r;
4630c349dbc7Sjsg }
4631c349dbc7Sjsg
4632c349dbc7Sjsg adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4633c349dbc7Sjsg
4634c349dbc7Sjsg gfx_v10_0_gpu_early_init(adev);
4635c349dbc7Sjsg
4636c349dbc7Sjsg return 0;
4637c349dbc7Sjsg }
4638c349dbc7Sjsg
gfx_v10_0_pfp_fini(struct amdgpu_device * adev)4639c349dbc7Sjsg static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4640c349dbc7Sjsg {
4641c349dbc7Sjsg amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4642c349dbc7Sjsg &adev->gfx.pfp.pfp_fw_gpu_addr,
4643c349dbc7Sjsg (void **)&adev->gfx.pfp.pfp_fw_ptr);
4644c349dbc7Sjsg }
4645c349dbc7Sjsg
gfx_v10_0_ce_fini(struct amdgpu_device * adev)4646c349dbc7Sjsg static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4647c349dbc7Sjsg {
4648c349dbc7Sjsg amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4649c349dbc7Sjsg &adev->gfx.ce.ce_fw_gpu_addr,
4650c349dbc7Sjsg (void **)&adev->gfx.ce.ce_fw_ptr);
4651c349dbc7Sjsg }
4652c349dbc7Sjsg
gfx_v10_0_me_fini(struct amdgpu_device * adev)4653c349dbc7Sjsg static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4654c349dbc7Sjsg {
4655c349dbc7Sjsg amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4656c349dbc7Sjsg &adev->gfx.me.me_fw_gpu_addr,
4657c349dbc7Sjsg (void **)&adev->gfx.me.me_fw_ptr);
4658c349dbc7Sjsg }
4659c349dbc7Sjsg
gfx_v10_0_sw_fini(void * handle)4660c349dbc7Sjsg static int gfx_v10_0_sw_fini(void *handle)
4661c349dbc7Sjsg {
4662c349dbc7Sjsg int i;
4663c349dbc7Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4664c349dbc7Sjsg
4665c349dbc7Sjsg for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4666c349dbc7Sjsg amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4667c349dbc7Sjsg for (i = 0; i < adev->gfx.num_compute_rings; i++)
4668c349dbc7Sjsg amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4669c349dbc7Sjsg
4670f005ef32Sjsg amdgpu_gfx_mqd_sw_fini(adev, 0);
46711bb76ff1Sjsg
46721bb76ff1Sjsg if (!adev->enable_mes_kiq) {
4673f005ef32Sjsg amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
4674f005ef32Sjsg amdgpu_gfx_kiq_fini(adev, 0);
46751bb76ff1Sjsg }
4676c349dbc7Sjsg
4677c349dbc7Sjsg gfx_v10_0_pfp_fini(adev);
4678c349dbc7Sjsg gfx_v10_0_ce_fini(adev);
4679c349dbc7Sjsg gfx_v10_0_me_fini(adev);
4680c349dbc7Sjsg gfx_v10_0_rlc_fini(adev);
4681c349dbc7Sjsg gfx_v10_0_mec_fini(adev);
4682c349dbc7Sjsg
4683c349dbc7Sjsg if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4684c349dbc7Sjsg gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4685c349dbc7Sjsg
4686c349dbc7Sjsg gfx_v10_0_free_microcode(adev);
4687c349dbc7Sjsg
4688c349dbc7Sjsg return 0;
4689c349dbc7Sjsg }
4690c349dbc7Sjsg
gfx_v10_0_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance,int xcc_id)4691c349dbc7Sjsg static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4692f005ef32Sjsg u32 sh_num, u32 instance, int xcc_id)
4693c349dbc7Sjsg {
4694c349dbc7Sjsg u32 data;
4695c349dbc7Sjsg
4696c349dbc7Sjsg if (instance == 0xffffffff)
4697c349dbc7Sjsg data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4698c349dbc7Sjsg INSTANCE_BROADCAST_WRITES, 1);
4699c349dbc7Sjsg else
4700c349dbc7Sjsg data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4701c349dbc7Sjsg instance);
4702c349dbc7Sjsg
4703c349dbc7Sjsg if (se_num == 0xffffffff)
4704c349dbc7Sjsg data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4705c349dbc7Sjsg 1);
4706c349dbc7Sjsg else
4707c349dbc7Sjsg data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4708c349dbc7Sjsg
4709c349dbc7Sjsg if (sh_num == 0xffffffff)
4710c349dbc7Sjsg data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4711c349dbc7Sjsg 1);
4712c349dbc7Sjsg else
4713c349dbc7Sjsg data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4714c349dbc7Sjsg
4715c349dbc7Sjsg WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4716c349dbc7Sjsg }
4717c349dbc7Sjsg
gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device * adev)4718c349dbc7Sjsg static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4719c349dbc7Sjsg {
4720c349dbc7Sjsg u32 data, mask;
4721c349dbc7Sjsg
4722c349dbc7Sjsg data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4723c349dbc7Sjsg data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4724c349dbc7Sjsg
4725c349dbc7Sjsg data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4726c349dbc7Sjsg data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4727c349dbc7Sjsg
4728c349dbc7Sjsg mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4729c349dbc7Sjsg adev->gfx.config.max_sh_per_se);
4730c349dbc7Sjsg
4731c349dbc7Sjsg return (~data) & mask;
4732c349dbc7Sjsg }
4733c349dbc7Sjsg
gfx_v10_0_setup_rb(struct amdgpu_device * adev)4734c349dbc7Sjsg static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4735c349dbc7Sjsg {
4736c349dbc7Sjsg int i, j;
4737c349dbc7Sjsg u32 data;
4738c349dbc7Sjsg u32 active_rbs = 0;
4739ad8b1aafSjsg u32 bitmap;
4740c349dbc7Sjsg u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4741c349dbc7Sjsg adev->gfx.config.max_sh_per_se;
4742c349dbc7Sjsg
4743c349dbc7Sjsg mutex_lock(&adev->grbm_idx_mutex);
4744c349dbc7Sjsg for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4745c349dbc7Sjsg for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4746ad8b1aafSjsg bitmap = i * adev->gfx.config.max_sh_per_se + j;
47471bb76ff1Sjsg if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
47481bb76ff1Sjsg (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
47491bb76ff1Sjsg (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6))) &&
4750ad8b1aafSjsg ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4751ad8b1aafSjsg continue;
4752f005ef32Sjsg gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
4753c349dbc7Sjsg data = gfx_v10_0_get_rb_active_bitmap(adev);
4754c349dbc7Sjsg active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4755c349dbc7Sjsg rb_bitmap_width_per_sh);
4756c349dbc7Sjsg }
4757c349dbc7Sjsg }
4758f005ef32Sjsg gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
4759c349dbc7Sjsg mutex_unlock(&adev->grbm_idx_mutex);
4760c349dbc7Sjsg
4761c349dbc7Sjsg adev->gfx.config.backend_enable_mask = active_rbs;
4762c349dbc7Sjsg adev->gfx.config.num_rbs = hweight32(active_rbs);
4763c349dbc7Sjsg }
4764c349dbc7Sjsg
gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device * adev)4765c349dbc7Sjsg static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4766c349dbc7Sjsg {
4767c349dbc7Sjsg uint32_t num_sc;
4768c349dbc7Sjsg uint32_t enabled_rb_per_sh;
4769c349dbc7Sjsg uint32_t active_rb_bitmap;
4770c349dbc7Sjsg uint32_t num_rb_per_sc;
4771c349dbc7Sjsg uint32_t num_packer_per_sc;
4772c349dbc7Sjsg uint32_t pa_sc_tile_steering_override;
4773c349dbc7Sjsg
4774ad8b1aafSjsg /* for ASICs that integrates GFX v10.3
4775f005ef32Sjsg * pa_sc_tile_steering_override should be set to 0
4776f005ef32Sjsg */
47771bb76ff1Sjsg if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
4778ad8b1aafSjsg return 0;
4779ad8b1aafSjsg
4780c349dbc7Sjsg /* init num_sc */
4781c349dbc7Sjsg num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4782c349dbc7Sjsg adev->gfx.config.num_sc_per_sh;
4783c349dbc7Sjsg /* init num_rb_per_sc */
4784c349dbc7Sjsg active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4785c349dbc7Sjsg enabled_rb_per_sh = hweight32(active_rb_bitmap);
4786c349dbc7Sjsg num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4787c349dbc7Sjsg /* init num_packer_per_sc */
4788c349dbc7Sjsg num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4789c349dbc7Sjsg
4790c349dbc7Sjsg pa_sc_tile_steering_override = 0;
4791c349dbc7Sjsg pa_sc_tile_steering_override |=
4792c349dbc7Sjsg (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4793c349dbc7Sjsg PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4794c349dbc7Sjsg pa_sc_tile_steering_override |=
4795c349dbc7Sjsg (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4796c349dbc7Sjsg PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4797c349dbc7Sjsg pa_sc_tile_steering_override |=
4798c349dbc7Sjsg (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4799c349dbc7Sjsg PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4800c349dbc7Sjsg
4801c349dbc7Sjsg return pa_sc_tile_steering_override;
4802c349dbc7Sjsg }
4803c349dbc7Sjsg
4804c349dbc7Sjsg #define DEFAULT_SH_MEM_BASES (0x6000)
4805c349dbc7Sjsg
gfx_v10_0_debug_trap_config_init(struct amdgpu_device * adev,uint32_t first_vmid,uint32_t last_vmid)4806f005ef32Sjsg static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev,
4807f005ef32Sjsg uint32_t first_vmid,
4808f005ef32Sjsg uint32_t last_vmid)
4809f005ef32Sjsg {
4810f005ef32Sjsg uint32_t data;
4811f005ef32Sjsg uint32_t trap_config_vmid_mask = 0;
4812f005ef32Sjsg int i;
4813f005ef32Sjsg
4814f005ef32Sjsg /* Calculate trap config vmid mask */
4815f005ef32Sjsg for (i = first_vmid; i < last_vmid; i++)
4816f005ef32Sjsg trap_config_vmid_mask |= (1 << i);
4817f005ef32Sjsg
4818f005ef32Sjsg data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG,
4819f005ef32Sjsg VMID_SEL, trap_config_vmid_mask);
4820f005ef32Sjsg data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
4821f005ef32Sjsg TRAP_EN, 1);
4822f005ef32Sjsg WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
4823f005ef32Sjsg WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
4824f005ef32Sjsg
4825f005ef32Sjsg WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
4826f005ef32Sjsg WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
4827f005ef32Sjsg }
4828f005ef32Sjsg
gfx_v10_0_init_compute_vmid(struct amdgpu_device * adev)4829c349dbc7Sjsg static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4830c349dbc7Sjsg {
4831c349dbc7Sjsg int i;
4832c349dbc7Sjsg uint32_t sh_mem_bases;
4833c349dbc7Sjsg
4834c349dbc7Sjsg /*
4835c349dbc7Sjsg * Configure apertures:
4836c349dbc7Sjsg * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
4837c349dbc7Sjsg * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
4838c349dbc7Sjsg * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
4839c349dbc7Sjsg */
4840c349dbc7Sjsg sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4841c349dbc7Sjsg
4842c349dbc7Sjsg mutex_lock(&adev->srbm_mutex);
4843ad8b1aafSjsg for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4844c349dbc7Sjsg nv_grbm_select(adev, 0, 0, 0, i);
4845c349dbc7Sjsg /* CP and shaders */
4846c349dbc7Sjsg WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4847c349dbc7Sjsg WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4848c349dbc7Sjsg }
4849c349dbc7Sjsg nv_grbm_select(adev, 0, 0, 0, 0);
4850c349dbc7Sjsg mutex_unlock(&adev->srbm_mutex);
4851c349dbc7Sjsg
4852f005ef32Sjsg /*
4853f005ef32Sjsg * Initialize all compute VMIDs to have no GDS, GWS, or OA
4854f005ef32Sjsg * access. These should be enabled by FW for target VMIDs.
4855f005ef32Sjsg */
4856ad8b1aafSjsg for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4857c349dbc7Sjsg WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4858c349dbc7Sjsg WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4859c349dbc7Sjsg WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4860c349dbc7Sjsg WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4861c349dbc7Sjsg }
4862f005ef32Sjsg
4863f005ef32Sjsg gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid,
4864f005ef32Sjsg AMDGPU_NUM_VMID);
4865c349dbc7Sjsg }
4866c349dbc7Sjsg
gfx_v10_0_init_gds_vmid(struct amdgpu_device * adev)4867c349dbc7Sjsg static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4868c349dbc7Sjsg {
4869c349dbc7Sjsg int vmid;
4870c349dbc7Sjsg
4871c349dbc7Sjsg /*
4872c349dbc7Sjsg * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4873c349dbc7Sjsg * access. Compute VMIDs should be enabled by FW for target VMIDs,
4874c349dbc7Sjsg * the driver can enable them for graphics. VMID0 should maintain
4875c349dbc7Sjsg * access so that HWS firmware can save/restore entries.
4876c349dbc7Sjsg */
48775ca02815Sjsg for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
4878c349dbc7Sjsg WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4879c349dbc7Sjsg WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4880c349dbc7Sjsg WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4881c349dbc7Sjsg WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4882c349dbc7Sjsg }
4883c349dbc7Sjsg }
4884c349dbc7Sjsg
4885c349dbc7Sjsg
gfx_v10_0_tcp_harvest(struct amdgpu_device * adev)4886c349dbc7Sjsg static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4887c349dbc7Sjsg {
4888c349dbc7Sjsg int i, j, k;
4889c349dbc7Sjsg int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4890c349dbc7Sjsg u32 tmp, wgp_active_bitmap = 0;
4891c349dbc7Sjsg u32 gcrd_targets_disable_tcp = 0;
4892c349dbc7Sjsg u32 utcl_invreq_disable = 0;
4893c349dbc7Sjsg /*
4894c349dbc7Sjsg * GCRD_TARGETS_DISABLE field contains
4895c349dbc7Sjsg * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4896c349dbc7Sjsg * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4897c349dbc7Sjsg */
4898c349dbc7Sjsg u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4899c349dbc7Sjsg 2 * max_wgp_per_sh + /* TCP */
4900c349dbc7Sjsg max_wgp_per_sh + /* SQC */
4901c349dbc7Sjsg 4); /* GL1C */
4902c349dbc7Sjsg /*
4903c349dbc7Sjsg * UTCL1_UTCL0_INVREQ_DISABLE field contains
4904c349dbc7Sjsg * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4905c349dbc7Sjsg * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4906c349dbc7Sjsg */
4907c349dbc7Sjsg u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4908c349dbc7Sjsg 2 * max_wgp_per_sh + /* TCP */
4909c349dbc7Sjsg 2 * max_wgp_per_sh + /* SQC */
4910c349dbc7Sjsg 4 + /* RMI */
4911c349dbc7Sjsg 1); /* SQG */
4912c349dbc7Sjsg
4913c349dbc7Sjsg mutex_lock(&adev->grbm_idx_mutex);
4914c349dbc7Sjsg for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4915c349dbc7Sjsg for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4916f005ef32Sjsg gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
4917c349dbc7Sjsg wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4918c349dbc7Sjsg /*
4919c349dbc7Sjsg * Set corresponding TCP bits for the inactive WGPs in
4920c349dbc7Sjsg * GCRD_SA_TARGETS_DISABLE
4921c349dbc7Sjsg */
4922c349dbc7Sjsg gcrd_targets_disable_tcp = 0;
4923c349dbc7Sjsg /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4924c349dbc7Sjsg utcl_invreq_disable = 0;
4925c349dbc7Sjsg
4926c349dbc7Sjsg for (k = 0; k < max_wgp_per_sh; k++) {
4927c349dbc7Sjsg if (!(wgp_active_bitmap & (1 << k))) {
4928c349dbc7Sjsg gcrd_targets_disable_tcp |= 3 << (2 * k);
49295ca02815Sjsg gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
4930c349dbc7Sjsg utcl_invreq_disable |= (3 << (2 * k)) |
4931c349dbc7Sjsg (3 << (2 * (max_wgp_per_sh + k)));
4932c349dbc7Sjsg }
4933c349dbc7Sjsg }
4934c349dbc7Sjsg
4935c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
4936c349dbc7Sjsg /* only override TCP & SQC bits */
49375ca02815Sjsg tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
4938c349dbc7Sjsg tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4939c349dbc7Sjsg WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
4940c349dbc7Sjsg
4941c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
49425ca02815Sjsg /* only override TCP & SQC bits */
49435ca02815Sjsg tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
4944c349dbc7Sjsg tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4945c349dbc7Sjsg WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
4946c349dbc7Sjsg }
4947c349dbc7Sjsg }
4948c349dbc7Sjsg
4949f005ef32Sjsg gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
4950c349dbc7Sjsg mutex_unlock(&adev->grbm_idx_mutex);
4951c349dbc7Sjsg }
4952c349dbc7Sjsg
gfx_v10_0_get_tcc_info(struct amdgpu_device * adev)4953c349dbc7Sjsg static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4954c349dbc7Sjsg {
4955c349dbc7Sjsg /* TCCs are global (not instanced). */
49565ca02815Sjsg uint32_t tcc_disable;
49575ca02815Sjsg
49581bb76ff1Sjsg if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
49595ca02815Sjsg tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
49605ca02815Sjsg RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
49615ca02815Sjsg } else {
49625ca02815Sjsg tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
4963c349dbc7Sjsg RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
49645ca02815Sjsg }
4965c349dbc7Sjsg
4966c349dbc7Sjsg adev->gfx.config.tcc_disabled_mask =
4967c349dbc7Sjsg REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
4968c349dbc7Sjsg (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
4969c349dbc7Sjsg }
4970c349dbc7Sjsg
gfx_v10_0_constants_init(struct amdgpu_device * adev)4971c349dbc7Sjsg static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4972c349dbc7Sjsg {
4973c349dbc7Sjsg u32 tmp;
4974c349dbc7Sjsg int i;
4975c349dbc7Sjsg
4976c349dbc7Sjsg WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
4977c349dbc7Sjsg
4978c349dbc7Sjsg gfx_v10_0_setup_rb(adev);
4979c349dbc7Sjsg gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4980c349dbc7Sjsg gfx_v10_0_get_tcc_info(adev);
4981c349dbc7Sjsg adev->gfx.config.pa_sc_tile_steering_override =
4982c349dbc7Sjsg gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4983c349dbc7Sjsg
4984c349dbc7Sjsg /* XXX SH_MEM regs */
4985c349dbc7Sjsg /* where to put LDS, scratch, GPUVM in FSA64 space */
4986c349dbc7Sjsg mutex_lock(&adev->srbm_mutex);
4987f005ef32Sjsg for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
4988c349dbc7Sjsg nv_grbm_select(adev, 0, 0, 0, i);
4989c349dbc7Sjsg /* CP and shaders */
4990c349dbc7Sjsg WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4991c349dbc7Sjsg if (i != 0) {
4992c349dbc7Sjsg tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
4993c349dbc7Sjsg (adev->gmc.private_aperture_start >> 48));
4994c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
4995c349dbc7Sjsg (adev->gmc.shared_aperture_start >> 48));
4996c349dbc7Sjsg WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
4997c349dbc7Sjsg }
4998c349dbc7Sjsg }
4999c349dbc7Sjsg nv_grbm_select(adev, 0, 0, 0, 0);
5000c349dbc7Sjsg
5001c349dbc7Sjsg mutex_unlock(&adev->srbm_mutex);
5002c349dbc7Sjsg
5003c349dbc7Sjsg gfx_v10_0_init_compute_vmid(adev);
5004c349dbc7Sjsg gfx_v10_0_init_gds_vmid(adev);
5005c349dbc7Sjsg
5006c349dbc7Sjsg }
5007c349dbc7Sjsg
gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device * adev,bool enable)5008c349dbc7Sjsg static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5009c349dbc7Sjsg bool enable)
5010c349dbc7Sjsg {
5011ad8b1aafSjsg u32 tmp;
5012ad8b1aafSjsg
5013ad8b1aafSjsg if (amdgpu_sriov_vf(adev))
5014ad8b1aafSjsg return;
5015ad8b1aafSjsg
5016ad8b1aafSjsg tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5017c349dbc7Sjsg
5018c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5019c349dbc7Sjsg enable ? 1 : 0);
5020c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5021c349dbc7Sjsg enable ? 1 : 0);
5022c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5023c349dbc7Sjsg enable ? 1 : 0);
5024c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5025c349dbc7Sjsg enable ? 1 : 0);
5026c349dbc7Sjsg
5027c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5028c349dbc7Sjsg }
5029c349dbc7Sjsg
gfx_v10_0_init_csb(struct amdgpu_device * adev)5030c349dbc7Sjsg static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5031c349dbc7Sjsg {
5032c349dbc7Sjsg adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5033c349dbc7Sjsg
5034c349dbc7Sjsg /* csib */
50351bb76ff1Sjsg if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
5036c349dbc7Sjsg WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5037c349dbc7Sjsg adev->gfx.rlc.clear_state_gpu_addr >> 32);
5038c349dbc7Sjsg WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5039c349dbc7Sjsg adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5040c349dbc7Sjsg WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5041ad8b1aafSjsg } else {
5042ad8b1aafSjsg WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5043ad8b1aafSjsg adev->gfx.rlc.clear_state_gpu_addr >> 32);
5044ad8b1aafSjsg WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5045ad8b1aafSjsg adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5046ad8b1aafSjsg WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5047ad8b1aafSjsg }
5048c349dbc7Sjsg return 0;
5049c349dbc7Sjsg }
5050c349dbc7Sjsg
gfx_v10_0_rlc_stop(struct amdgpu_device * adev)50515ca02815Sjsg static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5052c349dbc7Sjsg {
5053c349dbc7Sjsg u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5054c349dbc7Sjsg
5055c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5056c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5057c349dbc7Sjsg }
5058c349dbc7Sjsg
gfx_v10_0_rlc_reset(struct amdgpu_device * adev)5059c349dbc7Sjsg static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5060c349dbc7Sjsg {
5061c349dbc7Sjsg WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5062c349dbc7Sjsg udelay(50);
5063c349dbc7Sjsg WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5064c349dbc7Sjsg udelay(50);
5065c349dbc7Sjsg }
5066c349dbc7Sjsg
gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device * adev,bool enable)5067c349dbc7Sjsg static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5068c349dbc7Sjsg bool enable)
5069c349dbc7Sjsg {
5070c349dbc7Sjsg uint32_t rlc_pg_cntl;
5071c349dbc7Sjsg
5072c349dbc7Sjsg rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5073c349dbc7Sjsg
5074c349dbc7Sjsg if (!enable) {
5075c349dbc7Sjsg /* RLC_PG_CNTL[23] = 0 (default)
5076c349dbc7Sjsg * RLC will wait for handshake acks with SMU
5077c349dbc7Sjsg * GFXOFF will be enabled
5078c349dbc7Sjsg * RLC_PG_CNTL[23] = 1
5079c349dbc7Sjsg * RLC will not issue any message to SMU
5080c349dbc7Sjsg * hence no handshake between SMU & RLC
5081c349dbc7Sjsg * GFXOFF will be disabled
5082c349dbc7Sjsg */
5083c349dbc7Sjsg rlc_pg_cntl |= 0x800000;
5084c349dbc7Sjsg } else
5085c349dbc7Sjsg rlc_pg_cntl &= ~0x800000;
5086c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5087c349dbc7Sjsg }
5088c349dbc7Sjsg
gfx_v10_0_rlc_start(struct amdgpu_device * adev)5089c349dbc7Sjsg static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5090c349dbc7Sjsg {
5091f005ef32Sjsg /*
5092f005ef32Sjsg * TODO: enable rlc & smu handshake until smu
5093f005ef32Sjsg * and gfxoff feature works as expected
5094f005ef32Sjsg */
5095c349dbc7Sjsg if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5096c349dbc7Sjsg gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5097c349dbc7Sjsg
5098c349dbc7Sjsg WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5099c349dbc7Sjsg udelay(50);
5100c349dbc7Sjsg }
5101c349dbc7Sjsg
gfx_v10_0_rlc_enable_srm(struct amdgpu_device * adev)5102c349dbc7Sjsg static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5103c349dbc7Sjsg {
5104c349dbc7Sjsg uint32_t tmp;
5105c349dbc7Sjsg
5106c349dbc7Sjsg /* enable Save Restore Machine */
51075ca02815Sjsg tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5108c349dbc7Sjsg tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5109c349dbc7Sjsg tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
51105ca02815Sjsg WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5111c349dbc7Sjsg }
5112c349dbc7Sjsg
gfx_v10_0_rlc_load_microcode(struct amdgpu_device * adev)5113c349dbc7Sjsg static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5114c349dbc7Sjsg {
5115c349dbc7Sjsg const struct rlc_firmware_header_v2_0 *hdr;
5116c349dbc7Sjsg const __le32 *fw_data;
5117f005ef32Sjsg unsigned int i, fw_size;
5118c349dbc7Sjsg
5119c349dbc7Sjsg if (!adev->gfx.rlc_fw)
5120c349dbc7Sjsg return -EINVAL;
5121c349dbc7Sjsg
5122c349dbc7Sjsg hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5123c349dbc7Sjsg amdgpu_ucode_print_rlc_hdr(&hdr->header);
5124c349dbc7Sjsg
5125c349dbc7Sjsg fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5126c349dbc7Sjsg le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5127c349dbc7Sjsg fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5128c349dbc7Sjsg
5129c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5130c349dbc7Sjsg RLCG_UCODE_LOADING_START_ADDRESS);
5131c349dbc7Sjsg
5132c349dbc7Sjsg for (i = 0; i < fw_size; i++)
5133c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5134c349dbc7Sjsg le32_to_cpup(fw_data++));
5135c349dbc7Sjsg
5136c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5137c349dbc7Sjsg
5138c349dbc7Sjsg return 0;
5139c349dbc7Sjsg }
5140c349dbc7Sjsg
gfx_v10_0_rlc_resume(struct amdgpu_device * adev)5141c349dbc7Sjsg static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5142c349dbc7Sjsg {
5143c349dbc7Sjsg int r;
5144c349dbc7Sjsg
51455ca02815Sjsg if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
51465ca02815Sjsg adev->psp.autoload_supported) {
5147c349dbc7Sjsg
5148c349dbc7Sjsg r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5149c349dbc7Sjsg if (r)
5150c349dbc7Sjsg return r;
5151c349dbc7Sjsg
5152c349dbc7Sjsg gfx_v10_0_init_csb(adev);
5153c349dbc7Sjsg
5154f005ef32Sjsg gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5155f005ef32Sjsg
5156c349dbc7Sjsg if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5157c349dbc7Sjsg gfx_v10_0_rlc_enable_srm(adev);
5158c349dbc7Sjsg } else {
5159c349dbc7Sjsg if (amdgpu_sriov_vf(adev)) {
5160c349dbc7Sjsg gfx_v10_0_init_csb(adev);
5161c349dbc7Sjsg return 0;
5162c349dbc7Sjsg }
5163c349dbc7Sjsg
5164c349dbc7Sjsg adev->gfx.rlc.funcs->stop(adev);
5165c349dbc7Sjsg
5166c349dbc7Sjsg /* disable CG */
5167c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5168c349dbc7Sjsg
5169c349dbc7Sjsg /* disable PG */
5170c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5171c349dbc7Sjsg
5172c349dbc7Sjsg if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5173c349dbc7Sjsg /* legacy rlc firmware loading */
5174c349dbc7Sjsg r = gfx_v10_0_rlc_load_microcode(adev);
5175c349dbc7Sjsg if (r)
5176c349dbc7Sjsg return r;
5177c349dbc7Sjsg } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5178c349dbc7Sjsg /* rlc backdoor autoload firmware */
5179c349dbc7Sjsg r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5180c349dbc7Sjsg if (r)
5181c349dbc7Sjsg return r;
5182c349dbc7Sjsg }
5183c349dbc7Sjsg
5184c349dbc7Sjsg gfx_v10_0_init_csb(adev);
5185c349dbc7Sjsg
5186f005ef32Sjsg gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5187f005ef32Sjsg
5188c349dbc7Sjsg adev->gfx.rlc.funcs->start(adev);
5189c349dbc7Sjsg
5190c349dbc7Sjsg if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5191c349dbc7Sjsg r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5192c349dbc7Sjsg if (r)
5193c349dbc7Sjsg return r;
5194c349dbc7Sjsg }
5195c349dbc7Sjsg }
5196f005ef32Sjsg
5197c349dbc7Sjsg return 0;
5198c349dbc7Sjsg }
5199c349dbc7Sjsg
5200c349dbc7Sjsg static struct {
5201c349dbc7Sjsg FIRMWARE_ID id;
5202c349dbc7Sjsg unsigned int offset;
5203c349dbc7Sjsg unsigned int size;
5204c349dbc7Sjsg } rlc_autoload_info[FIRMWARE_ID_MAX];
5205c349dbc7Sjsg
gfx_v10_0_parse_rlc_toc(struct amdgpu_device * adev)5206c349dbc7Sjsg static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5207c349dbc7Sjsg {
5208c349dbc7Sjsg int ret;
5209c349dbc7Sjsg RLC_TABLE_OF_CONTENT *rlc_toc;
5210c349dbc7Sjsg
52115ca02815Sjsg ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE,
5212c349dbc7Sjsg AMDGPU_GEM_DOMAIN_GTT,
5213c349dbc7Sjsg &adev->gfx.rlc.rlc_toc_bo,
5214c349dbc7Sjsg &adev->gfx.rlc.rlc_toc_gpu_addr,
5215c349dbc7Sjsg (void **)&adev->gfx.rlc.rlc_toc_buf);
5216c349dbc7Sjsg if (ret) {
5217c349dbc7Sjsg dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5218c349dbc7Sjsg return ret;
5219c349dbc7Sjsg }
5220c349dbc7Sjsg
5221c349dbc7Sjsg /* Copy toc from psp sos fw to rlc toc buffer */
52225ca02815Sjsg memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
5223c349dbc7Sjsg
5224c349dbc7Sjsg rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5225c349dbc7Sjsg while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5226c349dbc7Sjsg (rlc_toc->id < FIRMWARE_ID_MAX)) {
5227c349dbc7Sjsg if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5228c349dbc7Sjsg (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5229c349dbc7Sjsg /* Offset needs 4KB alignment */
5230f005ef32Sjsg rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5231c349dbc7Sjsg }
5232c349dbc7Sjsg
5233c349dbc7Sjsg rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5234c349dbc7Sjsg rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5235c349dbc7Sjsg rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5236c349dbc7Sjsg
5237c349dbc7Sjsg rlc_toc++;
5238c349dbc7Sjsg }
5239c349dbc7Sjsg
5240c349dbc7Sjsg return 0;
5241c349dbc7Sjsg }
5242c349dbc7Sjsg
gfx_v10_0_calc_toc_total_size(struct amdgpu_device * adev)5243c349dbc7Sjsg static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5244c349dbc7Sjsg {
5245c349dbc7Sjsg uint32_t total_size = 0;
5246c349dbc7Sjsg FIRMWARE_ID id;
5247c349dbc7Sjsg int ret;
5248c349dbc7Sjsg
5249c349dbc7Sjsg ret = gfx_v10_0_parse_rlc_toc(adev);
5250c349dbc7Sjsg if (ret) {
5251c349dbc7Sjsg dev_err(adev->dev, "failed to parse rlc toc\n");
5252c349dbc7Sjsg return 0;
5253c349dbc7Sjsg }
5254c349dbc7Sjsg
5255c349dbc7Sjsg for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5256c349dbc7Sjsg total_size += rlc_autoload_info[id].size;
5257c349dbc7Sjsg
5258c349dbc7Sjsg /* In case the offset in rlc toc ucode is aligned */
5259c349dbc7Sjsg if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5260c349dbc7Sjsg total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5261c349dbc7Sjsg rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5262c349dbc7Sjsg
5263c349dbc7Sjsg return total_size;
5264c349dbc7Sjsg }
5265c349dbc7Sjsg
gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device * adev)5266c349dbc7Sjsg static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5267c349dbc7Sjsg {
5268c349dbc7Sjsg int r;
5269c349dbc7Sjsg uint32_t total_size;
5270c349dbc7Sjsg
5271c349dbc7Sjsg total_size = gfx_v10_0_calc_toc_total_size(adev);
5272c349dbc7Sjsg
5273c349dbc7Sjsg r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5274c349dbc7Sjsg AMDGPU_GEM_DOMAIN_GTT,
5275c349dbc7Sjsg &adev->gfx.rlc.rlc_autoload_bo,
5276c349dbc7Sjsg &adev->gfx.rlc.rlc_autoload_gpu_addr,
5277c349dbc7Sjsg (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5278c349dbc7Sjsg if (r) {
5279c349dbc7Sjsg dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5280c349dbc7Sjsg return r;
5281c349dbc7Sjsg }
5282c349dbc7Sjsg
5283c349dbc7Sjsg return 0;
5284c349dbc7Sjsg }
5285c349dbc7Sjsg
gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device * adev)5286c349dbc7Sjsg static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5287c349dbc7Sjsg {
5288c349dbc7Sjsg amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5289c349dbc7Sjsg &adev->gfx.rlc.rlc_toc_gpu_addr,
5290c349dbc7Sjsg (void **)&adev->gfx.rlc.rlc_toc_buf);
5291c349dbc7Sjsg amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5292c349dbc7Sjsg &adev->gfx.rlc.rlc_autoload_gpu_addr,
5293c349dbc7Sjsg (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5294c349dbc7Sjsg }
5295c349dbc7Sjsg
gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device * adev,FIRMWARE_ID id,const void * fw_data,uint32_t fw_size)5296c349dbc7Sjsg static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5297c349dbc7Sjsg FIRMWARE_ID id,
5298c349dbc7Sjsg const void *fw_data,
5299c349dbc7Sjsg uint32_t fw_size)
5300c349dbc7Sjsg {
5301c349dbc7Sjsg uint32_t toc_offset;
5302c349dbc7Sjsg uint32_t toc_fw_size;
5303c349dbc7Sjsg char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5304c349dbc7Sjsg
5305c349dbc7Sjsg if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5306c349dbc7Sjsg return;
5307c349dbc7Sjsg
5308c349dbc7Sjsg toc_offset = rlc_autoload_info[id].offset;
5309c349dbc7Sjsg toc_fw_size = rlc_autoload_info[id].size;
5310c349dbc7Sjsg
5311c349dbc7Sjsg if (fw_size == 0)
5312c349dbc7Sjsg fw_size = toc_fw_size;
5313c349dbc7Sjsg
5314c349dbc7Sjsg if (fw_size > toc_fw_size)
5315c349dbc7Sjsg fw_size = toc_fw_size;
5316c349dbc7Sjsg
5317c349dbc7Sjsg memcpy(ptr + toc_offset, fw_data, fw_size);
5318c349dbc7Sjsg
5319c349dbc7Sjsg if (fw_size < toc_fw_size)
5320c349dbc7Sjsg memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5321c349dbc7Sjsg }
5322c349dbc7Sjsg
gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device * adev)5323c349dbc7Sjsg static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5324c349dbc7Sjsg {
5325c349dbc7Sjsg void *data;
5326c349dbc7Sjsg uint32_t size;
5327c349dbc7Sjsg
5328c349dbc7Sjsg data = adev->gfx.rlc.rlc_toc_buf;
5329c349dbc7Sjsg size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5330c349dbc7Sjsg
5331c349dbc7Sjsg gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5332c349dbc7Sjsg FIRMWARE_ID_RLC_TOC,
5333c349dbc7Sjsg data, size);
5334c349dbc7Sjsg }
5335c349dbc7Sjsg
gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device * adev)5336c349dbc7Sjsg static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5337c349dbc7Sjsg {
5338c349dbc7Sjsg const __le32 *fw_data;
5339c349dbc7Sjsg uint32_t fw_size;
5340c349dbc7Sjsg const struct gfx_firmware_header_v1_0 *cp_hdr;
5341c349dbc7Sjsg const struct rlc_firmware_header_v2_0 *rlc_hdr;
5342c349dbc7Sjsg
5343c349dbc7Sjsg /* pfp ucode */
5344c349dbc7Sjsg cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5345c349dbc7Sjsg adev->gfx.pfp_fw->data;
5346c349dbc7Sjsg fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5347c349dbc7Sjsg le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5348c349dbc7Sjsg fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5349c349dbc7Sjsg gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5350c349dbc7Sjsg FIRMWARE_ID_CP_PFP,
5351c349dbc7Sjsg fw_data, fw_size);
5352c349dbc7Sjsg
5353c349dbc7Sjsg /* ce ucode */
5354c349dbc7Sjsg cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5355c349dbc7Sjsg adev->gfx.ce_fw->data;
5356c349dbc7Sjsg fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5357c349dbc7Sjsg le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5358c349dbc7Sjsg fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5359c349dbc7Sjsg gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5360c349dbc7Sjsg FIRMWARE_ID_CP_CE,
5361c349dbc7Sjsg fw_data, fw_size);
5362c349dbc7Sjsg
5363c349dbc7Sjsg /* me ucode */
5364c349dbc7Sjsg cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5365c349dbc7Sjsg adev->gfx.me_fw->data;
5366c349dbc7Sjsg fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5367c349dbc7Sjsg le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5368c349dbc7Sjsg fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5369c349dbc7Sjsg gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5370c349dbc7Sjsg FIRMWARE_ID_CP_ME,
5371c349dbc7Sjsg fw_data, fw_size);
5372c349dbc7Sjsg
5373c349dbc7Sjsg /* rlc ucode */
5374c349dbc7Sjsg rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5375c349dbc7Sjsg adev->gfx.rlc_fw->data;
5376c349dbc7Sjsg fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5377c349dbc7Sjsg le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5378c349dbc7Sjsg fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5379c349dbc7Sjsg gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5380c349dbc7Sjsg FIRMWARE_ID_RLC_G_UCODE,
5381c349dbc7Sjsg fw_data, fw_size);
5382c349dbc7Sjsg
5383c349dbc7Sjsg /* mec1 ucode */
5384c349dbc7Sjsg cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5385c349dbc7Sjsg adev->gfx.mec_fw->data;
5386c349dbc7Sjsg fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5387c349dbc7Sjsg le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5388c349dbc7Sjsg fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5389c349dbc7Sjsg cp_hdr->jt_size * 4;
5390c349dbc7Sjsg gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5391c349dbc7Sjsg FIRMWARE_ID_CP_MEC,
5392c349dbc7Sjsg fw_data, fw_size);
5393c349dbc7Sjsg /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5394c349dbc7Sjsg }
5395c349dbc7Sjsg
5396c349dbc7Sjsg /* Temporarily put sdma part here */
gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device * adev)5397c349dbc7Sjsg static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5398c349dbc7Sjsg {
5399c349dbc7Sjsg const __le32 *fw_data;
5400c349dbc7Sjsg uint32_t fw_size;
5401c349dbc7Sjsg const struct sdma_firmware_header_v1_0 *sdma_hdr;
5402c349dbc7Sjsg int i;
5403c349dbc7Sjsg
5404c349dbc7Sjsg for (i = 0; i < adev->sdma.num_instances; i++) {
5405c349dbc7Sjsg sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5406c349dbc7Sjsg adev->sdma.instance[i].fw->data;
5407c349dbc7Sjsg fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5408c349dbc7Sjsg le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5409c349dbc7Sjsg fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5410c349dbc7Sjsg
5411c349dbc7Sjsg if (i == 0) {
5412c349dbc7Sjsg gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5413c349dbc7Sjsg FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5414c349dbc7Sjsg gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5415c349dbc7Sjsg FIRMWARE_ID_SDMA0_JT,
5416c349dbc7Sjsg (uint32_t *)fw_data +
5417c349dbc7Sjsg sdma_hdr->jt_offset,
5418c349dbc7Sjsg sdma_hdr->jt_size * 4);
5419c349dbc7Sjsg } else if (i == 1) {
5420c349dbc7Sjsg gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5421c349dbc7Sjsg FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5422c349dbc7Sjsg gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5423c349dbc7Sjsg FIRMWARE_ID_SDMA1_JT,
5424c349dbc7Sjsg (uint32_t *)fw_data +
5425c349dbc7Sjsg sdma_hdr->jt_offset,
5426c349dbc7Sjsg sdma_hdr->jt_size * 4);
5427c349dbc7Sjsg }
5428c349dbc7Sjsg }
5429c349dbc7Sjsg }
5430c349dbc7Sjsg
gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device * adev)5431c349dbc7Sjsg static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5432c349dbc7Sjsg {
5433c349dbc7Sjsg uint32_t rlc_g_offset, rlc_g_size, tmp;
5434c349dbc7Sjsg uint64_t gpu_addr;
5435c349dbc7Sjsg
5436c349dbc7Sjsg gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5437c349dbc7Sjsg gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5438c349dbc7Sjsg gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5439c349dbc7Sjsg
5440c349dbc7Sjsg rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5441c349dbc7Sjsg rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5442c349dbc7Sjsg gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5443c349dbc7Sjsg
5444c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5445c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5446c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5447c349dbc7Sjsg
5448c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5449c349dbc7Sjsg if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5450c349dbc7Sjsg RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5451c349dbc7Sjsg DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5452c349dbc7Sjsg return -EINVAL;
5453c349dbc7Sjsg }
5454c349dbc7Sjsg
5455c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5456c349dbc7Sjsg if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5457c349dbc7Sjsg DRM_ERROR("RLC ROM should halt itself\n");
5458c349dbc7Sjsg return -EINVAL;
5459c349dbc7Sjsg }
5460c349dbc7Sjsg
5461c349dbc7Sjsg return 0;
5462c349dbc7Sjsg }
5463c349dbc7Sjsg
gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device * adev)5464c349dbc7Sjsg static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5465c349dbc7Sjsg {
5466c349dbc7Sjsg uint32_t usec_timeout = 50000; /* wait for 50ms */
5467c349dbc7Sjsg uint32_t tmp;
5468c349dbc7Sjsg int i;
5469c349dbc7Sjsg uint64_t addr;
5470c349dbc7Sjsg
5471c349dbc7Sjsg /* Trigger an invalidation of the L1 instruction caches */
5472c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5473c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5474c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5475c349dbc7Sjsg
5476c349dbc7Sjsg /* Wait for invalidation complete */
5477c349dbc7Sjsg for (i = 0; i < usec_timeout; i++) {
5478c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5479c349dbc7Sjsg if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5480c349dbc7Sjsg INVALIDATE_CACHE_COMPLETE))
5481c349dbc7Sjsg break;
5482c349dbc7Sjsg udelay(1);
5483c349dbc7Sjsg }
5484c349dbc7Sjsg
5485c349dbc7Sjsg if (i >= usec_timeout) {
5486c349dbc7Sjsg dev_err(adev->dev, "failed to invalidate instruction cache\n");
5487c349dbc7Sjsg return -EINVAL;
5488c349dbc7Sjsg }
5489c349dbc7Sjsg
5490c349dbc7Sjsg /* Program me ucode address into intruction cache address register */
5491c349dbc7Sjsg addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5492c349dbc7Sjsg rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5493c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5494c349dbc7Sjsg lower_32_bits(addr) & 0xFFFFF000);
5495c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5496c349dbc7Sjsg upper_32_bits(addr));
5497c349dbc7Sjsg
5498c349dbc7Sjsg return 0;
5499c349dbc7Sjsg }
5500c349dbc7Sjsg
gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device * adev)5501c349dbc7Sjsg static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5502c349dbc7Sjsg {
5503c349dbc7Sjsg uint32_t usec_timeout = 50000; /* wait for 50ms */
5504c349dbc7Sjsg uint32_t tmp;
5505c349dbc7Sjsg int i;
5506c349dbc7Sjsg uint64_t addr;
5507c349dbc7Sjsg
5508c349dbc7Sjsg /* Trigger an invalidation of the L1 instruction caches */
5509c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5510c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5511c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5512c349dbc7Sjsg
5513c349dbc7Sjsg /* Wait for invalidation complete */
5514c349dbc7Sjsg for (i = 0; i < usec_timeout; i++) {
5515c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5516c349dbc7Sjsg if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5517c349dbc7Sjsg INVALIDATE_CACHE_COMPLETE))
5518c349dbc7Sjsg break;
5519c349dbc7Sjsg udelay(1);
5520c349dbc7Sjsg }
5521c349dbc7Sjsg
5522c349dbc7Sjsg if (i >= usec_timeout) {
5523c349dbc7Sjsg dev_err(adev->dev, "failed to invalidate instruction cache\n");
5524c349dbc7Sjsg return -EINVAL;
5525c349dbc7Sjsg }
5526c349dbc7Sjsg
5527c349dbc7Sjsg /* Program ce ucode address into intruction cache address register */
5528c349dbc7Sjsg addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5529c349dbc7Sjsg rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5530c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5531c349dbc7Sjsg lower_32_bits(addr) & 0xFFFFF000);
5532c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5533c349dbc7Sjsg upper_32_bits(addr));
5534c349dbc7Sjsg
5535c349dbc7Sjsg return 0;
5536c349dbc7Sjsg }
5537c349dbc7Sjsg
gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device * adev)5538c349dbc7Sjsg static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5539c349dbc7Sjsg {
5540c349dbc7Sjsg uint32_t usec_timeout = 50000; /* wait for 50ms */
5541c349dbc7Sjsg uint32_t tmp;
5542c349dbc7Sjsg int i;
5543c349dbc7Sjsg uint64_t addr;
5544c349dbc7Sjsg
5545c349dbc7Sjsg /* Trigger an invalidation of the L1 instruction caches */
5546c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5547c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5548c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5549c349dbc7Sjsg
5550c349dbc7Sjsg /* Wait for invalidation complete */
5551c349dbc7Sjsg for (i = 0; i < usec_timeout; i++) {
5552c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5553c349dbc7Sjsg if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5554c349dbc7Sjsg INVALIDATE_CACHE_COMPLETE))
5555c349dbc7Sjsg break;
5556c349dbc7Sjsg udelay(1);
5557c349dbc7Sjsg }
5558c349dbc7Sjsg
5559c349dbc7Sjsg if (i >= usec_timeout) {
5560c349dbc7Sjsg dev_err(adev->dev, "failed to invalidate instruction cache\n");
5561c349dbc7Sjsg return -EINVAL;
5562c349dbc7Sjsg }
5563c349dbc7Sjsg
5564c349dbc7Sjsg /* Program pfp ucode address into intruction cache address register */
5565c349dbc7Sjsg addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5566c349dbc7Sjsg rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5567c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5568c349dbc7Sjsg lower_32_bits(addr) & 0xFFFFF000);
5569c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5570c349dbc7Sjsg upper_32_bits(addr));
5571c349dbc7Sjsg
5572c349dbc7Sjsg return 0;
5573c349dbc7Sjsg }
5574c349dbc7Sjsg
gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device * adev)5575c349dbc7Sjsg static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5576c349dbc7Sjsg {
5577c349dbc7Sjsg uint32_t usec_timeout = 50000; /* wait for 50ms */
5578c349dbc7Sjsg uint32_t tmp;
5579c349dbc7Sjsg int i;
5580c349dbc7Sjsg uint64_t addr;
5581c349dbc7Sjsg
5582c349dbc7Sjsg /* Trigger an invalidation of the L1 instruction caches */
5583c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5584c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5585c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5586c349dbc7Sjsg
5587c349dbc7Sjsg /* Wait for invalidation complete */
5588c349dbc7Sjsg for (i = 0; i < usec_timeout; i++) {
5589c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5590c349dbc7Sjsg if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5591c349dbc7Sjsg INVALIDATE_CACHE_COMPLETE))
5592c349dbc7Sjsg break;
5593c349dbc7Sjsg udelay(1);
5594c349dbc7Sjsg }
5595c349dbc7Sjsg
5596c349dbc7Sjsg if (i >= usec_timeout) {
5597c349dbc7Sjsg dev_err(adev->dev, "failed to invalidate instruction cache\n");
5598c349dbc7Sjsg return -EINVAL;
5599c349dbc7Sjsg }
5600c349dbc7Sjsg
5601c349dbc7Sjsg /* Program mec1 ucode address into intruction cache address register */
5602c349dbc7Sjsg addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5603c349dbc7Sjsg rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5604c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5605c349dbc7Sjsg lower_32_bits(addr) & 0xFFFFF000);
5606c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5607c349dbc7Sjsg upper_32_bits(addr));
5608c349dbc7Sjsg
5609c349dbc7Sjsg return 0;
5610c349dbc7Sjsg }
5611c349dbc7Sjsg
gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device * adev)5612c349dbc7Sjsg static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5613c349dbc7Sjsg {
5614c349dbc7Sjsg uint32_t cp_status;
5615c349dbc7Sjsg uint32_t bootload_status;
5616c349dbc7Sjsg int i, r;
5617c349dbc7Sjsg
5618c349dbc7Sjsg for (i = 0; i < adev->usec_timeout; i++) {
5619c349dbc7Sjsg cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5620c349dbc7Sjsg bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5621c349dbc7Sjsg if ((cp_status == 0) &&
5622c349dbc7Sjsg (REG_GET_FIELD(bootload_status,
5623c349dbc7Sjsg RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5624c349dbc7Sjsg break;
5625c349dbc7Sjsg }
5626c349dbc7Sjsg udelay(1);
5627c349dbc7Sjsg }
5628c349dbc7Sjsg
5629c349dbc7Sjsg if (i >= adev->usec_timeout) {
5630c349dbc7Sjsg dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5631c349dbc7Sjsg return -ETIMEDOUT;
5632c349dbc7Sjsg }
5633c349dbc7Sjsg
5634c349dbc7Sjsg if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5635c349dbc7Sjsg r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5636c349dbc7Sjsg if (r)
5637c349dbc7Sjsg return r;
5638c349dbc7Sjsg
5639c349dbc7Sjsg r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5640c349dbc7Sjsg if (r)
5641c349dbc7Sjsg return r;
5642c349dbc7Sjsg
5643c349dbc7Sjsg r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5644c349dbc7Sjsg if (r)
5645c349dbc7Sjsg return r;
5646c349dbc7Sjsg
5647c349dbc7Sjsg r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5648c349dbc7Sjsg if (r)
5649c349dbc7Sjsg return r;
5650c349dbc7Sjsg }
5651c349dbc7Sjsg
5652c349dbc7Sjsg return 0;
5653c349dbc7Sjsg }
5654c349dbc7Sjsg
gfx_v10_0_cp_gfx_enable(struct amdgpu_device * adev,bool enable)5655c349dbc7Sjsg static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5656c349dbc7Sjsg {
5657c349dbc7Sjsg int i;
5658c349dbc7Sjsg u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5659c349dbc7Sjsg
5660c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5661c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5662c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5663ad8b1aafSjsg
5664f005ef32Sjsg if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))
5665c349dbc7Sjsg WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5666f005ef32Sjsg else
5667ad8b1aafSjsg WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5668c349dbc7Sjsg
56691bb76ff1Sjsg if (adev->job_hang && !enable)
56701bb76ff1Sjsg return 0;
56711bb76ff1Sjsg
5672c349dbc7Sjsg for (i = 0; i < adev->usec_timeout; i++) {
5673c349dbc7Sjsg if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5674c349dbc7Sjsg break;
5675c349dbc7Sjsg udelay(1);
5676c349dbc7Sjsg }
5677c349dbc7Sjsg
5678c349dbc7Sjsg if (i >= adev->usec_timeout)
5679c349dbc7Sjsg DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5680c349dbc7Sjsg
5681c349dbc7Sjsg return 0;
5682c349dbc7Sjsg }
5683c349dbc7Sjsg
gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device * adev)5684c349dbc7Sjsg static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5685c349dbc7Sjsg {
5686c349dbc7Sjsg int r;
5687c349dbc7Sjsg const struct gfx_firmware_header_v1_0 *pfp_hdr;
5688c349dbc7Sjsg const __le32 *fw_data;
5689f005ef32Sjsg unsigned int i, fw_size;
5690c349dbc7Sjsg uint32_t tmp;
5691c349dbc7Sjsg uint32_t usec_timeout = 50000; /* wait for 50ms */
5692c349dbc7Sjsg
5693c349dbc7Sjsg pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5694c349dbc7Sjsg adev->gfx.pfp_fw->data;
5695c349dbc7Sjsg
5696c349dbc7Sjsg amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5697c349dbc7Sjsg
5698c349dbc7Sjsg fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5699c349dbc7Sjsg le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5700c349dbc7Sjsg fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5701c349dbc7Sjsg
5702c349dbc7Sjsg r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5703c349dbc7Sjsg PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5704c349dbc7Sjsg &adev->gfx.pfp.pfp_fw_obj,
5705c349dbc7Sjsg &adev->gfx.pfp.pfp_fw_gpu_addr,
5706c349dbc7Sjsg (void **)&adev->gfx.pfp.pfp_fw_ptr);
5707c349dbc7Sjsg if (r) {
5708c349dbc7Sjsg dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5709c349dbc7Sjsg gfx_v10_0_pfp_fini(adev);
5710c349dbc7Sjsg return r;
5711c349dbc7Sjsg }
5712c349dbc7Sjsg
5713c349dbc7Sjsg memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5714c349dbc7Sjsg
5715c349dbc7Sjsg amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5716c349dbc7Sjsg amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5717c349dbc7Sjsg
5718c349dbc7Sjsg /* Trigger an invalidation of the L1 instruction caches */
5719c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5720c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5721c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5722c349dbc7Sjsg
5723c349dbc7Sjsg /* Wait for invalidation complete */
5724c349dbc7Sjsg for (i = 0; i < usec_timeout; i++) {
5725c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5726c349dbc7Sjsg if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5727c349dbc7Sjsg INVALIDATE_CACHE_COMPLETE))
5728c349dbc7Sjsg break;
5729c349dbc7Sjsg udelay(1);
5730c349dbc7Sjsg }
5731c349dbc7Sjsg
5732c349dbc7Sjsg if (i >= usec_timeout) {
5733c349dbc7Sjsg dev_err(adev->dev, "failed to invalidate instruction cache\n");
5734c349dbc7Sjsg return -EINVAL;
5735c349dbc7Sjsg }
5736c349dbc7Sjsg
5737c349dbc7Sjsg if (amdgpu_emu_mode == 1)
57385ca02815Sjsg adev->hdp.funcs->flush_hdp(adev, NULL);
5739c349dbc7Sjsg
5740c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5741c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5742c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5743c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5744c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5745c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5746c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5747c349dbc7Sjsg adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5748c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5749c349dbc7Sjsg upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5750c349dbc7Sjsg
5751ad8b1aafSjsg WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5752ad8b1aafSjsg
5753ad8b1aafSjsg for (i = 0; i < pfp_hdr->jt_size; i++)
5754ad8b1aafSjsg WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5755ad8b1aafSjsg le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5756ad8b1aafSjsg
5757ad8b1aafSjsg WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5758ad8b1aafSjsg
5759c349dbc7Sjsg return 0;
5760c349dbc7Sjsg }
5761c349dbc7Sjsg
gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device * adev)5762c349dbc7Sjsg static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5763c349dbc7Sjsg {
5764c349dbc7Sjsg int r;
5765c349dbc7Sjsg const struct gfx_firmware_header_v1_0 *ce_hdr;
5766c349dbc7Sjsg const __le32 *fw_data;
5767f005ef32Sjsg unsigned int i, fw_size;
5768c349dbc7Sjsg uint32_t tmp;
5769c349dbc7Sjsg uint32_t usec_timeout = 50000; /* wait for 50ms */
5770c349dbc7Sjsg
5771c349dbc7Sjsg ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5772c349dbc7Sjsg adev->gfx.ce_fw->data;
5773c349dbc7Sjsg
5774c349dbc7Sjsg amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5775c349dbc7Sjsg
5776c349dbc7Sjsg fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5777c349dbc7Sjsg le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5778c349dbc7Sjsg fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5779c349dbc7Sjsg
5780c349dbc7Sjsg r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5781c349dbc7Sjsg PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5782c349dbc7Sjsg &adev->gfx.ce.ce_fw_obj,
5783c349dbc7Sjsg &adev->gfx.ce.ce_fw_gpu_addr,
5784c349dbc7Sjsg (void **)&adev->gfx.ce.ce_fw_ptr);
5785c349dbc7Sjsg if (r) {
5786c349dbc7Sjsg dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5787c349dbc7Sjsg gfx_v10_0_ce_fini(adev);
5788c349dbc7Sjsg return r;
5789c349dbc7Sjsg }
5790c349dbc7Sjsg
5791c349dbc7Sjsg memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5792c349dbc7Sjsg
5793c349dbc7Sjsg amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5794c349dbc7Sjsg amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5795c349dbc7Sjsg
5796c349dbc7Sjsg /* Trigger an invalidation of the L1 instruction caches */
5797c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5798c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5799c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5800c349dbc7Sjsg
5801c349dbc7Sjsg /* Wait for invalidation complete */
5802c349dbc7Sjsg for (i = 0; i < usec_timeout; i++) {
5803c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5804c349dbc7Sjsg if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5805c349dbc7Sjsg INVALIDATE_CACHE_COMPLETE))
5806c349dbc7Sjsg break;
5807c349dbc7Sjsg udelay(1);
5808c349dbc7Sjsg }
5809c349dbc7Sjsg
5810c349dbc7Sjsg if (i >= usec_timeout) {
5811c349dbc7Sjsg dev_err(adev->dev, "failed to invalidate instruction cache\n");
5812c349dbc7Sjsg return -EINVAL;
5813c349dbc7Sjsg }
5814c349dbc7Sjsg
5815c349dbc7Sjsg if (amdgpu_emu_mode == 1)
58165ca02815Sjsg adev->hdp.funcs->flush_hdp(adev, NULL);
5817c349dbc7Sjsg
5818c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5819c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5820c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5821c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5822c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5823c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5824c349dbc7Sjsg adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5825c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5826c349dbc7Sjsg upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5827c349dbc7Sjsg
5828ad8b1aafSjsg WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5829ad8b1aafSjsg
5830ad8b1aafSjsg for (i = 0; i < ce_hdr->jt_size; i++)
5831ad8b1aafSjsg WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5832ad8b1aafSjsg le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5833ad8b1aafSjsg
5834ad8b1aafSjsg WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5835ad8b1aafSjsg
5836c349dbc7Sjsg return 0;
5837c349dbc7Sjsg }
5838c349dbc7Sjsg
gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device * adev)5839c349dbc7Sjsg static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5840c349dbc7Sjsg {
5841c349dbc7Sjsg int r;
5842c349dbc7Sjsg const struct gfx_firmware_header_v1_0 *me_hdr;
5843c349dbc7Sjsg const __le32 *fw_data;
5844f005ef32Sjsg unsigned int i, fw_size;
5845c349dbc7Sjsg uint32_t tmp;
5846c349dbc7Sjsg uint32_t usec_timeout = 50000; /* wait for 50ms */
5847c349dbc7Sjsg
5848c349dbc7Sjsg me_hdr = (const struct gfx_firmware_header_v1_0 *)
5849c349dbc7Sjsg adev->gfx.me_fw->data;
5850c349dbc7Sjsg
5851c349dbc7Sjsg amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5852c349dbc7Sjsg
5853c349dbc7Sjsg fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5854c349dbc7Sjsg le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5855c349dbc7Sjsg fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5856c349dbc7Sjsg
5857c349dbc7Sjsg r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5858c349dbc7Sjsg PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5859c349dbc7Sjsg &adev->gfx.me.me_fw_obj,
5860c349dbc7Sjsg &adev->gfx.me.me_fw_gpu_addr,
5861c349dbc7Sjsg (void **)&adev->gfx.me.me_fw_ptr);
5862c349dbc7Sjsg if (r) {
5863c349dbc7Sjsg dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5864c349dbc7Sjsg gfx_v10_0_me_fini(adev);
5865c349dbc7Sjsg return r;
5866c349dbc7Sjsg }
5867c349dbc7Sjsg
5868c349dbc7Sjsg memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5869c349dbc7Sjsg
5870c349dbc7Sjsg amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5871c349dbc7Sjsg amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5872c349dbc7Sjsg
5873c349dbc7Sjsg /* Trigger an invalidation of the L1 instruction caches */
5874c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5875c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5876c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5877c349dbc7Sjsg
5878c349dbc7Sjsg /* Wait for invalidation complete */
5879c349dbc7Sjsg for (i = 0; i < usec_timeout; i++) {
5880c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5881c349dbc7Sjsg if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5882c349dbc7Sjsg INVALIDATE_CACHE_COMPLETE))
5883c349dbc7Sjsg break;
5884c349dbc7Sjsg udelay(1);
5885c349dbc7Sjsg }
5886c349dbc7Sjsg
5887c349dbc7Sjsg if (i >= usec_timeout) {
5888c349dbc7Sjsg dev_err(adev->dev, "failed to invalidate instruction cache\n");
5889c349dbc7Sjsg return -EINVAL;
5890c349dbc7Sjsg }
5891c349dbc7Sjsg
5892c349dbc7Sjsg if (amdgpu_emu_mode == 1)
58935ca02815Sjsg adev->hdp.funcs->flush_hdp(adev, NULL);
5894c349dbc7Sjsg
5895c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5896c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5897c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5898c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5899c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5900c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5901c349dbc7Sjsg adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5902c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5903c349dbc7Sjsg upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5904c349dbc7Sjsg
5905ad8b1aafSjsg WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5906ad8b1aafSjsg
5907ad8b1aafSjsg for (i = 0; i < me_hdr->jt_size; i++)
5908ad8b1aafSjsg WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5909ad8b1aafSjsg le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5910ad8b1aafSjsg
5911ad8b1aafSjsg WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5912ad8b1aafSjsg
5913c349dbc7Sjsg return 0;
5914c349dbc7Sjsg }
5915c349dbc7Sjsg
gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device * adev)5916c349dbc7Sjsg static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5917c349dbc7Sjsg {
5918c349dbc7Sjsg int r;
5919c349dbc7Sjsg
5920c349dbc7Sjsg if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5921c349dbc7Sjsg return -EINVAL;
5922c349dbc7Sjsg
5923c349dbc7Sjsg gfx_v10_0_cp_gfx_enable(adev, false);
5924c349dbc7Sjsg
5925c349dbc7Sjsg r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5926c349dbc7Sjsg if (r) {
5927c349dbc7Sjsg dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5928c349dbc7Sjsg return r;
5929c349dbc7Sjsg }
5930c349dbc7Sjsg
5931c349dbc7Sjsg r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5932c349dbc7Sjsg if (r) {
5933c349dbc7Sjsg dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
5934c349dbc7Sjsg return r;
5935c349dbc7Sjsg }
5936c349dbc7Sjsg
5937c349dbc7Sjsg r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5938c349dbc7Sjsg if (r) {
5939c349dbc7Sjsg dev_err(adev->dev, "(%d) failed to load me fw\n", r);
5940c349dbc7Sjsg return r;
5941c349dbc7Sjsg }
5942c349dbc7Sjsg
5943c349dbc7Sjsg return 0;
5944c349dbc7Sjsg }
5945c349dbc7Sjsg
gfx_v10_0_cp_gfx_start(struct amdgpu_device * adev)5946c349dbc7Sjsg static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5947c349dbc7Sjsg {
5948c349dbc7Sjsg struct amdgpu_ring *ring;
5949c349dbc7Sjsg const struct cs_section_def *sect = NULL;
5950c349dbc7Sjsg const struct cs_extent_def *ext = NULL;
5951c349dbc7Sjsg int r, i;
5952c349dbc7Sjsg int ctx_reg_offset;
5953c349dbc7Sjsg
5954c349dbc7Sjsg /* init the CP */
5955c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
5956c349dbc7Sjsg adev->gfx.config.max_hw_contexts - 1);
5957c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
5958c349dbc7Sjsg
5959c349dbc7Sjsg gfx_v10_0_cp_gfx_enable(adev, true);
5960c349dbc7Sjsg
5961c349dbc7Sjsg ring = &adev->gfx.gfx_ring[0];
5962c349dbc7Sjsg r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5963c349dbc7Sjsg if (r) {
5964c349dbc7Sjsg DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5965c349dbc7Sjsg return r;
5966c349dbc7Sjsg }
5967c349dbc7Sjsg
5968c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5969c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5970c349dbc7Sjsg
5971c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5972c349dbc7Sjsg amdgpu_ring_write(ring, 0x80000000);
5973c349dbc7Sjsg amdgpu_ring_write(ring, 0x80000000);
5974c349dbc7Sjsg
5975c349dbc7Sjsg for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
5976c349dbc7Sjsg for (ext = sect->section; ext->extent != NULL; ++ext) {
5977c349dbc7Sjsg if (sect->id == SECT_CONTEXT) {
5978c349dbc7Sjsg amdgpu_ring_write(ring,
5979c349dbc7Sjsg PACKET3(PACKET3_SET_CONTEXT_REG,
5980c349dbc7Sjsg ext->reg_count));
5981c349dbc7Sjsg amdgpu_ring_write(ring, ext->reg_index -
5982c349dbc7Sjsg PACKET3_SET_CONTEXT_REG_START);
5983c349dbc7Sjsg for (i = 0; i < ext->reg_count; i++)
5984c349dbc7Sjsg amdgpu_ring_write(ring, ext->extent[i]);
5985c349dbc7Sjsg }
5986c349dbc7Sjsg }
5987c349dbc7Sjsg }
5988c349dbc7Sjsg
5989c349dbc7Sjsg ctx_reg_offset =
5990c349dbc7Sjsg SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
5991c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5992c349dbc7Sjsg amdgpu_ring_write(ring, ctx_reg_offset);
5993c349dbc7Sjsg amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
5994c349dbc7Sjsg
5995c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5996c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
5997c349dbc7Sjsg
5998c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5999c349dbc7Sjsg amdgpu_ring_write(ring, 0);
6000c349dbc7Sjsg
6001c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6002c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6003c349dbc7Sjsg amdgpu_ring_write(ring, 0x8000);
6004c349dbc7Sjsg amdgpu_ring_write(ring, 0x8000);
6005c349dbc7Sjsg
6006c349dbc7Sjsg amdgpu_ring_commit(ring);
6007c349dbc7Sjsg
6008c349dbc7Sjsg /* submit cs packet to copy state 0 to next available state */
6009c349dbc7Sjsg if (adev->gfx.num_gfx_rings > 1) {
6010c349dbc7Sjsg /* maximum supported gfx ring is 2 */
6011c349dbc7Sjsg ring = &adev->gfx.gfx_ring[1];
6012c349dbc7Sjsg r = amdgpu_ring_alloc(ring, 2);
6013c349dbc7Sjsg if (r) {
6014c349dbc7Sjsg DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6015c349dbc7Sjsg return r;
6016c349dbc7Sjsg }
6017c349dbc7Sjsg
6018c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6019c349dbc7Sjsg amdgpu_ring_write(ring, 0);
6020c349dbc7Sjsg
6021c349dbc7Sjsg amdgpu_ring_commit(ring);
6022c349dbc7Sjsg }
6023c349dbc7Sjsg return 0;
6024c349dbc7Sjsg }
6025c349dbc7Sjsg
gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device * adev,CP_PIPE_ID pipe)6026c349dbc7Sjsg static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6027c349dbc7Sjsg CP_PIPE_ID pipe)
6028c349dbc7Sjsg {
6029c349dbc7Sjsg u32 tmp;
6030c349dbc7Sjsg
6031c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6032c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6033c349dbc7Sjsg
6034c349dbc7Sjsg WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6035c349dbc7Sjsg }
6036c349dbc7Sjsg
gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device * adev,struct amdgpu_ring * ring)6037c349dbc7Sjsg static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6038c349dbc7Sjsg struct amdgpu_ring *ring)
6039c349dbc7Sjsg {
6040c349dbc7Sjsg u32 tmp;
6041c349dbc7Sjsg
60425ca02815Sjsg if (!amdgpu_async_gfx_ring) {
6043c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6044c349dbc7Sjsg if (ring->use_doorbell) {
6045c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6046c349dbc7Sjsg DOORBELL_OFFSET, ring->doorbell_index);
6047c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6048c349dbc7Sjsg DOORBELL_EN, 1);
6049c349dbc7Sjsg } else {
6050c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6051c349dbc7Sjsg DOORBELL_EN, 0);
6052c349dbc7Sjsg }
6053c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
60545ca02815Sjsg }
60551bb76ff1Sjsg switch (adev->ip_versions[GC_HWIP][0]) {
60561bb76ff1Sjsg case IP_VERSION(10, 3, 0):
60571bb76ff1Sjsg case IP_VERSION(10, 3, 2):
60581bb76ff1Sjsg case IP_VERSION(10, 3, 1):
60591bb76ff1Sjsg case IP_VERSION(10, 3, 4):
60601bb76ff1Sjsg case IP_VERSION(10, 3, 5):
60611bb76ff1Sjsg case IP_VERSION(10, 3, 6):
60621bb76ff1Sjsg case IP_VERSION(10, 3, 3):
60631bb76ff1Sjsg case IP_VERSION(10, 3, 7):
6064ad8b1aafSjsg tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6065ad8b1aafSjsg DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6066ad8b1aafSjsg WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6067ad8b1aafSjsg
6068ad8b1aafSjsg WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6069ad8b1aafSjsg CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6070ad8b1aafSjsg break;
6071ad8b1aafSjsg default:
6072c349dbc7Sjsg tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6073c349dbc7Sjsg DOORBELL_RANGE_LOWER, ring->doorbell_index);
6074c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6075c349dbc7Sjsg
6076c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6077c349dbc7Sjsg CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6078ad8b1aafSjsg break;
6079ad8b1aafSjsg }
6080c349dbc7Sjsg }
6081c349dbc7Sjsg
gfx_v10_0_cp_gfx_resume(struct amdgpu_device * adev)6082c349dbc7Sjsg static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6083c349dbc7Sjsg {
6084c349dbc7Sjsg struct amdgpu_ring *ring;
6085c349dbc7Sjsg u32 tmp;
6086c349dbc7Sjsg u32 rb_bufsz;
6087c349dbc7Sjsg u64 rb_addr, rptr_addr, wptr_gpu_addr;
6088c349dbc7Sjsg
6089c349dbc7Sjsg /* Set the write pointer delay */
6090c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6091c349dbc7Sjsg
6092c349dbc7Sjsg /* set the RB to use vmid 0 */
6093c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6094c349dbc7Sjsg
6095c349dbc7Sjsg /* Init gfx ring 0 for pipe 0 */
6096c349dbc7Sjsg mutex_lock(&adev->srbm_mutex);
6097c349dbc7Sjsg gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6098c349dbc7Sjsg
6099c349dbc7Sjsg /* Set ring buffer size */
6100c349dbc7Sjsg ring = &adev->gfx.gfx_ring[0];
6101c349dbc7Sjsg rb_bufsz = order_base_2(ring->ring_size / 8);
6102c349dbc7Sjsg tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6103c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6104c349dbc7Sjsg #ifdef __BIG_ENDIAN
6105c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6106c349dbc7Sjsg #endif
6107c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6108c349dbc7Sjsg
6109c349dbc7Sjsg /* Initialize the ring buffer's write pointers */
6110c349dbc7Sjsg ring->wptr = 0;
6111c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6112c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6113c349dbc7Sjsg
6114c349dbc7Sjsg /* set the wb address wether it's enabled or not */
61151bb76ff1Sjsg rptr_addr = ring->rptr_gpu_addr;
6116c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6117c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6118c349dbc7Sjsg CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6119c349dbc7Sjsg
61201bb76ff1Sjsg wptr_gpu_addr = ring->wptr_gpu_addr;
6121c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6122c349dbc7Sjsg lower_32_bits(wptr_gpu_addr));
6123c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6124c349dbc7Sjsg upper_32_bits(wptr_gpu_addr));
6125c349dbc7Sjsg
6126c349dbc7Sjsg mdelay(1);
6127c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6128c349dbc7Sjsg
6129c349dbc7Sjsg rb_addr = ring->gpu_addr >> 8;
6130c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6131c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6132c349dbc7Sjsg
6133c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6134c349dbc7Sjsg
6135c349dbc7Sjsg gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6136c349dbc7Sjsg mutex_unlock(&adev->srbm_mutex);
6137c349dbc7Sjsg
6138c349dbc7Sjsg /* Init gfx ring 1 for pipe 1 */
6139c349dbc7Sjsg if (adev->gfx.num_gfx_rings > 1) {
6140c349dbc7Sjsg mutex_lock(&adev->srbm_mutex);
6141c349dbc7Sjsg gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6142c349dbc7Sjsg /* maximum supported gfx ring is 2 */
6143c349dbc7Sjsg ring = &adev->gfx.gfx_ring[1];
6144c349dbc7Sjsg rb_bufsz = order_base_2(ring->ring_size / 8);
6145c349dbc7Sjsg tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6146c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6147c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6148c349dbc7Sjsg /* Initialize the ring buffer's write pointers */
6149c349dbc7Sjsg ring->wptr = 0;
6150c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6151c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6152c349dbc7Sjsg /* Set the wb address wether it's enabled or not */
61531bb76ff1Sjsg rptr_addr = ring->rptr_gpu_addr;
6154c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6155c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6156c349dbc7Sjsg CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
61571bb76ff1Sjsg wptr_gpu_addr = ring->wptr_gpu_addr;
6158c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6159c349dbc7Sjsg lower_32_bits(wptr_gpu_addr));
6160c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6161c349dbc7Sjsg upper_32_bits(wptr_gpu_addr));
6162c349dbc7Sjsg
6163c349dbc7Sjsg mdelay(1);
6164c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6165c349dbc7Sjsg
6166c349dbc7Sjsg rb_addr = ring->gpu_addr >> 8;
6167c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6168c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6169c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6170c349dbc7Sjsg
6171c349dbc7Sjsg gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6172c349dbc7Sjsg mutex_unlock(&adev->srbm_mutex);
6173c349dbc7Sjsg }
6174c349dbc7Sjsg /* Switch to pipe 0 */
6175c349dbc7Sjsg mutex_lock(&adev->srbm_mutex);
6176c349dbc7Sjsg gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6177c349dbc7Sjsg mutex_unlock(&adev->srbm_mutex);
6178c349dbc7Sjsg
6179c349dbc7Sjsg /* start the ring */
6180c349dbc7Sjsg gfx_v10_0_cp_gfx_start(adev);
6181c349dbc7Sjsg
6182c349dbc7Sjsg return 0;
6183c349dbc7Sjsg }
6184c349dbc7Sjsg
gfx_v10_0_cp_compute_enable(struct amdgpu_device * adev,bool enable)6185c349dbc7Sjsg static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6186c349dbc7Sjsg {
6187c349dbc7Sjsg if (enable) {
61881bb76ff1Sjsg switch (adev->ip_versions[GC_HWIP][0]) {
61891bb76ff1Sjsg case IP_VERSION(10, 3, 0):
61901bb76ff1Sjsg case IP_VERSION(10, 3, 2):
61911bb76ff1Sjsg case IP_VERSION(10, 3, 1):
61921bb76ff1Sjsg case IP_VERSION(10, 3, 4):
61931bb76ff1Sjsg case IP_VERSION(10, 3, 5):
61941bb76ff1Sjsg case IP_VERSION(10, 3, 6):
61951bb76ff1Sjsg case IP_VERSION(10, 3, 3):
61961bb76ff1Sjsg case IP_VERSION(10, 3, 7):
6197ad8b1aafSjsg WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6198ad8b1aafSjsg break;
6199ad8b1aafSjsg default:
6200c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6201ad8b1aafSjsg break;
6202ad8b1aafSjsg }
6203c349dbc7Sjsg } else {
62041bb76ff1Sjsg switch (adev->ip_versions[GC_HWIP][0]) {
62051bb76ff1Sjsg case IP_VERSION(10, 3, 0):
62061bb76ff1Sjsg case IP_VERSION(10, 3, 2):
62071bb76ff1Sjsg case IP_VERSION(10, 3, 1):
62081bb76ff1Sjsg case IP_VERSION(10, 3, 4):
62091bb76ff1Sjsg case IP_VERSION(10, 3, 5):
62101bb76ff1Sjsg case IP_VERSION(10, 3, 6):
62111bb76ff1Sjsg case IP_VERSION(10, 3, 3):
62121bb76ff1Sjsg case IP_VERSION(10, 3, 7):
6213ad8b1aafSjsg WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6214ad8b1aafSjsg (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6215ad8b1aafSjsg CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6216ad8b1aafSjsg break;
6217ad8b1aafSjsg default:
6218c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6219c349dbc7Sjsg (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6220c349dbc7Sjsg CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6221ad8b1aafSjsg break;
6222ad8b1aafSjsg }
6223f005ef32Sjsg adev->gfx.kiq[0].ring.sched.ready = false;
6224c349dbc7Sjsg }
6225c349dbc7Sjsg udelay(50);
6226c349dbc7Sjsg }
6227c349dbc7Sjsg
gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device * adev)6228c349dbc7Sjsg static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6229c349dbc7Sjsg {
6230c349dbc7Sjsg const struct gfx_firmware_header_v1_0 *mec_hdr;
6231c349dbc7Sjsg const __le32 *fw_data;
6232f005ef32Sjsg unsigned int i;
6233c349dbc7Sjsg u32 tmp;
6234c349dbc7Sjsg u32 usec_timeout = 50000; /* Wait for 50 ms */
6235c349dbc7Sjsg
6236c349dbc7Sjsg if (!adev->gfx.mec_fw)
6237c349dbc7Sjsg return -EINVAL;
6238c349dbc7Sjsg
6239c349dbc7Sjsg gfx_v10_0_cp_compute_enable(adev, false);
6240c349dbc7Sjsg
6241c349dbc7Sjsg mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6242c349dbc7Sjsg amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6243c349dbc7Sjsg
6244c349dbc7Sjsg fw_data = (const __le32 *)
6245c349dbc7Sjsg (adev->gfx.mec_fw->data +
6246c349dbc7Sjsg le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6247c349dbc7Sjsg
6248c349dbc7Sjsg /* Trigger an invalidation of the L1 instruction caches */
6249c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6250c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6251c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6252c349dbc7Sjsg
6253c349dbc7Sjsg /* Wait for invalidation complete */
6254c349dbc7Sjsg for (i = 0; i < usec_timeout; i++) {
6255c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6256c349dbc7Sjsg if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6257c349dbc7Sjsg INVALIDATE_CACHE_COMPLETE))
6258c349dbc7Sjsg break;
6259c349dbc7Sjsg udelay(1);
6260c349dbc7Sjsg }
6261c349dbc7Sjsg
6262c349dbc7Sjsg if (i >= usec_timeout) {
6263c349dbc7Sjsg dev_err(adev->dev, "failed to invalidate instruction cache\n");
6264c349dbc7Sjsg return -EINVAL;
6265c349dbc7Sjsg }
6266c349dbc7Sjsg
6267c349dbc7Sjsg if (amdgpu_emu_mode == 1)
62685ca02815Sjsg adev->hdp.funcs->flush_hdp(adev, NULL);
6269c349dbc7Sjsg
6270c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6271c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6272c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6273c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6274c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6275c349dbc7Sjsg
6276c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6277c349dbc7Sjsg 0xFFFFF000);
6278c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6279c349dbc7Sjsg upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6280c349dbc7Sjsg
6281c349dbc7Sjsg /* MEC1 */
6282c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6283c349dbc7Sjsg
6284c349dbc7Sjsg for (i = 0; i < mec_hdr->jt_size; i++)
6285c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6286c349dbc7Sjsg le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6287c349dbc7Sjsg
6288c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6289c349dbc7Sjsg
6290c349dbc7Sjsg /*
6291c349dbc7Sjsg * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6292c349dbc7Sjsg * different microcode than MEC1.
6293c349dbc7Sjsg */
6294c349dbc7Sjsg
6295c349dbc7Sjsg return 0;
6296c349dbc7Sjsg }
6297c349dbc7Sjsg
gfx_v10_0_kiq_setting(struct amdgpu_ring * ring)6298c349dbc7Sjsg static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6299c349dbc7Sjsg {
6300c349dbc7Sjsg uint32_t tmp;
6301c349dbc7Sjsg struct amdgpu_device *adev = ring->adev;
6302c349dbc7Sjsg
6303c349dbc7Sjsg /* tell RLC which is KIQ queue */
63041bb76ff1Sjsg switch (adev->ip_versions[GC_HWIP][0]) {
63051bb76ff1Sjsg case IP_VERSION(10, 3, 0):
63061bb76ff1Sjsg case IP_VERSION(10, 3, 2):
63071bb76ff1Sjsg case IP_VERSION(10, 3, 1):
63081bb76ff1Sjsg case IP_VERSION(10, 3, 4):
63091bb76ff1Sjsg case IP_VERSION(10, 3, 5):
63101bb76ff1Sjsg case IP_VERSION(10, 3, 6):
63111bb76ff1Sjsg case IP_VERSION(10, 3, 3):
63121bb76ff1Sjsg case IP_VERSION(10, 3, 7):
6313ad8b1aafSjsg tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6314ad8b1aafSjsg tmp &= 0xffffff00;
6315ad8b1aafSjsg tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6316ad8b1aafSjsg WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6317ad8b1aafSjsg tmp |= 0x80;
6318ad8b1aafSjsg WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6319ad8b1aafSjsg break;
6320ad8b1aafSjsg default:
6321c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6322c349dbc7Sjsg tmp &= 0xffffff00;
6323c349dbc7Sjsg tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6324c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6325c349dbc7Sjsg tmp |= 0x80;
6326c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6327ad8b1aafSjsg break;
6328ad8b1aafSjsg }
6329c349dbc7Sjsg }
6330c349dbc7Sjsg
gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device * adev,struct v10_gfx_mqd * mqd,struct amdgpu_mqd_prop * prop)63311bb76ff1Sjsg static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
63321bb76ff1Sjsg struct v10_gfx_mqd *mqd,
63331bb76ff1Sjsg struct amdgpu_mqd_prop *prop)
6334c349dbc7Sjsg {
63351bb76ff1Sjsg bool priority = 0;
63361bb76ff1Sjsg u32 tmp;
63371bb76ff1Sjsg
63381bb76ff1Sjsg /* set up default queue priority level
63391bb76ff1Sjsg * 0x0 = low priority, 0x1 = high priority
63401bb76ff1Sjsg */
63411bb76ff1Sjsg if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
63421bb76ff1Sjsg priority = 1;
63431bb76ff1Sjsg
63441bb76ff1Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
63451bb76ff1Sjsg tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
63461bb76ff1Sjsg mqd->cp_gfx_hqd_queue_priority = tmp;
63471bb76ff1Sjsg }
63481bb76ff1Sjsg
gfx_v10_0_gfx_mqd_init(struct amdgpu_device * adev,void * m,struct amdgpu_mqd_prop * prop)63491bb76ff1Sjsg static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
63501bb76ff1Sjsg struct amdgpu_mqd_prop *prop)
63511bb76ff1Sjsg {
63521bb76ff1Sjsg struct v10_gfx_mqd *mqd = m;
6353c349dbc7Sjsg uint64_t hqd_gpu_addr, wb_gpu_addr;
6354c349dbc7Sjsg uint32_t tmp;
6355c349dbc7Sjsg uint32_t rb_bufsz;
6356c349dbc7Sjsg
6357c349dbc7Sjsg /* set up gfx hqd wptr */
6358c349dbc7Sjsg mqd->cp_gfx_hqd_wptr = 0;
6359c349dbc7Sjsg mqd->cp_gfx_hqd_wptr_hi = 0;
6360c349dbc7Sjsg
6361c349dbc7Sjsg /* set the pointer to the MQD */
63621bb76ff1Sjsg mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
63631bb76ff1Sjsg mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6364c349dbc7Sjsg
6365c349dbc7Sjsg /* set up mqd control */
6366c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6367c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6368c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6369c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6370c349dbc7Sjsg mqd->cp_gfx_mqd_control = tmp;
6371c349dbc7Sjsg
6372c349dbc7Sjsg /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6373c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6374c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6375c349dbc7Sjsg mqd->cp_gfx_hqd_vmid = 0;
6376c349dbc7Sjsg
63771bb76ff1Sjsg /* set up gfx queue priority */
63781bb76ff1Sjsg gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop);
6379c349dbc7Sjsg
6380c349dbc7Sjsg /* set up time quantum */
6381c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6382c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6383c349dbc7Sjsg mqd->cp_gfx_hqd_quantum = tmp;
6384c349dbc7Sjsg
6385c349dbc7Sjsg /* set up gfx hqd base. this is similar as CP_RB_BASE */
63861bb76ff1Sjsg hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6387c349dbc7Sjsg mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6388c349dbc7Sjsg mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6389c349dbc7Sjsg
6390c349dbc7Sjsg /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
63911bb76ff1Sjsg wb_gpu_addr = prop->rptr_gpu_addr;
6392c349dbc7Sjsg mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6393c349dbc7Sjsg mqd->cp_gfx_hqd_rptr_addr_hi =
6394c349dbc7Sjsg upper_32_bits(wb_gpu_addr) & 0xffff;
6395c349dbc7Sjsg
6396c349dbc7Sjsg /* set up rb_wptr_poll addr */
63971bb76ff1Sjsg wb_gpu_addr = prop->wptr_gpu_addr;
6398c349dbc7Sjsg mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6399c349dbc7Sjsg mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6400c349dbc7Sjsg
6401c349dbc7Sjsg /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
64021bb76ff1Sjsg rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
6403c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6404c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6405c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6406c349dbc7Sjsg #ifdef __BIG_ENDIAN
6407c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6408c349dbc7Sjsg #endif
6409c349dbc7Sjsg mqd->cp_gfx_hqd_cntl = tmp;
6410c349dbc7Sjsg
6411c349dbc7Sjsg /* set up cp_doorbell_control */
6412c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
64131bb76ff1Sjsg if (prop->use_doorbell) {
6414c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
64151bb76ff1Sjsg DOORBELL_OFFSET, prop->doorbell_index);
6416c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6417c349dbc7Sjsg DOORBELL_EN, 1);
6418c349dbc7Sjsg } else
6419c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6420c349dbc7Sjsg DOORBELL_EN, 0);
6421c349dbc7Sjsg mqd->cp_rb_doorbell_control = tmp;
6422c349dbc7Sjsg
6423c349dbc7Sjsg /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6424c349dbc7Sjsg mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6425c349dbc7Sjsg
6426c349dbc7Sjsg /* active the queue */
6427c349dbc7Sjsg mqd->cp_gfx_hqd_active = 1;
6428c349dbc7Sjsg
6429c349dbc7Sjsg return 0;
6430c349dbc7Sjsg }
6431c349dbc7Sjsg
gfx_v10_0_gfx_init_queue(struct amdgpu_ring * ring)6432c349dbc7Sjsg static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6433c349dbc7Sjsg {
6434c349dbc7Sjsg struct amdgpu_device *adev = ring->adev;
6435c349dbc7Sjsg struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6436c349dbc7Sjsg int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6437c349dbc7Sjsg
6438ad8b1aafSjsg if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6439c349dbc7Sjsg memset((void *)mqd, 0, sizeof(*mqd));
6440c349dbc7Sjsg mutex_lock(&adev->srbm_mutex);
6441c349dbc7Sjsg nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
64421bb76ff1Sjsg amdgpu_ring_init_mqd(ring);
64431bb76ff1Sjsg
64441bb76ff1Sjsg /*
64451bb76ff1Sjsg * if there are 2 gfx rings, set the lower doorbell
64461bb76ff1Sjsg * range of the first ring, otherwise the range of
64471bb76ff1Sjsg * the second ring will override the first ring
64481bb76ff1Sjsg */
64491bb76ff1Sjsg if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
64501bb76ff1Sjsg gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
64511bb76ff1Sjsg
6452c349dbc7Sjsg nv_grbm_select(adev, 0, 0, 0, 0);
6453c349dbc7Sjsg mutex_unlock(&adev->srbm_mutex);
6454c349dbc7Sjsg if (adev->gfx.me.mqd_backup[mqd_idx])
6455f005ef32Sjsg memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6456f005ef32Sjsg } else {
6457f005ef32Sjsg /* restore mqd with the backup copy */
6458c349dbc7Sjsg if (adev->gfx.me.mqd_backup[mqd_idx])
6459f005ef32Sjsg memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6460c349dbc7Sjsg /* reset the ring */
6461c349dbc7Sjsg ring->wptr = 0;
64621bb76ff1Sjsg *ring->wptr_cpu_addr = 0;
6463c349dbc7Sjsg amdgpu_ring_clear_ring(ring);
6464c349dbc7Sjsg }
6465c349dbc7Sjsg
6466c349dbc7Sjsg return 0;
6467c349dbc7Sjsg }
6468c349dbc7Sjsg
gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device * adev)6469c349dbc7Sjsg static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6470c349dbc7Sjsg {
6471c349dbc7Sjsg int r, i;
6472c349dbc7Sjsg struct amdgpu_ring *ring;
6473c349dbc7Sjsg
6474c349dbc7Sjsg for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6475c349dbc7Sjsg ring = &adev->gfx.gfx_ring[i];
6476c349dbc7Sjsg
6477c349dbc7Sjsg r = amdgpu_bo_reserve(ring->mqd_obj, false);
6478c349dbc7Sjsg if (unlikely(r != 0))
6479f005ef32Sjsg return r;
6480c349dbc7Sjsg
6481c349dbc7Sjsg r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6482c349dbc7Sjsg if (!r) {
6483c349dbc7Sjsg r = gfx_v10_0_gfx_init_queue(ring);
6484c349dbc7Sjsg amdgpu_bo_kunmap(ring->mqd_obj);
6485c349dbc7Sjsg ring->mqd_ptr = NULL;
6486c349dbc7Sjsg }
6487c349dbc7Sjsg amdgpu_bo_unreserve(ring->mqd_obj);
6488c349dbc7Sjsg if (r)
6489c349dbc7Sjsg return r;
6490c349dbc7Sjsg }
6491c349dbc7Sjsg
6492f005ef32Sjsg r = amdgpu_gfx_enable_kgq(adev, 0);
6493f005ef32Sjsg if (r)
6494f005ef32Sjsg return r;
6495f005ef32Sjsg
6496f005ef32Sjsg return gfx_v10_0_cp_gfx_start(adev);
6497f005ef32Sjsg }
6498f005ef32Sjsg
gfx_v10_0_compute_mqd_init(struct amdgpu_device * adev,void * m,struct amdgpu_mqd_prop * prop)64991bb76ff1Sjsg static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
65001bb76ff1Sjsg struct amdgpu_mqd_prop *prop)
6501c349dbc7Sjsg {
65021bb76ff1Sjsg struct v10_compute_mqd *mqd = m;
6503c349dbc7Sjsg uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6504c349dbc7Sjsg uint32_t tmp;
6505c349dbc7Sjsg
6506c349dbc7Sjsg mqd->header = 0xC0310800;
6507c349dbc7Sjsg mqd->compute_pipelinestat_enable = 0x00000001;
6508c349dbc7Sjsg mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6509c349dbc7Sjsg mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6510c349dbc7Sjsg mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6511c349dbc7Sjsg mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6512c349dbc7Sjsg mqd->compute_misc_reserved = 0x00000003;
6513c349dbc7Sjsg
65141bb76ff1Sjsg eop_base_addr = prop->eop_gpu_addr >> 8;
6515c349dbc7Sjsg mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6516c349dbc7Sjsg mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6517c349dbc7Sjsg
6518c349dbc7Sjsg /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6519c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6520c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6521c349dbc7Sjsg (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6522c349dbc7Sjsg
6523c349dbc7Sjsg mqd->cp_hqd_eop_control = tmp;
6524c349dbc7Sjsg
6525c349dbc7Sjsg /* enable doorbell? */
6526c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6527c349dbc7Sjsg
65281bb76ff1Sjsg if (prop->use_doorbell) {
6529c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
65301bb76ff1Sjsg DOORBELL_OFFSET, prop->doorbell_index);
6531c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6532c349dbc7Sjsg DOORBELL_EN, 1);
6533c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6534c349dbc7Sjsg DOORBELL_SOURCE, 0);
6535c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6536c349dbc7Sjsg DOORBELL_HIT, 0);
6537c349dbc7Sjsg } else {
6538c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6539c349dbc7Sjsg DOORBELL_EN, 0);
6540c349dbc7Sjsg }
6541c349dbc7Sjsg
6542c349dbc7Sjsg mqd->cp_hqd_pq_doorbell_control = tmp;
6543c349dbc7Sjsg
6544c349dbc7Sjsg /* disable the queue if it's active */
6545c349dbc7Sjsg mqd->cp_hqd_dequeue_request = 0;
6546c349dbc7Sjsg mqd->cp_hqd_pq_rptr = 0;
6547c349dbc7Sjsg mqd->cp_hqd_pq_wptr_lo = 0;
6548c349dbc7Sjsg mqd->cp_hqd_pq_wptr_hi = 0;
6549c349dbc7Sjsg
6550c349dbc7Sjsg /* set the pointer to the MQD */
65511bb76ff1Sjsg mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
65521bb76ff1Sjsg mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6553c349dbc7Sjsg
6554c349dbc7Sjsg /* set MQD vmid to 0 */
6555c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6556c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6557c349dbc7Sjsg mqd->cp_mqd_control = tmp;
6558c349dbc7Sjsg
6559c349dbc7Sjsg /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
65601bb76ff1Sjsg hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6561c349dbc7Sjsg mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6562c349dbc7Sjsg mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6563c349dbc7Sjsg
6564c349dbc7Sjsg /* set up the HQD, this is similar to CP_RB0_CNTL */
6565c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6566c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
65671bb76ff1Sjsg (order_base_2(prop->queue_size / 4) - 1));
6568c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
65691bb76ff1Sjsg (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
6570c349dbc7Sjsg #ifdef __BIG_ENDIAN
6571c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6572c349dbc7Sjsg #endif
6573*d732de98Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
6574c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6575c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6576c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6577c349dbc7Sjsg mqd->cp_hqd_pq_control = tmp;
6578c349dbc7Sjsg
6579c349dbc7Sjsg /* set the wb address whether it's enabled or not */
65801bb76ff1Sjsg wb_gpu_addr = prop->rptr_gpu_addr;
6581c349dbc7Sjsg mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6582c349dbc7Sjsg mqd->cp_hqd_pq_rptr_report_addr_hi =
6583c349dbc7Sjsg upper_32_bits(wb_gpu_addr) & 0xffff;
6584c349dbc7Sjsg
6585c349dbc7Sjsg /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
65861bb76ff1Sjsg wb_gpu_addr = prop->wptr_gpu_addr;
6587c349dbc7Sjsg mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6588c349dbc7Sjsg mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6589c349dbc7Sjsg
6590c349dbc7Sjsg /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6591c349dbc7Sjsg mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6592c349dbc7Sjsg
6593c349dbc7Sjsg /* set the vmid for the queue */
6594c349dbc7Sjsg mqd->cp_hqd_vmid = 0;
6595c349dbc7Sjsg
6596c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6597c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6598c349dbc7Sjsg mqd->cp_hqd_persistent_state = tmp;
6599c349dbc7Sjsg
6600c349dbc7Sjsg /* set MIN_IB_AVAIL_SIZE */
6601c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6602c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6603c349dbc7Sjsg mqd->cp_hqd_ib_control = tmp;
6604c349dbc7Sjsg
6605c349dbc7Sjsg /* set static priority for a compute queue/ring */
66061bb76ff1Sjsg mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
66071bb76ff1Sjsg mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
6608c349dbc7Sjsg
66091bb76ff1Sjsg mqd->cp_hqd_active = prop->hqd_active;
6610c349dbc7Sjsg
6611c349dbc7Sjsg return 0;
6612c349dbc7Sjsg }
6613c349dbc7Sjsg
gfx_v10_0_kiq_init_register(struct amdgpu_ring * ring)6614c349dbc7Sjsg static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6615c349dbc7Sjsg {
6616c349dbc7Sjsg struct amdgpu_device *adev = ring->adev;
6617c349dbc7Sjsg struct v10_compute_mqd *mqd = ring->mqd_ptr;
6618c349dbc7Sjsg int j;
6619c349dbc7Sjsg
6620ad8b1aafSjsg /* inactivate the queue */
6621ad8b1aafSjsg if (amdgpu_sriov_vf(adev))
6622ad8b1aafSjsg WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6623ad8b1aafSjsg
6624c349dbc7Sjsg /* disable wptr polling */
6625c349dbc7Sjsg WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6626c349dbc7Sjsg
6627c349dbc7Sjsg /* disable the queue if it's active */
6628c349dbc7Sjsg if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6629c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6630c349dbc7Sjsg for (j = 0; j < adev->usec_timeout; j++) {
6631c349dbc7Sjsg if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6632c349dbc7Sjsg break;
6633c349dbc7Sjsg udelay(1);
6634c349dbc7Sjsg }
6635c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6636c349dbc7Sjsg mqd->cp_hqd_dequeue_request);
6637c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6638c349dbc7Sjsg mqd->cp_hqd_pq_rptr);
6639c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6640c349dbc7Sjsg mqd->cp_hqd_pq_wptr_lo);
6641c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6642c349dbc7Sjsg mqd->cp_hqd_pq_wptr_hi);
6643c349dbc7Sjsg }
6644c349dbc7Sjsg
66451bb76ff1Sjsg /* disable doorbells */
66461bb76ff1Sjsg WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
66471bb76ff1Sjsg
66481bb76ff1Sjsg /* write the EOP addr */
66491bb76ff1Sjsg WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
66501bb76ff1Sjsg mqd->cp_hqd_eop_base_addr_lo);
66511bb76ff1Sjsg WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
66521bb76ff1Sjsg mqd->cp_hqd_eop_base_addr_hi);
66531bb76ff1Sjsg
66541bb76ff1Sjsg /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
66551bb76ff1Sjsg WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
66561bb76ff1Sjsg mqd->cp_hqd_eop_control);
66571bb76ff1Sjsg
6658c349dbc7Sjsg /* set the pointer to the MQD */
6659c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6660c349dbc7Sjsg mqd->cp_mqd_base_addr_lo);
6661c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6662c349dbc7Sjsg mqd->cp_mqd_base_addr_hi);
6663c349dbc7Sjsg
6664c349dbc7Sjsg /* set MQD vmid to 0 */
6665c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6666c349dbc7Sjsg mqd->cp_mqd_control);
6667c349dbc7Sjsg
6668c349dbc7Sjsg /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6669c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6670c349dbc7Sjsg mqd->cp_hqd_pq_base_lo);
6671c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6672c349dbc7Sjsg mqd->cp_hqd_pq_base_hi);
6673c349dbc7Sjsg
6674c349dbc7Sjsg /* set up the HQD, this is similar to CP_RB0_CNTL */
6675c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6676c349dbc7Sjsg mqd->cp_hqd_pq_control);
6677c349dbc7Sjsg
6678c349dbc7Sjsg /* set the wb address whether it's enabled or not */
6679c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6680c349dbc7Sjsg mqd->cp_hqd_pq_rptr_report_addr_lo);
6681c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6682c349dbc7Sjsg mqd->cp_hqd_pq_rptr_report_addr_hi);
6683c349dbc7Sjsg
6684c349dbc7Sjsg /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6685c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6686c349dbc7Sjsg mqd->cp_hqd_pq_wptr_poll_addr_lo);
6687c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6688c349dbc7Sjsg mqd->cp_hqd_pq_wptr_poll_addr_hi);
6689c349dbc7Sjsg
6690c349dbc7Sjsg /* enable the doorbell if requested */
6691c349dbc7Sjsg if (ring->use_doorbell) {
6692c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6693c349dbc7Sjsg (adev->doorbell_index.kiq * 2) << 2);
6694c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6695c349dbc7Sjsg (adev->doorbell_index.userqueue_end * 2) << 2);
6696c349dbc7Sjsg }
6697c349dbc7Sjsg
6698c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6699c349dbc7Sjsg mqd->cp_hqd_pq_doorbell_control);
6700c349dbc7Sjsg
6701c349dbc7Sjsg /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6702c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6703c349dbc7Sjsg mqd->cp_hqd_pq_wptr_lo);
6704c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6705c349dbc7Sjsg mqd->cp_hqd_pq_wptr_hi);
6706c349dbc7Sjsg
6707c349dbc7Sjsg /* set the vmid for the queue */
6708c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6709c349dbc7Sjsg
6710c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6711c349dbc7Sjsg mqd->cp_hqd_persistent_state);
6712c349dbc7Sjsg
6713c349dbc7Sjsg /* activate the queue */
6714c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6715c349dbc7Sjsg mqd->cp_hqd_active);
6716c349dbc7Sjsg
6717c349dbc7Sjsg if (ring->use_doorbell)
6718c349dbc7Sjsg WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6719c349dbc7Sjsg
6720c349dbc7Sjsg return 0;
6721c349dbc7Sjsg }
6722c349dbc7Sjsg
gfx_v10_0_kiq_init_queue(struct amdgpu_ring * ring)6723c349dbc7Sjsg static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6724c349dbc7Sjsg {
6725c349dbc7Sjsg struct amdgpu_device *adev = ring->adev;
6726c349dbc7Sjsg struct v10_compute_mqd *mqd = ring->mqd_ptr;
6727c349dbc7Sjsg
6728c349dbc7Sjsg gfx_v10_0_kiq_setting(ring);
6729c349dbc7Sjsg
6730ad8b1aafSjsg if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6731c349dbc7Sjsg /* reset MQD to a clean status */
6732f005ef32Sjsg if (adev->gfx.kiq[0].mqd_backup)
6733f005ef32Sjsg memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd));
6734c349dbc7Sjsg
6735c349dbc7Sjsg /* reset ring buffer */
6736c349dbc7Sjsg ring->wptr = 0;
6737c349dbc7Sjsg amdgpu_ring_clear_ring(ring);
6738c349dbc7Sjsg
6739c349dbc7Sjsg mutex_lock(&adev->srbm_mutex);
6740c349dbc7Sjsg nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6741c349dbc7Sjsg gfx_v10_0_kiq_init_register(ring);
6742c349dbc7Sjsg nv_grbm_select(adev, 0, 0, 0, 0);
6743c349dbc7Sjsg mutex_unlock(&adev->srbm_mutex);
6744c349dbc7Sjsg } else {
6745c349dbc7Sjsg memset((void *)mqd, 0, sizeof(*mqd));
6746f005ef32Sjsg if (amdgpu_sriov_vf(adev) && adev->in_suspend)
6747f005ef32Sjsg amdgpu_ring_clear_ring(ring);
6748c349dbc7Sjsg mutex_lock(&adev->srbm_mutex);
6749c349dbc7Sjsg nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
67501bb76ff1Sjsg amdgpu_ring_init_mqd(ring);
6751c349dbc7Sjsg gfx_v10_0_kiq_init_register(ring);
6752c349dbc7Sjsg nv_grbm_select(adev, 0, 0, 0, 0);
6753c349dbc7Sjsg mutex_unlock(&adev->srbm_mutex);
6754c349dbc7Sjsg
6755f005ef32Sjsg if (adev->gfx.kiq[0].mqd_backup)
6756f005ef32Sjsg memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd));
6757c349dbc7Sjsg }
6758c349dbc7Sjsg
6759c349dbc7Sjsg return 0;
6760c349dbc7Sjsg }
6761c349dbc7Sjsg
gfx_v10_0_kcq_init_queue(struct amdgpu_ring * ring)6762c349dbc7Sjsg static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6763c349dbc7Sjsg {
6764c349dbc7Sjsg struct amdgpu_device *adev = ring->adev;
6765c349dbc7Sjsg struct v10_compute_mqd *mqd = ring->mqd_ptr;
6766c349dbc7Sjsg int mqd_idx = ring - &adev->gfx.compute_ring[0];
6767c349dbc7Sjsg
6768ad8b1aafSjsg if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6769c349dbc7Sjsg memset((void *)mqd, 0, sizeof(*mqd));
6770c349dbc7Sjsg mutex_lock(&adev->srbm_mutex);
6771c349dbc7Sjsg nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
67721bb76ff1Sjsg amdgpu_ring_init_mqd(ring);
6773c349dbc7Sjsg nv_grbm_select(adev, 0, 0, 0, 0);
6774c349dbc7Sjsg mutex_unlock(&adev->srbm_mutex);
6775c349dbc7Sjsg
6776c349dbc7Sjsg if (adev->gfx.mec.mqd_backup[mqd_idx])
6777f005ef32Sjsg memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6778f005ef32Sjsg } else {
6779f005ef32Sjsg /* restore MQD to a clean status */
6780c349dbc7Sjsg if (adev->gfx.mec.mqd_backup[mqd_idx])
6781f005ef32Sjsg memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6782c349dbc7Sjsg /* reset ring buffer */
6783c349dbc7Sjsg ring->wptr = 0;
67841bb76ff1Sjsg atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
6785c349dbc7Sjsg amdgpu_ring_clear_ring(ring);
6786c349dbc7Sjsg }
6787c349dbc7Sjsg
6788c349dbc7Sjsg return 0;
6789c349dbc7Sjsg }
6790c349dbc7Sjsg
gfx_v10_0_kiq_resume(struct amdgpu_device * adev)6791c349dbc7Sjsg static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6792c349dbc7Sjsg {
6793c349dbc7Sjsg struct amdgpu_ring *ring;
6794c349dbc7Sjsg int r;
6795c349dbc7Sjsg
6796f005ef32Sjsg ring = &adev->gfx.kiq[0].ring;
6797c349dbc7Sjsg
6798c349dbc7Sjsg r = amdgpu_bo_reserve(ring->mqd_obj, false);
6799c349dbc7Sjsg if (unlikely(r != 0))
6800c349dbc7Sjsg return r;
6801c349dbc7Sjsg
6802c349dbc7Sjsg r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
68037e7270cfSjsg if (unlikely(r != 0)) {
68047e7270cfSjsg amdgpu_bo_unreserve(ring->mqd_obj);
6805c349dbc7Sjsg return r;
68067e7270cfSjsg }
6807c349dbc7Sjsg
6808c349dbc7Sjsg gfx_v10_0_kiq_init_queue(ring);
6809c349dbc7Sjsg amdgpu_bo_kunmap(ring->mqd_obj);
6810c349dbc7Sjsg ring->mqd_ptr = NULL;
6811c349dbc7Sjsg amdgpu_bo_unreserve(ring->mqd_obj);
6812c349dbc7Sjsg return 0;
6813c349dbc7Sjsg }
6814c349dbc7Sjsg
gfx_v10_0_kcq_resume(struct amdgpu_device * adev)6815c349dbc7Sjsg static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6816c349dbc7Sjsg {
6817c349dbc7Sjsg struct amdgpu_ring *ring = NULL;
6818c349dbc7Sjsg int r = 0, i;
6819c349dbc7Sjsg
6820c349dbc7Sjsg gfx_v10_0_cp_compute_enable(adev, true);
6821c349dbc7Sjsg
6822c349dbc7Sjsg for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6823c349dbc7Sjsg ring = &adev->gfx.compute_ring[i];
6824c349dbc7Sjsg
6825c349dbc7Sjsg r = amdgpu_bo_reserve(ring->mqd_obj, false);
6826c349dbc7Sjsg if (unlikely(r != 0))
6827c349dbc7Sjsg goto done;
6828c349dbc7Sjsg r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6829c349dbc7Sjsg if (!r) {
6830c349dbc7Sjsg r = gfx_v10_0_kcq_init_queue(ring);
6831c349dbc7Sjsg amdgpu_bo_kunmap(ring->mqd_obj);
6832c349dbc7Sjsg ring->mqd_ptr = NULL;
6833c349dbc7Sjsg }
6834c349dbc7Sjsg amdgpu_bo_unreserve(ring->mqd_obj);
6835c349dbc7Sjsg if (r)
6836c349dbc7Sjsg goto done;
6837c349dbc7Sjsg }
6838c349dbc7Sjsg
6839f005ef32Sjsg r = amdgpu_gfx_enable_kcq(adev, 0);
6840c349dbc7Sjsg done:
6841c349dbc7Sjsg return r;
6842c349dbc7Sjsg }
6843c349dbc7Sjsg
gfx_v10_0_cp_resume(struct amdgpu_device * adev)6844c349dbc7Sjsg static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6845c349dbc7Sjsg {
6846c349dbc7Sjsg int r, i;
6847c349dbc7Sjsg struct amdgpu_ring *ring;
6848c349dbc7Sjsg
6849c349dbc7Sjsg if (!(adev->flags & AMD_IS_APU))
6850c349dbc7Sjsg gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6851c349dbc7Sjsg
6852c349dbc7Sjsg if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6853c349dbc7Sjsg /* legacy firmware loading */
6854c349dbc7Sjsg r = gfx_v10_0_cp_gfx_load_microcode(adev);
6855c349dbc7Sjsg if (r)
6856c349dbc7Sjsg return r;
6857c349dbc7Sjsg
6858c349dbc7Sjsg r = gfx_v10_0_cp_compute_load_microcode(adev);
6859c349dbc7Sjsg if (r)
6860c349dbc7Sjsg return r;
6861c349dbc7Sjsg }
6862c349dbc7Sjsg
68631bb76ff1Sjsg if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
68641bb76ff1Sjsg r = amdgpu_mes_kiq_hw_init(adev);
68651bb76ff1Sjsg else
6866c349dbc7Sjsg r = gfx_v10_0_kiq_resume(adev);
6867c349dbc7Sjsg if (r)
6868c349dbc7Sjsg return r;
6869c349dbc7Sjsg
6870c349dbc7Sjsg r = gfx_v10_0_kcq_resume(adev);
6871c349dbc7Sjsg if (r)
6872c349dbc7Sjsg return r;
6873c349dbc7Sjsg
6874c349dbc7Sjsg if (!amdgpu_async_gfx_ring) {
6875c349dbc7Sjsg r = gfx_v10_0_cp_gfx_resume(adev);
6876c349dbc7Sjsg if (r)
6877c349dbc7Sjsg return r;
6878c349dbc7Sjsg } else {
6879c349dbc7Sjsg r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6880c349dbc7Sjsg if (r)
6881c349dbc7Sjsg return r;
6882c349dbc7Sjsg }
6883c349dbc7Sjsg
6884c349dbc7Sjsg for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6885c349dbc7Sjsg ring = &adev->gfx.gfx_ring[i];
6886c349dbc7Sjsg r = amdgpu_ring_test_helper(ring);
6887c349dbc7Sjsg if (r)
6888c349dbc7Sjsg return r;
6889c349dbc7Sjsg }
6890c349dbc7Sjsg
6891c349dbc7Sjsg for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6892c349dbc7Sjsg ring = &adev->gfx.compute_ring[i];
6893c349dbc7Sjsg r = amdgpu_ring_test_helper(ring);
6894c349dbc7Sjsg if (r)
6895c349dbc7Sjsg return r;
6896c349dbc7Sjsg }
6897c349dbc7Sjsg
6898c349dbc7Sjsg return 0;
6899c349dbc7Sjsg }
6900c349dbc7Sjsg
gfx_v10_0_cp_enable(struct amdgpu_device * adev,bool enable)6901c349dbc7Sjsg static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
6902c349dbc7Sjsg {
6903c349dbc7Sjsg gfx_v10_0_cp_gfx_enable(adev, enable);
6904c349dbc7Sjsg gfx_v10_0_cp_compute_enable(adev, enable);
6905c349dbc7Sjsg }
6906c349dbc7Sjsg
gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device * adev)6907c349dbc7Sjsg static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6908c349dbc7Sjsg {
6909c349dbc7Sjsg uint32_t data, pattern = 0xDEADBEEF;
6910c349dbc7Sjsg
6911f005ef32Sjsg /*
6912f005ef32Sjsg * check if mmVGT_ESGS_RING_SIZE_UMD
6913f005ef32Sjsg * has been remapped to mmVGT_ESGS_RING_SIZE
6914f005ef32Sjsg */
69151bb76ff1Sjsg switch (adev->ip_versions[GC_HWIP][0]) {
69161bb76ff1Sjsg case IP_VERSION(10, 3, 0):
69171bb76ff1Sjsg case IP_VERSION(10, 3, 2):
69181bb76ff1Sjsg case IP_VERSION(10, 3, 4):
69191bb76ff1Sjsg case IP_VERSION(10, 3, 5):
6920ad8b1aafSjsg data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
6921ad8b1aafSjsg WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
6922ad8b1aafSjsg WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6923ad8b1aafSjsg
6924ad8b1aafSjsg if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
6925ad8b1aafSjsg WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
6926ad8b1aafSjsg return true;
6927ad8b1aafSjsg }
6928f005ef32Sjsg WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
6929ad8b1aafSjsg break;
69301bb76ff1Sjsg case IP_VERSION(10, 3, 1):
69311bb76ff1Sjsg case IP_VERSION(10, 3, 3):
69321bb76ff1Sjsg case IP_VERSION(10, 3, 6):
69331bb76ff1Sjsg case IP_VERSION(10, 3, 7):
69345ca02815Sjsg return true;
6935ad8b1aafSjsg default:
6936c349dbc7Sjsg data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
6937c349dbc7Sjsg WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
6938c349dbc7Sjsg WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6939c349dbc7Sjsg
6940c349dbc7Sjsg if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
6941c349dbc7Sjsg WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
6942c349dbc7Sjsg return true;
6943c349dbc7Sjsg }
6944f005ef32Sjsg WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
6945ad8b1aafSjsg break;
6946ad8b1aafSjsg }
6947f005ef32Sjsg
6948f005ef32Sjsg return false;
6949c349dbc7Sjsg }
6950c349dbc7Sjsg
gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device * adev)6951c349dbc7Sjsg static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
6952c349dbc7Sjsg {
6953c349dbc7Sjsg uint32_t data;
6954c349dbc7Sjsg
69555ca02815Sjsg if (amdgpu_sriov_vf(adev))
69565ca02815Sjsg return;
69575ca02815Sjsg
6958f005ef32Sjsg /*
6959f005ef32Sjsg * Initialize cam_index to 0
6960f005ef32Sjsg * index will auto-inc after each data writing
6961f005ef32Sjsg */
6962c349dbc7Sjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
6963c349dbc7Sjsg
69641bb76ff1Sjsg switch (adev->ip_versions[GC_HWIP][0]) {
69651bb76ff1Sjsg case IP_VERSION(10, 3, 0):
69661bb76ff1Sjsg case IP_VERSION(10, 3, 2):
69671bb76ff1Sjsg case IP_VERSION(10, 3, 1):
69681bb76ff1Sjsg case IP_VERSION(10, 3, 4):
69691bb76ff1Sjsg case IP_VERSION(10, 3, 5):
69701bb76ff1Sjsg case IP_VERSION(10, 3, 6):
69711bb76ff1Sjsg case IP_VERSION(10, 3, 3):
69721bb76ff1Sjsg case IP_VERSION(10, 3, 7):
6973ad8b1aafSjsg /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6974ad8b1aafSjsg data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6975ad8b1aafSjsg GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6976ad8b1aafSjsg (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
6977ad8b1aafSjsg GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6978ad8b1aafSjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6979ad8b1aafSjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6980ad8b1aafSjsg
6981ad8b1aafSjsg /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6982ad8b1aafSjsg data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6983ad8b1aafSjsg GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6984ad8b1aafSjsg (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
6985ad8b1aafSjsg GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6986ad8b1aafSjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6987ad8b1aafSjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6988ad8b1aafSjsg
6989ad8b1aafSjsg /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6990ad8b1aafSjsg data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6991ad8b1aafSjsg GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6992ad8b1aafSjsg (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
6993ad8b1aafSjsg GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6994ad8b1aafSjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6995ad8b1aafSjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6996ad8b1aafSjsg
6997ad8b1aafSjsg /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6998ad8b1aafSjsg data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6999ad8b1aafSjsg GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7000ad8b1aafSjsg (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7001ad8b1aafSjsg GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7002ad8b1aafSjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7003ad8b1aafSjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7004ad8b1aafSjsg
7005ad8b1aafSjsg /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7006ad8b1aafSjsg data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7007ad8b1aafSjsg GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7008ad8b1aafSjsg (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7009ad8b1aafSjsg GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7010ad8b1aafSjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7011ad8b1aafSjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7012ad8b1aafSjsg
7013ad8b1aafSjsg /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7014ad8b1aafSjsg data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7015ad8b1aafSjsg GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7016ad8b1aafSjsg (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7017ad8b1aafSjsg GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7018ad8b1aafSjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7019ad8b1aafSjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7020ad8b1aafSjsg
7021ad8b1aafSjsg /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7022ad8b1aafSjsg data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7023ad8b1aafSjsg GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7024ad8b1aafSjsg (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7025ad8b1aafSjsg GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7026ad8b1aafSjsg break;
7027ad8b1aafSjsg default:
7028c349dbc7Sjsg /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7029c349dbc7Sjsg data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7030c349dbc7Sjsg GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7031c349dbc7Sjsg (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7032c349dbc7Sjsg GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7033c349dbc7Sjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7034c349dbc7Sjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7035c349dbc7Sjsg
7036c349dbc7Sjsg /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7037c349dbc7Sjsg data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7038c349dbc7Sjsg GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7039c349dbc7Sjsg (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7040c349dbc7Sjsg GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7041c349dbc7Sjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7042c349dbc7Sjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7043c349dbc7Sjsg
7044c349dbc7Sjsg /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7045c349dbc7Sjsg data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7046c349dbc7Sjsg GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7047c349dbc7Sjsg (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7048c349dbc7Sjsg GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7049c349dbc7Sjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7050c349dbc7Sjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7051c349dbc7Sjsg
7052c349dbc7Sjsg /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7053c349dbc7Sjsg data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7054c349dbc7Sjsg GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7055c349dbc7Sjsg (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7056c349dbc7Sjsg GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7057c349dbc7Sjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7058c349dbc7Sjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7059c349dbc7Sjsg
7060c349dbc7Sjsg /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7061c349dbc7Sjsg data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7062c349dbc7Sjsg GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7063c349dbc7Sjsg (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7064c349dbc7Sjsg GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7065c349dbc7Sjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7066c349dbc7Sjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7067c349dbc7Sjsg
7068c349dbc7Sjsg /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7069c349dbc7Sjsg data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7070c349dbc7Sjsg GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7071c349dbc7Sjsg (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7072c349dbc7Sjsg GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7073c349dbc7Sjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7074c349dbc7Sjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7075c349dbc7Sjsg
7076c349dbc7Sjsg /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7077c349dbc7Sjsg data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7078c349dbc7Sjsg GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7079c349dbc7Sjsg (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7080c349dbc7Sjsg GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7081ad8b1aafSjsg break;
7082ad8b1aafSjsg }
7083ad8b1aafSjsg
7084c349dbc7Sjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7085c349dbc7Sjsg WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7086c349dbc7Sjsg }
7087c349dbc7Sjsg
gfx_v10_0_disable_gpa_mode(struct amdgpu_device * adev)70885ca02815Sjsg static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
70895ca02815Sjsg {
70905ca02815Sjsg uint32_t data;
7091f005ef32Sjsg
70925ca02815Sjsg data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
70935ca02815Sjsg data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
70945ca02815Sjsg WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
70955ca02815Sjsg
70965ca02815Sjsg data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
70975ca02815Sjsg data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
70985ca02815Sjsg WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
70995ca02815Sjsg }
71005ca02815Sjsg
gfx_v10_0_hw_init(void * handle)7101c349dbc7Sjsg static int gfx_v10_0_hw_init(void *handle)
7102c349dbc7Sjsg {
7103c349dbc7Sjsg int r;
7104c349dbc7Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7105c349dbc7Sjsg
7106c349dbc7Sjsg if (!amdgpu_emu_mode)
7107c349dbc7Sjsg gfx_v10_0_init_golden_registers(adev);
7108c349dbc7Sjsg
7109c349dbc7Sjsg if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7110c349dbc7Sjsg /**
7111c349dbc7Sjsg * For gfx 10, rlc firmware loading relies on smu firmware is
7112c349dbc7Sjsg * loaded firstly, so in direct type, it has to load smc ucode
7113c349dbc7Sjsg * here before rlc.
7114c349dbc7Sjsg */
71155ca02815Sjsg if (!(adev->flags & AMD_IS_APU)) {
71165ca02815Sjsg r = amdgpu_pm_load_smu_firmware(adev, NULL);
7117c349dbc7Sjsg if (r)
7118c349dbc7Sjsg return r;
7119c349dbc7Sjsg }
71205ca02815Sjsg gfx_v10_0_disable_gpa_mode(adev);
7121ad8b1aafSjsg }
7122c349dbc7Sjsg
7123c349dbc7Sjsg /* if GRBM CAM not remapped, set up the remapping */
7124c349dbc7Sjsg if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7125c349dbc7Sjsg gfx_v10_0_setup_grbm_cam_remapping(adev);
7126c349dbc7Sjsg
7127c349dbc7Sjsg gfx_v10_0_constants_init(adev);
7128c349dbc7Sjsg
7129c349dbc7Sjsg r = gfx_v10_0_rlc_resume(adev);
7130c349dbc7Sjsg if (r)
7131c349dbc7Sjsg return r;
7132c349dbc7Sjsg
7133c349dbc7Sjsg /*
7134c349dbc7Sjsg * init golden registers and rlc resume may override some registers,
7135c349dbc7Sjsg * reconfig them here
7136c349dbc7Sjsg */
71371bb76ff1Sjsg if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10) ||
71381bb76ff1Sjsg adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) ||
71391bb76ff1Sjsg adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))
7140c349dbc7Sjsg gfx_v10_0_tcp_harvest(adev);
7141c349dbc7Sjsg
7142c349dbc7Sjsg r = gfx_v10_0_cp_resume(adev);
7143c349dbc7Sjsg if (r)
7144c349dbc7Sjsg return r;
7145c349dbc7Sjsg
71461bb76ff1Sjsg if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
7147ad8b1aafSjsg gfx_v10_3_program_pbb_mode(adev);
7148ad8b1aafSjsg
71491bb76ff1Sjsg if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
71505ca02815Sjsg gfx_v10_3_set_power_brake_sequence(adev);
71515ca02815Sjsg
7152c349dbc7Sjsg return r;
7153c349dbc7Sjsg }
7154c349dbc7Sjsg
gfx_v10_0_hw_fini(void * handle)7155c349dbc7Sjsg static int gfx_v10_0_hw_fini(void *handle)
7156c349dbc7Sjsg {
7157c349dbc7Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7158c349dbc7Sjsg
7159c349dbc7Sjsg amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7160c349dbc7Sjsg amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7161ad8b1aafSjsg
71625ca02815Sjsg if (!adev->no_hw_access) {
7163c349dbc7Sjsg if (amdgpu_async_gfx_ring) {
7164f005ef32Sjsg if (amdgpu_gfx_disable_kgq(adev, 0))
7165c349dbc7Sjsg DRM_ERROR("KGQ disable failed\n");
7166c349dbc7Sjsg }
7167f005ef32Sjsg
7168f005ef32Sjsg if (amdgpu_gfx_disable_kcq(adev, 0))
7169c349dbc7Sjsg DRM_ERROR("KCQ disable failed\n");
7170ad8b1aafSjsg }
7171ad8b1aafSjsg
7172c349dbc7Sjsg if (amdgpu_sriov_vf(adev)) {
7173c349dbc7Sjsg gfx_v10_0_cp_gfx_enable(adev, false);
7174f005ef32Sjsg /* Remove the steps of clearing KIQ position.
7175f005ef32Sjsg * It causes GFX hang when another Win guest is rendering.
7176f005ef32Sjsg */
7177c349dbc7Sjsg return 0;
7178c349dbc7Sjsg }
7179c349dbc7Sjsg gfx_v10_0_cp_enable(adev, false);
7180c349dbc7Sjsg gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7181c349dbc7Sjsg
7182c349dbc7Sjsg return 0;
7183c349dbc7Sjsg }
7184c349dbc7Sjsg
gfx_v10_0_suspend(void * handle)7185c349dbc7Sjsg static int gfx_v10_0_suspend(void *handle)
7186c349dbc7Sjsg {
7187c349dbc7Sjsg return gfx_v10_0_hw_fini(handle);
7188c349dbc7Sjsg }
7189c349dbc7Sjsg
gfx_v10_0_resume(void * handle)7190c349dbc7Sjsg static int gfx_v10_0_resume(void *handle)
7191c349dbc7Sjsg {
7192c349dbc7Sjsg return gfx_v10_0_hw_init(handle);
7193c349dbc7Sjsg }
7194c349dbc7Sjsg
gfx_v10_0_is_idle(void * handle)7195c349dbc7Sjsg static bool gfx_v10_0_is_idle(void *handle)
7196c349dbc7Sjsg {
7197c349dbc7Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7198c349dbc7Sjsg
7199c349dbc7Sjsg if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7200c349dbc7Sjsg GRBM_STATUS, GUI_ACTIVE))
7201c349dbc7Sjsg return false;
7202c349dbc7Sjsg else
7203c349dbc7Sjsg return true;
7204c349dbc7Sjsg }
7205c349dbc7Sjsg
gfx_v10_0_wait_for_idle(void * handle)7206c349dbc7Sjsg static int gfx_v10_0_wait_for_idle(void *handle)
7207c349dbc7Sjsg {
7208f005ef32Sjsg unsigned int i;
7209c349dbc7Sjsg u32 tmp;
7210c349dbc7Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7211c349dbc7Sjsg
7212c349dbc7Sjsg for (i = 0; i < adev->usec_timeout; i++) {
7213c349dbc7Sjsg /* read MC_STATUS */
7214c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7215c349dbc7Sjsg GRBM_STATUS__GUI_ACTIVE_MASK;
7216c349dbc7Sjsg
7217c349dbc7Sjsg if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7218c349dbc7Sjsg return 0;
7219c349dbc7Sjsg udelay(1);
7220c349dbc7Sjsg }
7221c349dbc7Sjsg return -ETIMEDOUT;
7222c349dbc7Sjsg }
7223c349dbc7Sjsg
gfx_v10_0_soft_reset(void * handle)7224c349dbc7Sjsg static int gfx_v10_0_soft_reset(void *handle)
7225c349dbc7Sjsg {
7226c349dbc7Sjsg u32 grbm_soft_reset = 0;
7227c349dbc7Sjsg u32 tmp;
7228c349dbc7Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7229c349dbc7Sjsg
7230c349dbc7Sjsg /* GRBM_STATUS */
7231c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7232c349dbc7Sjsg if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7233c349dbc7Sjsg GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7234c349dbc7Sjsg GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7235c349dbc7Sjsg GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7236ad8b1aafSjsg GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7237c349dbc7Sjsg grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7238c349dbc7Sjsg GRBM_SOFT_RESET, SOFT_RESET_CP,
7239c349dbc7Sjsg 1);
7240c349dbc7Sjsg grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7241c349dbc7Sjsg GRBM_SOFT_RESET, SOFT_RESET_GFX,
7242c349dbc7Sjsg 1);
7243c349dbc7Sjsg }
7244c349dbc7Sjsg
7245c349dbc7Sjsg if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7246c349dbc7Sjsg grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7247c349dbc7Sjsg GRBM_SOFT_RESET, SOFT_RESET_CP,
7248c349dbc7Sjsg 1);
7249c349dbc7Sjsg }
7250c349dbc7Sjsg
7251c349dbc7Sjsg /* GRBM_STATUS2 */
7252c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
72531bb76ff1Sjsg switch (adev->ip_versions[GC_HWIP][0]) {
72541bb76ff1Sjsg case IP_VERSION(10, 3, 0):
72551bb76ff1Sjsg case IP_VERSION(10, 3, 2):
72561bb76ff1Sjsg case IP_VERSION(10, 3, 1):
72571bb76ff1Sjsg case IP_VERSION(10, 3, 4):
72581bb76ff1Sjsg case IP_VERSION(10, 3, 5):
72591bb76ff1Sjsg case IP_VERSION(10, 3, 6):
72601bb76ff1Sjsg case IP_VERSION(10, 3, 3):
7261ad8b1aafSjsg if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7262ad8b1aafSjsg grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7263ad8b1aafSjsg GRBM_SOFT_RESET,
7264ad8b1aafSjsg SOFT_RESET_RLC,
7265ad8b1aafSjsg 1);
7266ad8b1aafSjsg break;
7267ad8b1aafSjsg default:
7268c349dbc7Sjsg if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7269c349dbc7Sjsg grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7270ad8b1aafSjsg GRBM_SOFT_RESET,
7271ad8b1aafSjsg SOFT_RESET_RLC,
7272c349dbc7Sjsg 1);
7273ad8b1aafSjsg break;
7274ad8b1aafSjsg }
7275c349dbc7Sjsg
7276c349dbc7Sjsg if (grbm_soft_reset) {
7277c349dbc7Sjsg /* stop the rlc */
7278c349dbc7Sjsg gfx_v10_0_rlc_stop(adev);
7279c349dbc7Sjsg
7280c349dbc7Sjsg /* Disable GFX parsing/prefetching */
7281c349dbc7Sjsg gfx_v10_0_cp_gfx_enable(adev, false);
7282c349dbc7Sjsg
7283c349dbc7Sjsg /* Disable MEC parsing/prefetching */
7284c349dbc7Sjsg gfx_v10_0_cp_compute_enable(adev, false);
7285c349dbc7Sjsg
7286c349dbc7Sjsg if (grbm_soft_reset) {
7287c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7288c349dbc7Sjsg tmp |= grbm_soft_reset;
7289c349dbc7Sjsg dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7290c349dbc7Sjsg WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7291c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7292c349dbc7Sjsg
7293c349dbc7Sjsg udelay(50);
7294c349dbc7Sjsg
7295c349dbc7Sjsg tmp &= ~grbm_soft_reset;
7296c349dbc7Sjsg WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7297c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7298c349dbc7Sjsg }
7299c349dbc7Sjsg
7300c349dbc7Sjsg /* Wait a little for things to settle down */
7301c349dbc7Sjsg udelay(50);
7302c349dbc7Sjsg }
7303c349dbc7Sjsg return 0;
7304c349dbc7Sjsg }
7305c349dbc7Sjsg
gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device * adev)7306c349dbc7Sjsg static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7307c349dbc7Sjsg {
73085ca02815Sjsg uint64_t clock, clock_lo, clock_hi, hi_check;
7309c349dbc7Sjsg
73101bb76ff1Sjsg switch (adev->ip_versions[GC_HWIP][0]) {
73111bb76ff1Sjsg case IP_VERSION(10, 3, 1):
73121bb76ff1Sjsg case IP_VERSION(10, 3, 3):
73131bb76ff1Sjsg case IP_VERSION(10, 3, 7):
73145ca02815Sjsg preempt_disable();
73155ca02815Sjsg clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
73165ca02815Sjsg clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
73175ca02815Sjsg hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
73185ca02815Sjsg /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
73195ca02815Sjsg * roughly every 42 seconds.
73205ca02815Sjsg */
73215ca02815Sjsg if (hi_check != clock_hi) {
73225ca02815Sjsg clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
73235ca02815Sjsg clock_hi = hi_check;
73245ca02815Sjsg }
73255ca02815Sjsg preempt_enable();
73265ca02815Sjsg clock = clock_lo | (clock_hi << 32ULL);
73275ca02815Sjsg break;
73281bb76ff1Sjsg case IP_VERSION(10, 3, 6):
73291bb76ff1Sjsg preempt_disable();
73301bb76ff1Sjsg clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
73311bb76ff1Sjsg clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
73321bb76ff1Sjsg hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
73331bb76ff1Sjsg /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
73341bb76ff1Sjsg * roughly every 42 seconds.
73351bb76ff1Sjsg */
73361bb76ff1Sjsg if (hi_check != clock_hi) {
73371bb76ff1Sjsg clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
73381bb76ff1Sjsg clock_hi = hi_check;
73391bb76ff1Sjsg }
73401bb76ff1Sjsg preempt_enable();
73411bb76ff1Sjsg clock = clock_lo | (clock_hi << 32ULL);
73421bb76ff1Sjsg break;
73435ca02815Sjsg default:
73445ca02815Sjsg preempt_disable();
73455ca02815Sjsg clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
73465ca02815Sjsg clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
73475ca02815Sjsg hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
73485ca02815Sjsg /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
73495ca02815Sjsg * roughly every 42 seconds.
73505ca02815Sjsg */
73515ca02815Sjsg if (hi_check != clock_hi) {
73525ca02815Sjsg clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
73535ca02815Sjsg clock_hi = hi_check;
73545ca02815Sjsg }
73555ca02815Sjsg preempt_enable();
73565ca02815Sjsg clock = clock_lo | (clock_hi << 32ULL);
73575ca02815Sjsg break;
73585ca02815Sjsg }
7359c349dbc7Sjsg return clock;
7360c349dbc7Sjsg }
7361c349dbc7Sjsg
gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring * ring,uint32_t vmid,uint32_t gds_base,uint32_t gds_size,uint32_t gws_base,uint32_t gws_size,uint32_t oa_base,uint32_t oa_size)7362c349dbc7Sjsg static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7363c349dbc7Sjsg uint32_t vmid,
7364c349dbc7Sjsg uint32_t gds_base, uint32_t gds_size,
7365c349dbc7Sjsg uint32_t gws_base, uint32_t gws_size,
7366c349dbc7Sjsg uint32_t oa_base, uint32_t oa_size)
7367c349dbc7Sjsg {
7368c349dbc7Sjsg struct amdgpu_device *adev = ring->adev;
7369c349dbc7Sjsg
7370c349dbc7Sjsg /* GDS Base */
7371c349dbc7Sjsg gfx_v10_0_write_data_to_reg(ring, 0, false,
7372c349dbc7Sjsg SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7373c349dbc7Sjsg gds_base);
7374c349dbc7Sjsg
7375c349dbc7Sjsg /* GDS Size */
7376c349dbc7Sjsg gfx_v10_0_write_data_to_reg(ring, 0, false,
7377c349dbc7Sjsg SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7378c349dbc7Sjsg gds_size);
7379c349dbc7Sjsg
7380c349dbc7Sjsg /* GWS */
7381c349dbc7Sjsg gfx_v10_0_write_data_to_reg(ring, 0, false,
7382c349dbc7Sjsg SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7383c349dbc7Sjsg gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7384c349dbc7Sjsg
7385c349dbc7Sjsg /* OA */
7386c349dbc7Sjsg gfx_v10_0_write_data_to_reg(ring, 0, false,
7387c349dbc7Sjsg SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7388c349dbc7Sjsg (1 << (oa_size + oa_base)) - (1 << oa_base));
7389c349dbc7Sjsg }
7390c349dbc7Sjsg
gfx_v10_0_early_init(void * handle)7391c349dbc7Sjsg static int gfx_v10_0_early_init(void *handle)
7392c349dbc7Sjsg {
7393c349dbc7Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7394c349dbc7Sjsg
7395f005ef32Sjsg adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
7396f005ef32Sjsg
73971bb76ff1Sjsg switch (adev->ip_versions[GC_HWIP][0]) {
73981bb76ff1Sjsg case IP_VERSION(10, 1, 10):
73991bb76ff1Sjsg case IP_VERSION(10, 1, 1):
74001bb76ff1Sjsg case IP_VERSION(10, 1, 2):
74011bb76ff1Sjsg case IP_VERSION(10, 1, 3):
74021bb76ff1Sjsg case IP_VERSION(10, 1, 4):
7403c349dbc7Sjsg adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7404ad8b1aafSjsg break;
74051bb76ff1Sjsg case IP_VERSION(10, 3, 0):
74061bb76ff1Sjsg case IP_VERSION(10, 3, 2):
74071bb76ff1Sjsg case IP_VERSION(10, 3, 1):
74081bb76ff1Sjsg case IP_VERSION(10, 3, 4):
74091bb76ff1Sjsg case IP_VERSION(10, 3, 5):
74101bb76ff1Sjsg case IP_VERSION(10, 3, 6):
74111bb76ff1Sjsg case IP_VERSION(10, 3, 3):
74121bb76ff1Sjsg case IP_VERSION(10, 3, 7):
7413ad8b1aafSjsg adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7414ad8b1aafSjsg break;
7415ad8b1aafSjsg default:
7416ad8b1aafSjsg break;
7417ad8b1aafSjsg }
7418c349dbc7Sjsg
74195ca02815Sjsg adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
74205ca02815Sjsg AMDGPU_MAX_COMPUTE_RINGS);
7421c349dbc7Sjsg
7422c349dbc7Sjsg gfx_v10_0_set_kiq_pm4_funcs(adev);
7423c349dbc7Sjsg gfx_v10_0_set_ring_funcs(adev);
7424c349dbc7Sjsg gfx_v10_0_set_irq_funcs(adev);
7425c349dbc7Sjsg gfx_v10_0_set_gds_init(adev);
7426c349dbc7Sjsg gfx_v10_0_set_rlc_funcs(adev);
74271bb76ff1Sjsg gfx_v10_0_set_mqd_funcs(adev);
74281bb76ff1Sjsg
74291bb76ff1Sjsg /* init rlcg reg access ctrl */
74301bb76ff1Sjsg gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
7431c349dbc7Sjsg
7432f005ef32Sjsg return gfx_v10_0_init_microcode(adev);
7433c349dbc7Sjsg }
7434c349dbc7Sjsg
gfx_v10_0_late_init(void * handle)7435c349dbc7Sjsg static int gfx_v10_0_late_init(void *handle)
7436c349dbc7Sjsg {
7437c349dbc7Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7438c349dbc7Sjsg int r;
7439c349dbc7Sjsg
7440c349dbc7Sjsg r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7441c349dbc7Sjsg if (r)
7442c349dbc7Sjsg return r;
7443c349dbc7Sjsg
7444c349dbc7Sjsg r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7445c349dbc7Sjsg if (r)
7446c349dbc7Sjsg return r;
7447c349dbc7Sjsg
7448c349dbc7Sjsg return 0;
7449c349dbc7Sjsg }
7450c349dbc7Sjsg
gfx_v10_0_is_rlc_enabled(struct amdgpu_device * adev)7451c349dbc7Sjsg static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7452c349dbc7Sjsg {
7453c349dbc7Sjsg uint32_t rlc_cntl;
7454c349dbc7Sjsg
7455c349dbc7Sjsg /* if RLC is not enabled, do nothing */
7456c349dbc7Sjsg rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7457c349dbc7Sjsg return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7458c349dbc7Sjsg }
7459c349dbc7Sjsg
gfx_v10_0_set_safe_mode(struct amdgpu_device * adev,int xcc_id)7460f005ef32Sjsg static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
7461c349dbc7Sjsg {
7462c349dbc7Sjsg uint32_t data;
7463f005ef32Sjsg unsigned int i;
7464c349dbc7Sjsg
7465c349dbc7Sjsg data = RLC_SAFE_MODE__CMD_MASK;
7466c349dbc7Sjsg data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7467ad8b1aafSjsg
74681bb76ff1Sjsg switch (adev->ip_versions[GC_HWIP][0]) {
74691bb76ff1Sjsg case IP_VERSION(10, 3, 0):
74701bb76ff1Sjsg case IP_VERSION(10, 3, 2):
74711bb76ff1Sjsg case IP_VERSION(10, 3, 1):
74721bb76ff1Sjsg case IP_VERSION(10, 3, 4):
74731bb76ff1Sjsg case IP_VERSION(10, 3, 5):
74741bb76ff1Sjsg case IP_VERSION(10, 3, 6):
74751bb76ff1Sjsg case IP_VERSION(10, 3, 3):
74761bb76ff1Sjsg case IP_VERSION(10, 3, 7):
7477ad8b1aafSjsg WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7478ad8b1aafSjsg
7479ad8b1aafSjsg /* wait for RLC_SAFE_MODE */
7480ad8b1aafSjsg for (i = 0; i < adev->usec_timeout; i++) {
7481ad8b1aafSjsg if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7482ad8b1aafSjsg RLC_SAFE_MODE, CMD))
7483ad8b1aafSjsg break;
7484ad8b1aafSjsg udelay(1);
7485ad8b1aafSjsg }
7486ad8b1aafSjsg break;
7487ad8b1aafSjsg default:
7488c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7489c349dbc7Sjsg
7490c349dbc7Sjsg /* wait for RLC_SAFE_MODE */
7491c349dbc7Sjsg for (i = 0; i < adev->usec_timeout; i++) {
7492ad8b1aafSjsg if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7493ad8b1aafSjsg RLC_SAFE_MODE, CMD))
7494c349dbc7Sjsg break;
7495c349dbc7Sjsg udelay(1);
7496c349dbc7Sjsg }
7497ad8b1aafSjsg break;
7498ad8b1aafSjsg }
7499c349dbc7Sjsg }
7500c349dbc7Sjsg
gfx_v10_0_unset_safe_mode(struct amdgpu_device * adev,int xcc_id)7501f005ef32Sjsg static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
7502c349dbc7Sjsg {
7503c349dbc7Sjsg uint32_t data;
7504c349dbc7Sjsg
7505c349dbc7Sjsg data = RLC_SAFE_MODE__CMD_MASK;
75061bb76ff1Sjsg switch (adev->ip_versions[GC_HWIP][0]) {
75071bb76ff1Sjsg case IP_VERSION(10, 3, 0):
75081bb76ff1Sjsg case IP_VERSION(10, 3, 2):
75091bb76ff1Sjsg case IP_VERSION(10, 3, 1):
75101bb76ff1Sjsg case IP_VERSION(10, 3, 4):
75111bb76ff1Sjsg case IP_VERSION(10, 3, 5):
75121bb76ff1Sjsg case IP_VERSION(10, 3, 6):
75131bb76ff1Sjsg case IP_VERSION(10, 3, 3):
75141bb76ff1Sjsg case IP_VERSION(10, 3, 7):
7515ad8b1aafSjsg WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7516ad8b1aafSjsg break;
7517ad8b1aafSjsg default:
7518c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7519ad8b1aafSjsg break;
7520ad8b1aafSjsg }
7521c349dbc7Sjsg }
7522c349dbc7Sjsg
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)7523c349dbc7Sjsg static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7524c349dbc7Sjsg bool enable)
7525c349dbc7Sjsg {
7526c349dbc7Sjsg uint32_t data, def;
7527c349dbc7Sjsg
75285ca02815Sjsg if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
75295ca02815Sjsg return;
75305ca02815Sjsg
7531c349dbc7Sjsg /* It is disabled by HW by default */
7532c349dbc7Sjsg if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7533c349dbc7Sjsg /* 0 - Disable some blocks' MGCG */
7534c349dbc7Sjsg WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7535c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7536c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7537c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7538c349dbc7Sjsg
7539c349dbc7Sjsg /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7540c349dbc7Sjsg def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7541c349dbc7Sjsg data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
75425ca02815Sjsg RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7543c349dbc7Sjsg RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7544ad8b1aafSjsg RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
75455ca02815Sjsg RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7546ad8b1aafSjsg RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7547c349dbc7Sjsg
7548c349dbc7Sjsg if (def != data)
7549c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7550c349dbc7Sjsg
7551c349dbc7Sjsg /* MGLS is a global flag to control all MGLS in GFX */
7552c349dbc7Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7553c349dbc7Sjsg /* 2 - RLC memory Light sleep */
7554c349dbc7Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7555c349dbc7Sjsg def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7556c349dbc7Sjsg data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7557c349dbc7Sjsg if (def != data)
7558c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7559c349dbc7Sjsg }
7560c349dbc7Sjsg /* 3 - CP memory Light sleep */
7561c349dbc7Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7562c349dbc7Sjsg def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7563c349dbc7Sjsg data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7564c349dbc7Sjsg if (def != data)
7565c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7566c349dbc7Sjsg }
7567c349dbc7Sjsg }
75685ca02815Sjsg } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7569c349dbc7Sjsg /* 1 - MGCG_OVERRIDE */
7570c349dbc7Sjsg def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7571c349dbc7Sjsg data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7572c349dbc7Sjsg RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7573c349dbc7Sjsg RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
75745ca02815Sjsg RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
75755ca02815Sjsg RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
75765ca02815Sjsg RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7577c349dbc7Sjsg if (def != data)
7578c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7579c349dbc7Sjsg
7580c349dbc7Sjsg /* 2 - disable MGLS in CP */
7581c349dbc7Sjsg data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7582c349dbc7Sjsg if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7583c349dbc7Sjsg data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7584c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7585c349dbc7Sjsg }
7586c349dbc7Sjsg
7587c349dbc7Sjsg /* 3 - disable MGLS in RLC */
7588c349dbc7Sjsg data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7589c349dbc7Sjsg if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7590c349dbc7Sjsg data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7591c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7592c349dbc7Sjsg }
7593c349dbc7Sjsg
7594c349dbc7Sjsg }
7595c349dbc7Sjsg }
7596c349dbc7Sjsg
gfx_v10_0_update_3d_clock_gating(struct amdgpu_device * adev,bool enable)7597c349dbc7Sjsg static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7598c349dbc7Sjsg bool enable)
7599c349dbc7Sjsg {
7600c349dbc7Sjsg uint32_t data, def;
7601c349dbc7Sjsg
76025ca02815Sjsg if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
76035ca02815Sjsg return;
76045ca02815Sjsg
7605c349dbc7Sjsg /* Enable 3D CGCG/CGLS */
76065ca02815Sjsg if (enable) {
7607c349dbc7Sjsg /* write cmd to clear cgcg/cgls ov */
7608c349dbc7Sjsg def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
76095ca02815Sjsg
7610c349dbc7Sjsg /* unset CGCG override */
76115ca02815Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7612c349dbc7Sjsg data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
76135ca02815Sjsg
7614c349dbc7Sjsg /* update CGCG and CGLS override bits */
7615c349dbc7Sjsg if (def != data)
7616c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
76175ca02815Sjsg
7618c349dbc7Sjsg /* enable 3Dcgcg FSM(0x0000363f) */
7619c349dbc7Sjsg def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
76205ca02815Sjsg data = 0;
76215ca02815Sjsg
76225ca02815Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7623c349dbc7Sjsg data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7624c349dbc7Sjsg RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
76255ca02815Sjsg
7626c349dbc7Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7627c349dbc7Sjsg data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7628c349dbc7Sjsg RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
76295ca02815Sjsg
7630c349dbc7Sjsg if (def != data)
7631c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7632c349dbc7Sjsg
7633c349dbc7Sjsg /* set IDLE_POLL_COUNT(0x00900100) */
7634c349dbc7Sjsg def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7635c349dbc7Sjsg data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7636c349dbc7Sjsg (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7637c349dbc7Sjsg if (def != data)
7638c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7639c349dbc7Sjsg } else {
7640c349dbc7Sjsg /* Disable CGCG/CGLS */
7641c349dbc7Sjsg def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
76425ca02815Sjsg
7643c349dbc7Sjsg /* disable cgcg, cgls should be disabled */
76445ca02815Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
76455ca02815Sjsg data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
76465ca02815Sjsg
76475ca02815Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
76485ca02815Sjsg data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
76495ca02815Sjsg
7650c349dbc7Sjsg /* disable cgcg and cgls in FSM */
7651c349dbc7Sjsg if (def != data)
7652c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7653c349dbc7Sjsg }
7654c349dbc7Sjsg }
7655c349dbc7Sjsg
gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device * adev,bool enable)7656c349dbc7Sjsg static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7657c349dbc7Sjsg bool enable)
7658c349dbc7Sjsg {
7659c349dbc7Sjsg uint32_t def, data;
7660c349dbc7Sjsg
76615ca02815Sjsg if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
76625ca02815Sjsg return;
76635ca02815Sjsg
76645ca02815Sjsg if (enable) {
7665c349dbc7Sjsg def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
76665ca02815Sjsg
7667c349dbc7Sjsg /* unset CGCG override */
76685ca02815Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7669c349dbc7Sjsg data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
76705ca02815Sjsg
7671c349dbc7Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7672c349dbc7Sjsg data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
76735ca02815Sjsg
7674c349dbc7Sjsg /* update CGCG and CGLS override bits */
7675c349dbc7Sjsg if (def != data)
7676c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7677c349dbc7Sjsg
7678c349dbc7Sjsg /* enable cgcg FSM(0x0000363F) */
7679c349dbc7Sjsg def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
76805ca02815Sjsg data = 0;
76815ca02815Sjsg
76825ca02815Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7683c349dbc7Sjsg data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7684c349dbc7Sjsg RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
76855ca02815Sjsg
7686c349dbc7Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7687c349dbc7Sjsg data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7688c349dbc7Sjsg RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
76895ca02815Sjsg
7690c349dbc7Sjsg if (def != data)
7691c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7692c349dbc7Sjsg
7693c349dbc7Sjsg /* set IDLE_POLL_COUNT(0x00900100) */
7694c349dbc7Sjsg def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7695c349dbc7Sjsg data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7696c349dbc7Sjsg (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7697c349dbc7Sjsg if (def != data)
7698c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7699c349dbc7Sjsg } else {
7700c349dbc7Sjsg def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
77015ca02815Sjsg
7702c349dbc7Sjsg /* reset CGCG/CGLS bits */
77035ca02815Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
77045ca02815Sjsg data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
77055ca02815Sjsg
77065ca02815Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
77075ca02815Sjsg data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
77085ca02815Sjsg
7709c349dbc7Sjsg /* disable cgcg and cgls in FSM */
7710c349dbc7Sjsg if (def != data)
7711c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7712c349dbc7Sjsg }
7713c349dbc7Sjsg }
7714c349dbc7Sjsg
gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device * adev,bool enable)77155ca02815Sjsg static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
77165ca02815Sjsg bool enable)
77175ca02815Sjsg {
77185ca02815Sjsg uint32_t def, data;
77195ca02815Sjsg
77205ca02815Sjsg if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
77215ca02815Sjsg return;
77225ca02815Sjsg
77235ca02815Sjsg if (enable) {
77245ca02815Sjsg def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
77255ca02815Sjsg /* unset FGCG override */
77265ca02815Sjsg data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
77275ca02815Sjsg /* update FGCG override bits */
77285ca02815Sjsg if (def != data)
77295ca02815Sjsg WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
77305ca02815Sjsg
77315ca02815Sjsg def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
77325ca02815Sjsg /* unset RLC SRAM CLK GATER override */
77335ca02815Sjsg data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
77345ca02815Sjsg /* update RLC SRAM CLK GATER override bits */
77355ca02815Sjsg if (def != data)
77365ca02815Sjsg WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
77375ca02815Sjsg } else {
77385ca02815Sjsg def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
77395ca02815Sjsg /* reset FGCG bits */
77405ca02815Sjsg data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
77415ca02815Sjsg /* disable FGCG*/
77425ca02815Sjsg if (def != data)
77435ca02815Sjsg WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
77445ca02815Sjsg
77455ca02815Sjsg def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
77465ca02815Sjsg /* reset RLC SRAM CLK GATER bits */
77475ca02815Sjsg data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
77485ca02815Sjsg /* disable RLC SRAM CLK*/
77495ca02815Sjsg if (def != data)
77505ca02815Sjsg WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
77515ca02815Sjsg }
77525ca02815Sjsg }
77535ca02815Sjsg
gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device * adev)77545ca02815Sjsg static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
77555ca02815Sjsg {
77565ca02815Sjsg uint32_t reg_data = 0;
77575ca02815Sjsg uint32_t reg_idx = 0;
77585ca02815Sjsg uint32_t i;
77595ca02815Sjsg
77605ca02815Sjsg const uint32_t tcp_ctrl_regs[] = {
77615ca02815Sjsg mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
77625ca02815Sjsg mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
77635ca02815Sjsg mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
77645ca02815Sjsg mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
77655ca02815Sjsg mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
77665ca02815Sjsg mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
77675ca02815Sjsg mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
77685ca02815Sjsg mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
77695ca02815Sjsg mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
77705ca02815Sjsg mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
77715ca02815Sjsg mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
77725ca02815Sjsg mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
77735ca02815Sjsg mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
77745ca02815Sjsg mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
77755ca02815Sjsg mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
77765ca02815Sjsg mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
77775ca02815Sjsg mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
77785ca02815Sjsg mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
77795ca02815Sjsg mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
77805ca02815Sjsg mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
77815ca02815Sjsg mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
77825ca02815Sjsg mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
77835ca02815Sjsg mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
77845ca02815Sjsg mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
77855ca02815Sjsg };
77865ca02815Sjsg
77875ca02815Sjsg const uint32_t tcp_ctrl_regs_nv12[] = {
77885ca02815Sjsg mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
77895ca02815Sjsg mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
77905ca02815Sjsg mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
77915ca02815Sjsg mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
77925ca02815Sjsg mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
77935ca02815Sjsg mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
77945ca02815Sjsg mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
77955ca02815Sjsg mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
77965ca02815Sjsg mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
77975ca02815Sjsg mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
77985ca02815Sjsg mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
77995ca02815Sjsg mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
78005ca02815Sjsg mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
78015ca02815Sjsg mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
78025ca02815Sjsg mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
78035ca02815Sjsg mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
78045ca02815Sjsg mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
78055ca02815Sjsg mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
78065ca02815Sjsg mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
78075ca02815Sjsg mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
78085ca02815Sjsg };
78095ca02815Sjsg
78105ca02815Sjsg const uint32_t sm_ctlr_regs[] = {
78115ca02815Sjsg mmCGTS_SA0_QUAD0_SM_CTRL_REG,
78125ca02815Sjsg mmCGTS_SA0_QUAD1_SM_CTRL_REG,
78135ca02815Sjsg mmCGTS_SA1_QUAD0_SM_CTRL_REG,
78145ca02815Sjsg mmCGTS_SA1_QUAD1_SM_CTRL_REG
78155ca02815Sjsg };
78165ca02815Sjsg
78171bb76ff1Sjsg if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
78185ca02815Sjsg for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
78195ca02815Sjsg reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
78205ca02815Sjsg tcp_ctrl_regs_nv12[i];
78215ca02815Sjsg reg_data = RREG32(reg_idx);
78225ca02815Sjsg reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
78235ca02815Sjsg WREG32(reg_idx, reg_data);
78245ca02815Sjsg }
78255ca02815Sjsg } else {
78265ca02815Sjsg for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
78275ca02815Sjsg reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
78285ca02815Sjsg tcp_ctrl_regs[i];
78295ca02815Sjsg reg_data = RREG32(reg_idx);
78305ca02815Sjsg reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
78315ca02815Sjsg WREG32(reg_idx, reg_data);
78325ca02815Sjsg }
78335ca02815Sjsg }
78345ca02815Sjsg
78355ca02815Sjsg for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
78365ca02815Sjsg reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
78375ca02815Sjsg sm_ctlr_regs[i];
78385ca02815Sjsg reg_data = RREG32(reg_idx);
78395ca02815Sjsg reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
78405ca02815Sjsg reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
78415ca02815Sjsg WREG32(reg_idx, reg_data);
78425ca02815Sjsg }
78435ca02815Sjsg }
78445ca02815Sjsg
gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device * adev,bool enable)7845c349dbc7Sjsg static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7846c349dbc7Sjsg bool enable)
7847c349dbc7Sjsg {
7848f005ef32Sjsg amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
7849c349dbc7Sjsg
7850c349dbc7Sjsg if (enable) {
78515ca02815Sjsg /* enable FGCG firstly*/
78525ca02815Sjsg gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7853c349dbc7Sjsg /* CGCG/CGLS should be enabled after MGCG/MGLS
7854c349dbc7Sjsg * === MGCG + MGLS ===
7855c349dbc7Sjsg */
7856c349dbc7Sjsg gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7857c349dbc7Sjsg /* === CGCG /CGLS for GFX 3D Only === */
7858c349dbc7Sjsg gfx_v10_0_update_3d_clock_gating(adev, enable);
7859c349dbc7Sjsg /* === CGCG + CGLS === */
7860c349dbc7Sjsg gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
78615ca02815Sjsg
78621bb76ff1Sjsg if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10)) ||
78631bb76ff1Sjsg (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1)) ||
78641bb76ff1Sjsg (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)))
78655ca02815Sjsg gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
7866c349dbc7Sjsg } else {
7867c349dbc7Sjsg /* CGCG/CGLS should be disabled before MGCG/MGLS
7868c349dbc7Sjsg * === CGCG + CGLS ===
7869c349dbc7Sjsg */
7870c349dbc7Sjsg gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7871c349dbc7Sjsg /* === CGCG /CGLS for GFX 3D Only === */
7872c349dbc7Sjsg gfx_v10_0_update_3d_clock_gating(adev, enable);
7873c349dbc7Sjsg /* === MGCG + MGLS === */
7874c349dbc7Sjsg gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
78755ca02815Sjsg /* disable fgcg at last*/
78765ca02815Sjsg gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7877c349dbc7Sjsg }
7878c349dbc7Sjsg
7879c349dbc7Sjsg if (adev->cg_flags &
7880c349dbc7Sjsg (AMD_CG_SUPPORT_GFX_MGCG |
7881c349dbc7Sjsg AMD_CG_SUPPORT_GFX_CGLS |
7882c349dbc7Sjsg AMD_CG_SUPPORT_GFX_CGCG |
7883c349dbc7Sjsg AMD_CG_SUPPORT_GFX_3D_CGCG |
7884c349dbc7Sjsg AMD_CG_SUPPORT_GFX_3D_CGLS))
7885c349dbc7Sjsg gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7886c349dbc7Sjsg
7887f005ef32Sjsg amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
7888c349dbc7Sjsg
7889c349dbc7Sjsg return 0;
7890c349dbc7Sjsg }
7891c349dbc7Sjsg
gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device * adev,unsigned int vmid)7892f005ef32Sjsg static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
7893f005ef32Sjsg unsigned int vmid)
7894c349dbc7Sjsg {
7895ad8b1aafSjsg u32 reg, data;
78961bb76ff1Sjsg
78975ca02815Sjsg /* not for *_SOC15 */
7898ad8b1aafSjsg reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7899ad8b1aafSjsg if (amdgpu_sriov_is_pp_one_vf(adev))
7900ad8b1aafSjsg data = RREG32_NO_KIQ(reg);
7901ad8b1aafSjsg else
79025ca02815Sjsg data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
7903c349dbc7Sjsg
7904c349dbc7Sjsg data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7905c349dbc7Sjsg data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7906c349dbc7Sjsg
7907ad8b1aafSjsg if (amdgpu_sriov_is_pp_one_vf(adev))
7908ad8b1aafSjsg WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7909ad8b1aafSjsg else
7910c349dbc7Sjsg WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7911f005ef32Sjsg }
7912f005ef32Sjsg
gfx_v10_0_update_spm_vmid(struct amdgpu_device * adev,unsigned int vmid)7913f005ef32Sjsg static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned int vmid)
7914f005ef32Sjsg {
7915f005ef32Sjsg amdgpu_gfx_off_ctrl(adev, false);
7916f005ef32Sjsg
7917f005ef32Sjsg gfx_v10_0_update_spm_vmid_internal(adev, vmid);
79181bb76ff1Sjsg
79191bb76ff1Sjsg amdgpu_gfx_off_ctrl(adev, true);
7920c349dbc7Sjsg }
7921c349dbc7Sjsg
gfx_v10_0_check_rlcg_range(struct amdgpu_device * adev,uint32_t offset,struct soc15_reg_rlcg * entries,int arr_size)7922c349dbc7Sjsg static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7923c349dbc7Sjsg uint32_t offset,
7924c349dbc7Sjsg struct soc15_reg_rlcg *entries, int arr_size)
7925c349dbc7Sjsg {
7926c349dbc7Sjsg int i;
7927c349dbc7Sjsg uint32_t reg;
7928c349dbc7Sjsg
7929c349dbc7Sjsg if (!entries)
7930c349dbc7Sjsg return false;
7931c349dbc7Sjsg
7932c349dbc7Sjsg for (i = 0; i < arr_size; i++) {
7933c349dbc7Sjsg const struct soc15_reg_rlcg *entry;
7934c349dbc7Sjsg
7935c349dbc7Sjsg entry = &entries[i];
7936c349dbc7Sjsg reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7937c349dbc7Sjsg if (offset == reg)
7938c349dbc7Sjsg return true;
7939c349dbc7Sjsg }
7940c349dbc7Sjsg
7941c349dbc7Sjsg return false;
7942c349dbc7Sjsg }
7943c349dbc7Sjsg
gfx_v10_0_is_rlcg_access_range(struct amdgpu_device * adev,u32 offset)7944c349dbc7Sjsg static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7945c349dbc7Sjsg {
7946c349dbc7Sjsg return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7947c349dbc7Sjsg }
7948c349dbc7Sjsg
gfx_v10_cntl_power_gating(struct amdgpu_device * adev,bool enable)79495ca02815Sjsg static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
79505ca02815Sjsg {
79515ca02815Sjsg u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
79525ca02815Sjsg
79535ca02815Sjsg if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
79545ca02815Sjsg data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
79555ca02815Sjsg else
79565ca02815Sjsg data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
79575ca02815Sjsg
79585ca02815Sjsg WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
79595ca02815Sjsg
79605ca02815Sjsg /*
79615ca02815Sjsg * CGPG enablement required and the register to program the hysteresis value
79625ca02815Sjsg * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
79635ca02815Sjsg * in refclk count. Note that RLC FW is modified to take 16 bits from
79645ca02815Sjsg * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
79655ca02815Sjsg *
79665ca02815Sjsg * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
79675ca02815Sjsg * of CGPG enablement starting point.
79685ca02815Sjsg * Power/performance team will optimize it and might give a new value later.
79695ca02815Sjsg */
79705ca02815Sjsg if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
79711bb76ff1Sjsg switch (adev->ip_versions[GC_HWIP][0]) {
79721bb76ff1Sjsg case IP_VERSION(10, 3, 1):
79731bb76ff1Sjsg case IP_VERSION(10, 3, 3):
79741bb76ff1Sjsg case IP_VERSION(10, 3, 6):
79751bb76ff1Sjsg case IP_VERSION(10, 3, 7):
79765ca02815Sjsg data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
79775ca02815Sjsg WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
79785ca02815Sjsg break;
79795ca02815Sjsg default:
79805ca02815Sjsg break;
79815ca02815Sjsg }
79825ca02815Sjsg }
79835ca02815Sjsg }
79845ca02815Sjsg
gfx_v10_cntl_pg(struct amdgpu_device * adev,bool enable)79855ca02815Sjsg static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
79865ca02815Sjsg {
7987f005ef32Sjsg amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
79885ca02815Sjsg
79895ca02815Sjsg gfx_v10_cntl_power_gating(adev, enable);
79905ca02815Sjsg
7991f005ef32Sjsg amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
79925ca02815Sjsg }
79935ca02815Sjsg
7994c349dbc7Sjsg static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7995c349dbc7Sjsg .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7996c349dbc7Sjsg .set_safe_mode = gfx_v10_0_set_safe_mode,
7997c349dbc7Sjsg .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7998c349dbc7Sjsg .init = gfx_v10_0_rlc_init,
7999c349dbc7Sjsg .get_csb_size = gfx_v10_0_get_csb_size,
8000c349dbc7Sjsg .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8001c349dbc7Sjsg .resume = gfx_v10_0_rlc_resume,
8002c349dbc7Sjsg .stop = gfx_v10_0_rlc_stop,
8003c349dbc7Sjsg .reset = gfx_v10_0_rlc_reset,
8004c349dbc7Sjsg .start = gfx_v10_0_rlc_start,
8005c349dbc7Sjsg .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8006ad8b1aafSjsg };
8007ad8b1aafSjsg
8008ad8b1aafSjsg static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8009ad8b1aafSjsg .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8010ad8b1aafSjsg .set_safe_mode = gfx_v10_0_set_safe_mode,
8011ad8b1aafSjsg .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8012ad8b1aafSjsg .init = gfx_v10_0_rlc_init,
8013ad8b1aafSjsg .get_csb_size = gfx_v10_0_get_csb_size,
8014ad8b1aafSjsg .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8015ad8b1aafSjsg .resume = gfx_v10_0_rlc_resume,
8016ad8b1aafSjsg .stop = gfx_v10_0_rlc_stop,
8017ad8b1aafSjsg .reset = gfx_v10_0_rlc_reset,
8018ad8b1aafSjsg .start = gfx_v10_0_rlc_start,
8019ad8b1aafSjsg .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8020c349dbc7Sjsg .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8021c349dbc7Sjsg };
8022c349dbc7Sjsg
gfx_v10_0_set_powergating_state(void * handle,enum amd_powergating_state state)8023c349dbc7Sjsg static int gfx_v10_0_set_powergating_state(void *handle,
8024c349dbc7Sjsg enum amd_powergating_state state)
8025c349dbc7Sjsg {
8026c349dbc7Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8027c349dbc7Sjsg bool enable = (state == AMD_PG_STATE_GATE);
8028ad8b1aafSjsg
8029ad8b1aafSjsg if (amdgpu_sriov_vf(adev))
8030ad8b1aafSjsg return 0;
8031ad8b1aafSjsg
80321bb76ff1Sjsg switch (adev->ip_versions[GC_HWIP][0]) {
80331bb76ff1Sjsg case IP_VERSION(10, 1, 10):
80341bb76ff1Sjsg case IP_VERSION(10, 1, 1):
80351bb76ff1Sjsg case IP_VERSION(10, 1, 2):
80361bb76ff1Sjsg case IP_VERSION(10, 3, 0):
80371bb76ff1Sjsg case IP_VERSION(10, 3, 2):
80381bb76ff1Sjsg case IP_VERSION(10, 3, 4):
80391bb76ff1Sjsg case IP_VERSION(10, 3, 5):
80405ca02815Sjsg amdgpu_gfx_off_ctrl(adev, enable);
80415ca02815Sjsg break;
80421bb76ff1Sjsg case IP_VERSION(10, 3, 1):
80431bb76ff1Sjsg case IP_VERSION(10, 3, 3):
80441bb76ff1Sjsg case IP_VERSION(10, 3, 6):
80451bb76ff1Sjsg case IP_VERSION(10, 3, 7):
8046702b98e6Sjsg if (!enable)
8047702b98e6Sjsg amdgpu_gfx_off_ctrl(adev, false);
8048702b98e6Sjsg
80495ca02815Sjsg gfx_v10_cntl_pg(adev, enable);
8050702b98e6Sjsg
8051702b98e6Sjsg if (enable)
8052702b98e6Sjsg amdgpu_gfx_off_ctrl(adev, true);
8053702b98e6Sjsg
8054c349dbc7Sjsg break;
8055c349dbc7Sjsg default:
8056c349dbc7Sjsg break;
8057c349dbc7Sjsg }
8058c349dbc7Sjsg return 0;
8059c349dbc7Sjsg }
8060c349dbc7Sjsg
gfx_v10_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)8061c349dbc7Sjsg static int gfx_v10_0_set_clockgating_state(void *handle,
8062c349dbc7Sjsg enum amd_clockgating_state state)
8063c349dbc7Sjsg {
8064c349dbc7Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8065c349dbc7Sjsg
8066ad8b1aafSjsg if (amdgpu_sriov_vf(adev))
8067ad8b1aafSjsg return 0;
8068ad8b1aafSjsg
80691bb76ff1Sjsg switch (adev->ip_versions[GC_HWIP][0]) {
80701bb76ff1Sjsg case IP_VERSION(10, 1, 10):
80711bb76ff1Sjsg case IP_VERSION(10, 1, 1):
80721bb76ff1Sjsg case IP_VERSION(10, 1, 2):
80731bb76ff1Sjsg case IP_VERSION(10, 3, 0):
80741bb76ff1Sjsg case IP_VERSION(10, 3, 2):
80751bb76ff1Sjsg case IP_VERSION(10, 3, 1):
80761bb76ff1Sjsg case IP_VERSION(10, 3, 4):
80771bb76ff1Sjsg case IP_VERSION(10, 3, 5):
80781bb76ff1Sjsg case IP_VERSION(10, 3, 6):
80791bb76ff1Sjsg case IP_VERSION(10, 3, 3):
80801bb76ff1Sjsg case IP_VERSION(10, 3, 7):
8081c349dbc7Sjsg gfx_v10_0_update_gfx_clock_gating(adev,
8082c349dbc7Sjsg state == AMD_CG_STATE_GATE);
8083c349dbc7Sjsg break;
8084c349dbc7Sjsg default:
8085c349dbc7Sjsg break;
8086c349dbc7Sjsg }
8087c349dbc7Sjsg return 0;
8088c349dbc7Sjsg }
8089c349dbc7Sjsg
gfx_v10_0_get_clockgating_state(void * handle,u64 * flags)80901bb76ff1Sjsg static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags)
8091c349dbc7Sjsg {
8092c349dbc7Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8093c349dbc7Sjsg int data;
8094c349dbc7Sjsg
80955ca02815Sjsg /* AMD_CG_SUPPORT_GFX_FGCG */
80965ca02815Sjsg data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
80975ca02815Sjsg if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
80985ca02815Sjsg *flags |= AMD_CG_SUPPORT_GFX_FGCG;
80995ca02815Sjsg
8100c349dbc7Sjsg /* AMD_CG_SUPPORT_GFX_MGCG */
8101ad8b1aafSjsg data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8102c349dbc7Sjsg if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8103c349dbc7Sjsg *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8104c349dbc7Sjsg
8105c349dbc7Sjsg /* AMD_CG_SUPPORT_GFX_CGCG */
8106ad8b1aafSjsg data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8107c349dbc7Sjsg if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8108c349dbc7Sjsg *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8109c349dbc7Sjsg
8110c349dbc7Sjsg /* AMD_CG_SUPPORT_GFX_CGLS */
8111c349dbc7Sjsg if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8112c349dbc7Sjsg *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8113c349dbc7Sjsg
8114c349dbc7Sjsg /* AMD_CG_SUPPORT_GFX_RLC_LS */
8115ad8b1aafSjsg data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8116c349dbc7Sjsg if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8117c349dbc7Sjsg *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8118c349dbc7Sjsg
8119c349dbc7Sjsg /* AMD_CG_SUPPORT_GFX_CP_LS */
8120ad8b1aafSjsg data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8121c349dbc7Sjsg if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8122c349dbc7Sjsg *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8123c349dbc7Sjsg
8124c349dbc7Sjsg /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8125ad8b1aafSjsg data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8126c349dbc7Sjsg if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8127c349dbc7Sjsg *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8128c349dbc7Sjsg
8129c349dbc7Sjsg /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8130c349dbc7Sjsg if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8131c349dbc7Sjsg *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8132c349dbc7Sjsg }
8133c349dbc7Sjsg
gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring * ring)8134c349dbc7Sjsg static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8135c349dbc7Sjsg {
81361bb76ff1Sjsg /* gfx10 is 32bit rptr*/
81371bb76ff1Sjsg return *(uint32_t *)ring->rptr_cpu_addr;
8138c349dbc7Sjsg }
8139c349dbc7Sjsg
gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring * ring)8140c349dbc7Sjsg static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8141c349dbc7Sjsg {
8142c349dbc7Sjsg struct amdgpu_device *adev = ring->adev;
8143c349dbc7Sjsg u64 wptr;
8144c349dbc7Sjsg
8145c349dbc7Sjsg /* XXX check if swapping is necessary on BE */
8146c349dbc7Sjsg if (ring->use_doorbell) {
81471bb76ff1Sjsg wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8148c349dbc7Sjsg } else {
8149c349dbc7Sjsg wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8150c349dbc7Sjsg wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8151c349dbc7Sjsg }
8152c349dbc7Sjsg
8153c349dbc7Sjsg return wptr;
8154c349dbc7Sjsg }
8155c349dbc7Sjsg
gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring * ring)8156c349dbc7Sjsg static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8157c349dbc7Sjsg {
8158c349dbc7Sjsg struct amdgpu_device *adev = ring->adev;
81591bb76ff1Sjsg uint32_t *wptr_saved;
81601bb76ff1Sjsg uint32_t *is_queue_unmap;
81611bb76ff1Sjsg uint64_t aggregated_db_index;
81621bb76ff1Sjsg uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size;
81631bb76ff1Sjsg uint64_t wptr_tmp;
8164c349dbc7Sjsg
81651bb76ff1Sjsg if (ring->is_mes_queue) {
81661bb76ff1Sjsg wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
81671bb76ff1Sjsg is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
81681bb76ff1Sjsg sizeof(uint32_t));
81691bb76ff1Sjsg aggregated_db_index =
81701bb76ff1Sjsg amdgpu_mes_get_aggregated_doorbell_index(adev,
81711bb76ff1Sjsg AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
81721bb76ff1Sjsg
81731bb76ff1Sjsg wptr_tmp = ring->wptr & ring->buf_mask;
81741bb76ff1Sjsg atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
81751bb76ff1Sjsg *wptr_saved = wptr_tmp;
81761bb76ff1Sjsg /* assume doorbell always being used by mes mapped queue */
81771bb76ff1Sjsg if (*is_queue_unmap) {
81781bb76ff1Sjsg WDOORBELL64(aggregated_db_index, wptr_tmp);
81791bb76ff1Sjsg WDOORBELL64(ring->doorbell_index, wptr_tmp);
81801bb76ff1Sjsg } else {
81811bb76ff1Sjsg WDOORBELL64(ring->doorbell_index, wptr_tmp);
81821bb76ff1Sjsg
81831bb76ff1Sjsg if (*is_queue_unmap)
81841bb76ff1Sjsg WDOORBELL64(aggregated_db_index, wptr_tmp);
81851bb76ff1Sjsg }
81861bb76ff1Sjsg } else {
8187c349dbc7Sjsg if (ring->use_doorbell) {
8188c349dbc7Sjsg /* XXX check if swapping is necessary on BE */
81891bb76ff1Sjsg atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
81901bb76ff1Sjsg ring->wptr);
8191c349dbc7Sjsg WDOORBELL64(ring->doorbell_index, ring->wptr);
8192c349dbc7Sjsg } else {
81931bb76ff1Sjsg WREG32_SOC15(GC, 0, mmCP_RB0_WPTR,
81941bb76ff1Sjsg lower_32_bits(ring->wptr));
81951bb76ff1Sjsg WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI,
81961bb76ff1Sjsg upper_32_bits(ring->wptr));
81971bb76ff1Sjsg }
8198c349dbc7Sjsg }
8199c349dbc7Sjsg }
8200c349dbc7Sjsg
gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring * ring)8201c349dbc7Sjsg static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8202c349dbc7Sjsg {
82031bb76ff1Sjsg /* gfx10 hardware is 32bit rptr */
82041bb76ff1Sjsg return *(uint32_t *)ring->rptr_cpu_addr;
8205c349dbc7Sjsg }
8206c349dbc7Sjsg
gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring * ring)8207c349dbc7Sjsg static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8208c349dbc7Sjsg {
8209c349dbc7Sjsg u64 wptr;
8210c349dbc7Sjsg
8211c349dbc7Sjsg /* XXX check if swapping is necessary on BE */
8212c349dbc7Sjsg if (ring->use_doorbell)
82131bb76ff1Sjsg wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8214c349dbc7Sjsg else
8215c349dbc7Sjsg BUG();
8216c349dbc7Sjsg return wptr;
8217c349dbc7Sjsg }
8218c349dbc7Sjsg
gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring * ring)8219c349dbc7Sjsg static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8220c349dbc7Sjsg {
8221c349dbc7Sjsg struct amdgpu_device *adev = ring->adev;
82221bb76ff1Sjsg uint32_t *wptr_saved;
82231bb76ff1Sjsg uint32_t *is_queue_unmap;
82241bb76ff1Sjsg uint64_t aggregated_db_index;
82251bb76ff1Sjsg uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size;
82261bb76ff1Sjsg uint64_t wptr_tmp;
8227c349dbc7Sjsg
82281bb76ff1Sjsg if (ring->is_mes_queue) {
82291bb76ff1Sjsg wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
82301bb76ff1Sjsg is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
82311bb76ff1Sjsg sizeof(uint32_t));
82321bb76ff1Sjsg aggregated_db_index =
82331bb76ff1Sjsg amdgpu_mes_get_aggregated_doorbell_index(adev,
82341bb76ff1Sjsg AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
82351bb76ff1Sjsg
82361bb76ff1Sjsg wptr_tmp = ring->wptr & ring->buf_mask;
82371bb76ff1Sjsg atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
82381bb76ff1Sjsg *wptr_saved = wptr_tmp;
82391bb76ff1Sjsg /* assume doorbell always used by mes mapped queue */
82401bb76ff1Sjsg if (*is_queue_unmap) {
82411bb76ff1Sjsg WDOORBELL64(aggregated_db_index, wptr_tmp);
82421bb76ff1Sjsg WDOORBELL64(ring->doorbell_index, wptr_tmp);
82431bb76ff1Sjsg } else {
82441bb76ff1Sjsg WDOORBELL64(ring->doorbell_index, wptr_tmp);
82451bb76ff1Sjsg
82461bb76ff1Sjsg if (*is_queue_unmap)
82471bb76ff1Sjsg WDOORBELL64(aggregated_db_index, wptr_tmp);
82481bb76ff1Sjsg }
82491bb76ff1Sjsg } else {
8250c349dbc7Sjsg /* XXX check if swapping is necessary on BE */
8251c349dbc7Sjsg if (ring->use_doorbell) {
82521bb76ff1Sjsg atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
82531bb76ff1Sjsg ring->wptr);
8254c349dbc7Sjsg WDOORBELL64(ring->doorbell_index, ring->wptr);
8255c349dbc7Sjsg } else {
8256c349dbc7Sjsg BUG(); /* only DOORBELL method supported on gfx10 now */
8257c349dbc7Sjsg }
8258c349dbc7Sjsg }
82591bb76ff1Sjsg }
8260c349dbc7Sjsg
gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)8261c349dbc7Sjsg static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8262c349dbc7Sjsg {
8263c349dbc7Sjsg struct amdgpu_device *adev = ring->adev;
8264c349dbc7Sjsg u32 ref_and_mask, reg_mem_engine;
8265c349dbc7Sjsg const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8266c349dbc7Sjsg
8267c349dbc7Sjsg if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8268c349dbc7Sjsg switch (ring->me) {
8269c349dbc7Sjsg case 1:
8270c349dbc7Sjsg ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8271c349dbc7Sjsg break;
8272c349dbc7Sjsg case 2:
8273c349dbc7Sjsg ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8274c349dbc7Sjsg break;
8275c349dbc7Sjsg default:
8276c349dbc7Sjsg return;
8277c349dbc7Sjsg }
8278c349dbc7Sjsg reg_mem_engine = 0;
8279c349dbc7Sjsg } else {
8280c349dbc7Sjsg ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8281c349dbc7Sjsg reg_mem_engine = 1; /* pfp */
8282c349dbc7Sjsg }
8283c349dbc7Sjsg
8284c349dbc7Sjsg gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8285c349dbc7Sjsg adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8286c349dbc7Sjsg adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8287c349dbc7Sjsg ref_and_mask, ref_and_mask, 0x20);
8288c349dbc7Sjsg }
8289c349dbc7Sjsg
gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)8290c349dbc7Sjsg static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8291c349dbc7Sjsg struct amdgpu_job *job,
8292c349dbc7Sjsg struct amdgpu_ib *ib,
8293c349dbc7Sjsg uint32_t flags)
8294c349dbc7Sjsg {
8295f005ef32Sjsg unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8296c349dbc7Sjsg u32 header, control = 0;
8297c349dbc7Sjsg
8298c349dbc7Sjsg if (ib->flags & AMDGPU_IB_FLAG_CE)
8299c349dbc7Sjsg header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8300c349dbc7Sjsg else
8301c349dbc7Sjsg header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8302c349dbc7Sjsg
8303c349dbc7Sjsg control |= ib->length_dw | (vmid << 24);
8304c349dbc7Sjsg
8305f005ef32Sjsg if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8306c349dbc7Sjsg control |= INDIRECT_BUFFER_PRE_ENB(1);
8307c349dbc7Sjsg
8308c349dbc7Sjsg if (flags & AMDGPU_IB_PREEMPTED)
8309c349dbc7Sjsg control |= INDIRECT_BUFFER_PRE_RESUME(1);
8310c349dbc7Sjsg
8311c349dbc7Sjsg if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8312c349dbc7Sjsg gfx_v10_0_ring_emit_de_meta(ring,
8313c349dbc7Sjsg (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8314c349dbc7Sjsg }
8315c349dbc7Sjsg
83161bb76ff1Sjsg if (ring->is_mes_queue)
83171bb76ff1Sjsg /* inherit vmid from mqd */
83181bb76ff1Sjsg control |= 0x400000;
83191bb76ff1Sjsg
8320c349dbc7Sjsg amdgpu_ring_write(ring, header);
8321c349dbc7Sjsg BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8322c349dbc7Sjsg amdgpu_ring_write(ring,
8323c349dbc7Sjsg #ifdef __BIG_ENDIAN
8324c349dbc7Sjsg (2 << 0) |
8325c349dbc7Sjsg #endif
8326c349dbc7Sjsg lower_32_bits(ib->gpu_addr));
8327c349dbc7Sjsg amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8328c349dbc7Sjsg amdgpu_ring_write(ring, control);
8329c349dbc7Sjsg }
8330c349dbc7Sjsg
gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)8331c349dbc7Sjsg static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8332c349dbc7Sjsg struct amdgpu_job *job,
8333c349dbc7Sjsg struct amdgpu_ib *ib,
8334c349dbc7Sjsg uint32_t flags)
8335c349dbc7Sjsg {
8336f005ef32Sjsg unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8337c349dbc7Sjsg u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8338c349dbc7Sjsg
83391bb76ff1Sjsg if (ring->is_mes_queue)
83401bb76ff1Sjsg /* inherit vmid from mqd */
83411bb76ff1Sjsg control |= 0x40000000;
83421bb76ff1Sjsg
8343c349dbc7Sjsg /* Currently, there is a high possibility to get wave ID mismatch
8344c349dbc7Sjsg * between ME and GDS, leading to a hw deadlock, because ME generates
8345c349dbc7Sjsg * different wave IDs than the GDS expects. This situation happens
8346c349dbc7Sjsg * randomly when at least 5 compute pipes use GDS ordered append.
8347c349dbc7Sjsg * The wave IDs generated by ME are also wrong after suspend/resume.
8348c349dbc7Sjsg * Those are probably bugs somewhere else in the kernel driver.
8349c349dbc7Sjsg *
8350c349dbc7Sjsg * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8351c349dbc7Sjsg * GDS to 0 for this ring (me/pipe).
8352c349dbc7Sjsg */
8353c349dbc7Sjsg if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8354c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8355c349dbc7Sjsg amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8356c349dbc7Sjsg amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8357c349dbc7Sjsg }
8358c349dbc7Sjsg
8359c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8360c349dbc7Sjsg BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8361c349dbc7Sjsg amdgpu_ring_write(ring,
8362c349dbc7Sjsg #ifdef __BIG_ENDIAN
8363c349dbc7Sjsg (2 << 0) |
8364c349dbc7Sjsg #endif
8365c349dbc7Sjsg lower_32_bits(ib->gpu_addr));
8366c349dbc7Sjsg amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8367c349dbc7Sjsg amdgpu_ring_write(ring, control);
8368c349dbc7Sjsg }
8369c349dbc7Sjsg
gfx_v10_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned int flags)8370c349dbc7Sjsg static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8371f005ef32Sjsg u64 seq, unsigned int flags)
8372c349dbc7Sjsg {
8373c349dbc7Sjsg bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8374c349dbc7Sjsg bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8375c349dbc7Sjsg
8376c349dbc7Sjsg /* RELEASE_MEM - flush caches, send int */
8377c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8378c349dbc7Sjsg amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8379c349dbc7Sjsg PACKET3_RELEASE_MEM_GCR_GL2_WB |
8380c349dbc7Sjsg PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8381c349dbc7Sjsg PACKET3_RELEASE_MEM_GCR_GLM_WB |
8382c349dbc7Sjsg PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8383c349dbc7Sjsg PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8384c349dbc7Sjsg PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8385c349dbc7Sjsg amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8386c349dbc7Sjsg PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8387c349dbc7Sjsg
8388c349dbc7Sjsg /*
8389c349dbc7Sjsg * the address should be Qword aligned if 64bit write, Dword
8390c349dbc7Sjsg * aligned if only send 32bit data low (discard data high)
8391c349dbc7Sjsg */
8392c349dbc7Sjsg if (write64bit)
8393c349dbc7Sjsg BUG_ON(addr & 0x7);
8394c349dbc7Sjsg else
8395c349dbc7Sjsg BUG_ON(addr & 0x3);
8396c349dbc7Sjsg amdgpu_ring_write(ring, lower_32_bits(addr));
8397c349dbc7Sjsg amdgpu_ring_write(ring, upper_32_bits(addr));
8398c349dbc7Sjsg amdgpu_ring_write(ring, lower_32_bits(seq));
8399c349dbc7Sjsg amdgpu_ring_write(ring, upper_32_bits(seq));
84001bb76ff1Sjsg amdgpu_ring_write(ring, ring->is_mes_queue ?
84011bb76ff1Sjsg (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);
8402c349dbc7Sjsg }
8403c349dbc7Sjsg
gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)8404c349dbc7Sjsg static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8405c349dbc7Sjsg {
8406c349dbc7Sjsg int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8407c349dbc7Sjsg uint32_t seq = ring->fence_drv.sync_seq;
8408c349dbc7Sjsg uint64_t addr = ring->fence_drv.gpu_addr;
8409c349dbc7Sjsg
8410c349dbc7Sjsg gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8411c349dbc7Sjsg upper_32_bits(addr), seq, 0xffffffff, 4);
8412c349dbc7Sjsg }
8413c349dbc7Sjsg
gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring * ring,uint16_t pasid,uint32_t flush_type,bool all_hub,uint8_t dst_sel)84141bb76ff1Sjsg static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
84151bb76ff1Sjsg uint16_t pasid, uint32_t flush_type,
84161bb76ff1Sjsg bool all_hub, uint8_t dst_sel)
84171bb76ff1Sjsg {
84181bb76ff1Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
84191bb76ff1Sjsg amdgpu_ring_write(ring,
84201bb76ff1Sjsg PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
84211bb76ff1Sjsg PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
84221bb76ff1Sjsg PACKET3_INVALIDATE_TLBS_PASID(pasid) |
84231bb76ff1Sjsg PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
84241bb76ff1Sjsg }
84251bb76ff1Sjsg
gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)8426c349dbc7Sjsg static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8427f005ef32Sjsg unsigned int vmid, uint64_t pd_addr)
8428c349dbc7Sjsg {
84291bb76ff1Sjsg if (ring->is_mes_queue)
84301bb76ff1Sjsg gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);
84311bb76ff1Sjsg else
8432c349dbc7Sjsg amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8433c349dbc7Sjsg
8434c349dbc7Sjsg /* compute doesn't have PFP */
8435c349dbc7Sjsg if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8436c349dbc7Sjsg /* sync PFP to ME, otherwise we might get invalid PFP reads */
8437c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8438c349dbc7Sjsg amdgpu_ring_write(ring, 0x0);
8439c349dbc7Sjsg }
8440c349dbc7Sjsg }
8441c349dbc7Sjsg
gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned int flags)8442c349dbc7Sjsg static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8443c349dbc7Sjsg u64 seq, unsigned int flags)
8444c349dbc7Sjsg {
8445c349dbc7Sjsg struct amdgpu_device *adev = ring->adev;
8446c349dbc7Sjsg
8447c349dbc7Sjsg /* we only allocate 32bit for each seq wb address */
8448c349dbc7Sjsg BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8449c349dbc7Sjsg
8450c349dbc7Sjsg /* write fence seq to the "addr" */
8451c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8452c349dbc7Sjsg amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8453c349dbc7Sjsg WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8454c349dbc7Sjsg amdgpu_ring_write(ring, lower_32_bits(addr));
8455c349dbc7Sjsg amdgpu_ring_write(ring, upper_32_bits(addr));
8456c349dbc7Sjsg amdgpu_ring_write(ring, lower_32_bits(seq));
8457c349dbc7Sjsg
8458c349dbc7Sjsg if (flags & AMDGPU_FENCE_FLAG_INT) {
8459c349dbc7Sjsg /* set register to trigger INT */
8460c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8461c349dbc7Sjsg amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8462c349dbc7Sjsg WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8463c349dbc7Sjsg amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8464c349dbc7Sjsg amdgpu_ring_write(ring, 0);
8465c349dbc7Sjsg amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8466c349dbc7Sjsg }
8467c349dbc7Sjsg }
8468c349dbc7Sjsg
gfx_v10_0_ring_emit_sb(struct amdgpu_ring * ring)8469c349dbc7Sjsg static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8470c349dbc7Sjsg {
8471c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8472c349dbc7Sjsg amdgpu_ring_write(ring, 0);
8473c349dbc7Sjsg }
8474c349dbc7Sjsg
gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring * ring,uint32_t flags)8475ad8b1aafSjsg static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8476ad8b1aafSjsg uint32_t flags)
8477c349dbc7Sjsg {
8478c349dbc7Sjsg uint32_t dw2 = 0;
8479c349dbc7Sjsg
8480f005ef32Sjsg if (ring->adev->gfx.mcbp)
8481c349dbc7Sjsg gfx_v10_0_ring_emit_ce_meta(ring,
8482c349dbc7Sjsg (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8483c349dbc7Sjsg
8484c349dbc7Sjsg dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8485c349dbc7Sjsg if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8486c349dbc7Sjsg /* set load_global_config & load_global_uconfig */
8487c349dbc7Sjsg dw2 |= 0x8001;
8488c349dbc7Sjsg /* set load_cs_sh_regs */
8489c349dbc7Sjsg dw2 |= 0x01000000;
8490c349dbc7Sjsg /* set load_per_context_state & load_gfx_sh_regs for GFX */
8491c349dbc7Sjsg dw2 |= 0x10002;
8492c349dbc7Sjsg
8493c349dbc7Sjsg /* set load_ce_ram if preamble presented */
8494c349dbc7Sjsg if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8495c349dbc7Sjsg dw2 |= 0x10000000;
8496c349dbc7Sjsg } else {
8497c349dbc7Sjsg /* still load_ce_ram if this is the first time preamble presented
8498c349dbc7Sjsg * although there is no context switch happens.
8499c349dbc7Sjsg */
8500c349dbc7Sjsg if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8501c349dbc7Sjsg dw2 |= 0x10000000;
8502c349dbc7Sjsg }
8503c349dbc7Sjsg
8504c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8505c349dbc7Sjsg amdgpu_ring_write(ring, dw2);
8506c349dbc7Sjsg amdgpu_ring_write(ring, 0);
8507c349dbc7Sjsg }
8508c349dbc7Sjsg
gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring * ring)8509f005ef32Sjsg static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8510c349dbc7Sjsg {
8511f005ef32Sjsg unsigned int ret;
8512c349dbc7Sjsg
8513c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8514c349dbc7Sjsg amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8515c349dbc7Sjsg amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8516c349dbc7Sjsg amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8517c349dbc7Sjsg ret = ring->wptr & ring->buf_mask;
8518c349dbc7Sjsg amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8519c349dbc7Sjsg
8520c349dbc7Sjsg return ret;
8521c349dbc7Sjsg }
8522c349dbc7Sjsg
gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring * ring,unsigned int offset)8523f005ef32Sjsg static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned int offset)
8524c349dbc7Sjsg {
8525f005ef32Sjsg unsigned int cur;
8526f005ef32Sjsg
8527c349dbc7Sjsg BUG_ON(offset > ring->buf_mask);
8528c349dbc7Sjsg BUG_ON(ring->ring[offset] != 0x55aa55aa);
8529c349dbc7Sjsg
8530c349dbc7Sjsg cur = (ring->wptr - 1) & ring->buf_mask;
8531c349dbc7Sjsg if (likely(cur > offset))
8532c349dbc7Sjsg ring->ring[offset] = cur - offset;
8533c349dbc7Sjsg else
8534c349dbc7Sjsg ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8535c349dbc7Sjsg }
8536c349dbc7Sjsg
gfx_v10_0_ring_preempt_ib(struct amdgpu_ring * ring)8537c349dbc7Sjsg static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8538c349dbc7Sjsg {
8539c349dbc7Sjsg int i, r = 0;
8540c349dbc7Sjsg struct amdgpu_device *adev = ring->adev;
8541f005ef32Sjsg struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
8542c349dbc7Sjsg struct amdgpu_ring *kiq_ring = &kiq->ring;
854377f24a41Sjsg unsigned long flags;
8544c349dbc7Sjsg
8545c349dbc7Sjsg if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8546c349dbc7Sjsg return -EINVAL;
8547c349dbc7Sjsg
854877f24a41Sjsg spin_lock_irqsave(&kiq->ring_lock, flags);
854977f24a41Sjsg
855077f24a41Sjsg if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
855177f24a41Sjsg spin_unlock_irqrestore(&kiq->ring_lock, flags);
8552c349dbc7Sjsg return -ENOMEM;
855377f24a41Sjsg }
8554c349dbc7Sjsg
8555c349dbc7Sjsg /* assert preemption condition */
8556c349dbc7Sjsg amdgpu_ring_set_preempt_cond_exec(ring, false);
8557c349dbc7Sjsg
8558c349dbc7Sjsg /* assert IB preemption, emit the trailing fence */
8559c349dbc7Sjsg kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8560c349dbc7Sjsg ring->trail_fence_gpu_addr,
8561c349dbc7Sjsg ++ring->trail_seq);
8562c349dbc7Sjsg amdgpu_ring_commit(kiq_ring);
8563c349dbc7Sjsg
856477f24a41Sjsg spin_unlock_irqrestore(&kiq->ring_lock, flags);
856577f24a41Sjsg
8566c349dbc7Sjsg /* poll the trailing fence */
8567c349dbc7Sjsg for (i = 0; i < adev->usec_timeout; i++) {
8568c349dbc7Sjsg if (ring->trail_seq ==
8569c349dbc7Sjsg le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8570c349dbc7Sjsg break;
8571c349dbc7Sjsg udelay(1);
8572c349dbc7Sjsg }
8573c349dbc7Sjsg
8574c349dbc7Sjsg if (i >= adev->usec_timeout) {
8575c349dbc7Sjsg r = -EINVAL;
8576c349dbc7Sjsg DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8577c349dbc7Sjsg }
8578c349dbc7Sjsg
8579c349dbc7Sjsg /* deassert preemption condition */
8580c349dbc7Sjsg amdgpu_ring_set_preempt_cond_exec(ring, true);
8581c349dbc7Sjsg return r;
8582c349dbc7Sjsg }
8583c349dbc7Sjsg
gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring * ring,bool resume)8584c349dbc7Sjsg static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8585c349dbc7Sjsg {
8586c349dbc7Sjsg struct amdgpu_device *adev = ring->adev;
8587c349dbc7Sjsg struct v10_ce_ib_state ce_payload = {0};
85881bb76ff1Sjsg uint64_t offset, ce_payload_gpu_addr;
85891bb76ff1Sjsg void *ce_payload_cpu_addr;
8590c349dbc7Sjsg int cnt;
8591c349dbc7Sjsg
8592c349dbc7Sjsg cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
85931bb76ff1Sjsg
85941bb76ff1Sjsg if (ring->is_mes_queue) {
85951bb76ff1Sjsg offset = offsetof(struct amdgpu_mes_ctx_meta_data,
85961bb76ff1Sjsg gfx[0].gfx_meta_data) +
85971bb76ff1Sjsg offsetof(struct v10_gfx_meta_data, ce_payload);
85981bb76ff1Sjsg ce_payload_gpu_addr =
85991bb76ff1Sjsg amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
86001bb76ff1Sjsg ce_payload_cpu_addr =
86011bb76ff1Sjsg amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
86021bb76ff1Sjsg } else {
86031bb76ff1Sjsg offset = offsetof(struct v10_gfx_meta_data, ce_payload);
86041bb76ff1Sjsg ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
86051bb76ff1Sjsg ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
86061bb76ff1Sjsg }
8607c349dbc7Sjsg
8608c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8609c349dbc7Sjsg amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8610c349dbc7Sjsg WRITE_DATA_DST_SEL(8) |
8611c349dbc7Sjsg WR_CONFIRM) |
8612c349dbc7Sjsg WRITE_DATA_CACHE_POLICY(0));
86131bb76ff1Sjsg amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
86141bb76ff1Sjsg amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));
8615c349dbc7Sjsg
8616c349dbc7Sjsg if (resume)
86171bb76ff1Sjsg amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
8618c349dbc7Sjsg sizeof(ce_payload) >> 2);
8619c349dbc7Sjsg else
8620c349dbc7Sjsg amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8621c349dbc7Sjsg sizeof(ce_payload) >> 2);
8622c349dbc7Sjsg }
8623c349dbc7Sjsg
gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring * ring,bool resume)8624c349dbc7Sjsg static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8625c349dbc7Sjsg {
8626c349dbc7Sjsg struct amdgpu_device *adev = ring->adev;
8627c349dbc7Sjsg struct v10_de_ib_state de_payload = {0};
86281bb76ff1Sjsg uint64_t offset, gds_addr, de_payload_gpu_addr;
86291bb76ff1Sjsg void *de_payload_cpu_addr;
8630c349dbc7Sjsg int cnt;
8631c349dbc7Sjsg
86321bb76ff1Sjsg if (ring->is_mes_queue) {
86331bb76ff1Sjsg offset = offsetof(struct amdgpu_mes_ctx_meta_data,
86341bb76ff1Sjsg gfx[0].gfx_meta_data) +
86351bb76ff1Sjsg offsetof(struct v10_gfx_meta_data, de_payload);
86361bb76ff1Sjsg de_payload_gpu_addr =
86371bb76ff1Sjsg amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
86381bb76ff1Sjsg de_payload_cpu_addr =
86391bb76ff1Sjsg amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
86401bb76ff1Sjsg
86411bb76ff1Sjsg offset = offsetof(struct amdgpu_mes_ctx_meta_data,
86421bb76ff1Sjsg gfx[0].gds_backup) +
86431bb76ff1Sjsg offsetof(struct v10_gfx_meta_data, de_payload);
86441bb76ff1Sjsg gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
86451bb76ff1Sjsg } else {
86461bb76ff1Sjsg offset = offsetof(struct v10_gfx_meta_data, de_payload);
86471bb76ff1Sjsg de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
86481bb76ff1Sjsg de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
86491bb76ff1Sjsg
8650f005ef32Sjsg gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
86511bb76ff1Sjsg AMDGPU_CSA_SIZE - adev->gds.gds_size,
8652c349dbc7Sjsg PAGE_SIZE);
86531bb76ff1Sjsg }
86541bb76ff1Sjsg
8655c349dbc7Sjsg de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8656c349dbc7Sjsg de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8657c349dbc7Sjsg
8658c349dbc7Sjsg cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8659c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8660c349dbc7Sjsg amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8661c349dbc7Sjsg WRITE_DATA_DST_SEL(8) |
8662c349dbc7Sjsg WR_CONFIRM) |
8663c349dbc7Sjsg WRITE_DATA_CACHE_POLICY(0));
86641bb76ff1Sjsg amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
86651bb76ff1Sjsg amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
8666c349dbc7Sjsg
8667c349dbc7Sjsg if (resume)
86681bb76ff1Sjsg amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
8669c349dbc7Sjsg sizeof(de_payload) >> 2);
8670c349dbc7Sjsg else
8671c349dbc7Sjsg amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8672c349dbc7Sjsg sizeof(de_payload) >> 2);
8673c349dbc7Sjsg }
8674c349dbc7Sjsg
gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring * ring,bool start,bool secure)8675ad8b1aafSjsg static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8676ad8b1aafSjsg bool secure)
8677c349dbc7Sjsg {
8678ad8b1aafSjsg uint32_t v = secure ? FRAME_TMZ : 0;
8679ad8b1aafSjsg
8680c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8681ad8b1aafSjsg amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8682c349dbc7Sjsg }
8683c349dbc7Sjsg
gfx_v10_0_ring_emit_rreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t reg_val_offs)8684ad8b1aafSjsg static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8685ad8b1aafSjsg uint32_t reg_val_offs)
8686c349dbc7Sjsg {
8687c349dbc7Sjsg struct amdgpu_device *adev = ring->adev;
8688c349dbc7Sjsg
8689c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8690c349dbc7Sjsg amdgpu_ring_write(ring, 0 | /* src: register*/
8691c349dbc7Sjsg (5 << 8) | /* dst: memory */
8692c349dbc7Sjsg (1 << 20)); /* write confirm */
8693c349dbc7Sjsg amdgpu_ring_write(ring, reg);
8694c349dbc7Sjsg amdgpu_ring_write(ring, 0);
8695c349dbc7Sjsg amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8696ad8b1aafSjsg reg_val_offs * 4));
8697c349dbc7Sjsg amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8698ad8b1aafSjsg reg_val_offs * 4));
8699c349dbc7Sjsg }
8700c349dbc7Sjsg
gfx_v10_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)8701c349dbc7Sjsg static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8702c349dbc7Sjsg uint32_t val)
8703c349dbc7Sjsg {
8704c349dbc7Sjsg uint32_t cmd = 0;
8705c349dbc7Sjsg
8706c349dbc7Sjsg switch (ring->funcs->type) {
8707c349dbc7Sjsg case AMDGPU_RING_TYPE_GFX:
8708c349dbc7Sjsg cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8709c349dbc7Sjsg break;
8710c349dbc7Sjsg case AMDGPU_RING_TYPE_KIQ:
8711c349dbc7Sjsg cmd = (1 << 16); /* no inc addr */
8712c349dbc7Sjsg break;
8713c349dbc7Sjsg default:
8714c349dbc7Sjsg cmd = WR_CONFIRM;
8715c349dbc7Sjsg break;
8716c349dbc7Sjsg }
8717c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8718c349dbc7Sjsg amdgpu_ring_write(ring, cmd);
8719c349dbc7Sjsg amdgpu_ring_write(ring, reg);
8720c349dbc7Sjsg amdgpu_ring_write(ring, 0);
8721c349dbc7Sjsg amdgpu_ring_write(ring, val);
8722c349dbc7Sjsg }
8723c349dbc7Sjsg
gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)8724c349dbc7Sjsg static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8725c349dbc7Sjsg uint32_t val, uint32_t mask)
8726c349dbc7Sjsg {
8727c349dbc7Sjsg gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8728c349dbc7Sjsg }
8729c349dbc7Sjsg
gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)8730c349dbc7Sjsg static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8731c349dbc7Sjsg uint32_t reg0, uint32_t reg1,
8732c349dbc7Sjsg uint32_t ref, uint32_t mask)
8733c349dbc7Sjsg {
8734c349dbc7Sjsg int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8735c349dbc7Sjsg struct amdgpu_device *adev = ring->adev;
8736c349dbc7Sjsg bool fw_version_ok = false;
8737c349dbc7Sjsg
8738c349dbc7Sjsg fw_version_ok = adev->gfx.cp_fw_write_wait;
8739c349dbc7Sjsg
8740c349dbc7Sjsg if (fw_version_ok)
8741c349dbc7Sjsg gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8742c349dbc7Sjsg ref, mask, 0x20);
8743c349dbc7Sjsg else
8744c349dbc7Sjsg amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8745c349dbc7Sjsg ref, mask);
8746c349dbc7Sjsg }
8747c349dbc7Sjsg
gfx_v10_0_ring_soft_recovery(struct amdgpu_ring * ring,unsigned int vmid)8748c349dbc7Sjsg static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8749f005ef32Sjsg unsigned int vmid)
8750c349dbc7Sjsg {
8751c349dbc7Sjsg struct amdgpu_device *adev = ring->adev;
8752c349dbc7Sjsg uint32_t value = 0;
8753c349dbc7Sjsg
8754c349dbc7Sjsg value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8755c349dbc7Sjsg value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8756c349dbc7Sjsg value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8757c349dbc7Sjsg value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8758c349dbc7Sjsg WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8759c349dbc7Sjsg }
8760c349dbc7Sjsg
8761c349dbc7Sjsg static void
gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device * adev,uint32_t me,uint32_t pipe,enum amdgpu_interrupt_state state)8762c349dbc7Sjsg gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8763c349dbc7Sjsg uint32_t me, uint32_t pipe,
8764c349dbc7Sjsg enum amdgpu_interrupt_state state)
8765c349dbc7Sjsg {
8766c349dbc7Sjsg uint32_t cp_int_cntl, cp_int_cntl_reg;
8767c349dbc7Sjsg
8768c349dbc7Sjsg if (!me) {
8769c349dbc7Sjsg switch (pipe) {
8770c349dbc7Sjsg case 0:
8771c349dbc7Sjsg cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8772c349dbc7Sjsg break;
8773c349dbc7Sjsg case 1:
8774c349dbc7Sjsg cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8775c349dbc7Sjsg break;
8776c349dbc7Sjsg default:
8777c349dbc7Sjsg DRM_DEBUG("invalid pipe %d\n", pipe);
8778c349dbc7Sjsg return;
8779c349dbc7Sjsg }
8780c349dbc7Sjsg } else {
8781c349dbc7Sjsg DRM_DEBUG("invalid me %d\n", me);
8782c349dbc7Sjsg return;
8783c349dbc7Sjsg }
8784c349dbc7Sjsg
8785c349dbc7Sjsg switch (state) {
8786c349dbc7Sjsg case AMDGPU_IRQ_STATE_DISABLE:
87875ca02815Sjsg cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
8788c349dbc7Sjsg cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8789c349dbc7Sjsg TIME_STAMP_INT_ENABLE, 0);
87905ca02815Sjsg WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
8791c349dbc7Sjsg break;
8792c349dbc7Sjsg case AMDGPU_IRQ_STATE_ENABLE:
87935ca02815Sjsg cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
8794c349dbc7Sjsg cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8795c349dbc7Sjsg TIME_STAMP_INT_ENABLE, 1);
87965ca02815Sjsg WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
8797c349dbc7Sjsg break;
8798c349dbc7Sjsg default:
8799c349dbc7Sjsg break;
8800c349dbc7Sjsg }
8801c349dbc7Sjsg }
8802c349dbc7Sjsg
gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device * adev,int me,int pipe,enum amdgpu_interrupt_state state)8803c349dbc7Sjsg static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8804c349dbc7Sjsg int me, int pipe,
8805c349dbc7Sjsg enum amdgpu_interrupt_state state)
8806c349dbc7Sjsg {
8807c349dbc7Sjsg u32 mec_int_cntl, mec_int_cntl_reg;
8808c349dbc7Sjsg
8809c349dbc7Sjsg /*
8810c349dbc7Sjsg * amdgpu controls only the first MEC. That's why this function only
8811c349dbc7Sjsg * handles the setting of interrupts for this specific MEC. All other
8812c349dbc7Sjsg * pipes' interrupts are set by amdkfd.
8813c349dbc7Sjsg */
8814c349dbc7Sjsg
8815c349dbc7Sjsg if (me == 1) {
8816c349dbc7Sjsg switch (pipe) {
8817c349dbc7Sjsg case 0:
8818c349dbc7Sjsg mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8819c349dbc7Sjsg break;
8820c349dbc7Sjsg case 1:
8821c349dbc7Sjsg mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8822c349dbc7Sjsg break;
8823c349dbc7Sjsg case 2:
8824c349dbc7Sjsg mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8825c349dbc7Sjsg break;
8826c349dbc7Sjsg case 3:
8827c349dbc7Sjsg mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8828c349dbc7Sjsg break;
8829c349dbc7Sjsg default:
8830c349dbc7Sjsg DRM_DEBUG("invalid pipe %d\n", pipe);
8831c349dbc7Sjsg return;
8832c349dbc7Sjsg }
8833c349dbc7Sjsg } else {
8834c349dbc7Sjsg DRM_DEBUG("invalid me %d\n", me);
8835c349dbc7Sjsg return;
8836c349dbc7Sjsg }
8837c349dbc7Sjsg
8838c349dbc7Sjsg switch (state) {
8839c349dbc7Sjsg case AMDGPU_IRQ_STATE_DISABLE:
88405ca02815Sjsg mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
8841c349dbc7Sjsg mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8842c349dbc7Sjsg TIME_STAMP_INT_ENABLE, 0);
88435ca02815Sjsg WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
8844c349dbc7Sjsg break;
8845c349dbc7Sjsg case AMDGPU_IRQ_STATE_ENABLE:
88465ca02815Sjsg mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
8847c349dbc7Sjsg mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8848c349dbc7Sjsg TIME_STAMP_INT_ENABLE, 1);
88495ca02815Sjsg WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
8850c349dbc7Sjsg break;
8851c349dbc7Sjsg default:
8852c349dbc7Sjsg break;
8853c349dbc7Sjsg }
8854c349dbc7Sjsg }
8855c349dbc7Sjsg
gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type,enum amdgpu_interrupt_state state)8856c349dbc7Sjsg static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8857c349dbc7Sjsg struct amdgpu_irq_src *src,
8858f005ef32Sjsg unsigned int type,
8859c349dbc7Sjsg enum amdgpu_interrupt_state state)
8860c349dbc7Sjsg {
8861c349dbc7Sjsg switch (type) {
8862c349dbc7Sjsg case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8863c349dbc7Sjsg gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8864c349dbc7Sjsg break;
8865c349dbc7Sjsg case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8866c349dbc7Sjsg gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8867c349dbc7Sjsg break;
8868c349dbc7Sjsg case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8869c349dbc7Sjsg gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8870c349dbc7Sjsg break;
8871c349dbc7Sjsg case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8872c349dbc7Sjsg gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8873c349dbc7Sjsg break;
8874c349dbc7Sjsg case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8875c349dbc7Sjsg gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8876c349dbc7Sjsg break;
8877c349dbc7Sjsg case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8878c349dbc7Sjsg gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8879c349dbc7Sjsg break;
8880c349dbc7Sjsg case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8881c349dbc7Sjsg gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8882c349dbc7Sjsg break;
8883c349dbc7Sjsg case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8884c349dbc7Sjsg gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8885c349dbc7Sjsg break;
8886c349dbc7Sjsg case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8887c349dbc7Sjsg gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8888c349dbc7Sjsg break;
8889c349dbc7Sjsg case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8890c349dbc7Sjsg gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8891c349dbc7Sjsg break;
8892c349dbc7Sjsg default:
8893c349dbc7Sjsg break;
8894c349dbc7Sjsg }
8895c349dbc7Sjsg return 0;
8896c349dbc7Sjsg }
8897c349dbc7Sjsg
gfx_v10_0_eop_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)8898c349dbc7Sjsg static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8899c349dbc7Sjsg struct amdgpu_irq_src *source,
8900c349dbc7Sjsg struct amdgpu_iv_entry *entry)
8901c349dbc7Sjsg {
8902c349dbc7Sjsg int i;
8903c349dbc7Sjsg u8 me_id, pipe_id, queue_id;
8904c349dbc7Sjsg struct amdgpu_ring *ring;
89051bb76ff1Sjsg uint32_t mes_queue_id = entry->src_data[0];
8906c349dbc7Sjsg
8907c349dbc7Sjsg DRM_DEBUG("IH: CP EOP\n");
89081bb76ff1Sjsg
89091bb76ff1Sjsg if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
89101bb76ff1Sjsg struct amdgpu_mes_queue *queue;
89111bb76ff1Sjsg
89121bb76ff1Sjsg mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
89131bb76ff1Sjsg
89141bb76ff1Sjsg spin_lock(&adev->mes.queue_id_lock);
89151bb76ff1Sjsg queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
89161bb76ff1Sjsg if (queue) {
89171bb76ff1Sjsg DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);
89181bb76ff1Sjsg amdgpu_fence_process(queue->ring);
89191bb76ff1Sjsg }
89201bb76ff1Sjsg spin_unlock(&adev->mes.queue_id_lock);
89211bb76ff1Sjsg } else {
8922c349dbc7Sjsg me_id = (entry->ring_id & 0x0c) >> 2;
8923c349dbc7Sjsg pipe_id = (entry->ring_id & 0x03) >> 0;
8924c349dbc7Sjsg queue_id = (entry->ring_id & 0x70) >> 4;
8925c349dbc7Sjsg
8926c349dbc7Sjsg switch (me_id) {
8927c349dbc7Sjsg case 0:
8928c349dbc7Sjsg if (pipe_id == 0)
8929c349dbc7Sjsg amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8930c349dbc7Sjsg else
8931c349dbc7Sjsg amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8932c349dbc7Sjsg break;
8933c349dbc7Sjsg case 1:
8934c349dbc7Sjsg case 2:
8935c349dbc7Sjsg for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8936c349dbc7Sjsg ring = &adev->gfx.compute_ring[i];
8937c349dbc7Sjsg /* Per-queue interrupt is supported for MEC starting from VI.
89381bb76ff1Sjsg * The interrupt can only be enabled/disabled per pipe instead
89391bb76ff1Sjsg * of per queue.
8940c349dbc7Sjsg */
89411bb76ff1Sjsg if ((ring->me == me_id) &&
89421bb76ff1Sjsg (ring->pipe == pipe_id) &&
89431bb76ff1Sjsg (ring->queue == queue_id))
8944c349dbc7Sjsg amdgpu_fence_process(ring);
8945c349dbc7Sjsg }
8946c349dbc7Sjsg break;
8947c349dbc7Sjsg }
89481bb76ff1Sjsg }
89491bb76ff1Sjsg
8950c349dbc7Sjsg return 0;
8951c349dbc7Sjsg }
8952c349dbc7Sjsg
gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)8953c349dbc7Sjsg static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8954c349dbc7Sjsg struct amdgpu_irq_src *source,
8955f005ef32Sjsg unsigned int type,
8956c349dbc7Sjsg enum amdgpu_interrupt_state state)
8957c349dbc7Sjsg {
8958c349dbc7Sjsg switch (state) {
8959c349dbc7Sjsg case AMDGPU_IRQ_STATE_DISABLE:
8960c349dbc7Sjsg case AMDGPU_IRQ_STATE_ENABLE:
8961c349dbc7Sjsg WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8962c349dbc7Sjsg PRIV_REG_INT_ENABLE,
8963c349dbc7Sjsg state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8964c349dbc7Sjsg break;
8965c349dbc7Sjsg default:
8966c349dbc7Sjsg break;
8967c349dbc7Sjsg }
8968c349dbc7Sjsg
8969c349dbc7Sjsg return 0;
8970c349dbc7Sjsg }
8971c349dbc7Sjsg
gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)8972c349dbc7Sjsg static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8973c349dbc7Sjsg struct amdgpu_irq_src *source,
8974f005ef32Sjsg unsigned int type,
8975c349dbc7Sjsg enum amdgpu_interrupt_state state)
8976c349dbc7Sjsg {
8977c349dbc7Sjsg switch (state) {
8978c349dbc7Sjsg case AMDGPU_IRQ_STATE_DISABLE:
8979c349dbc7Sjsg case AMDGPU_IRQ_STATE_ENABLE:
8980c349dbc7Sjsg WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8981c349dbc7Sjsg PRIV_INSTR_INT_ENABLE,
8982c349dbc7Sjsg state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
89835ca02815Sjsg break;
8984c349dbc7Sjsg default:
8985c349dbc7Sjsg break;
8986c349dbc7Sjsg }
8987c349dbc7Sjsg
8988c349dbc7Sjsg return 0;
8989c349dbc7Sjsg }
8990c349dbc7Sjsg
gfx_v10_0_handle_priv_fault(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry)8991c349dbc7Sjsg static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8992c349dbc7Sjsg struct amdgpu_iv_entry *entry)
8993c349dbc7Sjsg {
8994c349dbc7Sjsg u8 me_id, pipe_id, queue_id;
8995c349dbc7Sjsg struct amdgpu_ring *ring;
8996c349dbc7Sjsg int i;
8997c349dbc7Sjsg
8998c349dbc7Sjsg me_id = (entry->ring_id & 0x0c) >> 2;
8999c349dbc7Sjsg pipe_id = (entry->ring_id & 0x03) >> 0;
9000c349dbc7Sjsg queue_id = (entry->ring_id & 0x70) >> 4;
9001c349dbc7Sjsg
9002c349dbc7Sjsg switch (me_id) {
9003c349dbc7Sjsg case 0:
9004c349dbc7Sjsg for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9005c349dbc7Sjsg ring = &adev->gfx.gfx_ring[i];
9006c349dbc7Sjsg /* we only enabled 1 gfx queue per pipe for now */
9007c349dbc7Sjsg if (ring->me == me_id && ring->pipe == pipe_id)
9008c349dbc7Sjsg drm_sched_fault(&ring->sched);
9009c349dbc7Sjsg }
9010c349dbc7Sjsg break;
9011c349dbc7Sjsg case 1:
9012c349dbc7Sjsg case 2:
9013c349dbc7Sjsg for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9014c349dbc7Sjsg ring = &adev->gfx.compute_ring[i];
9015c349dbc7Sjsg if (ring->me == me_id && ring->pipe == pipe_id &&
9016c349dbc7Sjsg ring->queue == queue_id)
9017c349dbc7Sjsg drm_sched_fault(&ring->sched);
9018c349dbc7Sjsg }
9019c349dbc7Sjsg break;
9020c349dbc7Sjsg default:
9021c349dbc7Sjsg BUG();
9022c349dbc7Sjsg }
9023c349dbc7Sjsg }
9024c349dbc7Sjsg
gfx_v10_0_priv_reg_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)9025c349dbc7Sjsg static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9026c349dbc7Sjsg struct amdgpu_irq_src *source,
9027c349dbc7Sjsg struct amdgpu_iv_entry *entry)
9028c349dbc7Sjsg {
9029c349dbc7Sjsg DRM_ERROR("Illegal register access in command stream\n");
9030c349dbc7Sjsg gfx_v10_0_handle_priv_fault(adev, entry);
9031c349dbc7Sjsg return 0;
9032c349dbc7Sjsg }
9033c349dbc7Sjsg
gfx_v10_0_priv_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)9034c349dbc7Sjsg static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9035c349dbc7Sjsg struct amdgpu_irq_src *source,
9036c349dbc7Sjsg struct amdgpu_iv_entry *entry)
9037c349dbc7Sjsg {
9038c349dbc7Sjsg DRM_ERROR("Illegal instruction in command stream\n");
9039c349dbc7Sjsg gfx_v10_0_handle_priv_fault(adev, entry);
9040c349dbc7Sjsg return 0;
9041c349dbc7Sjsg }
9042c349dbc7Sjsg
gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type,enum amdgpu_interrupt_state state)9043c349dbc7Sjsg static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9044c349dbc7Sjsg struct amdgpu_irq_src *src,
9045c349dbc7Sjsg unsigned int type,
9046c349dbc7Sjsg enum amdgpu_interrupt_state state)
9047c349dbc7Sjsg {
9048c349dbc7Sjsg uint32_t tmp, target;
9049f005ef32Sjsg struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9050c349dbc7Sjsg
9051c349dbc7Sjsg if (ring->me == 1)
9052c349dbc7Sjsg target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9053c349dbc7Sjsg else
9054c349dbc7Sjsg target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
9055c349dbc7Sjsg target += ring->pipe;
9056c349dbc7Sjsg
9057c349dbc7Sjsg switch (type) {
9058c349dbc7Sjsg case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9059c349dbc7Sjsg if (state == AMDGPU_IRQ_STATE_DISABLE) {
9060c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9061c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9062c349dbc7Sjsg GENERIC2_INT_ENABLE, 0);
9063c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9064c349dbc7Sjsg
90655ca02815Sjsg tmp = RREG32_SOC15_IP(GC, target);
9066c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9067c349dbc7Sjsg GENERIC2_INT_ENABLE, 0);
90685ca02815Sjsg WREG32_SOC15_IP(GC, target, tmp);
9069c349dbc7Sjsg } else {
9070c349dbc7Sjsg tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9071c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9072c349dbc7Sjsg GENERIC2_INT_ENABLE, 1);
9073c349dbc7Sjsg WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9074c349dbc7Sjsg
90755ca02815Sjsg tmp = RREG32_SOC15_IP(GC, target);
9076c349dbc7Sjsg tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9077c349dbc7Sjsg GENERIC2_INT_ENABLE, 1);
90785ca02815Sjsg WREG32_SOC15_IP(GC, target, tmp);
9079c349dbc7Sjsg }
9080c349dbc7Sjsg break;
9081c349dbc7Sjsg default:
9082c349dbc7Sjsg BUG(); /* kiq only support GENERIC2_INT now */
9083c349dbc7Sjsg break;
9084c349dbc7Sjsg }
9085c349dbc7Sjsg return 0;
9086c349dbc7Sjsg }
9087c349dbc7Sjsg
gfx_v10_0_kiq_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)9088c349dbc7Sjsg static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9089c349dbc7Sjsg struct amdgpu_irq_src *source,
9090c349dbc7Sjsg struct amdgpu_iv_entry *entry)
9091c349dbc7Sjsg {
9092c349dbc7Sjsg u8 me_id, pipe_id, queue_id;
9093f005ef32Sjsg struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9094c349dbc7Sjsg
9095c349dbc7Sjsg me_id = (entry->ring_id & 0x0c) >> 2;
9096c349dbc7Sjsg pipe_id = (entry->ring_id & 0x03) >> 0;
9097c349dbc7Sjsg queue_id = (entry->ring_id & 0x70) >> 4;
9098c349dbc7Sjsg DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
9099c349dbc7Sjsg me_id, pipe_id, queue_id);
9100c349dbc7Sjsg
9101c349dbc7Sjsg amdgpu_fence_process(ring);
9102c349dbc7Sjsg return 0;
9103c349dbc7Sjsg }
9104c349dbc7Sjsg
gfx_v10_0_emit_mem_sync(struct amdgpu_ring * ring)9105ad8b1aafSjsg static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9106ad8b1aafSjsg {
9107ad8b1aafSjsg const unsigned int gcr_cntl =
9108ad8b1aafSjsg PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
9109ad8b1aafSjsg PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
9110ad8b1aafSjsg PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
9111ad8b1aafSjsg PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
9112ad8b1aafSjsg PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
9113ad8b1aafSjsg PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
9114ad8b1aafSjsg PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
9115ad8b1aafSjsg PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
9116ad8b1aafSjsg
9117ad8b1aafSjsg /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9118ad8b1aafSjsg amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
9119ad8b1aafSjsg amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9120ad8b1aafSjsg amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
9121ad8b1aafSjsg amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */
9122ad8b1aafSjsg amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9123ad8b1aafSjsg amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
9124ad8b1aafSjsg amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9125ad8b1aafSjsg amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9126ad8b1aafSjsg }
9127ad8b1aafSjsg
9128c349dbc7Sjsg static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9129c349dbc7Sjsg .name = "gfx_v10_0",
9130c349dbc7Sjsg .early_init = gfx_v10_0_early_init,
9131c349dbc7Sjsg .late_init = gfx_v10_0_late_init,
9132c349dbc7Sjsg .sw_init = gfx_v10_0_sw_init,
9133c349dbc7Sjsg .sw_fini = gfx_v10_0_sw_fini,
9134c349dbc7Sjsg .hw_init = gfx_v10_0_hw_init,
9135c349dbc7Sjsg .hw_fini = gfx_v10_0_hw_fini,
9136c349dbc7Sjsg .suspend = gfx_v10_0_suspend,
9137c349dbc7Sjsg .resume = gfx_v10_0_resume,
9138c349dbc7Sjsg .is_idle = gfx_v10_0_is_idle,
9139c349dbc7Sjsg .wait_for_idle = gfx_v10_0_wait_for_idle,
9140c349dbc7Sjsg .soft_reset = gfx_v10_0_soft_reset,
9141c349dbc7Sjsg .set_clockgating_state = gfx_v10_0_set_clockgating_state,
9142c349dbc7Sjsg .set_powergating_state = gfx_v10_0_set_powergating_state,
9143c349dbc7Sjsg .get_clockgating_state = gfx_v10_0_get_clockgating_state,
9144c349dbc7Sjsg };
9145c349dbc7Sjsg
9146c349dbc7Sjsg static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9147c349dbc7Sjsg .type = AMDGPU_RING_TYPE_GFX,
9148c349dbc7Sjsg .align_mask = 0xff,
9149c349dbc7Sjsg .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9150c349dbc7Sjsg .support_64bit_ptrs = true,
91511bb76ff1Sjsg .secure_submission_supported = true,
9152c349dbc7Sjsg .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9153c349dbc7Sjsg .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9154c349dbc7Sjsg .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9155c349dbc7Sjsg .emit_frame_size = /* totally 242 maximum if 16 IBs */
9156c349dbc7Sjsg 5 + /* COND_EXEC */
9157c349dbc7Sjsg 7 + /* PIPELINE_SYNC */
9158c349dbc7Sjsg SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9159c349dbc7Sjsg SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9160c349dbc7Sjsg 2 + /* VM_FLUSH */
9161c349dbc7Sjsg 8 + /* FENCE for VM_FLUSH */
9162c349dbc7Sjsg 20 + /* GDS switch */
9163c349dbc7Sjsg 4 + /* double SWITCH_BUFFER,
9164c349dbc7Sjsg * the first COND_EXEC jump to the place
9165c349dbc7Sjsg * just prior to this double SWITCH_BUFFER
9166c349dbc7Sjsg */
9167c349dbc7Sjsg 5 + /* COND_EXEC */
9168c349dbc7Sjsg 7 + /* HDP_flush */
9169c349dbc7Sjsg 4 + /* VGT_flush */
9170c349dbc7Sjsg 14 + /* CE_META */
9171c349dbc7Sjsg 31 + /* DE_META */
9172c349dbc7Sjsg 3 + /* CNTX_CTRL */
9173c349dbc7Sjsg 5 + /* HDP_INVL */
9174c349dbc7Sjsg 8 + 8 + /* FENCE x2 */
9175ad8b1aafSjsg 2 + /* SWITCH_BUFFER */
9176ad8b1aafSjsg 8, /* gfx_v10_0_emit_mem_sync */
9177c349dbc7Sjsg .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
9178c349dbc7Sjsg .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9179c349dbc7Sjsg .emit_fence = gfx_v10_0_ring_emit_fence,
9180c349dbc7Sjsg .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9181c349dbc7Sjsg .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9182c349dbc7Sjsg .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9183c349dbc7Sjsg .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9184c349dbc7Sjsg .test_ring = gfx_v10_0_ring_test_ring,
9185c349dbc7Sjsg .test_ib = gfx_v10_0_ring_test_ib,
9186c349dbc7Sjsg .insert_nop = amdgpu_ring_insert_nop,
9187c349dbc7Sjsg .pad_ib = amdgpu_ring_generic_pad_ib,
9188c349dbc7Sjsg .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9189c349dbc7Sjsg .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9190c349dbc7Sjsg .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9191c349dbc7Sjsg .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
9192c349dbc7Sjsg .preempt_ib = gfx_v10_0_ring_preempt_ib,
9193ad8b1aafSjsg .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9194c349dbc7Sjsg .emit_wreg = gfx_v10_0_ring_emit_wreg,
9195c349dbc7Sjsg .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9196c349dbc7Sjsg .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9197c349dbc7Sjsg .soft_recovery = gfx_v10_0_ring_soft_recovery,
9198ad8b1aafSjsg .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9199c349dbc7Sjsg };
9200c349dbc7Sjsg
9201c349dbc7Sjsg static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9202c349dbc7Sjsg .type = AMDGPU_RING_TYPE_COMPUTE,
9203c349dbc7Sjsg .align_mask = 0xff,
9204c349dbc7Sjsg .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9205c349dbc7Sjsg .support_64bit_ptrs = true,
9206c349dbc7Sjsg .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9207c349dbc7Sjsg .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9208c349dbc7Sjsg .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9209c349dbc7Sjsg .emit_frame_size =
9210c349dbc7Sjsg 20 + /* gfx_v10_0_ring_emit_gds_switch */
9211c349dbc7Sjsg 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9212c349dbc7Sjsg 5 + /* hdp invalidate */
9213c349dbc7Sjsg 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9214c349dbc7Sjsg SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9215c349dbc7Sjsg SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9216c349dbc7Sjsg 2 + /* gfx_v10_0_ring_emit_vm_flush */
9217ad8b1aafSjsg 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9218ad8b1aafSjsg 8, /* gfx_v10_0_emit_mem_sync */
9219c349dbc7Sjsg .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9220c349dbc7Sjsg .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9221c349dbc7Sjsg .emit_fence = gfx_v10_0_ring_emit_fence,
9222c349dbc7Sjsg .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9223c349dbc7Sjsg .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9224c349dbc7Sjsg .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9225c349dbc7Sjsg .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9226c349dbc7Sjsg .test_ring = gfx_v10_0_ring_test_ring,
9227c349dbc7Sjsg .test_ib = gfx_v10_0_ring_test_ib,
9228c349dbc7Sjsg .insert_nop = amdgpu_ring_insert_nop,
9229c349dbc7Sjsg .pad_ib = amdgpu_ring_generic_pad_ib,
9230c349dbc7Sjsg .emit_wreg = gfx_v10_0_ring_emit_wreg,
9231c349dbc7Sjsg .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9232c349dbc7Sjsg .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9233ad8b1aafSjsg .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9234c349dbc7Sjsg };
9235c349dbc7Sjsg
9236c349dbc7Sjsg static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9237c349dbc7Sjsg .type = AMDGPU_RING_TYPE_KIQ,
9238c349dbc7Sjsg .align_mask = 0xff,
9239c349dbc7Sjsg .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9240c349dbc7Sjsg .support_64bit_ptrs = true,
9241c349dbc7Sjsg .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9242c349dbc7Sjsg .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9243c349dbc7Sjsg .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9244c349dbc7Sjsg .emit_frame_size =
9245c349dbc7Sjsg 20 + /* gfx_v10_0_ring_emit_gds_switch */
9246c349dbc7Sjsg 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9247c349dbc7Sjsg 5 + /*hdp invalidate */
9248c349dbc7Sjsg 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9249c349dbc7Sjsg SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9250c349dbc7Sjsg SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9251c349dbc7Sjsg 2 + /* gfx_v10_0_ring_emit_vm_flush */
9252c349dbc7Sjsg 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9253c349dbc7Sjsg .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9254c349dbc7Sjsg .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9255c349dbc7Sjsg .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9256c349dbc7Sjsg .test_ring = gfx_v10_0_ring_test_ring,
9257c349dbc7Sjsg .test_ib = gfx_v10_0_ring_test_ib,
9258c349dbc7Sjsg .insert_nop = amdgpu_ring_insert_nop,
9259c349dbc7Sjsg .pad_ib = amdgpu_ring_generic_pad_ib,
9260c349dbc7Sjsg .emit_rreg = gfx_v10_0_ring_emit_rreg,
9261c349dbc7Sjsg .emit_wreg = gfx_v10_0_ring_emit_wreg,
9262c349dbc7Sjsg .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9263c349dbc7Sjsg .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9264c349dbc7Sjsg };
9265c349dbc7Sjsg
gfx_v10_0_set_ring_funcs(struct amdgpu_device * adev)9266c349dbc7Sjsg static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9267c349dbc7Sjsg {
9268c349dbc7Sjsg int i;
9269c349dbc7Sjsg
9270f005ef32Sjsg adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9271c349dbc7Sjsg
9272c349dbc7Sjsg for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9273c349dbc7Sjsg adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9274c349dbc7Sjsg
9275c349dbc7Sjsg for (i = 0; i < adev->gfx.num_compute_rings; i++)
9276c349dbc7Sjsg adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9277c349dbc7Sjsg }
9278c349dbc7Sjsg
9279c349dbc7Sjsg static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9280c349dbc7Sjsg .set = gfx_v10_0_set_eop_interrupt_state,
9281c349dbc7Sjsg .process = gfx_v10_0_eop_irq,
9282c349dbc7Sjsg };
9283c349dbc7Sjsg
9284c349dbc7Sjsg static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9285c349dbc7Sjsg .set = gfx_v10_0_set_priv_reg_fault_state,
9286c349dbc7Sjsg .process = gfx_v10_0_priv_reg_irq,
9287c349dbc7Sjsg };
9288c349dbc7Sjsg
9289c349dbc7Sjsg static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9290c349dbc7Sjsg .set = gfx_v10_0_set_priv_inst_fault_state,
9291c349dbc7Sjsg .process = gfx_v10_0_priv_inst_irq,
9292c349dbc7Sjsg };
9293c349dbc7Sjsg
9294c349dbc7Sjsg static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9295c349dbc7Sjsg .set = gfx_v10_0_kiq_set_interrupt_state,
9296c349dbc7Sjsg .process = gfx_v10_0_kiq_irq,
9297c349dbc7Sjsg };
9298c349dbc7Sjsg
gfx_v10_0_set_irq_funcs(struct amdgpu_device * adev)9299c349dbc7Sjsg static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9300c349dbc7Sjsg {
9301c349dbc7Sjsg adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9302c349dbc7Sjsg adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9303c349dbc7Sjsg
9304f005ef32Sjsg adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9305f005ef32Sjsg adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9306c349dbc7Sjsg
9307c349dbc7Sjsg adev->gfx.priv_reg_irq.num_types = 1;
9308c349dbc7Sjsg adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9309c349dbc7Sjsg
9310c349dbc7Sjsg adev->gfx.priv_inst_irq.num_types = 1;
9311c349dbc7Sjsg adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9312c349dbc7Sjsg }
9313c349dbc7Sjsg
gfx_v10_0_set_rlc_funcs(struct amdgpu_device * adev)9314c349dbc7Sjsg static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9315c349dbc7Sjsg {
93161bb76ff1Sjsg switch (adev->ip_versions[GC_HWIP][0]) {
93171bb76ff1Sjsg case IP_VERSION(10, 1, 10):
93181bb76ff1Sjsg case IP_VERSION(10, 1, 1):
93191bb76ff1Sjsg case IP_VERSION(10, 1, 3):
93201bb76ff1Sjsg case IP_VERSION(10, 1, 4):
93211bb76ff1Sjsg case IP_VERSION(10, 3, 2):
93221bb76ff1Sjsg case IP_VERSION(10, 3, 1):
93231bb76ff1Sjsg case IP_VERSION(10, 3, 4):
93241bb76ff1Sjsg case IP_VERSION(10, 3, 5):
93251bb76ff1Sjsg case IP_VERSION(10, 3, 6):
93261bb76ff1Sjsg case IP_VERSION(10, 3, 3):
93271bb76ff1Sjsg case IP_VERSION(10, 3, 7):
9328c349dbc7Sjsg adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9329c349dbc7Sjsg break;
93301bb76ff1Sjsg case IP_VERSION(10, 1, 2):
93311bb76ff1Sjsg case IP_VERSION(10, 3, 0):
9332ad8b1aafSjsg adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9333ad8b1aafSjsg break;
9334c349dbc7Sjsg default:
9335c349dbc7Sjsg break;
9336c349dbc7Sjsg }
9337c349dbc7Sjsg }
9338c349dbc7Sjsg
gfx_v10_0_set_gds_init(struct amdgpu_device * adev)9339c349dbc7Sjsg static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9340c349dbc7Sjsg {
9341f005ef32Sjsg unsigned int total_cu = adev->gfx.config.max_cu_per_sh *
9342c349dbc7Sjsg adev->gfx.config.max_sh_per_se *
9343c349dbc7Sjsg adev->gfx.config.max_shader_engines;
9344c349dbc7Sjsg
9345c349dbc7Sjsg adev->gds.gds_size = 0x10000;
9346c349dbc7Sjsg adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9347c349dbc7Sjsg adev->gds.gws_size = 64;
9348c349dbc7Sjsg adev->gds.oa_size = 16;
9349c349dbc7Sjsg }
9350c349dbc7Sjsg
gfx_v10_0_set_mqd_funcs(struct amdgpu_device * adev)93511bb76ff1Sjsg static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev)
93521bb76ff1Sjsg {
93531bb76ff1Sjsg /* set gfx eng mqd */
93541bb76ff1Sjsg adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
93551bb76ff1Sjsg sizeof(struct v10_gfx_mqd);
93561bb76ff1Sjsg adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
93571bb76ff1Sjsg gfx_v10_0_gfx_mqd_init;
93581bb76ff1Sjsg /* set compute eng mqd */
93591bb76ff1Sjsg adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
93601bb76ff1Sjsg sizeof(struct v10_compute_mqd);
93611bb76ff1Sjsg adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
93621bb76ff1Sjsg gfx_v10_0_compute_mqd_init;
93631bb76ff1Sjsg }
93641bb76ff1Sjsg
gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device * adev,u32 bitmap)9365c349dbc7Sjsg static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9366c349dbc7Sjsg u32 bitmap)
9367c349dbc7Sjsg {
9368c349dbc7Sjsg u32 data;
9369c349dbc7Sjsg
9370c349dbc7Sjsg if (!bitmap)
9371c349dbc7Sjsg return;
9372c349dbc7Sjsg
9373c349dbc7Sjsg data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9374c349dbc7Sjsg data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9375c349dbc7Sjsg
9376c349dbc7Sjsg WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9377c349dbc7Sjsg }
9378c349dbc7Sjsg
gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device * adev)9379c349dbc7Sjsg static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9380c349dbc7Sjsg {
93815ca02815Sjsg u32 disabled_mask =
93825ca02815Sjsg ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
93835ca02815Sjsg u32 efuse_setting = 0;
93845ca02815Sjsg u32 vbios_setting = 0;
9385c349dbc7Sjsg
93865ca02815Sjsg efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
93875ca02815Sjsg efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
93885ca02815Sjsg efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9389c349dbc7Sjsg
93905ca02815Sjsg vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
93915ca02815Sjsg vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
93925ca02815Sjsg vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9393c349dbc7Sjsg
93945ca02815Sjsg disabled_mask |= efuse_setting | vbios_setting;
93955ca02815Sjsg
93965ca02815Sjsg return (~disabled_mask);
9397c349dbc7Sjsg }
9398c349dbc7Sjsg
gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device * adev)9399c349dbc7Sjsg static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9400c349dbc7Sjsg {
9401c349dbc7Sjsg u32 wgp_idx, wgp_active_bitmap;
9402c349dbc7Sjsg u32 cu_bitmap_per_wgp, cu_active_bitmap;
9403c349dbc7Sjsg
9404c349dbc7Sjsg wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9405c349dbc7Sjsg cu_active_bitmap = 0;
9406c349dbc7Sjsg
9407c349dbc7Sjsg for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9408c349dbc7Sjsg /* if there is one WGP enabled, it means 2 CUs will be enabled */
9409c349dbc7Sjsg cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9410c349dbc7Sjsg if (wgp_active_bitmap & (1 << wgp_idx))
9411c349dbc7Sjsg cu_active_bitmap |= cu_bitmap_per_wgp;
9412c349dbc7Sjsg }
9413c349dbc7Sjsg
9414c349dbc7Sjsg return cu_active_bitmap;
9415c349dbc7Sjsg }
9416c349dbc7Sjsg
gfx_v10_0_get_cu_info(struct amdgpu_device * adev,struct amdgpu_cu_info * cu_info)9417c349dbc7Sjsg static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9418c349dbc7Sjsg struct amdgpu_cu_info *cu_info)
9419c349dbc7Sjsg {
9420c349dbc7Sjsg int i, j, k, counter, active_cu_number = 0;
9421c349dbc7Sjsg u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9422f005ef32Sjsg unsigned int disable_masks[4 * 2];
9423c349dbc7Sjsg
9424c349dbc7Sjsg if (!adev || !cu_info)
9425c349dbc7Sjsg return -EINVAL;
9426c349dbc7Sjsg
9427c349dbc7Sjsg amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9428c349dbc7Sjsg
9429c349dbc7Sjsg mutex_lock(&adev->grbm_idx_mutex);
9430c349dbc7Sjsg for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9431c349dbc7Sjsg for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9432ad8b1aafSjsg bitmap = i * adev->gfx.config.max_sh_per_se + j;
94331bb76ff1Sjsg if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
94341bb76ff1Sjsg (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
94351bb76ff1Sjsg (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6)) ||
94361bb76ff1Sjsg (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 7))) &&
9437ad8b1aafSjsg ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9438ad8b1aafSjsg continue;
9439c349dbc7Sjsg mask = 1;
9440c349dbc7Sjsg ao_bitmap = 0;
9441c349dbc7Sjsg counter = 0;
9442f005ef32Sjsg gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
9443c349dbc7Sjsg if (i < 4 && j < 2)
9444c349dbc7Sjsg gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9445c349dbc7Sjsg adev, disable_masks[i * 2 + j]);
9446c349dbc7Sjsg bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9447f005ef32Sjsg cu_info->bitmap[0][i][j] = bitmap;
9448c349dbc7Sjsg
9449c349dbc7Sjsg for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9450c349dbc7Sjsg if (bitmap & mask) {
9451c349dbc7Sjsg if (counter < adev->gfx.config.max_cu_per_sh)
9452c349dbc7Sjsg ao_bitmap |= mask;
9453c349dbc7Sjsg counter++;
9454c349dbc7Sjsg }
9455c349dbc7Sjsg mask <<= 1;
9456c349dbc7Sjsg }
9457c349dbc7Sjsg active_cu_number += counter;
9458c349dbc7Sjsg if (i < 2 && j < 2)
9459c349dbc7Sjsg ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9460c349dbc7Sjsg cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9461c349dbc7Sjsg }
9462c349dbc7Sjsg }
9463f005ef32Sjsg gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
9464c349dbc7Sjsg mutex_unlock(&adev->grbm_idx_mutex);
9465c349dbc7Sjsg
9466c349dbc7Sjsg cu_info->number = active_cu_number;
9467c349dbc7Sjsg cu_info->ao_cu_mask = ao_cu_mask;
9468c349dbc7Sjsg cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9469c349dbc7Sjsg
9470c349dbc7Sjsg return 0;
9471c349dbc7Sjsg }
9472c349dbc7Sjsg
gfx_v10_3_get_disabled_sa(struct amdgpu_device * adev)9473ad8b1aafSjsg static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9474ad8b1aafSjsg {
9475ad8b1aafSjsg uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9476ad8b1aafSjsg
9477ad8b1aafSjsg efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9478ad8b1aafSjsg efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9479ad8b1aafSjsg efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9480ad8b1aafSjsg
9481ad8b1aafSjsg vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9482ad8b1aafSjsg vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9483ad8b1aafSjsg vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9484ad8b1aafSjsg
9485ad8b1aafSjsg max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9486ad8b1aafSjsg adev->gfx.config.max_shader_engines);
9487ad8b1aafSjsg disabled_sa = efuse_setting | vbios_setting;
9488ad8b1aafSjsg disabled_sa &= max_sa_mask;
9489ad8b1aafSjsg
9490ad8b1aafSjsg return disabled_sa;
9491ad8b1aafSjsg }
9492ad8b1aafSjsg
gfx_v10_3_program_pbb_mode(struct amdgpu_device * adev)9493ad8b1aafSjsg static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9494ad8b1aafSjsg {
9495ad8b1aafSjsg uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9496ad8b1aafSjsg uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9497ad8b1aafSjsg
9498ad8b1aafSjsg disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9499ad8b1aafSjsg
9500ad8b1aafSjsg max_sa_per_se = adev->gfx.config.max_sh_per_se;
9501ad8b1aafSjsg max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9502ad8b1aafSjsg max_shader_engines = adev->gfx.config.max_shader_engines;
9503ad8b1aafSjsg
9504ad8b1aafSjsg for (se_index = 0; max_shader_engines > se_index; se_index++) {
9505ad8b1aafSjsg disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9506ad8b1aafSjsg disabled_sa_per_se &= max_sa_per_se_mask;
9507ad8b1aafSjsg if (disabled_sa_per_se == max_sa_per_se_mask) {
9508ad8b1aafSjsg WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9509ad8b1aafSjsg break;
9510ad8b1aafSjsg }
9511ad8b1aafSjsg }
9512ad8b1aafSjsg }
9513ad8b1aafSjsg
gfx_v10_3_set_power_brake_sequence(struct amdgpu_device * adev)95145ca02815Sjsg static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
95155ca02815Sjsg {
95165ca02815Sjsg WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
95175ca02815Sjsg (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
95185ca02815Sjsg (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
95195ca02815Sjsg (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
95205ca02815Sjsg
95215ca02815Sjsg WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
95225ca02815Sjsg WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
95235ca02815Sjsg (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
95245ca02815Sjsg (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
95255ca02815Sjsg (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
95265ca02815Sjsg (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
95275ca02815Sjsg
95285ca02815Sjsg WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
95295ca02815Sjsg (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
95305ca02815Sjsg (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
95315ca02815Sjsg (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
95325ca02815Sjsg
95335ca02815Sjsg WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
95345ca02815Sjsg
95355ca02815Sjsg WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
95365ca02815Sjsg (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
95375ca02815Sjsg }
95385ca02815Sjsg
9539f005ef32Sjsg const struct amdgpu_ip_block_version gfx_v10_0_ip_block = {
9540c349dbc7Sjsg .type = AMD_IP_BLOCK_TYPE_GFX,
9541c349dbc7Sjsg .major = 10,
9542c349dbc7Sjsg .minor = 0,
9543c349dbc7Sjsg .rev = 0,
9544c349dbc7Sjsg .funcs = &gfx_v10_0_ip_funcs,
9545c349dbc7Sjsg };
9546