1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_gfx.h" 32 #include "soc15.h" 33 #include "soc15d.h" 34 #include "amdgpu_atomfirmware.h" 35 #include "amdgpu_pm.h" 36 37 #include "gc/gc_9_0_offset.h" 38 #include "gc/gc_9_0_sh_mask.h" 39 40 #include "vega10_enum.h" 41 42 #include "soc15_common.h" 43 #include "clearstate_gfx9.h" 44 #include "v9_structs.h" 45 46 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 47 48 #include "amdgpu_ras.h" 49 50 #include "gfx_v9_4.h" 51 #include "gfx_v9_0.h" 52 #include "gfx_v9_4_2.h" 53 54 #include "asic_reg/pwr/pwr_10_0_offset.h" 55 #include "asic_reg/pwr/pwr_10_0_sh_mask.h" 56 #include "asic_reg/gc/gc_9_0_default.h" 57 58 #define GFX9_NUM_GFX_RINGS 1 59 #define GFX9_MEC_HPD_SIZE 4096 60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 61 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L 62 63 #define mmGCEA_PROBE_MAP 0x070c 64 #define mmGCEA_PROBE_MAP_BASE_IDX 0 65 66 MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); 67 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); 68 MODULE_FIRMWARE("amdgpu/vega10_me.bin"); 69 MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); 70 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); 71 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); 72 73 MODULE_FIRMWARE("amdgpu/vega12_ce.bin"); 74 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin"); 75 MODULE_FIRMWARE("amdgpu/vega12_me.bin"); 76 MODULE_FIRMWARE("amdgpu/vega12_mec.bin"); 77 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin"); 78 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin"); 79 80 MODULE_FIRMWARE("amdgpu/vega20_ce.bin"); 81 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin"); 82 MODULE_FIRMWARE("amdgpu/vega20_me.bin"); 83 MODULE_FIRMWARE("amdgpu/vega20_mec.bin"); 84 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin"); 85 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin"); 86 87 MODULE_FIRMWARE("amdgpu/raven_ce.bin"); 88 MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); 89 MODULE_FIRMWARE("amdgpu/raven_me.bin"); 90 MODULE_FIRMWARE("amdgpu/raven_mec.bin"); 91 MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); 92 MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); 93 94 MODULE_FIRMWARE("amdgpu/picasso_ce.bin"); 95 MODULE_FIRMWARE("amdgpu/picasso_pfp.bin"); 96 MODULE_FIRMWARE("amdgpu/picasso_me.bin"); 97 MODULE_FIRMWARE("amdgpu/picasso_mec.bin"); 98 MODULE_FIRMWARE("amdgpu/picasso_mec2.bin"); 99 MODULE_FIRMWARE("amdgpu/picasso_rlc.bin"); 100 MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin"); 101 102 MODULE_FIRMWARE("amdgpu/raven2_ce.bin"); 103 MODULE_FIRMWARE("amdgpu/raven2_pfp.bin"); 104 MODULE_FIRMWARE("amdgpu/raven2_me.bin"); 105 MODULE_FIRMWARE("amdgpu/raven2_mec.bin"); 106 MODULE_FIRMWARE("amdgpu/raven2_mec2.bin"); 107 MODULE_FIRMWARE("amdgpu/raven2_rlc.bin"); 108 MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin"); 109 110 MODULE_FIRMWARE("amdgpu/arcturus_mec.bin"); 111 MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin"); 112 113 MODULE_FIRMWARE("amdgpu/renoir_ce.bin"); 114 MODULE_FIRMWARE("amdgpu/renoir_pfp.bin"); 115 MODULE_FIRMWARE("amdgpu/renoir_me.bin"); 116 MODULE_FIRMWARE("amdgpu/renoir_mec.bin"); 117 MODULE_FIRMWARE("amdgpu/renoir_rlc.bin"); 118 119 MODULE_FIRMWARE("amdgpu/green_sardine_ce.bin"); 120 MODULE_FIRMWARE("amdgpu/green_sardine_pfp.bin"); 121 MODULE_FIRMWARE("amdgpu/green_sardine_me.bin"); 122 MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin"); 123 MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin"); 124 MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin"); 125 126 MODULE_FIRMWARE("amdgpu/aldebaran_mec.bin"); 127 MODULE_FIRMWARE("amdgpu/aldebaran_mec2.bin"); 128 MODULE_FIRMWARE("amdgpu/aldebaran_rlc.bin"); 129 MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec.bin"); 130 MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec2.bin"); 131 132 #define mmTCP_CHAN_STEER_0_ARCT 0x0b03 133 #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0 134 #define mmTCP_CHAN_STEER_1_ARCT 0x0b04 135 #define mmTCP_CHAN_STEER_1_ARCT_BASE_IDX 0 136 #define mmTCP_CHAN_STEER_2_ARCT 0x0b09 137 #define mmTCP_CHAN_STEER_2_ARCT_BASE_IDX 0 138 #define mmTCP_CHAN_STEER_3_ARCT 0x0b0a 139 #define mmTCP_CHAN_STEER_3_ARCT_BASE_IDX 0 140 #define mmTCP_CHAN_STEER_4_ARCT 0x0b0b 141 #define mmTCP_CHAN_STEER_4_ARCT_BASE_IDX 0 142 #define mmTCP_CHAN_STEER_5_ARCT 0x0b0c 143 #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX 0 144 145 #define mmGOLDEN_TSC_COUNT_UPPER_Renoir 0x0025 146 #define mmGOLDEN_TSC_COUNT_UPPER_Renoir_BASE_IDX 1 147 #define mmGOLDEN_TSC_COUNT_LOWER_Renoir 0x0026 148 #define mmGOLDEN_TSC_COUNT_LOWER_Renoir_BASE_IDX 1 149 150 enum ta_ras_gfx_subblock { 151 /*CPC*/ 152 TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0, 153 TA_RAS_BLOCK__GFX_CPC_SCRATCH = TA_RAS_BLOCK__GFX_CPC_INDEX_START, 154 TA_RAS_BLOCK__GFX_CPC_UCODE, 155 TA_RAS_BLOCK__GFX_DC_STATE_ME1, 156 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1, 157 TA_RAS_BLOCK__GFX_DC_RESTORE_ME1, 158 TA_RAS_BLOCK__GFX_DC_STATE_ME2, 159 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2, 160 TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, 161 TA_RAS_BLOCK__GFX_CPC_INDEX_END = TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, 162 /* CPF*/ 163 TA_RAS_BLOCK__GFX_CPF_INDEX_START, 164 TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 = TA_RAS_BLOCK__GFX_CPF_INDEX_START, 165 TA_RAS_BLOCK__GFX_CPF_ROQ_ME1, 166 TA_RAS_BLOCK__GFX_CPF_TAG, 167 TA_RAS_BLOCK__GFX_CPF_INDEX_END = TA_RAS_BLOCK__GFX_CPF_TAG, 168 /* CPG*/ 169 TA_RAS_BLOCK__GFX_CPG_INDEX_START, 170 TA_RAS_BLOCK__GFX_CPG_DMA_ROQ = TA_RAS_BLOCK__GFX_CPG_INDEX_START, 171 TA_RAS_BLOCK__GFX_CPG_DMA_TAG, 172 TA_RAS_BLOCK__GFX_CPG_TAG, 173 TA_RAS_BLOCK__GFX_CPG_INDEX_END = TA_RAS_BLOCK__GFX_CPG_TAG, 174 /* GDS*/ 175 TA_RAS_BLOCK__GFX_GDS_INDEX_START, 176 TA_RAS_BLOCK__GFX_GDS_MEM = TA_RAS_BLOCK__GFX_GDS_INDEX_START, 177 TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, 178 TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, 179 TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, 180 TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 181 TA_RAS_BLOCK__GFX_GDS_INDEX_END = TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 182 /* SPI*/ 183 TA_RAS_BLOCK__GFX_SPI_SR_MEM, 184 /* SQ*/ 185 TA_RAS_BLOCK__GFX_SQ_INDEX_START, 186 TA_RAS_BLOCK__GFX_SQ_SGPR = TA_RAS_BLOCK__GFX_SQ_INDEX_START, 187 TA_RAS_BLOCK__GFX_SQ_LDS_D, 188 TA_RAS_BLOCK__GFX_SQ_LDS_I, 189 TA_RAS_BLOCK__GFX_SQ_VGPR, /* VGPR = SP*/ 190 TA_RAS_BLOCK__GFX_SQ_INDEX_END = TA_RAS_BLOCK__GFX_SQ_VGPR, 191 /* SQC (3 ranges)*/ 192 TA_RAS_BLOCK__GFX_SQC_INDEX_START, 193 /* SQC range 0*/ 194 TA_RAS_BLOCK__GFX_SQC_INDEX0_START = TA_RAS_BLOCK__GFX_SQC_INDEX_START, 195 TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = 196 TA_RAS_BLOCK__GFX_SQC_INDEX0_START, 197 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 198 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, 199 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 200 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, 201 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 202 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 203 TA_RAS_BLOCK__GFX_SQC_INDEX0_END = 204 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 205 /* SQC range 1*/ 206 TA_RAS_BLOCK__GFX_SQC_INDEX1_START, 207 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = 208 TA_RAS_BLOCK__GFX_SQC_INDEX1_START, 209 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 210 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, 211 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, 212 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, 213 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, 214 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, 215 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 216 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 217 TA_RAS_BLOCK__GFX_SQC_INDEX1_END = 218 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 219 /* SQC range 2*/ 220 TA_RAS_BLOCK__GFX_SQC_INDEX2_START, 221 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = 222 TA_RAS_BLOCK__GFX_SQC_INDEX2_START, 223 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 224 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, 225 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, 226 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, 227 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, 228 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, 229 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 230 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 231 TA_RAS_BLOCK__GFX_SQC_INDEX2_END = 232 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 233 TA_RAS_BLOCK__GFX_SQC_INDEX_END = TA_RAS_BLOCK__GFX_SQC_INDEX2_END, 234 /* TA*/ 235 TA_RAS_BLOCK__GFX_TA_INDEX_START, 236 TA_RAS_BLOCK__GFX_TA_FS_DFIFO = TA_RAS_BLOCK__GFX_TA_INDEX_START, 237 TA_RAS_BLOCK__GFX_TA_FS_AFIFO, 238 TA_RAS_BLOCK__GFX_TA_FL_LFIFO, 239 TA_RAS_BLOCK__GFX_TA_FX_LFIFO, 240 TA_RAS_BLOCK__GFX_TA_FS_CFIFO, 241 TA_RAS_BLOCK__GFX_TA_INDEX_END = TA_RAS_BLOCK__GFX_TA_FS_CFIFO, 242 /* TCA*/ 243 TA_RAS_BLOCK__GFX_TCA_INDEX_START, 244 TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO = TA_RAS_BLOCK__GFX_TCA_INDEX_START, 245 TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, 246 TA_RAS_BLOCK__GFX_TCA_INDEX_END = TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, 247 /* TCC (5 sub-ranges)*/ 248 TA_RAS_BLOCK__GFX_TCC_INDEX_START, 249 /* TCC range 0*/ 250 TA_RAS_BLOCK__GFX_TCC_INDEX0_START = TA_RAS_BLOCK__GFX_TCC_INDEX_START, 251 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX0_START, 252 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, 253 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, 254 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, 255 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, 256 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, 257 TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, 258 TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 259 TA_RAS_BLOCK__GFX_TCC_INDEX0_END = TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 260 /* TCC range 1*/ 261 TA_RAS_BLOCK__GFX_TCC_INDEX1_START, 262 TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC = TA_RAS_BLOCK__GFX_TCC_INDEX1_START, 263 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 264 TA_RAS_BLOCK__GFX_TCC_INDEX1_END = 265 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 266 /* TCC range 2*/ 267 TA_RAS_BLOCK__GFX_TCC_INDEX2_START, 268 TA_RAS_BLOCK__GFX_TCC_RETURN_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX2_START, 269 TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, 270 TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, 271 TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN, 272 TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, 273 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO, 274 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, 275 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 276 TA_RAS_BLOCK__GFX_TCC_INDEX2_END = 277 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 278 /* TCC range 3*/ 279 TA_RAS_BLOCK__GFX_TCC_INDEX3_START, 280 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = TA_RAS_BLOCK__GFX_TCC_INDEX3_START, 281 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 282 TA_RAS_BLOCK__GFX_TCC_INDEX3_END = 283 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 284 /* TCC range 4*/ 285 TA_RAS_BLOCK__GFX_TCC_INDEX4_START, 286 TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = 287 TA_RAS_BLOCK__GFX_TCC_INDEX4_START, 288 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 289 TA_RAS_BLOCK__GFX_TCC_INDEX4_END = 290 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 291 TA_RAS_BLOCK__GFX_TCC_INDEX_END = TA_RAS_BLOCK__GFX_TCC_INDEX4_END, 292 /* TCI*/ 293 TA_RAS_BLOCK__GFX_TCI_WRITE_RAM, 294 /* TCP*/ 295 TA_RAS_BLOCK__GFX_TCP_INDEX_START, 296 TA_RAS_BLOCK__GFX_TCP_CACHE_RAM = TA_RAS_BLOCK__GFX_TCP_INDEX_START, 297 TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM, 298 TA_RAS_BLOCK__GFX_TCP_CMD_FIFO, 299 TA_RAS_BLOCK__GFX_TCP_VM_FIFO, 300 TA_RAS_BLOCK__GFX_TCP_DB_RAM, 301 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, 302 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 303 TA_RAS_BLOCK__GFX_TCP_INDEX_END = TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 304 /* TD*/ 305 TA_RAS_BLOCK__GFX_TD_INDEX_START, 306 TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO = TA_RAS_BLOCK__GFX_TD_INDEX_START, 307 TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI, 308 TA_RAS_BLOCK__GFX_TD_CS_FIFO, 309 TA_RAS_BLOCK__GFX_TD_INDEX_END = TA_RAS_BLOCK__GFX_TD_CS_FIFO, 310 /* EA (3 sub-ranges)*/ 311 TA_RAS_BLOCK__GFX_EA_INDEX_START, 312 /* EA range 0*/ 313 TA_RAS_BLOCK__GFX_EA_INDEX0_START = TA_RAS_BLOCK__GFX_EA_INDEX_START, 314 TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = TA_RAS_BLOCK__GFX_EA_INDEX0_START, 315 TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, 316 TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, 317 TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM, 318 TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM, 319 TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, 320 TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, 321 TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 322 TA_RAS_BLOCK__GFX_EA_INDEX0_END = TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 323 /* EA range 1*/ 324 TA_RAS_BLOCK__GFX_EA_INDEX1_START, 325 TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = TA_RAS_BLOCK__GFX_EA_INDEX1_START, 326 TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, 327 TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM, 328 TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, 329 TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, 330 TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, 331 TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 332 TA_RAS_BLOCK__GFX_EA_INDEX1_END = TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 333 /* EA range 2*/ 334 TA_RAS_BLOCK__GFX_EA_INDEX2_START, 335 TA_RAS_BLOCK__GFX_EA_MAM_D0MEM = TA_RAS_BLOCK__GFX_EA_INDEX2_START, 336 TA_RAS_BLOCK__GFX_EA_MAM_D1MEM, 337 TA_RAS_BLOCK__GFX_EA_MAM_D2MEM, 338 TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, 339 TA_RAS_BLOCK__GFX_EA_INDEX2_END = TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, 340 TA_RAS_BLOCK__GFX_EA_INDEX_END = TA_RAS_BLOCK__GFX_EA_INDEX2_END, 341 /* UTC VM L2 bank*/ 342 TA_RAS_BLOCK__UTC_VML2_BANK_CACHE, 343 /* UTC VM walker*/ 344 TA_RAS_BLOCK__UTC_VML2_WALKER, 345 /* UTC ATC L2 2MB cache*/ 346 TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, 347 /* UTC ATC L2 4KB cache*/ 348 TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, 349 TA_RAS_BLOCK__GFX_MAX 350 }; 351 352 struct ras_gfx_subblock { 353 unsigned char *name; 354 int ta_subblock; 355 int hw_supported_error_type; 356 int sw_supported_error_type; 357 }; 358 359 #define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h) \ 360 [AMDGPU_RAS_BLOCK__##subblock] = { \ 361 #subblock, \ 362 TA_RAS_BLOCK__##subblock, \ 363 ((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)), \ 364 (((e) << 1) | ((f) << 3) | (g) | ((h) << 2)), \ 365 } 366 367 static const struct ras_gfx_subblock ras_gfx_subblocks[] = { 368 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1, 1, 0, 0, 1), 369 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1, 1, 0, 0, 1), 370 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1, 0, 0, 1, 0), 371 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1, 0, 0, 0, 0), 372 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1, 0, 0, 0, 0), 373 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 374 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 375 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 376 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 377 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1, 0, 0, 1, 0), 378 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1, 1, 0, 0, 1), 379 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1, 0, 0, 1, 0), 380 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1, 0, 1, 0, 1), 381 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1, 1, 1, 0, 1), 382 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1, 0, 0, 0, 0), 383 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1, 0, 0, 0, 0), 384 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1, 0, 0, 0, 385 0), 386 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1, 0, 0, 0, 387 0), 388 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1, 0, 0, 0, 0), 389 AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1, 0, 0, 0, 0), 390 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1, 0, 0, 0, 0), 391 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1, 1, 0, 0, 1), 392 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1, 0, 0, 0, 0), 393 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1, 0, 0, 0, 0), 394 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 1), 395 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 396 0, 0), 397 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 398 0), 399 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 400 0, 0), 401 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1, 1, 0, 0, 402 0), 403 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 404 0, 0), 405 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 406 0), 407 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, 408 1), 409 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, 410 0, 0, 0), 411 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 412 0), 413 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 414 0), 415 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, 416 0), 417 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, 418 0), 419 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 420 0), 421 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, 422 0, 0), 423 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 424 0), 425 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, 426 0), 427 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, 428 0, 0, 0), 429 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 430 0), 431 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 432 0), 433 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, 434 0), 435 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, 436 0), 437 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 438 0), 439 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, 440 0, 0), 441 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 442 0), 443 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1, 1, 0, 0, 1), 444 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 445 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 446 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 447 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 448 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1, 0, 1, 1, 0), 449 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 450 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1, 1, 0, 0, 1), 451 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1, 1, 0, 0, 452 1), 453 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1, 1, 0, 0, 454 1), 455 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1, 1, 0, 0, 456 1), 457 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1, 0, 0, 0, 458 0), 459 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1, 0, 0, 0, 460 0), 461 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), 462 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), 463 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1, 0, 0, 0, 0), 464 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1, 0, 0, 0, 0), 465 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1, 0, 0, 0, 0), 466 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1, 0, 0, 0, 0), 467 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 468 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1, 0, 1, 1, 0), 469 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1, 0, 0, 0, 0), 470 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), 471 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 1, 0), 472 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1, 0, 0, 0, 473 0), 474 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 475 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 0, 476 0), 477 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1, 0, 0, 478 0, 0), 479 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1, 0, 0, 0, 480 0), 481 AMDGPU_RAS_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1, 0, 0, 0, 0), 482 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1, 1, 0, 0, 1), 483 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1, 0, 0, 0, 0), 484 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 485 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), 486 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1, 0, 0, 0, 0), 487 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1, 0, 0, 0, 0), 488 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1, 0, 0, 0, 0), 489 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1, 1, 0, 0, 1), 490 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1, 0, 0, 0, 0), 491 AMDGPU_RAS_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 492 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1, 1, 0, 0, 1), 493 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 494 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), 495 AMDGPU_RAS_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), 496 AMDGPU_RAS_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), 497 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 498 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 499 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), 500 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 501 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 502 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), 503 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), 504 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1, 0, 0, 0, 0), 505 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 506 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 507 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1, 0, 0, 0, 0), 508 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1, 0, 0, 0, 0), 509 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1, 0, 0, 0, 0), 510 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1, 0, 0, 0, 0), 511 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1, 0, 0, 0, 0), 512 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1, 0, 0, 0, 0), 513 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1, 0, 0, 0, 0), 514 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1, 0, 0, 0, 0), 515 }; 516 517 static const struct soc15_reg_golden golden_settings_gc_9_0[] = 518 { 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x00ffff87), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x00ffff8f), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 539 }; 540 541 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = 542 { 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080) 561 }; 562 563 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] = 564 { 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000) 576 }; 577 578 static const struct soc15_reg_golden golden_settings_gc_9_1[] = 579 { 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 604 }; 605 606 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] = 607 { 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800) 615 }; 616 617 static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] = 618 { 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080), 638 }; 639 640 static const struct soc15_reg_golden golden_settings_gc_9_1_rn[] = 641 { 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x24000042), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x24000042), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_PROBE_MAP, 0xffffffff, 0x0000cccc), 654 }; 655 656 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] = 657 { 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0xffffffff, 0x000001ff), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382) 661 }; 662 663 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] = 664 { 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff) 681 }; 682 683 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] = 684 { 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 698 }; 699 700 static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] = 701 { 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_0_ARCT, 0x3fffffff, 0x346f0a4e), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_1_ARCT, 0x3fffffff, 0x1c642ca), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_2_ARCT, 0x3fffffff, 0x26f45098), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_UTCL1_CNTL1, 0x30000000, 0x30000000) 713 }; 714 715 static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = { 716 {SOC15_REG_ENTRY(GC, 0, mmGRBM_GFX_INDEX)}, 717 {SOC15_REG_ENTRY(GC, 0, mmSQ_IND_INDEX)}, 718 }; 719 720 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] = 721 { 722 mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 723 mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 724 mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 725 mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 726 mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 727 mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 728 mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 729 mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 730 }; 731 732 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] = 733 { 734 mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0, 735 mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0, 736 mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0, 737 mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0, 738 mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0, 739 mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0, 740 mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0, 741 mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0, 742 }; 743 744 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 745 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041 746 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042 747 #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041 748 749 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); 750 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev); 751 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev); 752 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev); 753 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 754 struct amdgpu_cu_info *cu_info); 755 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); 756 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring); 757 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring); 758 static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, 759 void *ras_error_status); 760 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, 761 void *inject_if); 762 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev); 763 764 static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 765 uint64_t queue_mask) 766 { 767 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 768 amdgpu_ring_write(kiq_ring, 769 PACKET3_SET_RESOURCES_VMID_MASK(0) | 770 /* vmid_mask:0* queue_type:0 (KIQ) */ 771 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 772 amdgpu_ring_write(kiq_ring, 773 lower_32_bits(queue_mask)); /* queue mask lo */ 774 amdgpu_ring_write(kiq_ring, 775 upper_32_bits(queue_mask)); /* queue mask hi */ 776 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 777 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 778 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 779 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 780 } 781 782 static void gfx_v9_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 783 struct amdgpu_ring *ring) 784 { 785 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 786 uint64_t wptr_addr = ring->wptr_gpu_addr; 787 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 788 789 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 790 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 791 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 792 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 793 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 794 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 795 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 796 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 797 /*queue_type: normal compute queue */ 798 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 799 /* alloc format: all_on_one_pipe */ 800 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 801 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 802 /* num_queues: must be 1 */ 803 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 804 amdgpu_ring_write(kiq_ring, 805 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 806 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 807 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 808 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 809 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 810 } 811 812 static void gfx_v9_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 813 struct amdgpu_ring *ring, 814 enum amdgpu_unmap_queues_action action, 815 u64 gpu_addr, u64 seq) 816 { 817 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 818 819 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 820 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 821 PACKET3_UNMAP_QUEUES_ACTION(action) | 822 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 823 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 824 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 825 amdgpu_ring_write(kiq_ring, 826 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 827 828 if (action == PREEMPT_QUEUES_NO_UNMAP) { 829 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 830 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 831 amdgpu_ring_write(kiq_ring, seq); 832 } else { 833 amdgpu_ring_write(kiq_ring, 0); 834 amdgpu_ring_write(kiq_ring, 0); 835 amdgpu_ring_write(kiq_ring, 0); 836 } 837 } 838 839 static void gfx_v9_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 840 struct amdgpu_ring *ring, 841 u64 addr, 842 u64 seq) 843 { 844 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 845 846 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 847 amdgpu_ring_write(kiq_ring, 848 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 849 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 850 PACKET3_QUERY_STATUS_COMMAND(2)); 851 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 852 amdgpu_ring_write(kiq_ring, 853 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 854 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 855 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 856 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 857 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 858 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 859 } 860 861 static void gfx_v9_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 862 uint16_t pasid, uint32_t flush_type, 863 bool all_hub) 864 { 865 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 866 amdgpu_ring_write(kiq_ring, 867 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 868 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 869 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 870 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 871 } 872 873 static const struct kiq_pm4_funcs gfx_v9_0_kiq_pm4_funcs = { 874 .kiq_set_resources = gfx_v9_0_kiq_set_resources, 875 .kiq_map_queues = gfx_v9_0_kiq_map_queues, 876 .kiq_unmap_queues = gfx_v9_0_kiq_unmap_queues, 877 .kiq_query_status = gfx_v9_0_kiq_query_status, 878 .kiq_invalidate_tlbs = gfx_v9_0_kiq_invalidate_tlbs, 879 .set_resources_size = 8, 880 .map_queues_size = 7, 881 .unmap_queues_size = 6, 882 .query_status_size = 7, 883 .invalidate_tlbs_size = 2, 884 }; 885 886 static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 887 { 888 adev->gfx.kiq.pmf = &gfx_v9_0_kiq_pm4_funcs; 889 } 890 891 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) 892 { 893 switch (adev->ip_versions[GC_HWIP][0]) { 894 case IP_VERSION(9, 0, 1): 895 soc15_program_register_sequence(adev, 896 golden_settings_gc_9_0, 897 ARRAY_SIZE(golden_settings_gc_9_0)); 898 soc15_program_register_sequence(adev, 899 golden_settings_gc_9_0_vg10, 900 ARRAY_SIZE(golden_settings_gc_9_0_vg10)); 901 break; 902 case IP_VERSION(9, 2, 1): 903 soc15_program_register_sequence(adev, 904 golden_settings_gc_9_2_1, 905 ARRAY_SIZE(golden_settings_gc_9_2_1)); 906 soc15_program_register_sequence(adev, 907 golden_settings_gc_9_2_1_vg12, 908 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12)); 909 break; 910 case IP_VERSION(9, 4, 0): 911 soc15_program_register_sequence(adev, 912 golden_settings_gc_9_0, 913 ARRAY_SIZE(golden_settings_gc_9_0)); 914 soc15_program_register_sequence(adev, 915 golden_settings_gc_9_0_vg20, 916 ARRAY_SIZE(golden_settings_gc_9_0_vg20)); 917 break; 918 case IP_VERSION(9, 4, 1): 919 soc15_program_register_sequence(adev, 920 golden_settings_gc_9_4_1_arct, 921 ARRAY_SIZE(golden_settings_gc_9_4_1_arct)); 922 break; 923 case IP_VERSION(9, 2, 2): 924 case IP_VERSION(9, 1, 0): 925 soc15_program_register_sequence(adev, golden_settings_gc_9_1, 926 ARRAY_SIZE(golden_settings_gc_9_1)); 927 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 928 soc15_program_register_sequence(adev, 929 golden_settings_gc_9_1_rv2, 930 ARRAY_SIZE(golden_settings_gc_9_1_rv2)); 931 else 932 soc15_program_register_sequence(adev, 933 golden_settings_gc_9_1_rv1, 934 ARRAY_SIZE(golden_settings_gc_9_1_rv1)); 935 break; 936 case IP_VERSION(9, 3, 0): 937 soc15_program_register_sequence(adev, 938 golden_settings_gc_9_1_rn, 939 ARRAY_SIZE(golden_settings_gc_9_1_rn)); 940 return; /* for renoir, don't need common goldensetting */ 941 case IP_VERSION(9, 4, 2): 942 gfx_v9_4_2_init_golden_registers(adev, 943 adev->smuio.funcs->get_die_id(adev)); 944 break; 945 default: 946 break; 947 } 948 949 if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) && 950 (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2))) 951 soc15_program_register_sequence(adev, golden_settings_gc_9_x_common, 952 (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common)); 953 } 954 955 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 956 bool wc, uint32_t reg, uint32_t val) 957 { 958 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 959 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 960 WRITE_DATA_DST_SEL(0) | 961 (wc ? WR_CONFIRM : 0)); 962 amdgpu_ring_write(ring, reg); 963 amdgpu_ring_write(ring, 0); 964 amdgpu_ring_write(ring, val); 965 } 966 967 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 968 int mem_space, int opt, uint32_t addr0, 969 uint32_t addr1, uint32_t ref, uint32_t mask, 970 uint32_t inv) 971 { 972 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 973 amdgpu_ring_write(ring, 974 /* memory (1) or register (0) */ 975 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 976 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 977 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 978 WAIT_REG_MEM_ENGINE(eng_sel))); 979 980 if (mem_space) 981 BUG_ON(addr0 & 0x3); /* Dword align */ 982 amdgpu_ring_write(ring, addr0); 983 amdgpu_ring_write(ring, addr1); 984 amdgpu_ring_write(ring, ref); 985 amdgpu_ring_write(ring, mask); 986 amdgpu_ring_write(ring, inv); /* poll interval */ 987 } 988 989 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring) 990 { 991 struct amdgpu_device *adev = ring->adev; 992 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 993 uint32_t tmp = 0; 994 unsigned i; 995 int r; 996 997 WREG32(scratch, 0xCAFEDEAD); 998 r = amdgpu_ring_alloc(ring, 3); 999 if (r) 1000 return r; 1001 1002 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 1003 amdgpu_ring_write(ring, scratch - PACKET3_SET_UCONFIG_REG_START); 1004 amdgpu_ring_write(ring, 0xDEADBEEF); 1005 amdgpu_ring_commit(ring); 1006 1007 for (i = 0; i < adev->usec_timeout; i++) { 1008 tmp = RREG32(scratch); 1009 if (tmp == 0xDEADBEEF) 1010 break; 1011 udelay(1); 1012 } 1013 1014 if (i >= adev->usec_timeout) 1015 r = -ETIMEDOUT; 1016 return r; 1017 } 1018 1019 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1020 { 1021 struct amdgpu_device *adev = ring->adev; 1022 struct amdgpu_ib ib; 1023 struct dma_fence *f = NULL; 1024 1025 unsigned index; 1026 uint64_t gpu_addr; 1027 uint32_t tmp; 1028 long r; 1029 1030 r = amdgpu_device_wb_get(adev, &index); 1031 if (r) 1032 return r; 1033 1034 gpu_addr = adev->wb.gpu_addr + (index * 4); 1035 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 1036 memset(&ib, 0, sizeof(ib)); 1037 r = amdgpu_ib_get(adev, NULL, 16, 1038 AMDGPU_IB_POOL_DIRECT, &ib); 1039 if (r) 1040 goto err1; 1041 1042 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 1043 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 1044 ib.ptr[2] = lower_32_bits(gpu_addr); 1045 ib.ptr[3] = upper_32_bits(gpu_addr); 1046 ib.ptr[4] = 0xDEADBEEF; 1047 ib.length_dw = 5; 1048 1049 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1050 if (r) 1051 goto err2; 1052 1053 r = dma_fence_wait_timeout(f, false, timeout); 1054 if (r == 0) { 1055 r = -ETIMEDOUT; 1056 goto err2; 1057 } else if (r < 0) { 1058 goto err2; 1059 } 1060 1061 tmp = adev->wb.wb[index]; 1062 if (tmp == 0xDEADBEEF) 1063 r = 0; 1064 else 1065 r = -EINVAL; 1066 1067 err2: 1068 amdgpu_ib_free(adev, &ib, NULL); 1069 dma_fence_put(f); 1070 err1: 1071 amdgpu_device_wb_free(adev, index); 1072 return r; 1073 } 1074 1075 1076 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev) 1077 { 1078 release_firmware(adev->gfx.pfp_fw); 1079 adev->gfx.pfp_fw = NULL; 1080 release_firmware(adev->gfx.me_fw); 1081 adev->gfx.me_fw = NULL; 1082 release_firmware(adev->gfx.ce_fw); 1083 adev->gfx.ce_fw = NULL; 1084 release_firmware(adev->gfx.rlc_fw); 1085 adev->gfx.rlc_fw = NULL; 1086 release_firmware(adev->gfx.mec_fw); 1087 adev->gfx.mec_fw = NULL; 1088 release_firmware(adev->gfx.mec2_fw); 1089 adev->gfx.mec2_fw = NULL; 1090 1091 kfree(adev->gfx.rlc.register_list_format); 1092 } 1093 1094 static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev) 1095 { 1096 adev->gfx.me_fw_write_wait = false; 1097 adev->gfx.mec_fw_write_wait = false; 1098 1099 if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) && 1100 ((adev->gfx.mec_fw_version < 0x000001a5) || 1101 (adev->gfx.mec_feature_version < 46) || 1102 (adev->gfx.pfp_fw_version < 0x000000b7) || 1103 (adev->gfx.pfp_feature_version < 46))) 1104 DRM_WARN_ONCE("CP firmware version too old, please update!"); 1105 1106 switch (adev->ip_versions[GC_HWIP][0]) { 1107 case IP_VERSION(9, 0, 1): 1108 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1109 (adev->gfx.me_feature_version >= 42) && 1110 (adev->gfx.pfp_fw_version >= 0x000000b1) && 1111 (adev->gfx.pfp_feature_version >= 42)) 1112 adev->gfx.me_fw_write_wait = true; 1113 1114 if ((adev->gfx.mec_fw_version >= 0x00000193) && 1115 (adev->gfx.mec_feature_version >= 42)) 1116 adev->gfx.mec_fw_write_wait = true; 1117 break; 1118 case IP_VERSION(9, 2, 1): 1119 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1120 (adev->gfx.me_feature_version >= 44) && 1121 (adev->gfx.pfp_fw_version >= 0x000000b2) && 1122 (adev->gfx.pfp_feature_version >= 44)) 1123 adev->gfx.me_fw_write_wait = true; 1124 1125 if ((adev->gfx.mec_fw_version >= 0x00000196) && 1126 (adev->gfx.mec_feature_version >= 44)) 1127 adev->gfx.mec_fw_write_wait = true; 1128 break; 1129 case IP_VERSION(9, 4, 0): 1130 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1131 (adev->gfx.me_feature_version >= 44) && 1132 (adev->gfx.pfp_fw_version >= 0x000000b2) && 1133 (adev->gfx.pfp_feature_version >= 44)) 1134 adev->gfx.me_fw_write_wait = true; 1135 1136 if ((adev->gfx.mec_fw_version >= 0x00000197) && 1137 (adev->gfx.mec_feature_version >= 44)) 1138 adev->gfx.mec_fw_write_wait = true; 1139 break; 1140 case IP_VERSION(9, 1, 0): 1141 case IP_VERSION(9, 2, 2): 1142 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1143 (adev->gfx.me_feature_version >= 42) && 1144 (adev->gfx.pfp_fw_version >= 0x000000b1) && 1145 (adev->gfx.pfp_feature_version >= 42)) 1146 adev->gfx.me_fw_write_wait = true; 1147 1148 if ((adev->gfx.mec_fw_version >= 0x00000192) && 1149 (adev->gfx.mec_feature_version >= 42)) 1150 adev->gfx.mec_fw_write_wait = true; 1151 break; 1152 default: 1153 adev->gfx.me_fw_write_wait = true; 1154 adev->gfx.mec_fw_write_wait = true; 1155 break; 1156 } 1157 } 1158 1159 struct amdgpu_gfxoff_quirk { 1160 u16 chip_vendor; 1161 u16 chip_device; 1162 u16 subsys_vendor; 1163 u16 subsys_device; 1164 u8 revision; 1165 }; 1166 1167 static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = { 1168 /* https://bugzilla.kernel.org/show_bug.cgi?id=204689 */ 1169 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, 1170 /* https://bugzilla.kernel.org/show_bug.cgi?id=207171 */ 1171 { 0x1002, 0x15dd, 0x103c, 0x83e7, 0xd3 }, 1172 /* GFXOFF is unstable on C6 parts with a VBIOS 113-RAVEN-114 */ 1173 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 }, 1174 /* Apple MacBook Pro (15-inch, 2019) Radeon Pro Vega 20 4 GB */ 1175 { 0x1002, 0x69af, 0x106b, 0x019a, 0xc0 }, 1176 { 0, 0, 0, 0, 0 }, 1177 }; 1178 1179 static bool gfx_v9_0_should_disable_gfxoff(struct pci_dev *pdev) 1180 { 1181 const struct amdgpu_gfxoff_quirk *p = amdgpu_gfxoff_quirk_list; 1182 1183 while (p && p->chip_device != 0) { 1184 if (pdev->vendor == p->chip_vendor && 1185 pdev->device == p->chip_device && 1186 pdev->subsystem_vendor == p->subsys_vendor && 1187 pdev->subsystem_device == p->subsys_device && 1188 pdev->revision == p->revision) { 1189 return true; 1190 } 1191 ++p; 1192 } 1193 return false; 1194 } 1195 1196 static bool is_raven_kicker(struct amdgpu_device *adev) 1197 { 1198 if (adev->pm.fw_version >= 0x41e2b) 1199 return true; 1200 else 1201 return false; 1202 } 1203 1204 static bool check_if_enlarge_doorbell_range(struct amdgpu_device *adev) 1205 { 1206 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) && 1207 (adev->gfx.me_fw_version >= 0x000000a5) && 1208 (adev->gfx.me_feature_version >= 52)) 1209 return true; 1210 else 1211 return false; 1212 } 1213 1214 static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev) 1215 { 1216 if (gfx_v9_0_should_disable_gfxoff(adev->pdev)) 1217 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1218 1219 switch (adev->ip_versions[GC_HWIP][0]) { 1220 case IP_VERSION(9, 0, 1): 1221 case IP_VERSION(9, 2, 1): 1222 case IP_VERSION(9, 4, 0): 1223 break; 1224 case IP_VERSION(9, 2, 2): 1225 case IP_VERSION(9, 1, 0): 1226 if (!((adev->apu_flags & AMD_APU_IS_RAVEN2) || 1227 (adev->apu_flags & AMD_APU_IS_PICASSO)) && 1228 ((!is_raven_kicker(adev) && 1229 adev->gfx.rlc_fw_version < 531) || 1230 (adev->gfx.rlc_feature_version < 1) || 1231 !adev->gfx.rlc.is_rlc_v2_1)) 1232 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1233 1234 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 1235 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1236 AMD_PG_SUPPORT_CP | 1237 AMD_PG_SUPPORT_RLC_SMU_HS; 1238 break; 1239 case IP_VERSION(9, 3, 0): 1240 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 1241 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1242 AMD_PG_SUPPORT_CP | 1243 AMD_PG_SUPPORT_RLC_SMU_HS; 1244 break; 1245 default: 1246 break; 1247 } 1248 } 1249 1250 static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, 1251 const char *chip_name) 1252 { 1253 char fw_name[30]; 1254 int err; 1255 1256 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 1257 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 1258 if (err) 1259 goto out; 1260 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 1261 if (err) 1262 goto out; 1263 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 1264 1265 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 1266 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 1267 if (err) 1268 goto out; 1269 err = amdgpu_ucode_validate(adev->gfx.me_fw); 1270 if (err) 1271 goto out; 1272 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 1273 1274 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 1275 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 1276 if (err) 1277 goto out; 1278 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 1279 if (err) 1280 goto out; 1281 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); 1282 1283 out: 1284 if (err) { 1285 dev_err(adev->dev, 1286 "gfx9: Failed to init firmware \"%s\"\n", 1287 fw_name); 1288 release_firmware(adev->gfx.pfp_fw); 1289 adev->gfx.pfp_fw = NULL; 1290 release_firmware(adev->gfx.me_fw); 1291 adev->gfx.me_fw = NULL; 1292 release_firmware(adev->gfx.ce_fw); 1293 adev->gfx.ce_fw = NULL; 1294 } 1295 return err; 1296 } 1297 1298 static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, 1299 const char *chip_name) 1300 { 1301 char fw_name[30]; 1302 int err; 1303 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1304 uint16_t version_major; 1305 uint16_t version_minor; 1306 uint32_t smu_version; 1307 1308 /* 1309 * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin 1310 * instead of picasso_rlc.bin. 1311 * Judgment method: 1312 * PCO AM4: revision >= 0xC8 && revision <= 0xCF 1313 * or revision >= 0xD8 && revision <= 0xDF 1314 * otherwise is PCO FP5 1315 */ 1316 if (!strcmp(chip_name, "picasso") && 1317 (((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) || 1318 ((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF)))) 1319 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name); 1320 else if (!strcmp(chip_name, "raven") && (amdgpu_pm_load_smu_firmware(adev, &smu_version) == 0) && 1321 (smu_version >= 0x41e2b)) 1322 /** 1323 *SMC is loaded by SBIOS on APU and it's able to get the SMU version directly. 1324 */ 1325 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", chip_name); 1326 else 1327 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 1328 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 1329 if (err) 1330 goto out; 1331 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 1332 if (err) 1333 goto out; 1334 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1335 1336 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1337 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1338 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 1339 out: 1340 if (err) { 1341 dev_err(adev->dev, 1342 "gfx9: Failed to init firmware \"%s\"\n", 1343 fw_name); 1344 release_firmware(adev->gfx.rlc_fw); 1345 adev->gfx.rlc_fw = NULL; 1346 } 1347 return err; 1348 } 1349 1350 static bool gfx_v9_0_load_mec2_fw_bin_support(struct amdgpu_device *adev) 1351 { 1352 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || 1353 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || 1354 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) 1355 return false; 1356 1357 return true; 1358 } 1359 1360 static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, 1361 const char *chip_name) 1362 { 1363 char fw_name[30]; 1364 int err; 1365 1366 if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) 1367 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec.bin", chip_name); 1368 else 1369 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 1370 1371 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 1372 if (err) 1373 goto out; 1374 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 1375 if (err) 1376 goto out; 1377 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 1378 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 1379 1380 if (gfx_v9_0_load_mec2_fw_bin_support(adev)) { 1381 if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) 1382 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec2.bin", chip_name); 1383 else 1384 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 1385 1386 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 1387 if (!err) { 1388 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 1389 if (err) 1390 goto out; 1391 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 1392 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 1393 } else { 1394 err = 0; 1395 adev->gfx.mec2_fw = NULL; 1396 } 1397 } else { 1398 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 1399 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 1400 } 1401 1402 out: 1403 gfx_v9_0_check_if_need_gfxoff(adev); 1404 gfx_v9_0_check_fw_write_wait(adev); 1405 if (err) { 1406 dev_err(adev->dev, 1407 "gfx9: Failed to init firmware \"%s\"\n", 1408 fw_name); 1409 release_firmware(adev->gfx.mec_fw); 1410 adev->gfx.mec_fw = NULL; 1411 release_firmware(adev->gfx.mec2_fw); 1412 adev->gfx.mec2_fw = NULL; 1413 } 1414 return err; 1415 } 1416 1417 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) 1418 { 1419 const char *chip_name; 1420 int r; 1421 1422 DRM_DEBUG("\n"); 1423 1424 switch (adev->ip_versions[GC_HWIP][0]) { 1425 case IP_VERSION(9, 0, 1): 1426 chip_name = "vega10"; 1427 break; 1428 case IP_VERSION(9, 2, 1): 1429 chip_name = "vega12"; 1430 break; 1431 case IP_VERSION(9, 4, 0): 1432 chip_name = "vega20"; 1433 break; 1434 case IP_VERSION(9, 2, 2): 1435 case IP_VERSION(9, 1, 0): 1436 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1437 chip_name = "raven2"; 1438 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1439 chip_name = "picasso"; 1440 else 1441 chip_name = "raven"; 1442 break; 1443 case IP_VERSION(9, 4, 1): 1444 chip_name = "arcturus"; 1445 break; 1446 case IP_VERSION(9, 3, 0): 1447 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1448 chip_name = "renoir"; 1449 else 1450 chip_name = "green_sardine"; 1451 break; 1452 case IP_VERSION(9, 4, 2): 1453 chip_name = "aldebaran"; 1454 break; 1455 default: 1456 BUG(); 1457 } 1458 1459 /* No CPG in Arcturus */ 1460 if (adev->gfx.num_gfx_rings) { 1461 r = gfx_v9_0_init_cp_gfx_microcode(adev, chip_name); 1462 if (r) 1463 return r; 1464 } 1465 1466 r = gfx_v9_0_init_rlc_microcode(adev, chip_name); 1467 if (r) 1468 return r; 1469 1470 r = gfx_v9_0_init_cp_compute_microcode(adev, chip_name); 1471 if (r) 1472 return r; 1473 1474 return r; 1475 } 1476 1477 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) 1478 { 1479 u32 count = 0; 1480 const struct cs_section_def *sect = NULL; 1481 const struct cs_extent_def *ext = NULL; 1482 1483 /* begin clear state */ 1484 count += 2; 1485 /* context control state */ 1486 count += 3; 1487 1488 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 1489 for (ext = sect->section; ext->extent != NULL; ++ext) { 1490 if (sect->id == SECT_CONTEXT) 1491 count += 2 + ext->reg_count; 1492 else 1493 return 0; 1494 } 1495 } 1496 1497 /* end clear state */ 1498 count += 2; 1499 /* clear state */ 1500 count += 2; 1501 1502 return count; 1503 } 1504 1505 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, 1506 volatile u32 *buffer) 1507 { 1508 u32 count = 0, i; 1509 const struct cs_section_def *sect = NULL; 1510 const struct cs_extent_def *ext = NULL; 1511 1512 if (adev->gfx.rlc.cs_data == NULL) 1513 return; 1514 if (buffer == NULL) 1515 return; 1516 1517 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1518 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1519 1520 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 1521 buffer[count++] = cpu_to_le32(0x80000000); 1522 buffer[count++] = cpu_to_le32(0x80000000); 1523 1524 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 1525 for (ext = sect->section; ext->extent != NULL; ++ext) { 1526 if (sect->id == SECT_CONTEXT) { 1527 buffer[count++] = 1528 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 1529 buffer[count++] = cpu_to_le32(ext->reg_index - 1530 PACKET3_SET_CONTEXT_REG_START); 1531 for (i = 0; i < ext->reg_count; i++) 1532 buffer[count++] = cpu_to_le32(ext->extent[i]); 1533 } else { 1534 return; 1535 } 1536 } 1537 } 1538 1539 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1540 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 1541 1542 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 1543 buffer[count++] = cpu_to_le32(0); 1544 } 1545 1546 static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev) 1547 { 1548 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 1549 uint32_t pg_always_on_cu_num = 2; 1550 uint32_t always_on_cu_num; 1551 uint32_t i, j, k; 1552 uint32_t mask, cu_bitmap, counter; 1553 1554 if (adev->flags & AMD_IS_APU) 1555 always_on_cu_num = 4; 1556 else if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1)) 1557 always_on_cu_num = 8; 1558 else 1559 always_on_cu_num = 12; 1560 1561 mutex_lock(&adev->grbm_idx_mutex); 1562 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1563 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1564 mask = 1; 1565 cu_bitmap = 0; 1566 counter = 0; 1567 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 1568 1569 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 1570 if (cu_info->bitmap[i][j] & mask) { 1571 if (counter == pg_always_on_cu_num) 1572 WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap); 1573 if (counter < always_on_cu_num) 1574 cu_bitmap |= mask; 1575 else 1576 break; 1577 counter++; 1578 } 1579 mask <<= 1; 1580 } 1581 1582 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap); 1583 cu_info->ao_cu_bitmap[i][j] = cu_bitmap; 1584 } 1585 } 1586 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1587 mutex_unlock(&adev->grbm_idx_mutex); 1588 } 1589 1590 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev) 1591 { 1592 uint32_t data; 1593 1594 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 1595 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 1596 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7); 1597 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 1598 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16)); 1599 1600 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 1601 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 1602 1603 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 1604 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500); 1605 1606 mutex_lock(&adev->grbm_idx_mutex); 1607 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 1608 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1609 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 1610 1611 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 1612 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 1613 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 1614 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 1615 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 1616 1617 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 1618 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 1619 data &= 0x0000FFFF; 1620 data |= 0x00C00000; 1621 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 1622 1623 /* 1624 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xF (4 CUs AON for Raven), 1625 * programmed in gfx_v9_0_init_always_on_cu_mask() 1626 */ 1627 1628 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 1629 * but used for RLC_LB_CNTL configuration */ 1630 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 1631 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 1632 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 1633 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 1634 mutex_unlock(&adev->grbm_idx_mutex); 1635 1636 gfx_v9_0_init_always_on_cu_mask(adev); 1637 } 1638 1639 static void gfx_v9_4_init_lbpw(struct amdgpu_device *adev) 1640 { 1641 uint32_t data; 1642 1643 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 1644 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 1645 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8); 1646 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 1647 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16)); 1648 1649 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 1650 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 1651 1652 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 1653 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800); 1654 1655 mutex_lock(&adev->grbm_idx_mutex); 1656 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 1657 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1658 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 1659 1660 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 1661 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 1662 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 1663 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 1664 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 1665 1666 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 1667 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 1668 data &= 0x0000FFFF; 1669 data |= 0x00C00000; 1670 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 1671 1672 /* 1673 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF (12 CUs AON), 1674 * programmed in gfx_v9_0_init_always_on_cu_mask() 1675 */ 1676 1677 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 1678 * but used for RLC_LB_CNTL configuration */ 1679 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 1680 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 1681 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 1682 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 1683 mutex_unlock(&adev->grbm_idx_mutex); 1684 1685 gfx_v9_0_init_always_on_cu_mask(adev); 1686 } 1687 1688 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 1689 { 1690 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 1691 } 1692 1693 static int gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev) 1694 { 1695 if (gfx_v9_0_load_mec2_fw_bin_support(adev)) 1696 return 5; 1697 else 1698 return 4; 1699 } 1700 1701 static void gfx_v9_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1702 { 1703 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1704 1705 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; 1706 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 1707 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); 1708 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); 1709 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); 1710 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); 1711 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); 1712 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); 1713 adev->gfx.rlc.rlcg_reg_access_supported = true; 1714 } 1715 1716 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) 1717 { 1718 const struct cs_section_def *cs_data; 1719 int r; 1720 1721 adev->gfx.rlc.cs_data = gfx9_cs_data; 1722 1723 cs_data = adev->gfx.rlc.cs_data; 1724 1725 if (cs_data) { 1726 /* init clear state block */ 1727 r = amdgpu_gfx_rlc_init_csb(adev); 1728 if (r) 1729 return r; 1730 } 1731 1732 if (adev->flags & AMD_IS_APU) { 1733 /* TODO: double check the cp_table_size for RV */ 1734 adev->gfx.rlc.cp_table_size = roundup2(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ 1735 r = amdgpu_gfx_rlc_init_cpt(adev); 1736 if (r) 1737 return r; 1738 } 1739 1740 switch (adev->ip_versions[GC_HWIP][0]) { 1741 case IP_VERSION(9, 2, 2): 1742 case IP_VERSION(9, 1, 0): 1743 gfx_v9_0_init_lbpw(adev); 1744 break; 1745 case IP_VERSION(9, 4, 0): 1746 gfx_v9_4_init_lbpw(adev); 1747 break; 1748 default: 1749 break; 1750 } 1751 1752 /* init spm vmid with 0xf */ 1753 if (adev->gfx.rlc.funcs->update_spm_vmid) 1754 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 1755 1756 return 0; 1757 } 1758 1759 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev) 1760 { 1761 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 1762 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 1763 } 1764 1765 static int gfx_v9_0_mec_init(struct amdgpu_device *adev) 1766 { 1767 int r; 1768 u32 *hpd; 1769 const __le32 *fw_data; 1770 unsigned fw_size; 1771 u32 *fw; 1772 size_t mec_hpd_size; 1773 1774 const struct gfx_firmware_header_v1_0 *mec_hdr; 1775 1776 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1777 1778 /* take ownership of the relevant compute queues */ 1779 amdgpu_gfx_compute_queue_acquire(adev); 1780 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; 1781 if (mec_hpd_size) { 1782 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1783 AMDGPU_GEM_DOMAIN_VRAM, 1784 &adev->gfx.mec.hpd_eop_obj, 1785 &adev->gfx.mec.hpd_eop_gpu_addr, 1786 (void **)&hpd); 1787 if (r) { 1788 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1789 gfx_v9_0_mec_fini(adev); 1790 return r; 1791 } 1792 1793 memset(hpd, 0, mec_hpd_size); 1794 1795 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1796 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1797 } 1798 1799 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1800 1801 fw_data = (const __le32 *) 1802 (adev->gfx.mec_fw->data + 1803 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1804 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 1805 1806 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 1807 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 1808 &adev->gfx.mec.mec_fw_obj, 1809 &adev->gfx.mec.mec_fw_gpu_addr, 1810 (void **)&fw); 1811 if (r) { 1812 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 1813 gfx_v9_0_mec_fini(adev); 1814 return r; 1815 } 1816 1817 memcpy(fw, fw_data, fw_size); 1818 1819 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 1820 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 1821 1822 return 0; 1823 } 1824 1825 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 1826 { 1827 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, 1828 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1829 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1830 (address << SQ_IND_INDEX__INDEX__SHIFT) | 1831 (SQ_IND_INDEX__FORCE_READ_MASK)); 1832 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1833 } 1834 1835 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 1836 uint32_t wave, uint32_t thread, 1837 uint32_t regno, uint32_t num, uint32_t *out) 1838 { 1839 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, 1840 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1841 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1842 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1843 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 1844 (SQ_IND_INDEX__FORCE_READ_MASK) | 1845 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1846 while (num--) 1847 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1848 } 1849 1850 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1851 { 1852 /* type 1 wave data */ 1853 dst[(*no_fields)++] = 1; 1854 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 1855 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 1856 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 1857 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 1858 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 1859 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 1860 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 1861 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 1862 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 1863 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 1864 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 1865 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 1866 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 1867 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 1868 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); 1869 } 1870 1871 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 1872 uint32_t wave, uint32_t start, 1873 uint32_t size, uint32_t *dst) 1874 { 1875 wave_read_regs( 1876 adev, simd, wave, 0, 1877 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 1878 } 1879 1880 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 1881 uint32_t wave, uint32_t thread, 1882 uint32_t start, uint32_t size, 1883 uint32_t *dst) 1884 { 1885 wave_read_regs( 1886 adev, simd, wave, thread, 1887 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1888 } 1889 1890 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev, 1891 u32 me, u32 pipe, u32 q, u32 vm) 1892 { 1893 soc15_grbm_select(adev, me, pipe, q, vm); 1894 } 1895 1896 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { 1897 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, 1898 .select_se_sh = &gfx_v9_0_select_se_sh, 1899 .read_wave_data = &gfx_v9_0_read_wave_data, 1900 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, 1901 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, 1902 .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q, 1903 }; 1904 1905 const struct amdgpu_ras_block_hw_ops gfx_v9_0_ras_ops = { 1906 .ras_error_inject = &gfx_v9_0_ras_error_inject, 1907 .query_ras_error_count = &gfx_v9_0_query_ras_error_count, 1908 .reset_ras_error_count = &gfx_v9_0_reset_ras_error_count, 1909 }; 1910 1911 static struct amdgpu_gfx_ras gfx_v9_0_ras = { 1912 .ras_block = { 1913 .hw_ops = &gfx_v9_0_ras_ops, 1914 }, 1915 }; 1916 1917 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) 1918 { 1919 u32 gb_addr_config; 1920 int err; 1921 1922 adev->gfx.funcs = &gfx_v9_0_gfx_funcs; 1923 1924 switch (adev->ip_versions[GC_HWIP][0]) { 1925 case IP_VERSION(9, 0, 1): 1926 adev->gfx.config.max_hw_contexts = 8; 1927 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1928 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1929 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1930 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1931 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN; 1932 break; 1933 case IP_VERSION(9, 2, 1): 1934 adev->gfx.config.max_hw_contexts = 8; 1935 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1936 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1937 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1938 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1939 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN; 1940 DRM_INFO("fix gfx.config for vega12\n"); 1941 break; 1942 case IP_VERSION(9, 4, 0): 1943 adev->gfx.ras = &gfx_v9_0_ras; 1944 adev->gfx.config.max_hw_contexts = 8; 1945 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1946 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1947 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1948 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1949 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1950 gb_addr_config &= ~0xf3e777ff; 1951 gb_addr_config |= 0x22014042; 1952 /* check vbios table if gpu info is not available */ 1953 err = amdgpu_atomfirmware_get_gfx_info(adev); 1954 if (err) 1955 return err; 1956 break; 1957 case IP_VERSION(9, 2, 2): 1958 case IP_VERSION(9, 1, 0): 1959 adev->gfx.config.max_hw_contexts = 8; 1960 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1961 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1962 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1963 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1964 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1965 gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN; 1966 else 1967 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; 1968 break; 1969 case IP_VERSION(9, 4, 1): 1970 adev->gfx.ras = &gfx_v9_4_ras; 1971 adev->gfx.config.max_hw_contexts = 8; 1972 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1973 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1974 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1975 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1976 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1977 gb_addr_config &= ~0xf3e777ff; 1978 gb_addr_config |= 0x22014042; 1979 break; 1980 case IP_VERSION(9, 3, 0): 1981 adev->gfx.config.max_hw_contexts = 8; 1982 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1983 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1984 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 1985 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1986 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1987 gb_addr_config &= ~0xf3e777ff; 1988 gb_addr_config |= 0x22010042; 1989 break; 1990 case IP_VERSION(9, 4, 2): 1991 adev->gfx.ras = &gfx_v9_4_2_ras; 1992 adev->gfx.config.max_hw_contexts = 8; 1993 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1994 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1995 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1996 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1997 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1998 gb_addr_config &= ~0xf3e777ff; 1999 gb_addr_config |= 0x22014042; 2000 /* check vbios table if gpu info is not available */ 2001 err = amdgpu_atomfirmware_get_gfx_info(adev); 2002 if (err) 2003 return err; 2004 break; 2005 default: 2006 BUG(); 2007 break; 2008 } 2009 2010 if (adev->gfx.ras) { 2011 err = amdgpu_ras_register_ras_block(adev, &adev->gfx.ras->ras_block); 2012 if (err) { 2013 DRM_ERROR("Failed to register gfx ras block!\n"); 2014 return err; 2015 } 2016 2017 strlcpy(adev->gfx.ras->ras_block.ras_comm.name, "gfx", 2018 sizeof(adev->gfx.ras->ras_block.ras_comm.name)); 2019 adev->gfx.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__GFX; 2020 adev->gfx.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 2021 adev->gfx.ras_if = &adev->gfx.ras->ras_block.ras_comm; 2022 2023 /* If not define special ras_late_init function, use gfx default ras_late_init */ 2024 if (!adev->gfx.ras->ras_block.ras_late_init) 2025 adev->gfx.ras->ras_block.ras_late_init = amdgpu_gfx_ras_late_init; 2026 2027 /* If not defined special ras_cb function, use default ras_cb */ 2028 if (!adev->gfx.ras->ras_block.ras_cb) 2029 adev->gfx.ras->ras_block.ras_cb = amdgpu_gfx_process_ras_data_cb; 2030 } 2031 2032 adev->gfx.config.gb_addr_config = gb_addr_config; 2033 2034 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 2035 REG_GET_FIELD( 2036 adev->gfx.config.gb_addr_config, 2037 GB_ADDR_CONFIG, 2038 NUM_PIPES); 2039 2040 adev->gfx.config.max_tile_pipes = 2041 adev->gfx.config.gb_addr_config_fields.num_pipes; 2042 2043 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 2044 REG_GET_FIELD( 2045 adev->gfx.config.gb_addr_config, 2046 GB_ADDR_CONFIG, 2047 NUM_BANKS); 2048 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 2049 REG_GET_FIELD( 2050 adev->gfx.config.gb_addr_config, 2051 GB_ADDR_CONFIG, 2052 MAX_COMPRESSED_FRAGS); 2053 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 2054 REG_GET_FIELD( 2055 adev->gfx.config.gb_addr_config, 2056 GB_ADDR_CONFIG, 2057 NUM_RB_PER_SE); 2058 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 2059 REG_GET_FIELD( 2060 adev->gfx.config.gb_addr_config, 2061 GB_ADDR_CONFIG, 2062 NUM_SHADER_ENGINES); 2063 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 2064 REG_GET_FIELD( 2065 adev->gfx.config.gb_addr_config, 2066 GB_ADDR_CONFIG, 2067 PIPE_INTERLEAVE_SIZE)); 2068 2069 return 0; 2070 } 2071 2072 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 2073 int mec, int pipe, int queue) 2074 { 2075 unsigned irq_type; 2076 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 2077 unsigned int hw_prio; 2078 2079 ring = &adev->gfx.compute_ring[ring_id]; 2080 2081 /* mec0 is me1 */ 2082 ring->me = mec + 1; 2083 ring->pipe = pipe; 2084 ring->queue = queue; 2085 2086 ring->ring_obj = NULL; 2087 ring->use_doorbell = true; 2088 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 2089 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 2090 + (ring_id * GFX9_MEC_HPD_SIZE); 2091 snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 2092 2093 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2094 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 2095 + ring->pipe; 2096 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 2097 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; 2098 /* type-2 packets are deprecated on MEC, use type-3 instead */ 2099 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 2100 hw_prio, NULL); 2101 } 2102 2103 static int gfx_v9_0_sw_init(void *handle) 2104 { 2105 int i, j, k, r, ring_id; 2106 struct amdgpu_ring *ring; 2107 struct amdgpu_kiq *kiq; 2108 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2109 2110 switch (adev->ip_versions[GC_HWIP][0]) { 2111 case IP_VERSION(9, 0, 1): 2112 case IP_VERSION(9, 2, 1): 2113 case IP_VERSION(9, 4, 0): 2114 case IP_VERSION(9, 2, 2): 2115 case IP_VERSION(9, 1, 0): 2116 case IP_VERSION(9, 4, 1): 2117 case IP_VERSION(9, 3, 0): 2118 case IP_VERSION(9, 4, 2): 2119 adev->gfx.mec.num_mec = 2; 2120 break; 2121 default: 2122 adev->gfx.mec.num_mec = 1; 2123 break; 2124 } 2125 2126 adev->gfx.mec.num_pipe_per_mec = 4; 2127 adev->gfx.mec.num_queue_per_pipe = 8; 2128 2129 /* EOP Event */ 2130 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 2131 if (r) 2132 return r; 2133 2134 /* Privileged reg */ 2135 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 2136 &adev->gfx.priv_reg_irq); 2137 if (r) 2138 return r; 2139 2140 /* Privileged inst */ 2141 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 2142 &adev->gfx.priv_inst_irq); 2143 if (r) 2144 return r; 2145 2146 /* ECC error */ 2147 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_ECC_ERROR, 2148 &adev->gfx.cp_ecc_error_irq); 2149 if (r) 2150 return r; 2151 2152 /* FUE error */ 2153 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_FUE_ERROR, 2154 &adev->gfx.cp_ecc_error_irq); 2155 if (r) 2156 return r; 2157 2158 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 2159 2160 r = gfx_v9_0_init_microcode(adev); 2161 if (r) { 2162 DRM_ERROR("Failed to load gfx firmware!\n"); 2163 return r; 2164 } 2165 2166 if (adev->gfx.rlc.funcs) { 2167 if (adev->gfx.rlc.funcs->init) { 2168 r = adev->gfx.rlc.funcs->init(adev); 2169 if (r) { 2170 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 2171 return r; 2172 } 2173 } 2174 } 2175 2176 r = gfx_v9_0_mec_init(adev); 2177 if (r) { 2178 DRM_ERROR("Failed to init MEC BOs!\n"); 2179 return r; 2180 } 2181 2182 /* set up the gfx ring */ 2183 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2184 ring = &adev->gfx.gfx_ring[i]; 2185 ring->ring_obj = NULL; 2186 if (!i) 2187 snprintf(ring->name, sizeof(ring->name), "gfx"); 2188 else 2189 snprintf(ring->name, sizeof(ring->name), "gfx_%d", i); 2190 ring->use_doorbell = true; 2191 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 2192 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, 2193 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, 2194 AMDGPU_RING_PRIO_DEFAULT, NULL); 2195 if (r) 2196 return r; 2197 } 2198 2199 /* set up the compute queues - allocate horizontally across pipes */ 2200 ring_id = 0; 2201 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 2202 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 2203 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 2204 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) 2205 continue; 2206 2207 r = gfx_v9_0_compute_ring_init(adev, 2208 ring_id, 2209 i, k, j); 2210 if (r) 2211 return r; 2212 2213 ring_id++; 2214 } 2215 } 2216 } 2217 2218 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE); 2219 if (r) { 2220 DRM_ERROR("Failed to init KIQ BOs!\n"); 2221 return r; 2222 } 2223 2224 kiq = &adev->gfx.kiq; 2225 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 2226 if (r) 2227 return r; 2228 2229 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 2230 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation)); 2231 if (r) 2232 return r; 2233 2234 adev->gfx.ce_ram_size = 0x8000; 2235 2236 r = gfx_v9_0_gpu_early_init(adev); 2237 if (r) 2238 return r; 2239 2240 return 0; 2241 } 2242 2243 2244 static int gfx_v9_0_sw_fini(void *handle) 2245 { 2246 int i; 2247 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2248 2249 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2250 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 2251 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2252 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 2253 2254 amdgpu_gfx_mqd_sw_fini(adev); 2255 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 2256 amdgpu_gfx_kiq_fini(adev); 2257 2258 gfx_v9_0_mec_fini(adev); 2259 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 2260 &adev->gfx.rlc.clear_state_gpu_addr, 2261 (void **)&adev->gfx.rlc.cs_ptr); 2262 if (adev->flags & AMD_IS_APU) { 2263 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 2264 &adev->gfx.rlc.cp_table_gpu_addr, 2265 (void **)&adev->gfx.rlc.cp_table_ptr); 2266 } 2267 gfx_v9_0_free_microcode(adev); 2268 2269 return 0; 2270 } 2271 2272 2273 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev) 2274 { 2275 /* TODO */ 2276 } 2277 2278 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, 2279 u32 instance) 2280 { 2281 u32 data; 2282 2283 if (instance == 0xffffffff) 2284 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 2285 else 2286 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 2287 2288 if (se_num == 0xffffffff) 2289 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 2290 else 2291 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 2292 2293 if (sh_num == 0xffffffff) 2294 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 2295 else 2296 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 2297 2298 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data); 2299 } 2300 2301 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) 2302 { 2303 u32 data, mask; 2304 2305 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 2306 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 2307 2308 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 2309 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 2310 2311 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 2312 adev->gfx.config.max_sh_per_se); 2313 2314 return (~data) & mask; 2315 } 2316 2317 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev) 2318 { 2319 int i, j; 2320 u32 data; 2321 u32 active_rbs = 0; 2322 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 2323 adev->gfx.config.max_sh_per_se; 2324 2325 mutex_lock(&adev->grbm_idx_mutex); 2326 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2327 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 2328 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 2329 data = gfx_v9_0_get_rb_active_bitmap(adev); 2330 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 2331 rb_bitmap_width_per_sh); 2332 } 2333 } 2334 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2335 mutex_unlock(&adev->grbm_idx_mutex); 2336 2337 adev->gfx.config.backend_enable_mask = active_rbs; 2338 adev->gfx.config.num_rbs = hweight32(active_rbs); 2339 } 2340 2341 #define DEFAULT_SH_MEM_BASES (0x6000) 2342 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) 2343 { 2344 int i; 2345 uint32_t sh_mem_config; 2346 uint32_t sh_mem_bases; 2347 2348 /* 2349 * Configure apertures: 2350 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 2351 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 2352 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 2353 */ 2354 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 2355 2356 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 2357 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 2358 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 2359 2360 mutex_lock(&adev->srbm_mutex); 2361 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2362 soc15_grbm_select(adev, 0, 0, 0, i); 2363 /* CP and shaders */ 2364 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); 2365 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 2366 } 2367 soc15_grbm_select(adev, 0, 0, 0, 0); 2368 mutex_unlock(&adev->srbm_mutex); 2369 2370 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 2371 access. These should be enabled by FW for target VMIDs. */ 2372 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2373 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 2374 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 2375 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 2376 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 2377 } 2378 } 2379 2380 static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev) 2381 { 2382 int vmid; 2383 2384 /* 2385 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 2386 * access. Compute VMIDs should be enabled by FW for target VMIDs, 2387 * the driver can enable them for graphics. VMID0 should maintain 2388 * access so that HWS firmware can save/restore entries. 2389 */ 2390 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 2391 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 2392 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 2393 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 2394 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 2395 } 2396 } 2397 2398 static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev) 2399 { 2400 uint32_t tmp; 2401 2402 switch (adev->ip_versions[GC_HWIP][0]) { 2403 case IP_VERSION(9, 4, 1): 2404 tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG); 2405 tmp = REG_SET_FIELD(tmp, SQ_CONFIG, 2406 DISABLE_BARRIER_WAITCNT, 1); 2407 WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp); 2408 break; 2409 default: 2410 break; 2411 } 2412 } 2413 2414 static void gfx_v9_0_constants_init(struct amdgpu_device *adev) 2415 { 2416 u32 tmp; 2417 int i; 2418 2419 WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 2420 2421 gfx_v9_0_tiling_mode_table_init(adev); 2422 2423 if (adev->gfx.num_gfx_rings) 2424 gfx_v9_0_setup_rb(adev); 2425 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); 2426 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); 2427 2428 /* XXX SH_MEM regs */ 2429 /* where to put LDS, scratch, GPUVM in FSA64 space */ 2430 mutex_lock(&adev->srbm_mutex); 2431 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 2432 soc15_grbm_select(adev, 0, 0, 0, i); 2433 /* CP and shaders */ 2434 if (i == 0) { 2435 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 2436 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 2437 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 2438 !!adev->gmc.noretry); 2439 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); 2440 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0); 2441 } else { 2442 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 2443 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 2444 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 2445 !!adev->gmc.noretry); 2446 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); 2447 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 2448 (adev->gmc.private_aperture_start >> 48)); 2449 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 2450 (adev->gmc.shared_aperture_start >> 48)); 2451 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp); 2452 } 2453 } 2454 soc15_grbm_select(adev, 0, 0, 0, 0); 2455 2456 mutex_unlock(&adev->srbm_mutex); 2457 2458 gfx_v9_0_init_compute_vmid(adev); 2459 gfx_v9_0_init_gds_vmid(adev); 2460 gfx_v9_0_init_sq_config(adev); 2461 } 2462 2463 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2464 { 2465 u32 i, j, k; 2466 u32 mask; 2467 2468 mutex_lock(&adev->grbm_idx_mutex); 2469 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2470 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 2471 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 2472 for (k = 0; k < adev->usec_timeout; k++) { 2473 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0) 2474 break; 2475 udelay(1); 2476 } 2477 if (k == adev->usec_timeout) { 2478 gfx_v9_0_select_se_sh(adev, 0xffffffff, 2479 0xffffffff, 0xffffffff); 2480 mutex_unlock(&adev->grbm_idx_mutex); 2481 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 2482 i, j); 2483 return; 2484 } 2485 } 2486 } 2487 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2488 mutex_unlock(&adev->grbm_idx_mutex); 2489 2490 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 2491 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 2492 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 2493 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 2494 for (k = 0; k < adev->usec_timeout; k++) { 2495 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 2496 break; 2497 udelay(1); 2498 } 2499 } 2500 2501 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2502 bool enable) 2503 { 2504 u32 tmp; 2505 2506 /* These interrupts should be enabled to drive DS clock */ 2507 2508 tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 2509 2510 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 2511 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 2512 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 2513 if(adev->gfx.num_gfx_rings) 2514 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); 2515 2516 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 2517 } 2518 2519 static void gfx_v9_0_init_csb(struct amdgpu_device *adev) 2520 { 2521 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 2522 /* csib */ 2523 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), 2524 adev->gfx.rlc.clear_state_gpu_addr >> 32); 2525 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), 2526 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 2527 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), 2528 adev->gfx.rlc.clear_state_size); 2529 } 2530 2531 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format, 2532 int indirect_offset, 2533 int list_size, 2534 int *unique_indirect_regs, 2535 int unique_indirect_reg_count, 2536 int *indirect_start_offsets, 2537 int *indirect_start_offsets_count, 2538 int max_start_offsets_count) 2539 { 2540 int idx; 2541 2542 for (; indirect_offset < list_size; indirect_offset++) { 2543 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count); 2544 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset; 2545 *indirect_start_offsets_count = *indirect_start_offsets_count + 1; 2546 2547 while (register_list_format[indirect_offset] != 0xFFFFFFFF) { 2548 indirect_offset += 2; 2549 2550 /* look for the matching indice */ 2551 for (idx = 0; idx < unique_indirect_reg_count; idx++) { 2552 if (unique_indirect_regs[idx] == 2553 register_list_format[indirect_offset] || 2554 !unique_indirect_regs[idx]) 2555 break; 2556 } 2557 2558 BUG_ON(idx >= unique_indirect_reg_count); 2559 2560 if (!unique_indirect_regs[idx]) 2561 unique_indirect_regs[idx] = register_list_format[indirect_offset]; 2562 2563 indirect_offset++; 2564 } 2565 } 2566 } 2567 2568 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev) 2569 { 2570 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 2571 int unique_indirect_reg_count = 0; 2572 2573 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 2574 int indirect_start_offsets_count = 0; 2575 2576 int list_size = 0; 2577 int i = 0, j = 0; 2578 u32 tmp = 0; 2579 2580 u32 *register_list_format = 2581 kmemdup(adev->gfx.rlc.register_list_format, 2582 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); 2583 if (!register_list_format) 2584 return -ENOMEM; 2585 2586 /* setup unique_indirect_regs array and indirect_start_offsets array */ 2587 unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs); 2588 gfx_v9_1_parse_ind_reg_list(register_list_format, 2589 adev->gfx.rlc.reg_list_format_direct_reg_list_length, 2590 adev->gfx.rlc.reg_list_format_size_bytes >> 2, 2591 unique_indirect_regs, 2592 unique_indirect_reg_count, 2593 indirect_start_offsets, 2594 &indirect_start_offsets_count, 2595 ARRAY_SIZE(indirect_start_offsets)); 2596 2597 /* enable auto inc in case it is disabled */ 2598 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 2599 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2600 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 2601 2602 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */ 2603 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 2604 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET); 2605 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) 2606 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), 2607 adev->gfx.rlc.register_restore[i]); 2608 2609 /* load indirect register */ 2610 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2611 adev->gfx.rlc.reg_list_format_start); 2612 2613 /* direct register portion */ 2614 for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++) 2615 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 2616 register_list_format[i]); 2617 2618 /* indirect register portion */ 2619 while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) { 2620 if (register_list_format[i] == 0xFFFFFFFF) { 2621 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2622 continue; 2623 } 2624 2625 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2626 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2627 2628 for (j = 0; j < unique_indirect_reg_count; j++) { 2629 if (register_list_format[i] == unique_indirect_regs[j]) { 2630 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j); 2631 break; 2632 } 2633 } 2634 2635 BUG_ON(j >= unique_indirect_reg_count); 2636 2637 i++; 2638 } 2639 2640 /* set save/restore list size */ 2641 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; 2642 list_size = list_size >> 1; 2643 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2644 adev->gfx.rlc.reg_restore_list_size); 2645 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size); 2646 2647 /* write the starting offsets to RLC scratch ram */ 2648 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2649 adev->gfx.rlc.starting_offsets_start); 2650 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++) 2651 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 2652 indirect_start_offsets[i]); 2653 2654 /* load unique indirect regs*/ 2655 for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) { 2656 if (unique_indirect_regs[i] != 0) { 2657 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) 2658 + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i], 2659 unique_indirect_regs[i] & 0x3FFFF); 2660 2661 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) 2662 + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i], 2663 unique_indirect_regs[i] >> 20); 2664 } 2665 } 2666 2667 kfree(register_list_format); 2668 return 0; 2669 } 2670 2671 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev) 2672 { 2673 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1); 2674 } 2675 2676 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev, 2677 bool enable) 2678 { 2679 uint32_t data = 0; 2680 uint32_t default_data = 0; 2681 2682 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS)); 2683 if (enable) { 2684 /* enable GFXIP control over CGPG */ 2685 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2686 if(default_data != data) 2687 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2688 2689 /* update status */ 2690 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK; 2691 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT); 2692 if(default_data != data) 2693 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2694 } else { 2695 /* restore GFXIP control over GCPG */ 2696 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2697 if(default_data != data) 2698 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2699 } 2700 } 2701 2702 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev) 2703 { 2704 uint32_t data = 0; 2705 2706 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2707 AMD_PG_SUPPORT_GFX_SMG | 2708 AMD_PG_SUPPORT_GFX_DMG)) { 2709 /* init IDLE_POLL_COUNT = 60 */ 2710 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); 2711 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 2712 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2713 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); 2714 2715 /* init RLC PG Delay */ 2716 data = 0; 2717 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT); 2718 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT); 2719 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT); 2720 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT); 2721 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data); 2722 2723 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2)); 2724 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK; 2725 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT); 2726 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data); 2727 2728 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3)); 2729 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK; 2730 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT); 2731 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data); 2732 2733 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL)); 2734 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2735 2736 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */ 2737 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2738 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data); 2739 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 3, 0)) 2740 pwr_10_0_gfxip_control_over_cgpg(adev, true); 2741 } 2742 } 2743 2744 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, 2745 bool enable) 2746 { 2747 uint32_t data = 0; 2748 uint32_t default_data = 0; 2749 2750 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2751 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2752 SMU_CLK_SLOWDOWN_ON_PU_ENABLE, 2753 enable ? 1 : 0); 2754 if (default_data != data) 2755 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2756 } 2757 2758 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, 2759 bool enable) 2760 { 2761 uint32_t data = 0; 2762 uint32_t default_data = 0; 2763 2764 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2765 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2766 SMU_CLK_SLOWDOWN_ON_PD_ENABLE, 2767 enable ? 1 : 0); 2768 if(default_data != data) 2769 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2770 } 2771 2772 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev, 2773 bool enable) 2774 { 2775 uint32_t data = 0; 2776 uint32_t default_data = 0; 2777 2778 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2779 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2780 CP_PG_DISABLE, 2781 enable ? 0 : 1); 2782 if(default_data != data) 2783 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2784 } 2785 2786 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev, 2787 bool enable) 2788 { 2789 uint32_t data, default_data; 2790 2791 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2792 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2793 GFX_POWER_GATING_ENABLE, 2794 enable ? 1 : 0); 2795 if(default_data != data) 2796 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2797 } 2798 2799 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev, 2800 bool enable) 2801 { 2802 uint32_t data, default_data; 2803 2804 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2805 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2806 GFX_PIPELINE_PG_ENABLE, 2807 enable ? 1 : 0); 2808 if(default_data != data) 2809 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2810 2811 if (!enable) 2812 /* read any GFX register to wake up GFX */ 2813 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL)); 2814 } 2815 2816 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, 2817 bool enable) 2818 { 2819 uint32_t data, default_data; 2820 2821 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2822 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2823 STATIC_PER_CU_PG_ENABLE, 2824 enable ? 1 : 0); 2825 if(default_data != data) 2826 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2827 } 2828 2829 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, 2830 bool enable) 2831 { 2832 uint32_t data, default_data; 2833 2834 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2835 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2836 DYN_PER_CU_PG_ENABLE, 2837 enable ? 1 : 0); 2838 if(default_data != data) 2839 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2840 } 2841 2842 static void gfx_v9_0_init_pg(struct amdgpu_device *adev) 2843 { 2844 gfx_v9_0_init_csb(adev); 2845 2846 /* 2847 * Rlc save restore list is workable since v2_1. 2848 * And it's needed by gfxoff feature. 2849 */ 2850 if (adev->gfx.rlc.is_rlc_v2_1) { 2851 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1) || 2852 (adev->apu_flags & AMD_APU_IS_RAVEN2)) 2853 gfx_v9_1_init_rlc_save_restore_list(adev); 2854 gfx_v9_0_enable_save_restore_machine(adev); 2855 } 2856 2857 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2858 AMD_PG_SUPPORT_GFX_SMG | 2859 AMD_PG_SUPPORT_GFX_DMG | 2860 AMD_PG_SUPPORT_CP | 2861 AMD_PG_SUPPORT_GDS | 2862 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2863 WREG32_SOC15(GC, 0, mmRLC_JUMP_TABLE_RESTORE, 2864 adev->gfx.rlc.cp_table_gpu_addr >> 8); 2865 gfx_v9_0_init_gfx_power_gating(adev); 2866 } 2867 } 2868 2869 static void gfx_v9_0_rlc_stop(struct amdgpu_device *adev) 2870 { 2871 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0); 2872 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 2873 gfx_v9_0_wait_for_rlc_serdes(adev); 2874 } 2875 2876 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev) 2877 { 2878 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2879 udelay(50); 2880 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2881 udelay(50); 2882 } 2883 2884 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) 2885 { 2886 #ifdef AMDGPU_RLC_DEBUG_RETRY 2887 u32 rlc_ucode_ver; 2888 #endif 2889 2890 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2891 udelay(50); 2892 2893 /* carrizo do enable cp interrupt after cp inited */ 2894 if (!(adev->flags & AMD_IS_APU)) { 2895 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 2896 udelay(50); 2897 } 2898 2899 #ifdef AMDGPU_RLC_DEBUG_RETRY 2900 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 2901 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6); 2902 if(rlc_ucode_ver == 0x108) { 2903 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 2904 rlc_ucode_ver, adev->gfx.rlc_fw_version); 2905 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 2906 * default is 0x9C4 to create a 100us interval */ 2907 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4); 2908 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 2909 * to disable the page fault retry interrupts, default is 2910 * 0x100 (256) */ 2911 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100); 2912 } 2913 #endif 2914 } 2915 2916 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev) 2917 { 2918 const struct rlc_firmware_header_v2_0 *hdr; 2919 const __le32 *fw_data; 2920 unsigned i, fw_size; 2921 2922 if (!adev->gfx.rlc_fw) 2923 return -EINVAL; 2924 2925 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2926 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2927 2928 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2929 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2930 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2931 2932 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 2933 RLCG_UCODE_LOADING_START_ADDRESS); 2934 for (i = 0; i < fw_size; i++) 2935 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 2936 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2937 2938 return 0; 2939 } 2940 2941 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) 2942 { 2943 int r; 2944 2945 if (amdgpu_sriov_vf(adev)) { 2946 gfx_v9_0_init_csb(adev); 2947 return 0; 2948 } 2949 2950 adev->gfx.rlc.funcs->stop(adev); 2951 2952 /* disable CG */ 2953 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 2954 2955 gfx_v9_0_init_pg(adev); 2956 2957 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2958 /* legacy rlc firmware loading */ 2959 r = gfx_v9_0_rlc_load_microcode(adev); 2960 if (r) 2961 return r; 2962 } 2963 2964 switch (adev->ip_versions[GC_HWIP][0]) { 2965 case IP_VERSION(9, 2, 2): 2966 case IP_VERSION(9, 1, 0): 2967 if (amdgpu_lbpw == 0) 2968 gfx_v9_0_enable_lbpw(adev, false); 2969 else 2970 gfx_v9_0_enable_lbpw(adev, true); 2971 break; 2972 case IP_VERSION(9, 4, 0): 2973 if (amdgpu_lbpw > 0) 2974 gfx_v9_0_enable_lbpw(adev, true); 2975 else 2976 gfx_v9_0_enable_lbpw(adev, false); 2977 break; 2978 default: 2979 break; 2980 } 2981 2982 adev->gfx.rlc.funcs->start(adev); 2983 2984 return 0; 2985 } 2986 2987 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2988 { 2989 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 2990 2991 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2992 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2993 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 2994 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 2995 udelay(50); 2996 } 2997 2998 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2999 { 3000 const struct gfx_firmware_header_v1_0 *pfp_hdr; 3001 const struct gfx_firmware_header_v1_0 *ce_hdr; 3002 const struct gfx_firmware_header_v1_0 *me_hdr; 3003 const __le32 *fw_data; 3004 unsigned i, fw_size; 3005 3006 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 3007 return -EINVAL; 3008 3009 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 3010 adev->gfx.pfp_fw->data; 3011 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 3012 adev->gfx.ce_fw->data; 3013 me_hdr = (const struct gfx_firmware_header_v1_0 *) 3014 adev->gfx.me_fw->data; 3015 3016 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 3017 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 3018 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3019 3020 gfx_v9_0_cp_gfx_enable(adev, false); 3021 3022 /* PFP */ 3023 fw_data = (const __le32 *) 3024 (adev->gfx.pfp_fw->data + 3025 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 3026 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 3027 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0); 3028 for (i = 0; i < fw_size; i++) 3029 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 3030 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 3031 3032 /* CE */ 3033 fw_data = (const __le32 *) 3034 (adev->gfx.ce_fw->data + 3035 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 3036 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 3037 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0); 3038 for (i = 0; i < fw_size; i++) 3039 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 3040 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 3041 3042 /* ME */ 3043 fw_data = (const __le32 *) 3044 (adev->gfx.me_fw->data + 3045 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 3046 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 3047 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0); 3048 for (i = 0; i < fw_size; i++) 3049 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 3050 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 3051 3052 return 0; 3053 } 3054 3055 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) 3056 { 3057 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 3058 const struct cs_section_def *sect = NULL; 3059 const struct cs_extent_def *ext = NULL; 3060 int r, i, tmp; 3061 3062 /* init the CP */ 3063 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 3064 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 3065 3066 gfx_v9_0_cp_gfx_enable(adev, true); 3067 3068 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3); 3069 if (r) { 3070 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3071 return r; 3072 } 3073 3074 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3075 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3076 3077 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3078 amdgpu_ring_write(ring, 0x80000000); 3079 amdgpu_ring_write(ring, 0x80000000); 3080 3081 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 3082 for (ext = sect->section; ext->extent != NULL; ++ext) { 3083 if (sect->id == SECT_CONTEXT) { 3084 amdgpu_ring_write(ring, 3085 PACKET3(PACKET3_SET_CONTEXT_REG, 3086 ext->reg_count)); 3087 amdgpu_ring_write(ring, 3088 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 3089 for (i = 0; i < ext->reg_count; i++) 3090 amdgpu_ring_write(ring, ext->extent[i]); 3091 } 3092 } 3093 } 3094 3095 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3096 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3097 3098 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3099 amdgpu_ring_write(ring, 0); 3100 3101 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 3102 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 3103 amdgpu_ring_write(ring, 0x8000); 3104 amdgpu_ring_write(ring, 0x8000); 3105 3106 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1)); 3107 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE | 3108 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START)); 3109 amdgpu_ring_write(ring, tmp); 3110 amdgpu_ring_write(ring, 0); 3111 3112 amdgpu_ring_commit(ring); 3113 3114 return 0; 3115 } 3116 3117 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) 3118 { 3119 struct amdgpu_ring *ring; 3120 u32 tmp; 3121 u32 rb_bufsz; 3122 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3123 3124 /* Set the write pointer delay */ 3125 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 3126 3127 /* set the RB to use vmid 0 */ 3128 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 3129 3130 /* Set ring buffer size */ 3131 ring = &adev->gfx.gfx_ring[0]; 3132 rb_bufsz = order_base_2(ring->ring_size / 8); 3133 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3134 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3135 #ifdef __BIG_ENDIAN 3136 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 3137 #endif 3138 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 3139 3140 /* Initialize the ring buffer's write pointers */ 3141 ring->wptr = 0; 3142 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3143 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3144 3145 /* set the wb address wether it's enabled or not */ 3146 rptr_addr = ring->rptr_gpu_addr; 3147 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3148 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3149 3150 wptr_gpu_addr = ring->wptr_gpu_addr; 3151 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); 3152 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); 3153 3154 mdelay(1); 3155 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 3156 3157 rb_addr = ring->gpu_addr >> 8; 3158 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 3159 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3160 3161 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 3162 if (ring->use_doorbell) { 3163 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3164 DOORBELL_OFFSET, ring->doorbell_index); 3165 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3166 DOORBELL_EN, 1); 3167 } else { 3168 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); 3169 } 3170 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 3171 3172 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3173 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3174 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 3175 3176 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 3177 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3178 3179 3180 /* start the ring */ 3181 gfx_v9_0_cp_gfx_start(adev); 3182 ring->sched.ready = true; 3183 3184 return 0; 3185 } 3186 3187 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3188 { 3189 if (enable) { 3190 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0); 3191 } else { 3192 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 3193 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 3194 adev->gfx.kiq.ring.sched.ready = false; 3195 } 3196 udelay(50); 3197 } 3198 3199 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3200 { 3201 const struct gfx_firmware_header_v1_0 *mec_hdr; 3202 const __le32 *fw_data; 3203 unsigned i; 3204 u32 tmp; 3205 3206 if (!adev->gfx.mec_fw) 3207 return -EINVAL; 3208 3209 gfx_v9_0_cp_compute_enable(adev, false); 3210 3211 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3212 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3213 3214 fw_data = (const __le32 *) 3215 (adev->gfx.mec_fw->data + 3216 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3217 tmp = 0; 3218 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3219 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3220 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 3221 3222 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 3223 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 3224 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 3225 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3226 3227 /* MEC1 */ 3228 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 3229 mec_hdr->jt_offset); 3230 for (i = 0; i < mec_hdr->jt_size; i++) 3231 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 3232 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3233 3234 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 3235 adev->gfx.mec_fw_version); 3236 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 3237 3238 return 0; 3239 } 3240 3241 /* KIQ functions */ 3242 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) 3243 { 3244 uint32_t tmp; 3245 struct amdgpu_device *adev = ring->adev; 3246 3247 /* tell RLC which is KIQ queue */ 3248 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 3249 tmp &= 0xffffff00; 3250 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3251 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 3252 tmp |= 0x80; 3253 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 3254 } 3255 3256 static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 3257 { 3258 struct amdgpu_device *adev = ring->adev; 3259 3260 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 3261 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 3262 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 3263 mqd->cp_hqd_queue_priority = 3264 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 3265 } 3266 } 3267 } 3268 3269 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) 3270 { 3271 struct amdgpu_device *adev = ring->adev; 3272 struct v9_mqd *mqd = ring->mqd_ptr; 3273 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3274 uint32_t tmp; 3275 3276 mqd->header = 0xC0310800; 3277 mqd->compute_pipelinestat_enable = 0x00000001; 3278 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3279 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3280 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3281 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3282 mqd->compute_static_thread_mgmt_se4 = 0xffffffff; 3283 mqd->compute_static_thread_mgmt_se5 = 0xffffffff; 3284 mqd->compute_static_thread_mgmt_se6 = 0xffffffff; 3285 mqd->compute_static_thread_mgmt_se7 = 0xffffffff; 3286 mqd->compute_misc_reserved = 0x00000003; 3287 3288 mqd->dynamic_cu_mask_addr_lo = 3289 lower_32_bits(ring->mqd_gpu_addr 3290 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 3291 mqd->dynamic_cu_mask_addr_hi = 3292 upper_32_bits(ring->mqd_gpu_addr 3293 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 3294 3295 eop_base_addr = ring->eop_gpu_addr >> 8; 3296 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3297 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3298 3299 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3300 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 3301 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3302 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 3303 3304 mqd->cp_hqd_eop_control = tmp; 3305 3306 /* enable doorbell? */ 3307 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3308 3309 if (ring->use_doorbell) { 3310 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3311 DOORBELL_OFFSET, ring->doorbell_index); 3312 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3313 DOORBELL_EN, 1); 3314 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3315 DOORBELL_SOURCE, 0); 3316 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3317 DOORBELL_HIT, 0); 3318 } else { 3319 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3320 DOORBELL_EN, 0); 3321 } 3322 3323 mqd->cp_hqd_pq_doorbell_control = tmp; 3324 3325 /* disable the queue if it's active */ 3326 ring->wptr = 0; 3327 mqd->cp_hqd_dequeue_request = 0; 3328 mqd->cp_hqd_pq_rptr = 0; 3329 mqd->cp_hqd_pq_wptr_lo = 0; 3330 mqd->cp_hqd_pq_wptr_hi = 0; 3331 3332 /* set the pointer to the MQD */ 3333 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 3334 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 3335 3336 /* set MQD vmid to 0 */ 3337 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 3338 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3339 mqd->cp_mqd_control = tmp; 3340 3341 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3342 hqd_gpu_addr = ring->gpu_addr >> 8; 3343 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3344 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3345 3346 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3347 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 3348 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3349 (order_base_2(ring->ring_size / 4) - 1)); 3350 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3351 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3352 #ifdef __BIG_ENDIAN 3353 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 3354 #endif 3355 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3356 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 3357 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3358 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3359 mqd->cp_hqd_pq_control = tmp; 3360 3361 /* set the wb address whether it's enabled or not */ 3362 wb_gpu_addr = ring->rptr_gpu_addr; 3363 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3364 mqd->cp_hqd_pq_rptr_report_addr_hi = 3365 upper_32_bits(wb_gpu_addr) & 0xffff; 3366 3367 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3368 wb_gpu_addr = ring->wptr_gpu_addr; 3369 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3370 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3371 3372 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3373 ring->wptr = 0; 3374 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 3375 3376 /* set the vmid for the queue */ 3377 mqd->cp_hqd_vmid = 0; 3378 3379 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 3380 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 3381 mqd->cp_hqd_persistent_state = tmp; 3382 3383 /* set MIN_IB_AVAIL_SIZE */ 3384 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 3385 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3386 mqd->cp_hqd_ib_control = tmp; 3387 3388 /* set static priority for a queue/ring */ 3389 gfx_v9_0_mqd_set_priority(ring, mqd); 3390 mqd->cp_hqd_quantum = RREG32_SOC15(GC, 0, mmCP_HQD_QUANTUM); 3391 3392 /* map_queues packet doesn't need activate the queue, 3393 * so only kiq need set this field. 3394 */ 3395 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 3396 mqd->cp_hqd_active = 1; 3397 3398 return 0; 3399 } 3400 3401 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) 3402 { 3403 struct amdgpu_device *adev = ring->adev; 3404 struct v9_mqd *mqd = ring->mqd_ptr; 3405 int j; 3406 3407 /* disable wptr polling */ 3408 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3409 3410 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 3411 mqd->cp_hqd_eop_base_addr_lo); 3412 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 3413 mqd->cp_hqd_eop_base_addr_hi); 3414 3415 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3416 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_CONTROL, 3417 mqd->cp_hqd_eop_control); 3418 3419 /* enable doorbell? */ 3420 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3421 mqd->cp_hqd_pq_doorbell_control); 3422 3423 /* disable the queue if it's active */ 3424 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3425 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3426 for (j = 0; j < adev->usec_timeout; j++) { 3427 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3428 break; 3429 udelay(1); 3430 } 3431 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3432 mqd->cp_hqd_dequeue_request); 3433 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 3434 mqd->cp_hqd_pq_rptr); 3435 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3436 mqd->cp_hqd_pq_wptr_lo); 3437 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3438 mqd->cp_hqd_pq_wptr_hi); 3439 } 3440 3441 /* set the pointer to the MQD */ 3442 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR, 3443 mqd->cp_mqd_base_addr_lo); 3444 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR_HI, 3445 mqd->cp_mqd_base_addr_hi); 3446 3447 /* set MQD vmid to 0 */ 3448 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL, 3449 mqd->cp_mqd_control); 3450 3451 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3452 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE, 3453 mqd->cp_hqd_pq_base_lo); 3454 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI, 3455 mqd->cp_hqd_pq_base_hi); 3456 3457 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3458 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_CONTROL, 3459 mqd->cp_hqd_pq_control); 3460 3461 /* set the wb address whether it's enabled or not */ 3462 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 3463 mqd->cp_hqd_pq_rptr_report_addr_lo); 3464 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3465 mqd->cp_hqd_pq_rptr_report_addr_hi); 3466 3467 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3468 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 3469 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3470 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3471 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3472 3473 /* enable the doorbell if requested */ 3474 if (ring->use_doorbell) { 3475 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 3476 (adev->doorbell_index.kiq * 2) << 2); 3477 /* If GC has entered CGPG, ringing doorbell > first page 3478 * doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to 3479 * workaround this issue. And this change has to align with firmware 3480 * update. 3481 */ 3482 if (check_if_enlarge_doorbell_range(adev)) 3483 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 3484 (adev->doorbell.size - 4)); 3485 else 3486 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 3487 (adev->doorbell_index.userqueue_end * 2) << 2); 3488 } 3489 3490 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3491 mqd->cp_hqd_pq_doorbell_control); 3492 3493 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3494 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3495 mqd->cp_hqd_pq_wptr_lo); 3496 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3497 mqd->cp_hqd_pq_wptr_hi); 3498 3499 /* set the vmid for the queue */ 3500 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 3501 3502 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 3503 mqd->cp_hqd_persistent_state); 3504 3505 /* activate the queue */ 3506 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 3507 mqd->cp_hqd_active); 3508 3509 if (ring->use_doorbell) 3510 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3511 3512 return 0; 3513 } 3514 3515 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring) 3516 { 3517 struct amdgpu_device *adev = ring->adev; 3518 int j; 3519 3520 /* disable the queue if it's active */ 3521 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3522 3523 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3524 3525 for (j = 0; j < adev->usec_timeout; j++) { 3526 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3527 break; 3528 udelay(1); 3529 } 3530 3531 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 3532 DRM_DEBUG("KIQ dequeue request failed.\n"); 3533 3534 /* Manual disable if dequeue request times out */ 3535 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0); 3536 } 3537 3538 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3539 0); 3540 } 3541 3542 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IQ_TIMER, 0); 3543 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0); 3544 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0); 3545 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 3546 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 3547 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 0); 3548 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0); 3549 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0); 3550 3551 return 0; 3552 } 3553 3554 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) 3555 { 3556 struct amdgpu_device *adev = ring->adev; 3557 struct v9_mqd *mqd = ring->mqd_ptr; 3558 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3559 struct v9_mqd *tmp_mqd; 3560 3561 gfx_v9_0_kiq_setting(ring); 3562 3563 /* GPU could be in bad state during probe, driver trigger the reset 3564 * after load the SMU, in this case , the mqd is not be initialized. 3565 * driver need to re-init the mqd. 3566 * check mqd->cp_hqd_pq_control since this value should not be 0 3567 */ 3568 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 3569 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control){ 3570 /* for GPU_RESET case , reset MQD to a clean status */ 3571 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3572 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 3573 3574 /* reset ring buffer */ 3575 ring->wptr = 0; 3576 amdgpu_ring_clear_ring(ring); 3577 3578 mutex_lock(&adev->srbm_mutex); 3579 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3580 gfx_v9_0_kiq_init_register(ring); 3581 soc15_grbm_select(adev, 0, 0, 0, 0); 3582 mutex_unlock(&adev->srbm_mutex); 3583 } else { 3584 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3585 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3586 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3587 mutex_lock(&adev->srbm_mutex); 3588 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3589 gfx_v9_0_mqd_init(ring); 3590 gfx_v9_0_kiq_init_register(ring); 3591 soc15_grbm_select(adev, 0, 0, 0, 0); 3592 mutex_unlock(&adev->srbm_mutex); 3593 3594 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3595 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 3596 } 3597 3598 return 0; 3599 } 3600 3601 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) 3602 { 3603 struct amdgpu_device *adev = ring->adev; 3604 struct v9_mqd *mqd = ring->mqd_ptr; 3605 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3606 struct v9_mqd *tmp_mqd; 3607 3608 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 3609 * is not be initialized before 3610 */ 3611 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 3612 3613 if (!tmp_mqd->cp_hqd_pq_control || 3614 (!amdgpu_in_reset(adev) && !adev->in_suspend)) { 3615 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3616 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3617 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3618 mutex_lock(&adev->srbm_mutex); 3619 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3620 gfx_v9_0_mqd_init(ring); 3621 soc15_grbm_select(adev, 0, 0, 0, 0); 3622 mutex_unlock(&adev->srbm_mutex); 3623 3624 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3625 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 3626 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3627 /* reset MQD to a clean status */ 3628 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3629 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 3630 3631 /* reset ring buffer */ 3632 ring->wptr = 0; 3633 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3634 amdgpu_ring_clear_ring(ring); 3635 } else { 3636 amdgpu_ring_clear_ring(ring); 3637 } 3638 3639 return 0; 3640 } 3641 3642 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) 3643 { 3644 struct amdgpu_ring *ring; 3645 int r; 3646 3647 ring = &adev->gfx.kiq.ring; 3648 3649 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3650 if (unlikely(r != 0)) 3651 return r; 3652 3653 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3654 if (unlikely(r != 0)) { 3655 amdgpu_bo_unreserve(ring->mqd_obj); 3656 return r; 3657 } 3658 3659 gfx_v9_0_kiq_init_queue(ring); 3660 amdgpu_bo_kunmap(ring->mqd_obj); 3661 ring->mqd_ptr = NULL; 3662 amdgpu_bo_unreserve(ring->mqd_obj); 3663 ring->sched.ready = true; 3664 return 0; 3665 } 3666 3667 static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev) 3668 { 3669 struct amdgpu_ring *ring = NULL; 3670 int r = 0, i; 3671 3672 gfx_v9_0_cp_compute_enable(adev, true); 3673 3674 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3675 ring = &adev->gfx.compute_ring[i]; 3676 3677 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3678 if (unlikely(r != 0)) 3679 goto done; 3680 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3681 if (!r) { 3682 r = gfx_v9_0_kcq_init_queue(ring); 3683 amdgpu_bo_kunmap(ring->mqd_obj); 3684 ring->mqd_ptr = NULL; 3685 } 3686 amdgpu_bo_unreserve(ring->mqd_obj); 3687 if (r) 3688 goto done; 3689 } 3690 3691 r = amdgpu_gfx_enable_kcq(adev); 3692 done: 3693 return r; 3694 } 3695 3696 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) 3697 { 3698 int r, i; 3699 struct amdgpu_ring *ring; 3700 3701 if (!(adev->flags & AMD_IS_APU)) 3702 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 3703 3704 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 3705 if (adev->gfx.num_gfx_rings) { 3706 /* legacy firmware loading */ 3707 r = gfx_v9_0_cp_gfx_load_microcode(adev); 3708 if (r) 3709 return r; 3710 } 3711 3712 r = gfx_v9_0_cp_compute_load_microcode(adev); 3713 if (r) 3714 return r; 3715 } 3716 3717 r = gfx_v9_0_kiq_resume(adev); 3718 if (r) 3719 return r; 3720 3721 if (adev->gfx.num_gfx_rings) { 3722 r = gfx_v9_0_cp_gfx_resume(adev); 3723 if (r) 3724 return r; 3725 } 3726 3727 r = gfx_v9_0_kcq_resume(adev); 3728 if (r) 3729 return r; 3730 3731 if (adev->gfx.num_gfx_rings) { 3732 ring = &adev->gfx.gfx_ring[0]; 3733 r = amdgpu_ring_test_helper(ring); 3734 if (r) 3735 return r; 3736 } 3737 3738 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3739 ring = &adev->gfx.compute_ring[i]; 3740 amdgpu_ring_test_helper(ring); 3741 } 3742 3743 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 3744 3745 return 0; 3746 } 3747 3748 static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev) 3749 { 3750 u32 tmp; 3751 3752 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1) && 3753 adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2)) 3754 return; 3755 3756 tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG); 3757 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE64KHASH, 3758 adev->df.hash_status.hash_64k); 3759 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE2MHASH, 3760 adev->df.hash_status.hash_2m); 3761 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE1GHASH, 3762 adev->df.hash_status.hash_1g); 3763 WREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG, tmp); 3764 } 3765 3766 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable) 3767 { 3768 if (adev->gfx.num_gfx_rings) 3769 gfx_v9_0_cp_gfx_enable(adev, enable); 3770 gfx_v9_0_cp_compute_enable(adev, enable); 3771 } 3772 3773 static int gfx_v9_0_hw_init(void *handle) 3774 { 3775 int r; 3776 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3777 3778 if (!amdgpu_sriov_vf(adev)) 3779 gfx_v9_0_init_golden_registers(adev); 3780 3781 gfx_v9_0_constants_init(adev); 3782 3783 gfx_v9_0_init_tcp_config(adev); 3784 3785 r = adev->gfx.rlc.funcs->resume(adev); 3786 if (r) 3787 return r; 3788 3789 r = gfx_v9_0_cp_resume(adev); 3790 if (r) 3791 return r; 3792 3793 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 3794 gfx_v9_4_2_set_power_brake_sequence(adev); 3795 3796 return r; 3797 } 3798 3799 static int gfx_v9_0_hw_fini(void *handle) 3800 { 3801 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3802 3803 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 3804 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); 3805 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3806 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3807 3808 /* DF freeze and kcq disable will fail */ 3809 if (!amdgpu_ras_intr_triggered()) 3810 /* disable KCQ to avoid CPC touch memory not valid anymore */ 3811 amdgpu_gfx_disable_kcq(adev); 3812 3813 if (amdgpu_sriov_vf(adev)) { 3814 gfx_v9_0_cp_gfx_enable(adev, false); 3815 /* must disable polling for SRIOV when hw finished, otherwise 3816 * CPC engine may still keep fetching WB address which is already 3817 * invalid after sw finished and trigger DMAR reading error in 3818 * hypervisor side. 3819 */ 3820 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3821 return 0; 3822 } 3823 3824 /* Use deinitialize sequence from CAIL when unbinding device from driver, 3825 * otherwise KIQ is hanging when binding back 3826 */ 3827 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3828 mutex_lock(&adev->srbm_mutex); 3829 soc15_grbm_select(adev, adev->gfx.kiq.ring.me, 3830 adev->gfx.kiq.ring.pipe, 3831 adev->gfx.kiq.ring.queue, 0); 3832 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring); 3833 soc15_grbm_select(adev, 0, 0, 0, 0); 3834 mutex_unlock(&adev->srbm_mutex); 3835 } 3836 3837 gfx_v9_0_cp_enable(adev, false); 3838 3839 /* Skip stopping RLC with A+A reset or when RLC controls GFX clock */ 3840 if ((adev->gmc.xgmi.connected_to_cpu && amdgpu_in_reset(adev)) || 3841 (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2))) { 3842 dev_dbg(adev->dev, "Skipping RLC halt\n"); 3843 return 0; 3844 } 3845 3846 adev->gfx.rlc.funcs->stop(adev); 3847 return 0; 3848 } 3849 3850 static int gfx_v9_0_suspend(void *handle) 3851 { 3852 return gfx_v9_0_hw_fini(handle); 3853 } 3854 3855 static int gfx_v9_0_resume(void *handle) 3856 { 3857 return gfx_v9_0_hw_init(handle); 3858 } 3859 3860 static bool gfx_v9_0_is_idle(void *handle) 3861 { 3862 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3863 3864 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 3865 GRBM_STATUS, GUI_ACTIVE)) 3866 return false; 3867 else 3868 return true; 3869 } 3870 3871 static int gfx_v9_0_wait_for_idle(void *handle) 3872 { 3873 unsigned i; 3874 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3875 3876 for (i = 0; i < adev->usec_timeout; i++) { 3877 if (gfx_v9_0_is_idle(handle)) 3878 return 0; 3879 udelay(1); 3880 } 3881 return -ETIMEDOUT; 3882 } 3883 3884 static int gfx_v9_0_soft_reset(void *handle) 3885 { 3886 u32 grbm_soft_reset = 0; 3887 u32 tmp; 3888 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3889 3890 /* GRBM_STATUS */ 3891 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 3892 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 3893 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 3894 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 3895 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 3896 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 3897 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 3898 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3899 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3900 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3901 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 3902 } 3903 3904 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 3905 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3906 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3907 } 3908 3909 /* GRBM_STATUS2 */ 3910 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 3911 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 3912 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3913 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 3914 3915 3916 if (grbm_soft_reset) { 3917 /* stop the rlc */ 3918 adev->gfx.rlc.funcs->stop(adev); 3919 3920 if (adev->gfx.num_gfx_rings) 3921 /* Disable GFX parsing/prefetching */ 3922 gfx_v9_0_cp_gfx_enable(adev, false); 3923 3924 /* Disable MEC parsing/prefetching */ 3925 gfx_v9_0_cp_compute_enable(adev, false); 3926 3927 if (grbm_soft_reset) { 3928 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3929 tmp |= grbm_soft_reset; 3930 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 3931 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3932 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3933 3934 udelay(50); 3935 3936 tmp &= ~grbm_soft_reset; 3937 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3938 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3939 } 3940 3941 /* Wait a little for things to settle down */ 3942 udelay(50); 3943 } 3944 return 0; 3945 } 3946 3947 static uint64_t gfx_v9_0_kiq_read_clock(struct amdgpu_device *adev) 3948 { 3949 signed long r, cnt = 0; 3950 unsigned long flags; 3951 uint32_t seq, reg_val_offs = 0; 3952 uint64_t value = 0; 3953 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3954 struct amdgpu_ring *ring = &kiq->ring; 3955 3956 BUG_ON(!ring->funcs->emit_rreg); 3957 3958 spin_lock_irqsave(&kiq->ring_lock, flags); 3959 if (amdgpu_device_wb_get(adev, ®_val_offs)) { 3960 pr_err("critical bug! too many kiq readers\n"); 3961 goto failed_unlock; 3962 } 3963 amdgpu_ring_alloc(ring, 32); 3964 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 3965 amdgpu_ring_write(ring, 9 | /* src: register*/ 3966 (5 << 8) | /* dst: memory */ 3967 (1 << 16) | /* count sel */ 3968 (1 << 20)); /* write confirm */ 3969 amdgpu_ring_write(ring, 0); 3970 amdgpu_ring_write(ring, 0); 3971 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 3972 reg_val_offs * 4)); 3973 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 3974 reg_val_offs * 4)); 3975 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 3976 if (r) 3977 goto failed_undo; 3978 3979 amdgpu_ring_commit(ring); 3980 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3981 3982 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 3983 3984 /* don't wait anymore for gpu reset case because this way may 3985 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg 3986 * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will 3987 * never return if we keep waiting in virt_kiq_rreg, which cause 3988 * gpu_recover() hang there. 3989 * 3990 * also don't wait anymore for IRQ context 3991 * */ 3992 if (r < 1 && (amdgpu_in_reset(adev))) 3993 goto failed_kiq_read; 3994 3995 might_sleep(); 3996 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { 3997 drm_msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); 3998 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 3999 } 4000 4001 if (cnt > MAX_KIQ_REG_TRY) 4002 goto failed_kiq_read; 4003 4004 mb(); 4005 value = (uint64_t)adev->wb.wb[reg_val_offs] | 4006 (uint64_t)adev->wb.wb[reg_val_offs + 1 ] << 32ULL; 4007 amdgpu_device_wb_free(adev, reg_val_offs); 4008 return value; 4009 4010 failed_undo: 4011 amdgpu_ring_undo(ring); 4012 failed_unlock: 4013 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4014 failed_kiq_read: 4015 if (reg_val_offs) 4016 amdgpu_device_wb_free(adev, reg_val_offs); 4017 pr_err("failed to read gpu clock\n"); 4018 return ~0; 4019 } 4020 4021 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4022 { 4023 uint64_t clock, clock_lo, clock_hi, hi_check; 4024 4025 switch (adev->ip_versions[GC_HWIP][0]) { 4026 case IP_VERSION(9, 3, 0): 4027 preempt_disable(); 4028 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir); 4029 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir); 4030 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir); 4031 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 4032 * roughly every 42 seconds. 4033 */ 4034 if (hi_check != clock_hi) { 4035 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir); 4036 clock_hi = hi_check; 4037 } 4038 preempt_enable(); 4039 clock = clock_lo | (clock_hi << 32ULL); 4040 break; 4041 default: 4042 amdgpu_gfx_off_ctrl(adev, false); 4043 mutex_lock(&adev->gfx.gpu_clock_mutex); 4044 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 0, 1) && amdgpu_sriov_runtime(adev)) { 4045 clock = gfx_v9_0_kiq_read_clock(adev); 4046 } else { 4047 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4048 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | 4049 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4050 } 4051 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4052 amdgpu_gfx_off_ctrl(adev, true); 4053 break; 4054 } 4055 return clock; 4056 } 4057 4058 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4059 uint32_t vmid, 4060 uint32_t gds_base, uint32_t gds_size, 4061 uint32_t gws_base, uint32_t gws_size, 4062 uint32_t oa_base, uint32_t oa_size) 4063 { 4064 struct amdgpu_device *adev = ring->adev; 4065 4066 /* GDS Base */ 4067 gfx_v9_0_write_data_to_reg(ring, 0, false, 4068 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 4069 gds_base); 4070 4071 /* GDS Size */ 4072 gfx_v9_0_write_data_to_reg(ring, 0, false, 4073 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 4074 gds_size); 4075 4076 /* GWS */ 4077 gfx_v9_0_write_data_to_reg(ring, 0, false, 4078 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 4079 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4080 4081 /* OA */ 4082 gfx_v9_0_write_data_to_reg(ring, 0, false, 4083 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 4084 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4085 } 4086 4087 static const u32 vgpr_init_compute_shader[] = 4088 { 4089 0xb07c0000, 0xbe8000ff, 4090 0x000000f8, 0xbf110800, 4091 0x7e000280, 0x7e020280, 4092 0x7e040280, 0x7e060280, 4093 0x7e080280, 0x7e0a0280, 4094 0x7e0c0280, 0x7e0e0280, 4095 0x80808800, 0xbe803200, 4096 0xbf84fff5, 0xbf9c0000, 4097 0xd28c0001, 0x0001007f, 4098 0xd28d0001, 0x0002027e, 4099 0x10020288, 0xb8810904, 4100 0xb7814000, 0xd1196a01, 4101 0x00000301, 0xbe800087, 4102 0xbefc00c1, 0xd89c4000, 4103 0x00020201, 0xd89cc080, 4104 0x00040401, 0x320202ff, 4105 0x00000800, 0x80808100, 4106 0xbf84fff8, 0x7e020280, 4107 0xbf810000, 0x00000000, 4108 }; 4109 4110 static const u32 sgpr_init_compute_shader[] = 4111 { 4112 0xb07c0000, 0xbe8000ff, 4113 0x0000005f, 0xbee50080, 4114 0xbe812c65, 0xbe822c65, 4115 0xbe832c65, 0xbe842c65, 4116 0xbe852c65, 0xb77c0005, 4117 0x80808500, 0xbf84fff8, 4118 0xbe800080, 0xbf810000, 4119 }; 4120 4121 static const u32 vgpr_init_compute_shader_arcturus[] = { 4122 0xd3d94000, 0x18000080, 0xd3d94001, 0x18000080, 0xd3d94002, 0x18000080, 4123 0xd3d94003, 0x18000080, 0xd3d94004, 0x18000080, 0xd3d94005, 0x18000080, 4124 0xd3d94006, 0x18000080, 0xd3d94007, 0x18000080, 0xd3d94008, 0x18000080, 4125 0xd3d94009, 0x18000080, 0xd3d9400a, 0x18000080, 0xd3d9400b, 0x18000080, 4126 0xd3d9400c, 0x18000080, 0xd3d9400d, 0x18000080, 0xd3d9400e, 0x18000080, 4127 0xd3d9400f, 0x18000080, 0xd3d94010, 0x18000080, 0xd3d94011, 0x18000080, 4128 0xd3d94012, 0x18000080, 0xd3d94013, 0x18000080, 0xd3d94014, 0x18000080, 4129 0xd3d94015, 0x18000080, 0xd3d94016, 0x18000080, 0xd3d94017, 0x18000080, 4130 0xd3d94018, 0x18000080, 0xd3d94019, 0x18000080, 0xd3d9401a, 0x18000080, 4131 0xd3d9401b, 0x18000080, 0xd3d9401c, 0x18000080, 0xd3d9401d, 0x18000080, 4132 0xd3d9401e, 0x18000080, 0xd3d9401f, 0x18000080, 0xd3d94020, 0x18000080, 4133 0xd3d94021, 0x18000080, 0xd3d94022, 0x18000080, 0xd3d94023, 0x18000080, 4134 0xd3d94024, 0x18000080, 0xd3d94025, 0x18000080, 0xd3d94026, 0x18000080, 4135 0xd3d94027, 0x18000080, 0xd3d94028, 0x18000080, 0xd3d94029, 0x18000080, 4136 0xd3d9402a, 0x18000080, 0xd3d9402b, 0x18000080, 0xd3d9402c, 0x18000080, 4137 0xd3d9402d, 0x18000080, 0xd3d9402e, 0x18000080, 0xd3d9402f, 0x18000080, 4138 0xd3d94030, 0x18000080, 0xd3d94031, 0x18000080, 0xd3d94032, 0x18000080, 4139 0xd3d94033, 0x18000080, 0xd3d94034, 0x18000080, 0xd3d94035, 0x18000080, 4140 0xd3d94036, 0x18000080, 0xd3d94037, 0x18000080, 0xd3d94038, 0x18000080, 4141 0xd3d94039, 0x18000080, 0xd3d9403a, 0x18000080, 0xd3d9403b, 0x18000080, 4142 0xd3d9403c, 0x18000080, 0xd3d9403d, 0x18000080, 0xd3d9403e, 0x18000080, 4143 0xd3d9403f, 0x18000080, 0xd3d94040, 0x18000080, 0xd3d94041, 0x18000080, 4144 0xd3d94042, 0x18000080, 0xd3d94043, 0x18000080, 0xd3d94044, 0x18000080, 4145 0xd3d94045, 0x18000080, 0xd3d94046, 0x18000080, 0xd3d94047, 0x18000080, 4146 0xd3d94048, 0x18000080, 0xd3d94049, 0x18000080, 0xd3d9404a, 0x18000080, 4147 0xd3d9404b, 0x18000080, 0xd3d9404c, 0x18000080, 0xd3d9404d, 0x18000080, 4148 0xd3d9404e, 0x18000080, 0xd3d9404f, 0x18000080, 0xd3d94050, 0x18000080, 4149 0xd3d94051, 0x18000080, 0xd3d94052, 0x18000080, 0xd3d94053, 0x18000080, 4150 0xd3d94054, 0x18000080, 0xd3d94055, 0x18000080, 0xd3d94056, 0x18000080, 4151 0xd3d94057, 0x18000080, 0xd3d94058, 0x18000080, 0xd3d94059, 0x18000080, 4152 0xd3d9405a, 0x18000080, 0xd3d9405b, 0x18000080, 0xd3d9405c, 0x18000080, 4153 0xd3d9405d, 0x18000080, 0xd3d9405e, 0x18000080, 0xd3d9405f, 0x18000080, 4154 0xd3d94060, 0x18000080, 0xd3d94061, 0x18000080, 0xd3d94062, 0x18000080, 4155 0xd3d94063, 0x18000080, 0xd3d94064, 0x18000080, 0xd3d94065, 0x18000080, 4156 0xd3d94066, 0x18000080, 0xd3d94067, 0x18000080, 0xd3d94068, 0x18000080, 4157 0xd3d94069, 0x18000080, 0xd3d9406a, 0x18000080, 0xd3d9406b, 0x18000080, 4158 0xd3d9406c, 0x18000080, 0xd3d9406d, 0x18000080, 0xd3d9406e, 0x18000080, 4159 0xd3d9406f, 0x18000080, 0xd3d94070, 0x18000080, 0xd3d94071, 0x18000080, 4160 0xd3d94072, 0x18000080, 0xd3d94073, 0x18000080, 0xd3d94074, 0x18000080, 4161 0xd3d94075, 0x18000080, 0xd3d94076, 0x18000080, 0xd3d94077, 0x18000080, 4162 0xd3d94078, 0x18000080, 0xd3d94079, 0x18000080, 0xd3d9407a, 0x18000080, 4163 0xd3d9407b, 0x18000080, 0xd3d9407c, 0x18000080, 0xd3d9407d, 0x18000080, 4164 0xd3d9407e, 0x18000080, 0xd3d9407f, 0x18000080, 0xd3d94080, 0x18000080, 4165 0xd3d94081, 0x18000080, 0xd3d94082, 0x18000080, 0xd3d94083, 0x18000080, 4166 0xd3d94084, 0x18000080, 0xd3d94085, 0x18000080, 0xd3d94086, 0x18000080, 4167 0xd3d94087, 0x18000080, 0xd3d94088, 0x18000080, 0xd3d94089, 0x18000080, 4168 0xd3d9408a, 0x18000080, 0xd3d9408b, 0x18000080, 0xd3d9408c, 0x18000080, 4169 0xd3d9408d, 0x18000080, 0xd3d9408e, 0x18000080, 0xd3d9408f, 0x18000080, 4170 0xd3d94090, 0x18000080, 0xd3d94091, 0x18000080, 0xd3d94092, 0x18000080, 4171 0xd3d94093, 0x18000080, 0xd3d94094, 0x18000080, 0xd3d94095, 0x18000080, 4172 0xd3d94096, 0x18000080, 0xd3d94097, 0x18000080, 0xd3d94098, 0x18000080, 4173 0xd3d94099, 0x18000080, 0xd3d9409a, 0x18000080, 0xd3d9409b, 0x18000080, 4174 0xd3d9409c, 0x18000080, 0xd3d9409d, 0x18000080, 0xd3d9409e, 0x18000080, 4175 0xd3d9409f, 0x18000080, 0xd3d940a0, 0x18000080, 0xd3d940a1, 0x18000080, 4176 0xd3d940a2, 0x18000080, 0xd3d940a3, 0x18000080, 0xd3d940a4, 0x18000080, 4177 0xd3d940a5, 0x18000080, 0xd3d940a6, 0x18000080, 0xd3d940a7, 0x18000080, 4178 0xd3d940a8, 0x18000080, 0xd3d940a9, 0x18000080, 0xd3d940aa, 0x18000080, 4179 0xd3d940ab, 0x18000080, 0xd3d940ac, 0x18000080, 0xd3d940ad, 0x18000080, 4180 0xd3d940ae, 0x18000080, 0xd3d940af, 0x18000080, 0xd3d940b0, 0x18000080, 4181 0xd3d940b1, 0x18000080, 0xd3d940b2, 0x18000080, 0xd3d940b3, 0x18000080, 4182 0xd3d940b4, 0x18000080, 0xd3d940b5, 0x18000080, 0xd3d940b6, 0x18000080, 4183 0xd3d940b7, 0x18000080, 0xd3d940b8, 0x18000080, 0xd3d940b9, 0x18000080, 4184 0xd3d940ba, 0x18000080, 0xd3d940bb, 0x18000080, 0xd3d940bc, 0x18000080, 4185 0xd3d940bd, 0x18000080, 0xd3d940be, 0x18000080, 0xd3d940bf, 0x18000080, 4186 0xd3d940c0, 0x18000080, 0xd3d940c1, 0x18000080, 0xd3d940c2, 0x18000080, 4187 0xd3d940c3, 0x18000080, 0xd3d940c4, 0x18000080, 0xd3d940c5, 0x18000080, 4188 0xd3d940c6, 0x18000080, 0xd3d940c7, 0x18000080, 0xd3d940c8, 0x18000080, 4189 0xd3d940c9, 0x18000080, 0xd3d940ca, 0x18000080, 0xd3d940cb, 0x18000080, 4190 0xd3d940cc, 0x18000080, 0xd3d940cd, 0x18000080, 0xd3d940ce, 0x18000080, 4191 0xd3d940cf, 0x18000080, 0xd3d940d0, 0x18000080, 0xd3d940d1, 0x18000080, 4192 0xd3d940d2, 0x18000080, 0xd3d940d3, 0x18000080, 0xd3d940d4, 0x18000080, 4193 0xd3d940d5, 0x18000080, 0xd3d940d6, 0x18000080, 0xd3d940d7, 0x18000080, 4194 0xd3d940d8, 0x18000080, 0xd3d940d9, 0x18000080, 0xd3d940da, 0x18000080, 4195 0xd3d940db, 0x18000080, 0xd3d940dc, 0x18000080, 0xd3d940dd, 0x18000080, 4196 0xd3d940de, 0x18000080, 0xd3d940df, 0x18000080, 0xd3d940e0, 0x18000080, 4197 0xd3d940e1, 0x18000080, 0xd3d940e2, 0x18000080, 0xd3d940e3, 0x18000080, 4198 0xd3d940e4, 0x18000080, 0xd3d940e5, 0x18000080, 0xd3d940e6, 0x18000080, 4199 0xd3d940e7, 0x18000080, 0xd3d940e8, 0x18000080, 0xd3d940e9, 0x18000080, 4200 0xd3d940ea, 0x18000080, 0xd3d940eb, 0x18000080, 0xd3d940ec, 0x18000080, 4201 0xd3d940ed, 0x18000080, 0xd3d940ee, 0x18000080, 0xd3d940ef, 0x18000080, 4202 0xd3d940f0, 0x18000080, 0xd3d940f1, 0x18000080, 0xd3d940f2, 0x18000080, 4203 0xd3d940f3, 0x18000080, 0xd3d940f4, 0x18000080, 0xd3d940f5, 0x18000080, 4204 0xd3d940f6, 0x18000080, 0xd3d940f7, 0x18000080, 0xd3d940f8, 0x18000080, 4205 0xd3d940f9, 0x18000080, 0xd3d940fa, 0x18000080, 0xd3d940fb, 0x18000080, 4206 0xd3d940fc, 0x18000080, 0xd3d940fd, 0x18000080, 0xd3d940fe, 0x18000080, 4207 0xd3d940ff, 0x18000080, 0xb07c0000, 0xbe8a00ff, 0x000000f8, 0xbf11080a, 4208 0x7e000280, 0x7e020280, 0x7e040280, 0x7e060280, 0x7e080280, 0x7e0a0280, 4209 0x7e0c0280, 0x7e0e0280, 0x808a880a, 0xbe80320a, 0xbf84fff5, 0xbf9c0000, 4210 0xd28c0001, 0x0001007f, 0xd28d0001, 0x0002027e, 0x10020288, 0xb88b0904, 4211 0xb78b4000, 0xd1196a01, 0x00001701, 0xbe8a0087, 0xbefc00c1, 0xd89c4000, 4212 0x00020201, 0xd89cc080, 0x00040401, 0x320202ff, 0x00000800, 0x808a810a, 4213 0xbf84fff8, 0xbf810000, 4214 }; 4215 4216 /* When below register arrays changed, please update gpr_reg_size, 4217 and sec_ded_counter_reg_size in function gfx_v9_0_do_edc_gpr_workarounds, 4218 to cover all gfx9 ASICs */ 4219 static const struct soc15_reg_entry vgpr_init_regs[] = { 4220 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4221 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4222 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 }, 4223 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4224 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x3f }, 4225 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */ 4226 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, 4227 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, 4228 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, 4229 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, 4230 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, 4231 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, 4232 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, 4233 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, 4234 }; 4235 4236 static const struct soc15_reg_entry vgpr_init_regs_arcturus[] = { 4237 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4238 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4239 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 }, 4240 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4241 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0xbf }, 4242 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */ 4243 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, 4244 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, 4245 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, 4246 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, 4247 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, 4248 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, 4249 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, 4250 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, 4251 }; 4252 4253 static const struct soc15_reg_entry sgpr1_init_regs[] = { 4254 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4255 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4256 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 }, 4257 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4258 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */ 4259 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 }, 4260 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x000000ff }, 4261 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x000000ff }, 4262 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x000000ff }, 4263 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x000000ff }, 4264 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x000000ff }, 4265 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x000000ff }, 4266 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x000000ff }, 4267 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x000000ff }, 4268 }; 4269 4270 static const struct soc15_reg_entry sgpr2_init_regs[] = { 4271 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4272 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4273 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 }, 4274 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4275 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */ 4276 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 }, 4277 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x0000ff00 }, 4278 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x0000ff00 }, 4279 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x0000ff00 }, 4280 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x0000ff00 }, 4281 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x0000ff00 }, 4282 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x0000ff00 }, 4283 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x0000ff00 }, 4284 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x0000ff00 }, 4285 }; 4286 4287 static const struct soc15_reg_entry gfx_v9_0_edc_counter_regs[] = { 4288 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1}, 4289 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1}, 4290 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1}, 4291 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1}, 4292 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1, 1}, 4293 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1, 1}, 4294 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1}, 4295 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1}, 4296 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1}, 4297 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1}, 4298 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1}, 4299 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1}, 4300 { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1}, 4301 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 0, 4, 6}, 4302 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT), 0, 4, 16}, 4303 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 4, 16}, 4304 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 4, 16}, 4305 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16}, 4306 { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16}, 4307 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16}, 4308 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 0, 4, 16}, 4309 { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16}, 4310 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6}, 4311 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 4, 16}, 4312 { SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 0, 4, 16}, 4313 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, 1}, 4314 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, 1}, 4315 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 1, 32}, 4316 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 1, 32}, 4317 { SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 1, 72}, 4318 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16}, 4319 { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2}, 4320 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6}, 4321 }; 4322 4323 static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev) 4324 { 4325 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; 4326 int i, r; 4327 4328 /* only support when RAS is enabled */ 4329 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 4330 return 0; 4331 4332 r = amdgpu_ring_alloc(ring, 7); 4333 if (r) { 4334 DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n", 4335 ring->name, r); 4336 return r; 4337 } 4338 4339 WREG32_SOC15(GC, 0, mmGDS_VMID0_BASE, 0x00000000); 4340 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, adev->gds.gds_size); 4341 4342 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); 4343 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | 4344 PACKET3_DMA_DATA_DST_SEL(1) | 4345 PACKET3_DMA_DATA_SRC_SEL(2) | 4346 PACKET3_DMA_DATA_ENGINE(0))); 4347 amdgpu_ring_write(ring, 0); 4348 amdgpu_ring_write(ring, 0); 4349 amdgpu_ring_write(ring, 0); 4350 amdgpu_ring_write(ring, 0); 4351 amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | 4352 adev->gds.gds_size); 4353 4354 amdgpu_ring_commit(ring); 4355 4356 for (i = 0; i < adev->usec_timeout; i++) { 4357 if (ring->wptr == gfx_v9_0_ring_get_rptr_compute(ring)) 4358 break; 4359 udelay(1); 4360 } 4361 4362 if (i >= adev->usec_timeout) 4363 r = -ETIMEDOUT; 4364 4365 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, 0x00000000); 4366 4367 return r; 4368 } 4369 4370 static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) 4371 { 4372 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; 4373 struct amdgpu_ib ib; 4374 struct dma_fence *f = NULL; 4375 int r, i; 4376 unsigned total_size, vgpr_offset, sgpr_offset; 4377 u64 gpu_addr; 4378 4379 int compute_dim_x = adev->gfx.config.max_shader_engines * 4380 adev->gfx.config.max_cu_per_sh * 4381 adev->gfx.config.max_sh_per_se; 4382 int sgpr_work_group_size = 5; 4383 int gpr_reg_size = adev->gfx.config.max_shader_engines + 6; 4384 int vgpr_init_shader_size; 4385 const u32 *vgpr_init_shader_ptr; 4386 const struct soc15_reg_entry *vgpr_init_regs_ptr; 4387 4388 /* only support when RAS is enabled */ 4389 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 4390 return 0; 4391 4392 /* bail if the compute ring is not ready */ 4393 if (!ring->sched.ready) 4394 return 0; 4395 4396 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) { 4397 vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus; 4398 vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus); 4399 vgpr_init_regs_ptr = vgpr_init_regs_arcturus; 4400 } else { 4401 vgpr_init_shader_ptr = vgpr_init_compute_shader; 4402 vgpr_init_shader_size = sizeof(vgpr_init_compute_shader); 4403 vgpr_init_regs_ptr = vgpr_init_regs; 4404 } 4405 4406 total_size = 4407 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* VGPRS */ 4408 total_size += 4409 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS1 */ 4410 total_size += 4411 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS2 */ 4412 total_size = roundup2(total_size, 256); 4413 vgpr_offset = total_size; 4414 total_size += roundup2(vgpr_init_shader_size, 256); 4415 sgpr_offset = total_size; 4416 total_size += sizeof(sgpr_init_compute_shader); 4417 4418 /* allocate an indirect buffer to put the commands in */ 4419 memset(&ib, 0, sizeof(ib)); 4420 r = amdgpu_ib_get(adev, NULL, total_size, 4421 AMDGPU_IB_POOL_DIRECT, &ib); 4422 if (r) { 4423 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); 4424 return r; 4425 } 4426 4427 /* load the compute shaders */ 4428 for (i = 0; i < vgpr_init_shader_size/sizeof(u32); i++) 4429 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_shader_ptr[i]; 4430 4431 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++) 4432 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i]; 4433 4434 /* init the ib length to 0 */ 4435 ib.length_dw = 0; 4436 4437 /* VGPR */ 4438 /* write the register state for the compute dispatch */ 4439 for (i = 0; i < gpr_reg_size; i++) { 4440 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4441 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs_ptr[i]) 4442 - PACKET3_SET_SH_REG_START; 4443 ib.ptr[ib.length_dw++] = vgpr_init_regs_ptr[i].reg_value; 4444 } 4445 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4446 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8; 4447 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4448 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4449 - PACKET3_SET_SH_REG_START; 4450 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4451 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4452 4453 /* write dispatch packet */ 4454 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4455 ib.ptr[ib.length_dw++] = compute_dim_x * 2; /* x */ 4456 ib.ptr[ib.length_dw++] = 1; /* y */ 4457 ib.ptr[ib.length_dw++] = 1; /* z */ 4458 ib.ptr[ib.length_dw++] = 4459 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4460 4461 /* write CS partial flush packet */ 4462 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4463 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4464 4465 /* SGPR1 */ 4466 /* write the register state for the compute dispatch */ 4467 for (i = 0; i < gpr_reg_size; i++) { 4468 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4469 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i]) 4470 - PACKET3_SET_SH_REG_START; 4471 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i].reg_value; 4472 } 4473 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4474 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; 4475 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4476 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4477 - PACKET3_SET_SH_REG_START; 4478 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4479 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4480 4481 /* write dispatch packet */ 4482 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4483 ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */ 4484 ib.ptr[ib.length_dw++] = 1; /* y */ 4485 ib.ptr[ib.length_dw++] = 1; /* z */ 4486 ib.ptr[ib.length_dw++] = 4487 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4488 4489 /* write CS partial flush packet */ 4490 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4491 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4492 4493 /* SGPR2 */ 4494 /* write the register state for the compute dispatch */ 4495 for (i = 0; i < gpr_reg_size; i++) { 4496 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4497 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i]) 4498 - PACKET3_SET_SH_REG_START; 4499 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i].reg_value; 4500 } 4501 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4502 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; 4503 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4504 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4505 - PACKET3_SET_SH_REG_START; 4506 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4507 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4508 4509 /* write dispatch packet */ 4510 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4511 ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */ 4512 ib.ptr[ib.length_dw++] = 1; /* y */ 4513 ib.ptr[ib.length_dw++] = 1; /* z */ 4514 ib.ptr[ib.length_dw++] = 4515 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4516 4517 /* write CS partial flush packet */ 4518 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4519 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4520 4521 /* shedule the ib on the ring */ 4522 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 4523 if (r) { 4524 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r); 4525 goto fail; 4526 } 4527 4528 /* wait for the GPU to finish processing the IB */ 4529 r = dma_fence_wait(f, false); 4530 if (r) { 4531 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 4532 goto fail; 4533 } 4534 4535 fail: 4536 amdgpu_ib_free(adev, &ib, NULL); 4537 dma_fence_put(f); 4538 4539 return r; 4540 } 4541 4542 static int gfx_v9_0_early_init(void *handle) 4543 { 4544 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4545 4546 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || 4547 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 4548 adev->gfx.num_gfx_rings = 0; 4549 else 4550 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; 4551 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4552 AMDGPU_MAX_COMPUTE_RINGS); 4553 gfx_v9_0_set_kiq_pm4_funcs(adev); 4554 gfx_v9_0_set_ring_funcs(adev); 4555 gfx_v9_0_set_irq_funcs(adev); 4556 gfx_v9_0_set_gds_init(adev); 4557 gfx_v9_0_set_rlc_funcs(adev); 4558 4559 /* init rlcg reg access ctrl */ 4560 gfx_v9_0_init_rlcg_reg_access_ctrl(adev); 4561 4562 return 0; 4563 } 4564 4565 static int gfx_v9_0_ecc_late_init(void *handle) 4566 { 4567 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4568 int r; 4569 4570 /* 4571 * Temp workaround to fix the issue that CP firmware fails to 4572 * update read pointer when CPDMA is writing clearing operation 4573 * to GDS in suspend/resume sequence on several cards. So just 4574 * limit this operation in cold boot sequence. 4575 */ 4576 if ((!adev->in_suspend) && 4577 (adev->gds.gds_size)) { 4578 r = gfx_v9_0_do_edc_gds_workarounds(adev); 4579 if (r) 4580 return r; 4581 } 4582 4583 /* requires IBs so do in late init after IB pool is initialized */ 4584 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 4585 r = gfx_v9_4_2_do_edc_gpr_workarounds(adev); 4586 else 4587 r = gfx_v9_0_do_edc_gpr_workarounds(adev); 4588 4589 if (r) 4590 return r; 4591 4592 if (adev->gfx.ras && 4593 adev->gfx.ras->enable_watchdog_timer) 4594 adev->gfx.ras->enable_watchdog_timer(adev); 4595 4596 return 0; 4597 } 4598 4599 static int gfx_v9_0_late_init(void *handle) 4600 { 4601 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4602 int r; 4603 4604 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4605 if (r) 4606 return r; 4607 4608 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4609 if (r) 4610 return r; 4611 4612 r = gfx_v9_0_ecc_late_init(handle); 4613 if (r) 4614 return r; 4615 4616 return 0; 4617 } 4618 4619 static bool gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev) 4620 { 4621 uint32_t rlc_setting; 4622 4623 /* if RLC is not enabled, do nothing */ 4624 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); 4625 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 4626 return false; 4627 4628 return true; 4629 } 4630 4631 static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev) 4632 { 4633 uint32_t data; 4634 unsigned i; 4635 4636 data = RLC_SAFE_MODE__CMD_MASK; 4637 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4638 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4639 4640 /* wait for RLC_SAFE_MODE */ 4641 for (i = 0; i < adev->usec_timeout; i++) { 4642 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 4643 break; 4644 udelay(1); 4645 } 4646 } 4647 4648 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev) 4649 { 4650 uint32_t data; 4651 4652 data = RLC_SAFE_MODE__CMD_MASK; 4653 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4654 } 4655 4656 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, 4657 bool enable) 4658 { 4659 amdgpu_gfx_rlc_enter_safe_mode(adev); 4660 4661 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) { 4662 gfx_v9_0_enable_gfx_cg_power_gating(adev, true); 4663 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 4664 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true); 4665 } else { 4666 gfx_v9_0_enable_gfx_cg_power_gating(adev, false); 4667 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 4668 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false); 4669 } 4670 4671 amdgpu_gfx_rlc_exit_safe_mode(adev); 4672 } 4673 4674 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev, 4675 bool enable) 4676 { 4677 /* TODO: double check if we need to perform under safe mode */ 4678 /* gfx_v9_0_enter_rlc_safe_mode(adev); */ 4679 4680 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) 4681 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true); 4682 else 4683 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false); 4684 4685 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable) 4686 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true); 4687 else 4688 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false); 4689 4690 /* gfx_v9_0_exit_rlc_safe_mode(adev); */ 4691 } 4692 4693 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4694 bool enable) 4695 { 4696 uint32_t data, def; 4697 4698 amdgpu_gfx_rlc_enter_safe_mode(adev); 4699 4700 /* It is disabled by HW by default */ 4701 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 4702 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4703 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4704 4705 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1)) 4706 data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 4707 4708 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4709 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4710 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4711 4712 /* only for Vega10 & Raven1 */ 4713 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 4714 4715 if (def != data) 4716 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4717 4718 /* MGLS is a global flag to control all MGLS in GFX */ 4719 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 4720 /* 2 - RLC memory Light sleep */ 4721 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 4722 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4723 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4724 if (def != data) 4725 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4726 } 4727 /* 3 - CP memory Light sleep */ 4728 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 4729 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4730 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4731 if (def != data) 4732 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4733 } 4734 } 4735 } else { 4736 /* 1 - MGCG_OVERRIDE */ 4737 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4738 4739 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1)) 4740 data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 4741 4742 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4743 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4744 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4745 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4746 4747 if (def != data) 4748 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4749 4750 /* 2 - disable MGLS in RLC */ 4751 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4752 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 4753 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4754 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4755 } 4756 4757 /* 3 - disable MGLS in CP */ 4758 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4759 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 4760 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4761 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4762 } 4763 } 4764 4765 amdgpu_gfx_rlc_exit_safe_mode(adev); 4766 } 4767 4768 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, 4769 bool enable) 4770 { 4771 uint32_t data, def; 4772 4773 if (!adev->gfx.num_gfx_rings) 4774 return; 4775 4776 amdgpu_gfx_rlc_enter_safe_mode(adev); 4777 4778 /* Enable 3D CGCG/CGLS */ 4779 if (enable) { 4780 /* write cmd to clear cgcg/cgls ov */ 4781 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4782 /* unset CGCG override */ 4783 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4784 /* update CGCG and CGLS override bits */ 4785 if (def != data) 4786 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4787 4788 /* enable 3Dcgcg FSM(0x0000363f) */ 4789 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4790 4791 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4792 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4793 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4794 else 4795 data = 0x0 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT; 4796 4797 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4798 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4799 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4800 if (def != data) 4801 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4802 4803 /* set IDLE_POLL_COUNT(0x00900100) */ 4804 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4805 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4806 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4807 if (def != data) 4808 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4809 } else { 4810 /* Disable CGCG/CGLS */ 4811 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4812 /* disable cgcg, cgls should be disabled */ 4813 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 4814 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 4815 /* disable cgcg and cgls in FSM */ 4816 if (def != data) 4817 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4818 } 4819 4820 amdgpu_gfx_rlc_exit_safe_mode(adev); 4821 } 4822 4823 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4824 bool enable) 4825 { 4826 uint32_t def, data; 4827 4828 amdgpu_gfx_rlc_enter_safe_mode(adev); 4829 4830 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 4831 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4832 /* unset CGCG override */ 4833 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4834 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4835 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4836 else 4837 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4838 /* update CGCG and CGLS override bits */ 4839 if (def != data) 4840 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4841 4842 /* enable cgcg FSM(0x0000363F) */ 4843 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4844 4845 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) 4846 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4847 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4848 else 4849 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4850 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4851 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4852 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4853 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4854 if (def != data) 4855 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4856 4857 /* set IDLE_POLL_COUNT(0x00900100) */ 4858 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4859 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4860 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4861 if (def != data) 4862 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4863 } else { 4864 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4865 /* reset CGCG/CGLS bits */ 4866 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 4867 /* disable cgcg and cgls in FSM */ 4868 if (def != data) 4869 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4870 } 4871 4872 amdgpu_gfx_rlc_exit_safe_mode(adev); 4873 } 4874 4875 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4876 bool enable) 4877 { 4878 if (enable) { 4879 /* CGCG/CGLS should be enabled after MGCG/MGLS 4880 * === MGCG + MGLS === 4881 */ 4882 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 4883 /* === CGCG /CGLS for GFX 3D Only === */ 4884 gfx_v9_0_update_3d_clock_gating(adev, enable); 4885 /* === CGCG + CGLS === */ 4886 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 4887 } else { 4888 /* CGCG/CGLS should be disabled before MGCG/MGLS 4889 * === CGCG + CGLS === 4890 */ 4891 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 4892 /* === CGCG /CGLS for GFX 3D Only === */ 4893 gfx_v9_0_update_3d_clock_gating(adev, enable); 4894 /* === MGCG + MGLS === */ 4895 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 4896 } 4897 return 0; 4898 } 4899 4900 static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 4901 { 4902 u32 reg, data; 4903 4904 amdgpu_gfx_off_ctrl(adev, false); 4905 4906 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 4907 if (amdgpu_sriov_is_pp_one_vf(adev)) 4908 data = RREG32_NO_KIQ(reg); 4909 else 4910 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); 4911 4912 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 4913 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 4914 4915 if (amdgpu_sriov_is_pp_one_vf(adev)) 4916 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 4917 else 4918 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 4919 4920 amdgpu_gfx_off_ctrl(adev, true); 4921 } 4922 4923 static bool gfx_v9_0_check_rlcg_range(struct amdgpu_device *adev, 4924 uint32_t offset, 4925 struct soc15_reg_rlcg *entries, int arr_size) 4926 { 4927 int i; 4928 uint32_t reg; 4929 4930 if (!entries) 4931 return false; 4932 4933 for (i = 0; i < arr_size; i++) { 4934 const struct soc15_reg_rlcg *entry; 4935 4936 entry = &entries[i]; 4937 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 4938 if (offset == reg) 4939 return true; 4940 } 4941 4942 return false; 4943 } 4944 4945 static bool gfx_v9_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 4946 { 4947 return gfx_v9_0_check_rlcg_range(adev, offset, 4948 (void *)rlcg_access_gc_9_0, 4949 ARRAY_SIZE(rlcg_access_gc_9_0)); 4950 } 4951 4952 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { 4953 .is_rlc_enabled = gfx_v9_0_is_rlc_enabled, 4954 .set_safe_mode = gfx_v9_0_set_safe_mode, 4955 .unset_safe_mode = gfx_v9_0_unset_safe_mode, 4956 .init = gfx_v9_0_rlc_init, 4957 .get_csb_size = gfx_v9_0_get_csb_size, 4958 .get_csb_buffer = gfx_v9_0_get_csb_buffer, 4959 .get_cp_table_num = gfx_v9_0_cp_jump_table_num, 4960 .resume = gfx_v9_0_rlc_resume, 4961 .stop = gfx_v9_0_rlc_stop, 4962 .reset = gfx_v9_0_rlc_reset, 4963 .start = gfx_v9_0_rlc_start, 4964 .update_spm_vmid = gfx_v9_0_update_spm_vmid, 4965 .is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range, 4966 }; 4967 4968 static int gfx_v9_0_set_powergating_state(void *handle, 4969 enum amd_powergating_state state) 4970 { 4971 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4972 bool enable = (state == AMD_PG_STATE_GATE); 4973 4974 switch (adev->ip_versions[GC_HWIP][0]) { 4975 case IP_VERSION(9, 2, 2): 4976 case IP_VERSION(9, 1, 0): 4977 case IP_VERSION(9, 3, 0): 4978 if (!enable) 4979 amdgpu_gfx_off_ctrl(adev, false); 4980 4981 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 4982 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true); 4983 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true); 4984 } else { 4985 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false); 4986 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false); 4987 } 4988 4989 if (adev->pg_flags & AMD_PG_SUPPORT_CP) 4990 gfx_v9_0_enable_cp_power_gating(adev, true); 4991 else 4992 gfx_v9_0_enable_cp_power_gating(adev, false); 4993 4994 /* update gfx cgpg state */ 4995 gfx_v9_0_update_gfx_cg_power_gating(adev, enable); 4996 4997 /* update mgcg state */ 4998 gfx_v9_0_update_gfx_mg_power_gating(adev, enable); 4999 5000 if (enable) 5001 amdgpu_gfx_off_ctrl(adev, true); 5002 break; 5003 case IP_VERSION(9, 2, 1): 5004 amdgpu_gfx_off_ctrl(adev, enable); 5005 break; 5006 default: 5007 break; 5008 } 5009 5010 return 0; 5011 } 5012 5013 static int gfx_v9_0_set_clockgating_state(void *handle, 5014 enum amd_clockgating_state state) 5015 { 5016 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5017 5018 if (amdgpu_sriov_vf(adev)) 5019 return 0; 5020 5021 switch (adev->ip_versions[GC_HWIP][0]) { 5022 case IP_VERSION(9, 0, 1): 5023 case IP_VERSION(9, 2, 1): 5024 case IP_VERSION(9, 4, 0): 5025 case IP_VERSION(9, 2, 2): 5026 case IP_VERSION(9, 1, 0): 5027 case IP_VERSION(9, 4, 1): 5028 case IP_VERSION(9, 3, 0): 5029 case IP_VERSION(9, 4, 2): 5030 gfx_v9_0_update_gfx_clock_gating(adev, 5031 state == AMD_CG_STATE_GATE); 5032 break; 5033 default: 5034 break; 5035 } 5036 return 0; 5037 } 5038 5039 static void gfx_v9_0_get_clockgating_state(void *handle, u64 *flags) 5040 { 5041 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5042 int data; 5043 5044 if (amdgpu_sriov_vf(adev)) 5045 *flags = 0; 5046 5047 /* AMD_CG_SUPPORT_GFX_MGCG */ 5048 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 5049 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5050 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5051 5052 /* AMD_CG_SUPPORT_GFX_CGCG */ 5053 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 5054 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5055 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5056 5057 /* AMD_CG_SUPPORT_GFX_CGLS */ 5058 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5059 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5060 5061 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 5062 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 5063 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 5064 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 5065 5066 /* AMD_CG_SUPPORT_GFX_CP_LS */ 5067 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 5068 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 5069 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 5070 5071 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) { 5072 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5073 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 5074 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5075 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5076 5077 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5078 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5079 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5080 } 5081 } 5082 5083 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5084 { 5085 return *ring->rptr_cpu_addr; /* gfx9 is 32bit rptr*/ 5086 } 5087 5088 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5089 { 5090 struct amdgpu_device *adev = ring->adev; 5091 u64 wptr; 5092 5093 /* XXX check if swapping is necessary on BE */ 5094 if (ring->use_doorbell) { 5095 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5096 } else { 5097 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 5098 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 5099 } 5100 5101 return wptr; 5102 } 5103 5104 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5105 { 5106 struct amdgpu_device *adev = ring->adev; 5107 5108 if (ring->use_doorbell) { 5109 /* XXX check if swapping is necessary on BE */ 5110 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr); 5111 WDOORBELL64(ring->doorbell_index, ring->wptr); 5112 } else { 5113 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 5114 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 5115 } 5116 } 5117 5118 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5119 { 5120 struct amdgpu_device *adev = ring->adev; 5121 u32 ref_and_mask, reg_mem_engine; 5122 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5123 5124 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5125 switch (ring->me) { 5126 case 1: 5127 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5128 break; 5129 case 2: 5130 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5131 break; 5132 default: 5133 return; 5134 } 5135 reg_mem_engine = 0; 5136 } else { 5137 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 5138 reg_mem_engine = 1; /* pfp */ 5139 } 5140 5141 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5142 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5143 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5144 ref_and_mask, ref_and_mask, 0x20); 5145 } 5146 5147 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5148 struct amdgpu_job *job, 5149 struct amdgpu_ib *ib, 5150 uint32_t flags) 5151 { 5152 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5153 u32 header, control = 0; 5154 5155 if (ib->flags & AMDGPU_IB_FLAG_CE) 5156 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 5157 else 5158 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5159 5160 control |= ib->length_dw | (vmid << 24); 5161 5162 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5163 control |= INDIRECT_BUFFER_PRE_ENB(1); 5164 5165 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 5166 gfx_v9_0_ring_emit_de_meta(ring); 5167 } 5168 5169 amdgpu_ring_write(ring, header); 5170 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5171 amdgpu_ring_write(ring, 5172 #ifdef __BIG_ENDIAN 5173 (2 << 0) | 5174 #endif 5175 lower_32_bits(ib->gpu_addr)); 5176 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5177 amdgpu_ring_write(ring, control); 5178 } 5179 5180 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5181 struct amdgpu_job *job, 5182 struct amdgpu_ib *ib, 5183 uint32_t flags) 5184 { 5185 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5186 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5187 5188 /* Currently, there is a high possibility to get wave ID mismatch 5189 * between ME and GDS, leading to a hw deadlock, because ME generates 5190 * different wave IDs than the GDS expects. This situation happens 5191 * randomly when at least 5 compute pipes use GDS ordered append. 5192 * The wave IDs generated by ME are also wrong after suspend/resume. 5193 * Those are probably bugs somewhere else in the kernel driver. 5194 * 5195 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5196 * GDS to 0 for this ring (me/pipe). 5197 */ 5198 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5199 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5200 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 5201 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5202 } 5203 5204 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5205 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5206 amdgpu_ring_write(ring, 5207 #ifdef __BIG_ENDIAN 5208 (2 << 0) | 5209 #endif 5210 lower_32_bits(ib->gpu_addr)); 5211 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5212 amdgpu_ring_write(ring, control); 5213 } 5214 5215 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5216 u64 seq, unsigned flags) 5217 { 5218 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5219 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5220 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 5221 5222 /* RELEASE_MEM - flush caches, send int */ 5223 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5224 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 5225 EOP_TC_NC_ACTION_EN) : 5226 (EOP_TCL1_ACTION_EN | 5227 EOP_TC_ACTION_EN | 5228 EOP_TC_WB_ACTION_EN | 5229 EOP_TC_MD_ACTION_EN)) | 5230 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5231 EVENT_INDEX(5))); 5232 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 5233 5234 /* 5235 * the address should be Qword aligned if 64bit write, Dword 5236 * aligned if only send 32bit data low (discard data high) 5237 */ 5238 if (write64bit) 5239 BUG_ON(addr & 0x7); 5240 else 5241 BUG_ON(addr & 0x3); 5242 amdgpu_ring_write(ring, lower_32_bits(addr)); 5243 amdgpu_ring_write(ring, upper_32_bits(addr)); 5244 amdgpu_ring_write(ring, lower_32_bits(seq)); 5245 amdgpu_ring_write(ring, upper_32_bits(seq)); 5246 amdgpu_ring_write(ring, 0); 5247 } 5248 5249 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5250 { 5251 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5252 uint32_t seq = ring->fence_drv.sync_seq; 5253 uint64_t addr = ring->fence_drv.gpu_addr; 5254 5255 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0, 5256 lower_32_bits(addr), upper_32_bits(addr), 5257 seq, 0xffffffff, 4); 5258 } 5259 5260 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5261 unsigned vmid, uint64_t pd_addr) 5262 { 5263 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5264 5265 /* compute doesn't have PFP */ 5266 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5267 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5268 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5269 amdgpu_ring_write(ring, 0x0); 5270 } 5271 } 5272 5273 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5274 { 5275 return *ring->rptr_cpu_addr; /* gfx9 hardware is 32bit rptr */ 5276 } 5277 5278 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5279 { 5280 u64 wptr; 5281 5282 /* XXX check if swapping is necessary on BE */ 5283 if (ring->use_doorbell) 5284 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5285 else 5286 BUG(); 5287 return wptr; 5288 } 5289 5290 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5291 { 5292 struct amdgpu_device *adev = ring->adev; 5293 5294 /* XXX check if swapping is necessary on BE */ 5295 if (ring->use_doorbell) { 5296 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr); 5297 WDOORBELL64(ring->doorbell_index, ring->wptr); 5298 } else{ 5299 BUG(); /* only DOORBELL method supported on gfx9 now */ 5300 } 5301 } 5302 5303 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5304 u64 seq, unsigned int flags) 5305 { 5306 struct amdgpu_device *adev = ring->adev; 5307 5308 /* we only allocate 32bit for each seq wb address */ 5309 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5310 5311 /* write fence seq to the "addr" */ 5312 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5313 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5314 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5315 amdgpu_ring_write(ring, lower_32_bits(addr)); 5316 amdgpu_ring_write(ring, upper_32_bits(addr)); 5317 amdgpu_ring_write(ring, lower_32_bits(seq)); 5318 5319 if (flags & AMDGPU_FENCE_FLAG_INT) { 5320 /* set register to trigger INT */ 5321 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5322 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5323 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5324 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 5325 amdgpu_ring_write(ring, 0); 5326 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5327 } 5328 } 5329 5330 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring) 5331 { 5332 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 5333 amdgpu_ring_write(ring, 0); 5334 } 5335 5336 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring) 5337 { 5338 struct v9_ce_ib_state ce_payload = {0}; 5339 uint64_t csa_addr; 5340 int cnt; 5341 5342 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 5343 csa_addr = amdgpu_csa_vaddr(ring->adev); 5344 5345 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5346 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 5347 WRITE_DATA_DST_SEL(8) | 5348 WR_CONFIRM) | 5349 WRITE_DATA_CACHE_POLICY(0)); 5350 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); 5351 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); 5352 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2); 5353 } 5354 5355 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring) 5356 { 5357 struct v9_de_ib_state de_payload = {0}; 5358 uint64_t csa_addr, gds_addr; 5359 int cnt; 5360 5361 csa_addr = amdgpu_csa_vaddr(ring->adev); 5362 gds_addr = csa_addr + 4096; 5363 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5364 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5365 5366 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5367 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5368 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 5369 WRITE_DATA_DST_SEL(8) | 5370 WR_CONFIRM) | 5371 WRITE_DATA_CACHE_POLICY(0)); 5372 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); 5373 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); 5374 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2); 5375 } 5376 5377 static void gfx_v9_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 5378 bool secure) 5379 { 5380 uint32_t v = secure ? FRAME_TMZ : 0; 5381 5382 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 5383 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 5384 } 5385 5386 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 5387 { 5388 uint32_t dw2 = 0; 5389 5390 if (amdgpu_sriov_vf(ring->adev)) 5391 gfx_v9_0_ring_emit_ce_meta(ring); 5392 5393 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5394 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5395 /* set load_global_config & load_global_uconfig */ 5396 dw2 |= 0x8001; 5397 /* set load_cs_sh_regs */ 5398 dw2 |= 0x01000000; 5399 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5400 dw2 |= 0x10002; 5401 5402 /* set load_ce_ram if preamble presented */ 5403 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 5404 dw2 |= 0x10000000; 5405 } else { 5406 /* still load_ce_ram if this is the first time preamble presented 5407 * although there is no context switch happens. 5408 */ 5409 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 5410 dw2 |= 0x10000000; 5411 } 5412 5413 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5414 amdgpu_ring_write(ring, dw2); 5415 amdgpu_ring_write(ring, 0); 5416 } 5417 5418 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 5419 { 5420 unsigned ret; 5421 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5422 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 5423 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 5424 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 5425 ret = ring->wptr & ring->buf_mask; 5426 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 5427 return ret; 5428 } 5429 5430 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 5431 { 5432 unsigned cur; 5433 BUG_ON(offset > ring->buf_mask); 5434 BUG_ON(ring->ring[offset] != 0x55aa55aa); 5435 5436 cur = (ring->wptr - 1) & ring->buf_mask; 5437 if (likely(cur > offset)) 5438 ring->ring[offset] = cur - offset; 5439 else 5440 ring->ring[offset] = (ring->ring_size>>2) - offset + cur; 5441 } 5442 5443 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 5444 uint32_t reg_val_offs) 5445 { 5446 struct amdgpu_device *adev = ring->adev; 5447 5448 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 5449 amdgpu_ring_write(ring, 0 | /* src: register*/ 5450 (5 << 8) | /* dst: memory */ 5451 (1 << 20)); /* write confirm */ 5452 amdgpu_ring_write(ring, reg); 5453 amdgpu_ring_write(ring, 0); 5454 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 5455 reg_val_offs * 4)); 5456 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 5457 reg_val_offs * 4)); 5458 } 5459 5460 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 5461 uint32_t val) 5462 { 5463 uint32_t cmd = 0; 5464 5465 switch (ring->funcs->type) { 5466 case AMDGPU_RING_TYPE_GFX: 5467 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 5468 break; 5469 case AMDGPU_RING_TYPE_KIQ: 5470 cmd = (1 << 16); /* no inc addr */ 5471 break; 5472 default: 5473 cmd = WR_CONFIRM; 5474 break; 5475 } 5476 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5477 amdgpu_ring_write(ring, cmd); 5478 amdgpu_ring_write(ring, reg); 5479 amdgpu_ring_write(ring, 0); 5480 amdgpu_ring_write(ring, val); 5481 } 5482 5483 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 5484 uint32_t val, uint32_t mask) 5485 { 5486 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 5487 } 5488 5489 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 5490 uint32_t reg0, uint32_t reg1, 5491 uint32_t ref, uint32_t mask) 5492 { 5493 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5494 struct amdgpu_device *adev = ring->adev; 5495 bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ? 5496 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait; 5497 5498 if (fw_version_ok) 5499 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 5500 ref, mask, 0x20); 5501 else 5502 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 5503 ref, mask); 5504 } 5505 5506 static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) 5507 { 5508 struct amdgpu_device *adev = ring->adev; 5509 uint32_t value = 0; 5510 5511 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 5512 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 5513 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 5514 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 5515 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 5516 } 5517 5518 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 5519 enum amdgpu_interrupt_state state) 5520 { 5521 switch (state) { 5522 case AMDGPU_IRQ_STATE_DISABLE: 5523 case AMDGPU_IRQ_STATE_ENABLE: 5524 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5525 TIME_STAMP_INT_ENABLE, 5526 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5527 break; 5528 default: 5529 break; 5530 } 5531 } 5532 5533 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 5534 int me, int pipe, 5535 enum amdgpu_interrupt_state state) 5536 { 5537 u32 mec_int_cntl, mec_int_cntl_reg; 5538 5539 /* 5540 * amdgpu controls only the first MEC. That's why this function only 5541 * handles the setting of interrupts for this specific MEC. All other 5542 * pipes' interrupts are set by amdkfd. 5543 */ 5544 5545 if (me == 1) { 5546 switch (pipe) { 5547 case 0: 5548 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 5549 break; 5550 case 1: 5551 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 5552 break; 5553 case 2: 5554 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 5555 break; 5556 case 3: 5557 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 5558 break; 5559 default: 5560 DRM_DEBUG("invalid pipe %d\n", pipe); 5561 return; 5562 } 5563 } else { 5564 DRM_DEBUG("invalid me %d\n", me); 5565 return; 5566 } 5567 5568 switch (state) { 5569 case AMDGPU_IRQ_STATE_DISABLE: 5570 mec_int_cntl = RREG32_SOC15_IP(GC,mec_int_cntl_reg); 5571 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5572 TIME_STAMP_INT_ENABLE, 0); 5573 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5574 break; 5575 case AMDGPU_IRQ_STATE_ENABLE: 5576 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5577 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5578 TIME_STAMP_INT_ENABLE, 1); 5579 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5580 break; 5581 default: 5582 break; 5583 } 5584 } 5585 5586 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 5587 struct amdgpu_irq_src *source, 5588 unsigned type, 5589 enum amdgpu_interrupt_state state) 5590 { 5591 switch (state) { 5592 case AMDGPU_IRQ_STATE_DISABLE: 5593 case AMDGPU_IRQ_STATE_ENABLE: 5594 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5595 PRIV_REG_INT_ENABLE, 5596 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5597 break; 5598 default: 5599 break; 5600 } 5601 5602 return 0; 5603 } 5604 5605 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 5606 struct amdgpu_irq_src *source, 5607 unsigned type, 5608 enum amdgpu_interrupt_state state) 5609 { 5610 switch (state) { 5611 case AMDGPU_IRQ_STATE_DISABLE: 5612 case AMDGPU_IRQ_STATE_ENABLE: 5613 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5614 PRIV_INSTR_INT_ENABLE, 5615 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5616 break; 5617 default: 5618 break; 5619 } 5620 5621 return 0; 5622 } 5623 5624 #define ENABLE_ECC_ON_ME_PIPE(me, pipe) \ 5625 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ 5626 CP_ECC_ERROR_INT_ENABLE, 1) 5627 5628 #define DISABLE_ECC_ON_ME_PIPE(me, pipe) \ 5629 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ 5630 CP_ECC_ERROR_INT_ENABLE, 0) 5631 5632 static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev, 5633 struct amdgpu_irq_src *source, 5634 unsigned type, 5635 enum amdgpu_interrupt_state state) 5636 { 5637 switch (state) { 5638 case AMDGPU_IRQ_STATE_DISABLE: 5639 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5640 CP_ECC_ERROR_INT_ENABLE, 0); 5641 DISABLE_ECC_ON_ME_PIPE(1, 0); 5642 DISABLE_ECC_ON_ME_PIPE(1, 1); 5643 DISABLE_ECC_ON_ME_PIPE(1, 2); 5644 DISABLE_ECC_ON_ME_PIPE(1, 3); 5645 break; 5646 5647 case AMDGPU_IRQ_STATE_ENABLE: 5648 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5649 CP_ECC_ERROR_INT_ENABLE, 1); 5650 ENABLE_ECC_ON_ME_PIPE(1, 0); 5651 ENABLE_ECC_ON_ME_PIPE(1, 1); 5652 ENABLE_ECC_ON_ME_PIPE(1, 2); 5653 ENABLE_ECC_ON_ME_PIPE(1, 3); 5654 break; 5655 default: 5656 break; 5657 } 5658 5659 return 0; 5660 } 5661 5662 5663 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev, 5664 struct amdgpu_irq_src *src, 5665 unsigned type, 5666 enum amdgpu_interrupt_state state) 5667 { 5668 switch (type) { 5669 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 5670 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state); 5671 break; 5672 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 5673 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 5674 break; 5675 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 5676 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 5677 break; 5678 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 5679 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 5680 break; 5681 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 5682 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 5683 break; 5684 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 5685 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 5686 break; 5687 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 5688 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 5689 break; 5690 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 5691 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 5692 break; 5693 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 5694 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 5695 break; 5696 default: 5697 break; 5698 } 5699 return 0; 5700 } 5701 5702 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev, 5703 struct amdgpu_irq_src *source, 5704 struct amdgpu_iv_entry *entry) 5705 { 5706 int i; 5707 u8 me_id, pipe_id, queue_id; 5708 struct amdgpu_ring *ring; 5709 5710 DRM_DEBUG("IH: CP EOP\n"); 5711 me_id = (entry->ring_id & 0x0c) >> 2; 5712 pipe_id = (entry->ring_id & 0x03) >> 0; 5713 queue_id = (entry->ring_id & 0x70) >> 4; 5714 5715 switch (me_id) { 5716 case 0: 5717 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 5718 break; 5719 case 1: 5720 case 2: 5721 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5722 ring = &adev->gfx.compute_ring[i]; 5723 /* Per-queue interrupt is supported for MEC starting from VI. 5724 * The interrupt can only be enabled/disabled per pipe instead of per queue. 5725 */ 5726 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 5727 amdgpu_fence_process(ring); 5728 } 5729 break; 5730 } 5731 return 0; 5732 } 5733 5734 static void gfx_v9_0_fault(struct amdgpu_device *adev, 5735 struct amdgpu_iv_entry *entry) 5736 { 5737 u8 me_id, pipe_id, queue_id; 5738 struct amdgpu_ring *ring; 5739 int i; 5740 5741 me_id = (entry->ring_id & 0x0c) >> 2; 5742 pipe_id = (entry->ring_id & 0x03) >> 0; 5743 queue_id = (entry->ring_id & 0x70) >> 4; 5744 5745 switch (me_id) { 5746 case 0: 5747 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); 5748 break; 5749 case 1: 5750 case 2: 5751 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5752 ring = &adev->gfx.compute_ring[i]; 5753 if (ring->me == me_id && ring->pipe == pipe_id && 5754 ring->queue == queue_id) 5755 drm_sched_fault(&ring->sched); 5756 } 5757 break; 5758 } 5759 } 5760 5761 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev, 5762 struct amdgpu_irq_src *source, 5763 struct amdgpu_iv_entry *entry) 5764 { 5765 DRM_ERROR("Illegal register access in command stream\n"); 5766 gfx_v9_0_fault(adev, entry); 5767 return 0; 5768 } 5769 5770 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev, 5771 struct amdgpu_irq_src *source, 5772 struct amdgpu_iv_entry *entry) 5773 { 5774 DRM_ERROR("Illegal instruction in command stream\n"); 5775 gfx_v9_0_fault(adev, entry); 5776 return 0; 5777 } 5778 5779 5780 static const struct soc15_ras_field_entry gfx_v9_0_ras_fields[] = { 5781 { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 5782 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT), 5783 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT) 5784 }, 5785 { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 5786 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT), 5787 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT) 5788 }, 5789 { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 5790 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME1), 5791 0, 0 5792 }, 5793 { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 5794 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME2), 5795 0, 0 5796 }, 5797 { "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 5798 SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT), 5799 SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT) 5800 }, 5801 { "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 5802 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, ROQ_COUNT), 5803 0, 0 5804 }, 5805 { "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 5806 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_SEC_COUNT), 5807 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_DED_COUNT) 5808 }, 5809 { "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 5810 SOC15_REG_FIELD(CPG_EDC_TAG_CNT, SEC_COUNT), 5811 SOC15_REG_FIELD(CPG_EDC_TAG_CNT, DED_COUNT) 5812 }, 5813 { "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 5814 SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, COUNT_ME1), 5815 0, 0 5816 }, 5817 { "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 5818 SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, COUNT_ME1), 5819 0, 0 5820 }, 5821 { "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 5822 SOC15_REG_FIELD(DC_EDC_STATE_CNT, COUNT_ME1), 5823 0, 0 5824 }, 5825 { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 5826 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC), 5827 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED) 5828 }, 5829 { "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 5830 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED), 5831 0, 0 5832 }, 5833 { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 5834 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC), 5835 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) 5836 }, 5837 { "GDS_OA_PHY_PHY_CMD_RAM_MEM", 5838 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 5839 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC), 5840 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) 5841 }, 5842 { "GDS_OA_PHY_PHY_DATA_RAM_MEM", 5843 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 5844 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED), 5845 0, 0 5846 }, 5847 { "GDS_OA_PIPE_ME1_PIPE0_PIPE_MEM", 5848 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5849 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC), 5850 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) 5851 }, 5852 { "GDS_OA_PIPE_ME1_PIPE1_PIPE_MEM", 5853 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5854 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC), 5855 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) 5856 }, 5857 { "GDS_OA_PIPE_ME1_PIPE2_PIPE_MEM", 5858 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5859 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC), 5860 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) 5861 }, 5862 { "GDS_OA_PIPE_ME1_PIPE3_PIPE_MEM", 5863 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5864 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC), 5865 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) 5866 }, 5867 { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 5868 SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT), 5869 0, 0 5870 }, 5871 { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5872 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT), 5873 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) 5874 }, 5875 { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5876 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT), 5877 0, 0 5878 }, 5879 { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5880 SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT), 5881 0, 0 5882 }, 5883 { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5884 SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT), 5885 0, 0 5886 }, 5887 { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5888 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT), 5889 0, 0 5890 }, 5891 { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 5892 SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT), 5893 0, 0 5894 }, 5895 { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 5896 SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SED_COUNT), 5897 0, 0 5898 }, 5899 { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5900 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT), 5901 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) 5902 }, 5903 { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5904 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT), 5905 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) 5906 }, 5907 { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5908 SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT), 5909 SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) 5910 }, 5911 { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5912 SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT), 5913 SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) 5914 }, 5915 { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5916 SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT), 5917 SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) 5918 }, 5919 { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5920 SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT), 5921 0, 0 5922 }, 5923 { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5924 SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT), 5925 0, 0 5926 }, 5927 { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5928 SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT), 5929 0, 0 5930 }, 5931 { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5932 SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_DATA_SED_COUNT), 5933 0, 0 5934 }, 5935 { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5936 SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT), 5937 0, 0 5938 }, 5939 { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5940 SOC15_REG_FIELD(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT), 5941 0, 0 5942 }, 5943 { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 5944 SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT), 5945 0, 0 5946 }, 5947 { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 5948 SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT), 5949 0, 0 5950 }, 5951 { "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 5952 SOC15_REG_FIELD(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT), 5953 0, 0 5954 }, 5955 { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 5956 SOC15_REG_FIELD(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT), 5957 0, 0 5958 }, 5959 { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 5960 SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT), 5961 0, 0 5962 }, 5963 { "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 5964 SOC15_REG_FIELD(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT), 5965 0, 0 5966 }, 5967 { "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 5968 SOC15_REG_FIELD(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT), 5969 0, 0 5970 }, 5971 { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 5972 SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SED_COUNT), 5973 0, 0 5974 }, 5975 { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 5976 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT), 5977 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) 5978 }, 5979 { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 5980 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT), 5981 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) 5982 }, 5983 { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 5984 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT), 5985 0, 0 5986 }, 5987 { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 5988 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT), 5989 0, 0 5990 }, 5991 { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 5992 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT), 5993 0, 0 5994 }, 5995 { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 5996 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT), 5997 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) 5998 }, 5999 { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6000 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT), 6001 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) 6002 }, 6003 { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6004 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT), 6005 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) 6006 }, 6007 { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6008 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT), 6009 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) 6010 }, 6011 { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6012 SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SED_COUNT), 6013 0, 0 6014 }, 6015 { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6016 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT), 6017 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT) 6018 }, 6019 { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6020 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT), 6021 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT) 6022 }, 6023 { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6024 SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT), 6025 SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT) 6026 }, 6027 { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6028 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT), 6029 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT) 6030 }, 6031 { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6032 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT), 6033 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT) 6034 }, 6035 { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6036 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT), 6037 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT) 6038 }, 6039 { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6040 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT), 6041 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT) 6042 }, 6043 { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6044 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT), 6045 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) 6046 }, 6047 { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6048 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT), 6049 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) 6050 }, 6051 { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6052 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT), 6053 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) 6054 }, 6055 { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6056 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT), 6057 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) 6058 }, 6059 { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6060 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT), 6061 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) 6062 }, 6063 { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6064 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT), 6065 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) 6066 }, 6067 { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6068 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT), 6069 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) 6070 }, 6071 { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6072 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT), 6073 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) 6074 }, 6075 { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6076 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT), 6077 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) 6078 }, 6079 { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6080 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT), 6081 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) 6082 }, 6083 { "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6084 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT), 6085 0, 0 6086 }, 6087 { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6088 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT), 6089 0, 0 6090 }, 6091 { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6092 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT), 6093 0, 0 6094 }, 6095 { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6096 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT), 6097 0, 0 6098 }, 6099 { "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6100 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT), 6101 0, 0 6102 }, 6103 { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6104 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT), 6105 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) 6106 }, 6107 { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6108 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT), 6109 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) 6110 }, 6111 { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6112 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT), 6113 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) 6114 }, 6115 { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6116 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT), 6117 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) 6118 }, 6119 { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6120 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT), 6121 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) 6122 }, 6123 { "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6124 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT), 6125 0, 0 6126 }, 6127 { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6128 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT), 6129 0, 0 6130 }, 6131 { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6132 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT), 6133 0, 0 6134 }, 6135 { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6136 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT), 6137 0, 0 6138 }, 6139 { "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6140 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT), 6141 0, 0 6142 }, 6143 { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6144 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 6145 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) 6146 }, 6147 { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6148 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 6149 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) 6150 }, 6151 { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6152 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 6153 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) 6154 }, 6155 { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6156 SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 6157 SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) 6158 }, 6159 { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6160 SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 6161 SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) 6162 }, 6163 { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6164 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 6165 0, 0 6166 }, 6167 { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6168 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 6169 0, 0 6170 }, 6171 { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6172 SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 6173 0, 0 6174 }, 6175 { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6176 SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 6177 0, 0 6178 }, 6179 { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6180 SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 6181 0, 0 6182 }, 6183 { "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6184 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 6185 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) 6186 }, 6187 { "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6188 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 6189 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) 6190 }, 6191 { "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6192 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 6193 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) 6194 }, 6195 { "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6196 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 6197 0, 0 6198 }, 6199 { "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6200 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 6201 0, 0 6202 }, 6203 { "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6204 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT), 6205 0, 0 6206 }, 6207 { "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6208 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT), 6209 0, 0 6210 }, 6211 { "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6212 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT), 6213 0, 0 6214 }, 6215 { "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6216 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT), 6217 0, 0 6218 } 6219 }; 6220 6221 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, 6222 void *inject_if) 6223 { 6224 struct ras_inject_if *info = (struct ras_inject_if *)inject_if; 6225 int ret; 6226 struct ta_ras_trigger_error_input block_info = { 0 }; 6227 6228 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6229 return -EINVAL; 6230 6231 if (info->head.sub_block_index >= ARRAY_SIZE(ras_gfx_subblocks)) 6232 return -EINVAL; 6233 6234 if (!ras_gfx_subblocks[info->head.sub_block_index].name) 6235 return -EPERM; 6236 6237 if (!(ras_gfx_subblocks[info->head.sub_block_index].hw_supported_error_type & 6238 info->head.type)) { 6239 DRM_ERROR("GFX Subblock %s, hardware do not support type 0x%x\n", 6240 ras_gfx_subblocks[info->head.sub_block_index].name, 6241 info->head.type); 6242 return -EPERM; 6243 } 6244 6245 if (!(ras_gfx_subblocks[info->head.sub_block_index].sw_supported_error_type & 6246 info->head.type)) { 6247 DRM_ERROR("GFX Subblock %s, driver do not support type 0x%x\n", 6248 ras_gfx_subblocks[info->head.sub_block_index].name, 6249 info->head.type); 6250 return -EPERM; 6251 } 6252 6253 block_info.block_id = amdgpu_ras_block_to_ta(info->head.block); 6254 block_info.sub_block_index = 6255 ras_gfx_subblocks[info->head.sub_block_index].ta_subblock; 6256 block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type); 6257 block_info.address = info->address; 6258 block_info.value = info->value; 6259 6260 mutex_lock(&adev->grbm_idx_mutex); 6261 ret = psp_ras_trigger_error(&adev->psp, &block_info); 6262 mutex_unlock(&adev->grbm_idx_mutex); 6263 6264 return ret; 6265 } 6266 6267 static const char *vml2_mems[] = { 6268 "UTC_VML2_BANK_CACHE_0_BIGK_MEM0", 6269 "UTC_VML2_BANK_CACHE_0_BIGK_MEM1", 6270 "UTC_VML2_BANK_CACHE_0_4K_MEM0", 6271 "UTC_VML2_BANK_CACHE_0_4K_MEM1", 6272 "UTC_VML2_BANK_CACHE_1_BIGK_MEM0", 6273 "UTC_VML2_BANK_CACHE_1_BIGK_MEM1", 6274 "UTC_VML2_BANK_CACHE_1_4K_MEM0", 6275 "UTC_VML2_BANK_CACHE_1_4K_MEM1", 6276 "UTC_VML2_BANK_CACHE_2_BIGK_MEM0", 6277 "UTC_VML2_BANK_CACHE_2_BIGK_MEM1", 6278 "UTC_VML2_BANK_CACHE_2_4K_MEM0", 6279 "UTC_VML2_BANK_CACHE_2_4K_MEM1", 6280 "UTC_VML2_BANK_CACHE_3_BIGK_MEM0", 6281 "UTC_VML2_BANK_CACHE_3_BIGK_MEM1", 6282 "UTC_VML2_BANK_CACHE_3_4K_MEM0", 6283 "UTC_VML2_BANK_CACHE_3_4K_MEM1", 6284 }; 6285 6286 static const char *vml2_walker_mems[] = { 6287 "UTC_VML2_CACHE_PDE0_MEM0", 6288 "UTC_VML2_CACHE_PDE0_MEM1", 6289 "UTC_VML2_CACHE_PDE1_MEM0", 6290 "UTC_VML2_CACHE_PDE1_MEM1", 6291 "UTC_VML2_CACHE_PDE2_MEM0", 6292 "UTC_VML2_CACHE_PDE2_MEM1", 6293 "UTC_VML2_RDIF_LOG_FIFO", 6294 }; 6295 6296 static const char *atc_l2_cache_2m_mems[] = { 6297 "UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM", 6298 "UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM", 6299 "UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM", 6300 "UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM", 6301 }; 6302 6303 static const char *atc_l2_cache_4k_mems[] = { 6304 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0", 6305 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1", 6306 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2", 6307 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3", 6308 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4", 6309 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5", 6310 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6", 6311 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7", 6312 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0", 6313 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1", 6314 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2", 6315 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3", 6316 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4", 6317 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5", 6318 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6", 6319 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7", 6320 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0", 6321 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1", 6322 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2", 6323 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3", 6324 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4", 6325 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5", 6326 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6", 6327 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7", 6328 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0", 6329 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1", 6330 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2", 6331 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3", 6332 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4", 6333 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5", 6334 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6", 6335 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7", 6336 }; 6337 6338 static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev, 6339 struct ras_err_data *err_data) 6340 { 6341 uint32_t i, data; 6342 uint32_t sec_count, ded_count; 6343 6344 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6345 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0); 6346 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6347 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0); 6348 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6349 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0); 6350 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6351 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); 6352 6353 for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) { 6354 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i); 6355 data = RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT); 6356 6357 sec_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, SEC_COUNT); 6358 if (sec_count) { 6359 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6360 "SEC %d\n", i, vml2_mems[i], sec_count); 6361 err_data->ce_count += sec_count; 6362 } 6363 6364 ded_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, DED_COUNT); 6365 if (ded_count) { 6366 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6367 "DED %d\n", i, vml2_mems[i], ded_count); 6368 err_data->ue_count += ded_count; 6369 } 6370 } 6371 6372 for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) { 6373 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i); 6374 data = RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT); 6375 6376 sec_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, 6377 SEC_COUNT); 6378 if (sec_count) { 6379 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6380 "SEC %d\n", i, vml2_walker_mems[i], sec_count); 6381 err_data->ce_count += sec_count; 6382 } 6383 6384 ded_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, 6385 DED_COUNT); 6386 if (ded_count) { 6387 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6388 "DED %d\n", i, vml2_walker_mems[i], ded_count); 6389 err_data->ue_count += ded_count; 6390 } 6391 } 6392 6393 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) { 6394 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i); 6395 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT); 6396 6397 sec_count = (data & 0x00006000L) >> 0xd; 6398 if (sec_count) { 6399 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6400 "SEC %d\n", i, atc_l2_cache_2m_mems[i], 6401 sec_count); 6402 err_data->ce_count += sec_count; 6403 } 6404 } 6405 6406 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) { 6407 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i); 6408 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); 6409 6410 sec_count = (data & 0x00006000L) >> 0xd; 6411 if (sec_count) { 6412 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6413 "SEC %d\n", i, atc_l2_cache_4k_mems[i], 6414 sec_count); 6415 err_data->ce_count += sec_count; 6416 } 6417 6418 ded_count = (data & 0x00018000L) >> 0xf; 6419 if (ded_count) { 6420 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6421 "DED %d\n", i, atc_l2_cache_4k_mems[i], 6422 ded_count); 6423 err_data->ue_count += ded_count; 6424 } 6425 } 6426 6427 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6428 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6429 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6430 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6431 6432 return 0; 6433 } 6434 6435 static int gfx_v9_0_ras_error_count(struct amdgpu_device *adev, 6436 const struct soc15_reg_entry *reg, 6437 uint32_t se_id, uint32_t inst_id, uint32_t value, 6438 uint32_t *sec_count, uint32_t *ded_count) 6439 { 6440 uint32_t i; 6441 uint32_t sec_cnt, ded_cnt; 6442 6443 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_ras_fields); i++) { 6444 if(gfx_v9_0_ras_fields[i].reg_offset != reg->reg_offset || 6445 gfx_v9_0_ras_fields[i].seg != reg->seg || 6446 gfx_v9_0_ras_fields[i].inst != reg->inst) 6447 continue; 6448 6449 sec_cnt = (value & 6450 gfx_v9_0_ras_fields[i].sec_count_mask) >> 6451 gfx_v9_0_ras_fields[i].sec_count_shift; 6452 if (sec_cnt) { 6453 dev_info(adev->dev, "GFX SubBlock %s, " 6454 "Instance[%d][%d], SEC %d\n", 6455 gfx_v9_0_ras_fields[i].name, 6456 se_id, inst_id, 6457 sec_cnt); 6458 *sec_count += sec_cnt; 6459 } 6460 6461 ded_cnt = (value & 6462 gfx_v9_0_ras_fields[i].ded_count_mask) >> 6463 gfx_v9_0_ras_fields[i].ded_count_shift; 6464 if (ded_cnt) { 6465 dev_info(adev->dev, "GFX SubBlock %s, " 6466 "Instance[%d][%d], DED %d\n", 6467 gfx_v9_0_ras_fields[i].name, 6468 se_id, inst_id, 6469 ded_cnt); 6470 *ded_count += ded_cnt; 6471 } 6472 } 6473 6474 return 0; 6475 } 6476 6477 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev) 6478 { 6479 int i, j, k; 6480 6481 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6482 return; 6483 6484 /* read back registers to clear the counters */ 6485 mutex_lock(&adev->grbm_idx_mutex); 6486 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) { 6487 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { 6488 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { 6489 gfx_v9_0_select_se_sh(adev, j, 0x0, k); 6490 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); 6491 } 6492 } 6493 } 6494 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 6495 mutex_unlock(&adev->grbm_idx_mutex); 6496 6497 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6498 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0); 6499 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6500 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0); 6501 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6502 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0); 6503 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6504 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); 6505 6506 for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) { 6507 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i); 6508 RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT); 6509 } 6510 6511 for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) { 6512 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i); 6513 RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT); 6514 } 6515 6516 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) { 6517 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i); 6518 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT); 6519 } 6520 6521 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) { 6522 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i); 6523 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); 6524 } 6525 6526 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6527 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6528 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6529 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6530 } 6531 6532 static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, 6533 void *ras_error_status) 6534 { 6535 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 6536 uint32_t sec_count = 0, ded_count = 0; 6537 uint32_t i, j, k; 6538 uint32_t reg_value; 6539 6540 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6541 return; 6542 6543 err_data->ue_count = 0; 6544 err_data->ce_count = 0; 6545 6546 mutex_lock(&adev->grbm_idx_mutex); 6547 6548 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) { 6549 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { 6550 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { 6551 gfx_v9_0_select_se_sh(adev, j, 0, k); 6552 reg_value = 6553 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); 6554 if (reg_value) 6555 gfx_v9_0_ras_error_count(adev, 6556 &gfx_v9_0_edc_counter_regs[i], 6557 j, k, reg_value, 6558 &sec_count, &ded_count); 6559 } 6560 } 6561 } 6562 6563 err_data->ce_count += sec_count; 6564 err_data->ue_count += ded_count; 6565 6566 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 6567 mutex_unlock(&adev->grbm_idx_mutex); 6568 6569 gfx_v9_0_query_utc_edc_status(adev, err_data); 6570 } 6571 6572 static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring) 6573 { 6574 const unsigned int cp_coher_cntl = 6575 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 6576 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 6577 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 6578 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 6579 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 6580 6581 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 6582 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 6583 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 6584 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6585 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6586 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6587 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6588 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6589 } 6590 6591 static void gfx_v9_0_emit_wave_limit_cs(struct amdgpu_ring *ring, 6592 uint32_t pipe, bool enable) 6593 { 6594 struct amdgpu_device *adev = ring->adev; 6595 uint32_t val; 6596 uint32_t wcl_cs_reg; 6597 6598 /* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 6599 val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS0_DEFAULT; 6600 6601 switch (pipe) { 6602 case 0: 6603 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS0); 6604 break; 6605 case 1: 6606 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS1); 6607 break; 6608 case 2: 6609 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS2); 6610 break; 6611 case 3: 6612 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS3); 6613 break; 6614 default: 6615 DRM_DEBUG("invalid pipe %d\n", pipe); 6616 return; 6617 } 6618 6619 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 6620 6621 } 6622 static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 6623 { 6624 struct amdgpu_device *adev = ring->adev; 6625 uint32_t val; 6626 int i; 6627 6628 6629 /* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 6630 * number of gfx waves. Setting 5 bit will make sure gfx only gets 6631 * around 25% of gpu resources. 6632 */ 6633 val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT; 6634 amdgpu_ring_emit_wreg(ring, 6635 SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX), 6636 val); 6637 6638 /* Restrict waves for normal/low priority compute queues as well 6639 * to get best QoS for high priority compute jobs. 6640 * 6641 * amdgpu controls only 1st ME(0-3 CS pipes). 6642 */ 6643 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 6644 if (i != ring->pipe) 6645 gfx_v9_0_emit_wave_limit_cs(ring, i, enable); 6646 6647 } 6648 } 6649 6650 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = { 6651 .name = "gfx_v9_0", 6652 .early_init = gfx_v9_0_early_init, 6653 .late_init = gfx_v9_0_late_init, 6654 .sw_init = gfx_v9_0_sw_init, 6655 .sw_fini = gfx_v9_0_sw_fini, 6656 .hw_init = gfx_v9_0_hw_init, 6657 .hw_fini = gfx_v9_0_hw_fini, 6658 .suspend = gfx_v9_0_suspend, 6659 .resume = gfx_v9_0_resume, 6660 .is_idle = gfx_v9_0_is_idle, 6661 .wait_for_idle = gfx_v9_0_wait_for_idle, 6662 .soft_reset = gfx_v9_0_soft_reset, 6663 .set_clockgating_state = gfx_v9_0_set_clockgating_state, 6664 .set_powergating_state = gfx_v9_0_set_powergating_state, 6665 .get_clockgating_state = gfx_v9_0_get_clockgating_state, 6666 }; 6667 6668 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { 6669 .type = AMDGPU_RING_TYPE_GFX, 6670 .align_mask = 0xff, 6671 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6672 .support_64bit_ptrs = true, 6673 .secure_submission_supported = true, 6674 .vmhub = AMDGPU_GFXHUB_0, 6675 .get_rptr = gfx_v9_0_ring_get_rptr_gfx, 6676 .get_wptr = gfx_v9_0_ring_get_wptr_gfx, 6677 .set_wptr = gfx_v9_0_ring_set_wptr_gfx, 6678 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 6679 5 + /* COND_EXEC */ 6680 7 + /* PIPELINE_SYNC */ 6681 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6682 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6683 2 + /* VM_FLUSH */ 6684 8 + /* FENCE for VM_FLUSH */ 6685 20 + /* GDS switch */ 6686 4 + /* double SWITCH_BUFFER, 6687 the first COND_EXEC jump to the place just 6688 prior to this double SWITCH_BUFFER */ 6689 5 + /* COND_EXEC */ 6690 7 + /* HDP_flush */ 6691 4 + /* VGT_flush */ 6692 14 + /* CE_META */ 6693 31 + /* DE_META */ 6694 3 + /* CNTX_CTRL */ 6695 5 + /* HDP_INVL */ 6696 8 + 8 + /* FENCE x2 */ 6697 2 + /* SWITCH_BUFFER */ 6698 7, /* gfx_v9_0_emit_mem_sync */ 6699 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ 6700 .emit_ib = gfx_v9_0_ring_emit_ib_gfx, 6701 .emit_fence = gfx_v9_0_ring_emit_fence, 6702 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 6703 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 6704 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 6705 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 6706 .test_ring = gfx_v9_0_ring_test_ring, 6707 .test_ib = gfx_v9_0_ring_test_ib, 6708 .insert_nop = amdgpu_ring_insert_nop, 6709 .pad_ib = amdgpu_ring_generic_pad_ib, 6710 .emit_switch_buffer = gfx_v9_ring_emit_sb, 6711 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, 6712 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, 6713 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec, 6714 .emit_frame_cntl = gfx_v9_0_ring_emit_frame_cntl, 6715 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6716 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6717 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6718 .soft_recovery = gfx_v9_0_ring_soft_recovery, 6719 .emit_mem_sync = gfx_v9_0_emit_mem_sync, 6720 }; 6721 6722 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { 6723 .type = AMDGPU_RING_TYPE_COMPUTE, 6724 .align_mask = 0xff, 6725 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6726 .support_64bit_ptrs = true, 6727 .vmhub = AMDGPU_GFXHUB_0, 6728 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 6729 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 6730 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 6731 .emit_frame_size = 6732 20 + /* gfx_v9_0_ring_emit_gds_switch */ 6733 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 6734 5 + /* hdp invalidate */ 6735 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 6736 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6737 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6738 2 + /* gfx_v9_0_ring_emit_vm_flush */ 6739 8 + 8 + 8 + /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */ 6740 7 + /* gfx_v9_0_emit_mem_sync */ 6741 5 + /* gfx_v9_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */ 6742 15, /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */ 6743 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ 6744 .emit_ib = gfx_v9_0_ring_emit_ib_compute, 6745 .emit_fence = gfx_v9_0_ring_emit_fence, 6746 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 6747 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 6748 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 6749 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 6750 .test_ring = gfx_v9_0_ring_test_ring, 6751 .test_ib = gfx_v9_0_ring_test_ib, 6752 .insert_nop = amdgpu_ring_insert_nop, 6753 .pad_ib = amdgpu_ring_generic_pad_ib, 6754 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6755 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6756 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6757 .emit_mem_sync = gfx_v9_0_emit_mem_sync, 6758 .emit_wave_limit = gfx_v9_0_emit_wave_limit, 6759 }; 6760 6761 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { 6762 .type = AMDGPU_RING_TYPE_KIQ, 6763 .align_mask = 0xff, 6764 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6765 .support_64bit_ptrs = true, 6766 .vmhub = AMDGPU_GFXHUB_0, 6767 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 6768 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 6769 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 6770 .emit_frame_size = 6771 20 + /* gfx_v9_0_ring_emit_gds_switch */ 6772 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 6773 5 + /* hdp invalidate */ 6774 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 6775 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6776 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6777 2 + /* gfx_v9_0_ring_emit_vm_flush */ 6778 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 6779 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ 6780 .emit_fence = gfx_v9_0_ring_emit_fence_kiq, 6781 .test_ring = gfx_v9_0_ring_test_ring, 6782 .insert_nop = amdgpu_ring_insert_nop, 6783 .pad_ib = amdgpu_ring_generic_pad_ib, 6784 .emit_rreg = gfx_v9_0_ring_emit_rreg, 6785 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6786 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6787 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6788 }; 6789 6790 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev) 6791 { 6792 int i; 6793 6794 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq; 6795 6796 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6797 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx; 6798 6799 for (i = 0; i < adev->gfx.num_compute_rings; i++) 6800 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute; 6801 } 6802 6803 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = { 6804 .set = gfx_v9_0_set_eop_interrupt_state, 6805 .process = gfx_v9_0_eop_irq, 6806 }; 6807 6808 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = { 6809 .set = gfx_v9_0_set_priv_reg_fault_state, 6810 .process = gfx_v9_0_priv_reg_irq, 6811 }; 6812 6813 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = { 6814 .set = gfx_v9_0_set_priv_inst_fault_state, 6815 .process = gfx_v9_0_priv_inst_irq, 6816 }; 6817 6818 static const struct amdgpu_irq_src_funcs gfx_v9_0_cp_ecc_error_irq_funcs = { 6819 .set = gfx_v9_0_set_cp_ecc_error_state, 6820 .process = amdgpu_gfx_cp_ecc_error_irq, 6821 }; 6822 6823 6824 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) 6825 { 6826 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 6827 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; 6828 6829 adev->gfx.priv_reg_irq.num_types = 1; 6830 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; 6831 6832 adev->gfx.priv_inst_irq.num_types = 1; 6833 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs; 6834 6835 adev->gfx.cp_ecc_error_irq.num_types = 2; /*C5 ECC error and C9 FUE error*/ 6836 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v9_0_cp_ecc_error_irq_funcs; 6837 } 6838 6839 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) 6840 { 6841 switch (adev->ip_versions[GC_HWIP][0]) { 6842 case IP_VERSION(9, 0, 1): 6843 case IP_VERSION(9, 2, 1): 6844 case IP_VERSION(9, 4, 0): 6845 case IP_VERSION(9, 2, 2): 6846 case IP_VERSION(9, 1, 0): 6847 case IP_VERSION(9, 4, 1): 6848 case IP_VERSION(9, 3, 0): 6849 case IP_VERSION(9, 4, 2): 6850 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; 6851 break; 6852 default: 6853 break; 6854 } 6855 } 6856 6857 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) 6858 { 6859 /* init asci gds info */ 6860 switch (adev->ip_versions[GC_HWIP][0]) { 6861 case IP_VERSION(9, 0, 1): 6862 case IP_VERSION(9, 2, 1): 6863 case IP_VERSION(9, 4, 0): 6864 adev->gds.gds_size = 0x10000; 6865 break; 6866 case IP_VERSION(9, 2, 2): 6867 case IP_VERSION(9, 1, 0): 6868 case IP_VERSION(9, 4, 1): 6869 adev->gds.gds_size = 0x1000; 6870 break; 6871 case IP_VERSION(9, 4, 2): 6872 /* aldebaran removed all the GDS internal memory, 6873 * only support GWS opcode in kernel, like barrier 6874 * semaphore.etc */ 6875 adev->gds.gds_size = 0; 6876 break; 6877 default: 6878 adev->gds.gds_size = 0x10000; 6879 break; 6880 } 6881 6882 switch (adev->ip_versions[GC_HWIP][0]) { 6883 case IP_VERSION(9, 0, 1): 6884 case IP_VERSION(9, 4, 0): 6885 adev->gds.gds_compute_max_wave_id = 0x7ff; 6886 break; 6887 case IP_VERSION(9, 2, 1): 6888 adev->gds.gds_compute_max_wave_id = 0x27f; 6889 break; 6890 case IP_VERSION(9, 2, 2): 6891 case IP_VERSION(9, 1, 0): 6892 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 6893 adev->gds.gds_compute_max_wave_id = 0x77; /* raven2 */ 6894 else 6895 adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */ 6896 break; 6897 case IP_VERSION(9, 4, 1): 6898 adev->gds.gds_compute_max_wave_id = 0xfff; 6899 break; 6900 case IP_VERSION(9, 4, 2): 6901 /* deprecated for Aldebaran, no usage at all */ 6902 adev->gds.gds_compute_max_wave_id = 0; 6903 break; 6904 default: 6905 /* this really depends on the chip */ 6906 adev->gds.gds_compute_max_wave_id = 0x7ff; 6907 break; 6908 } 6909 6910 adev->gds.gws_size = 64; 6911 adev->gds.oa_size = 16; 6912 } 6913 6914 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 6915 u32 bitmap) 6916 { 6917 u32 data; 6918 6919 if (!bitmap) 6920 return; 6921 6922 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 6923 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 6924 6925 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 6926 } 6927 6928 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) 6929 { 6930 u32 data, mask; 6931 6932 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 6933 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 6934 6935 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 6936 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 6937 6938 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 6939 6940 return (~data) & mask; 6941 } 6942 6943 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 6944 struct amdgpu_cu_info *cu_info) 6945 { 6946 int i, j, k, counter, active_cu_number = 0; 6947 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 6948 unsigned disable_masks[4 * 4]; 6949 6950 if (!adev || !cu_info) 6951 return -EINVAL; 6952 6953 /* 6954 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 6955 */ 6956 if (adev->gfx.config.max_shader_engines * 6957 adev->gfx.config.max_sh_per_se > 16) 6958 return -EINVAL; 6959 6960 amdgpu_gfx_parse_disable_cu(disable_masks, 6961 adev->gfx.config.max_shader_engines, 6962 adev->gfx.config.max_sh_per_se); 6963 6964 mutex_lock(&adev->grbm_idx_mutex); 6965 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 6966 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 6967 mask = 1; 6968 ao_bitmap = 0; 6969 counter = 0; 6970 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 6971 gfx_v9_0_set_user_cu_inactive_bitmap( 6972 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); 6973 bitmap = gfx_v9_0_get_cu_active_bitmap(adev); 6974 6975 /* 6976 * The bitmap(and ao_cu_bitmap) in cu_info structure is 6977 * 4x4 size array, and it's usually suitable for Vega 6978 * ASICs which has 4*2 SE/SH layout. 6979 * But for Arcturus, SE/SH layout is changed to 8*1. 6980 * To mostly reduce the impact, we make it compatible 6981 * with current bitmap array as below: 6982 * SE4,SH0 --> bitmap[0][1] 6983 * SE5,SH0 --> bitmap[1][1] 6984 * SE6,SH0 --> bitmap[2][1] 6985 * SE7,SH0 --> bitmap[3][1] 6986 */ 6987 cu_info->bitmap[i % 4][j + i / 4] = bitmap; 6988 6989 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 6990 if (bitmap & mask) { 6991 if (counter < adev->gfx.config.max_cu_per_sh) 6992 ao_bitmap |= mask; 6993 counter ++; 6994 } 6995 mask <<= 1; 6996 } 6997 active_cu_number += counter; 6998 if (i < 2 && j < 2) 6999 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 7000 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; 7001 } 7002 } 7003 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 7004 mutex_unlock(&adev->grbm_idx_mutex); 7005 7006 cu_info->number = active_cu_number; 7007 cu_info->ao_cu_mask = ao_cu_mask; 7008 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 7009 7010 return 0; 7011 } 7012 7013 const struct amdgpu_ip_block_version gfx_v9_0_ip_block = 7014 { 7015 .type = AMD_IP_BLOCK_TYPE_GFX, 7016 .major = 9, 7017 .minor = 0, 7018 .rev = 0, 7019 .funcs = &gfx_v9_0_ip_funcs, 7020 }; 7021