15ca02815Sjsg /*
25ca02815Sjsg * Copyright 2020 Advanced Micro Devices, Inc.
35ca02815Sjsg *
45ca02815Sjsg * Permission is hereby granted, free of charge, to any person obtaining a
55ca02815Sjsg * copy of this software and associated documentation files (the "Software"),
65ca02815Sjsg * to deal in the Software without restriction, including without limitation
75ca02815Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
85ca02815Sjsg * and/or sell copies of the Software, and to permit persons to whom the
95ca02815Sjsg * Software is furnished to do so, subject to the following conditions:
105ca02815Sjsg *
115ca02815Sjsg * The above copyright notice and this permission notice shall be included in
125ca02815Sjsg * all copies or substantial portions of the Software.
135ca02815Sjsg *
145ca02815Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
155ca02815Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
165ca02815Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
175ca02815Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
185ca02815Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
195ca02815Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
205ca02815Sjsg * OTHER DEALINGS IN THE SOFTWARE.
215ca02815Sjsg *
225ca02815Sjsg */
231bb76ff1Sjsg #include <drm/drm_drv.h>
241bb76ff1Sjsg #include <linux/vmalloc.h>
255ca02815Sjsg #include "amdgpu.h"
265ca02815Sjsg #include "amdgpu_psp.h"
275ca02815Sjsg #include "amdgpu_ucode.h"
285ca02815Sjsg #include "soc15_common.h"
295ca02815Sjsg #include "psp_v13_0.h"
305ca02815Sjsg
315ca02815Sjsg #include "mp/mp_13_0_2_offset.h"
325ca02815Sjsg #include "mp/mp_13_0_2_sh_mask.h"
335ca02815Sjsg
345ca02815Sjsg MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
355ca02815Sjsg MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
361bb76ff1Sjsg MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin");
375ca02815Sjsg MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
385ca02815Sjsg MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
391bb76ff1Sjsg MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin");
401bb76ff1Sjsg MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
411bb76ff1Sjsg MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
421bb76ff1Sjsg MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
431bb76ff1Sjsg MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
441bb76ff1Sjsg MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
451bb76ff1Sjsg MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
461bb76ff1Sjsg MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
471bb76ff1Sjsg MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin");
481bb76ff1Sjsg MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin");
49d424a9b5Sjsg MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin");
50d424a9b5Sjsg MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin");
51*f005ef32Sjsg MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin");
52*f005ef32Sjsg MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin");
53*f005ef32Sjsg MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin");
54*f005ef32Sjsg MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin");
555ca02815Sjsg
565ca02815Sjsg /* For large FW files the time to complete can be very long */
575ca02815Sjsg #define USBC_PD_POLLING_LIMIT_S 240
585ca02815Sjsg
595ca02815Sjsg /* Read USB-PD from LFB */
605ca02815Sjsg #define GFX_CMD_USB_PD_USE_LFB 0x480
615ca02815Sjsg
62*f005ef32Sjsg /* Retry times for vmbx ready wait */
63*f005ef32Sjsg #define PSP_VMBX_POLLING_LIMIT 3000
64*f005ef32Sjsg
651bb76ff1Sjsg /* VBIOS gfl defines */
661bb76ff1Sjsg #define MBOX_READY_MASK 0x80000000
671bb76ff1Sjsg #define MBOX_STATUS_MASK 0x0000FFFF
681bb76ff1Sjsg #define MBOX_COMMAND_MASK 0x00FF0000
691bb76ff1Sjsg #define MBOX_READY_FLAG 0x80000000
701bb76ff1Sjsg #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
711bb76ff1Sjsg #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
721bb76ff1Sjsg #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
731bb76ff1Sjsg
741bb76ff1Sjsg /* memory training timeout define */
751bb76ff1Sjsg #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000
761bb76ff1Sjsg
psp_v13_0_init_microcode(struct psp_context * psp)775ca02815Sjsg static int psp_v13_0_init_microcode(struct psp_context *psp)
785ca02815Sjsg {
795ca02815Sjsg struct amdgpu_device *adev = psp->adev;
801bb76ff1Sjsg char ucode_prefix[30];
815ca02815Sjsg int err = 0;
825ca02815Sjsg
831bb76ff1Sjsg amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
841bb76ff1Sjsg
851bb76ff1Sjsg switch (adev->ip_versions[MP0_HWIP][0]) {
861bb76ff1Sjsg case IP_VERSION(13, 0, 2):
87*f005ef32Sjsg err = psp_init_sos_microcode(psp, ucode_prefix);
885ca02815Sjsg if (err)
895ca02815Sjsg return err;
901bb76ff1Sjsg /* It's not necessary to load ras ta on Guest side */
911bb76ff1Sjsg if (!amdgpu_sriov_vf(adev)) {
92*f005ef32Sjsg err = psp_init_ta_microcode(psp, ucode_prefix);
935ca02815Sjsg if (err)
945ca02815Sjsg return err;
951bb76ff1Sjsg }
965ca02815Sjsg break;
971bb76ff1Sjsg case IP_VERSION(13, 0, 1):
981bb76ff1Sjsg case IP_VERSION(13, 0, 3):
991bb76ff1Sjsg case IP_VERSION(13, 0, 5):
1001bb76ff1Sjsg case IP_VERSION(13, 0, 8):
101d424a9b5Sjsg case IP_VERSION(13, 0, 11):
102*f005ef32Sjsg case IP_VERSION(14, 0, 0):
103*f005ef32Sjsg err = psp_init_toc_microcode(psp, ucode_prefix);
1045ca02815Sjsg if (err)
1055ca02815Sjsg return err;
106*f005ef32Sjsg err = psp_init_ta_microcode(psp, ucode_prefix);
1075ca02815Sjsg if (err)
1085ca02815Sjsg return err;
1095ca02815Sjsg break;
1101bb76ff1Sjsg case IP_VERSION(13, 0, 0):
111*f005ef32Sjsg case IP_VERSION(13, 0, 6):
1121bb76ff1Sjsg case IP_VERSION(13, 0, 7):
1131bb76ff1Sjsg case IP_VERSION(13, 0, 10):
114*f005ef32Sjsg err = psp_init_sos_microcode(psp, ucode_prefix);
1151bb76ff1Sjsg if (err)
1161bb76ff1Sjsg return err;
1171bb76ff1Sjsg /* It's not necessary to load ras ta on Guest side */
118*f005ef32Sjsg err = psp_init_ta_microcode(psp, ucode_prefix);
1191bb76ff1Sjsg if (err)
1201bb76ff1Sjsg return err;
1211bb76ff1Sjsg break;
1225ca02815Sjsg default:
1235ca02815Sjsg BUG();
1245ca02815Sjsg }
1255ca02815Sjsg
1265ca02815Sjsg return 0;
1275ca02815Sjsg }
1285ca02815Sjsg
psp_v13_0_is_sos_alive(struct psp_context * psp)1295ca02815Sjsg static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
1305ca02815Sjsg {
1315ca02815Sjsg struct amdgpu_device *adev = psp->adev;
1325ca02815Sjsg uint32_t sol_reg;
1335ca02815Sjsg
1345ca02815Sjsg sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
1355ca02815Sjsg
1365ca02815Sjsg return sol_reg != 0x0;
1375ca02815Sjsg }
1385ca02815Sjsg
psp_v13_0_wait_for_vmbx_ready(struct psp_context * psp)139*f005ef32Sjsg static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp)
140*f005ef32Sjsg {
141*f005ef32Sjsg struct amdgpu_device *adev = psp->adev;
142*f005ef32Sjsg int retry_loop, ret;
143*f005ef32Sjsg
144*f005ef32Sjsg for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) {
145*f005ef32Sjsg /* Wait for bootloader to signify that is
146*f005ef32Sjsg ready having bit 31 of C2PMSG_33 set to 1 */
147*f005ef32Sjsg ret = psp_wait_for(
148*f005ef32Sjsg psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33),
149*f005ef32Sjsg 0x80000000, 0xffffffff, false);
150*f005ef32Sjsg
151*f005ef32Sjsg if (ret == 0)
152*f005ef32Sjsg break;
153*f005ef32Sjsg }
154*f005ef32Sjsg
155*f005ef32Sjsg if (ret)
156*f005ef32Sjsg dev_warn(adev->dev, "Bootloader wait timed out");
157*f005ef32Sjsg
158*f005ef32Sjsg return ret;
159*f005ef32Sjsg }
160*f005ef32Sjsg
psp_v13_0_wait_for_bootloader(struct psp_context * psp)1615ca02815Sjsg static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
1625ca02815Sjsg {
1635ca02815Sjsg struct amdgpu_device *adev = psp->adev;
164*f005ef32Sjsg int retry_loop, retry_cnt, ret;
1655ca02815Sjsg
166*f005ef32Sjsg retry_cnt =
167*f005ef32Sjsg (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6)) ?
168*f005ef32Sjsg PSP_VMBX_POLLING_LIMIT :
169*f005ef32Sjsg 10;
170108bce24Sjsg /* Wait for bootloader to signify that it is ready having bit 31 of
171108bce24Sjsg * C2PMSG_35 set to 1. All other bits are expected to be cleared.
172108bce24Sjsg * If there is an error in processing command, bits[7:0] will be set.
173108bce24Sjsg * This is applicable for PSP v13.0.6 and newer.
174108bce24Sjsg */
175*f005ef32Sjsg for (retry_loop = 0; retry_loop < retry_cnt; retry_loop++) {
176108bce24Sjsg ret = psp_wait_for(
177108bce24Sjsg psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
178108bce24Sjsg 0x80000000, 0xffffffff, false);
1795ca02815Sjsg
1805ca02815Sjsg if (ret == 0)
1815ca02815Sjsg return 0;
1825ca02815Sjsg }
1835ca02815Sjsg
1845ca02815Sjsg return ret;
1855ca02815Sjsg }
1865ca02815Sjsg
psp_v13_0_wait_for_bootloader_steady_state(struct psp_context * psp)187*f005ef32Sjsg static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp)
188*f005ef32Sjsg {
189*f005ef32Sjsg struct amdgpu_device *adev = psp->adev;
190*f005ef32Sjsg
191*f005ef32Sjsg if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6)) {
192*f005ef32Sjsg psp_v13_0_wait_for_vmbx_ready(psp);
193*f005ef32Sjsg
194*f005ef32Sjsg return psp_v13_0_wait_for_bootloader(psp);
195*f005ef32Sjsg }
196*f005ef32Sjsg
197*f005ef32Sjsg return 0;
198*f005ef32Sjsg }
199*f005ef32Sjsg
psp_v13_0_bootloader_load_component(struct psp_context * psp,struct psp_bin_desc * bin_desc,enum psp_bootloader_cmd bl_cmd)2005ca02815Sjsg static int psp_v13_0_bootloader_load_component(struct psp_context *psp,
2015ca02815Sjsg struct psp_bin_desc *bin_desc,
2025ca02815Sjsg enum psp_bootloader_cmd bl_cmd)
2035ca02815Sjsg {
2045ca02815Sjsg int ret;
2055ca02815Sjsg uint32_t psp_gfxdrv_command_reg = 0;
2065ca02815Sjsg struct amdgpu_device *adev = psp->adev;
2075ca02815Sjsg
2085ca02815Sjsg /* Check tOS sign of life register to confirm sys driver and sOS
2095ca02815Sjsg * are already been loaded.
2105ca02815Sjsg */
2115ca02815Sjsg if (psp_v13_0_is_sos_alive(psp))
2125ca02815Sjsg return 0;
2135ca02815Sjsg
2145ca02815Sjsg ret = psp_v13_0_wait_for_bootloader(psp);
2155ca02815Sjsg if (ret)
2165ca02815Sjsg return ret;
2175ca02815Sjsg
2185ca02815Sjsg memset(psp->fw_pri_buf, 0, PSP_1_MEG);
2195ca02815Sjsg
2205ca02815Sjsg /* Copy PSP KDB binary to memory */
2215ca02815Sjsg memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
2225ca02815Sjsg
2235ca02815Sjsg /* Provide the PSP KDB to bootloader */
2245ca02815Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
2255ca02815Sjsg (uint32_t)(psp->fw_pri_mc_addr >> 20));
2265ca02815Sjsg psp_gfxdrv_command_reg = bl_cmd;
2275ca02815Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
2285ca02815Sjsg psp_gfxdrv_command_reg);
2295ca02815Sjsg
2305ca02815Sjsg ret = psp_v13_0_wait_for_bootloader(psp);
2315ca02815Sjsg
2325ca02815Sjsg return ret;
2335ca02815Sjsg }
2345ca02815Sjsg
psp_v13_0_bootloader_load_kdb(struct psp_context * psp)2355ca02815Sjsg static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp)
2365ca02815Sjsg {
2375ca02815Sjsg return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
2385ca02815Sjsg }
2395ca02815Sjsg
psp_v13_0_bootloader_load_spl(struct psp_context * psp)2401bb76ff1Sjsg static int psp_v13_0_bootloader_load_spl(struct psp_context *psp)
2411bb76ff1Sjsg {
2421bb76ff1Sjsg return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
2431bb76ff1Sjsg }
2441bb76ff1Sjsg
psp_v13_0_bootloader_load_sysdrv(struct psp_context * psp)2455ca02815Sjsg static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp)
2465ca02815Sjsg {
2475ca02815Sjsg return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
2485ca02815Sjsg }
2495ca02815Sjsg
psp_v13_0_bootloader_load_soc_drv(struct psp_context * psp)2505ca02815Sjsg static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp)
2515ca02815Sjsg {
2525ca02815Sjsg return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
2535ca02815Sjsg }
2545ca02815Sjsg
psp_v13_0_bootloader_load_intf_drv(struct psp_context * psp)2555ca02815Sjsg static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp)
2565ca02815Sjsg {
2575ca02815Sjsg return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
2585ca02815Sjsg }
2595ca02815Sjsg
psp_v13_0_bootloader_load_dbg_drv(struct psp_context * psp)2605ca02815Sjsg static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp)
2615ca02815Sjsg {
2625ca02815Sjsg return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
2635ca02815Sjsg }
2645ca02815Sjsg
psp_v13_0_bootloader_load_ras_drv(struct psp_context * psp)2651bb76ff1Sjsg static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp)
2661bb76ff1Sjsg {
2671bb76ff1Sjsg return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV);
2681bb76ff1Sjsg }
2691bb76ff1Sjsg
2701bb76ff1Sjsg
psp_v13_0_bootloader_load_sos(struct psp_context * psp)2715ca02815Sjsg static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
2725ca02815Sjsg {
2735ca02815Sjsg int ret;
2745ca02815Sjsg unsigned int psp_gfxdrv_command_reg = 0;
2755ca02815Sjsg struct amdgpu_device *adev = psp->adev;
2765ca02815Sjsg
2775ca02815Sjsg /* Check sOS sign of life register to confirm sys driver and sOS
2785ca02815Sjsg * are already been loaded.
2795ca02815Sjsg */
2805ca02815Sjsg if (psp_v13_0_is_sos_alive(psp))
2815ca02815Sjsg return 0;
2825ca02815Sjsg
2835ca02815Sjsg ret = psp_v13_0_wait_for_bootloader(psp);
2845ca02815Sjsg if (ret)
2855ca02815Sjsg return ret;
2865ca02815Sjsg
2875ca02815Sjsg memset(psp->fw_pri_buf, 0, PSP_1_MEG);
2885ca02815Sjsg
2895ca02815Sjsg /* Copy Secure OS binary to PSP memory */
2905ca02815Sjsg memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
2915ca02815Sjsg
2925ca02815Sjsg /* Provide the PSP secure OS to bootloader */
2935ca02815Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
2945ca02815Sjsg (uint32_t)(psp->fw_pri_mc_addr >> 20));
2955ca02815Sjsg psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
2965ca02815Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
2975ca02815Sjsg psp_gfxdrv_command_reg);
2985ca02815Sjsg
2995ca02815Sjsg /* there might be handshake issue with hardware which needs delay */
3005ca02815Sjsg mdelay(20);
3015ca02815Sjsg ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
3025ca02815Sjsg RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
3035ca02815Sjsg 0, true);
3045ca02815Sjsg
3055ca02815Sjsg return ret;
3065ca02815Sjsg }
3075ca02815Sjsg
psp_v13_0_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)3085ca02815Sjsg static int psp_v13_0_ring_stop(struct psp_context *psp,
3095ca02815Sjsg enum psp_ring_type ring_type)
3105ca02815Sjsg {
3115ca02815Sjsg int ret = 0;
3125ca02815Sjsg struct amdgpu_device *adev = psp->adev;
3135ca02815Sjsg
3145ca02815Sjsg if (amdgpu_sriov_vf(adev)) {
3155ca02815Sjsg /* Write the ring destroy command*/
3165ca02815Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
3175ca02815Sjsg GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
3185ca02815Sjsg /* there might be handshake issue with hardware which needs delay */
3195ca02815Sjsg mdelay(20);
3205ca02815Sjsg /* Wait for response flag (bit 31) */
3215ca02815Sjsg ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
3225ca02815Sjsg 0x80000000, 0x80000000, false);
3235ca02815Sjsg } else {
3245ca02815Sjsg /* Write the ring destroy command*/
3255ca02815Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
3265ca02815Sjsg GFX_CTRL_CMD_ID_DESTROY_RINGS);
3275ca02815Sjsg /* there might be handshake issue with hardware which needs delay */
3285ca02815Sjsg mdelay(20);
3295ca02815Sjsg /* Wait for response flag (bit 31) */
3305ca02815Sjsg ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
3315ca02815Sjsg 0x80000000, 0x80000000, false);
3325ca02815Sjsg }
3335ca02815Sjsg
3345ca02815Sjsg return ret;
3355ca02815Sjsg }
3365ca02815Sjsg
psp_v13_0_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)3375ca02815Sjsg static int psp_v13_0_ring_create(struct psp_context *psp,
3385ca02815Sjsg enum psp_ring_type ring_type)
3395ca02815Sjsg {
3405ca02815Sjsg int ret = 0;
3415ca02815Sjsg unsigned int psp_ring_reg = 0;
3425ca02815Sjsg struct psp_ring *ring = &psp->km_ring;
3435ca02815Sjsg struct amdgpu_device *adev = psp->adev;
3445ca02815Sjsg
3455ca02815Sjsg if (amdgpu_sriov_vf(adev)) {
3465ca02815Sjsg ret = psp_v13_0_ring_stop(psp, ring_type);
3475ca02815Sjsg if (ret) {
3485ca02815Sjsg DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
3495ca02815Sjsg return ret;
3505ca02815Sjsg }
3515ca02815Sjsg
3525ca02815Sjsg /* Write low address of the ring to C2PMSG_102 */
3535ca02815Sjsg psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
3545ca02815Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
3555ca02815Sjsg /* Write high address of the ring to C2PMSG_103 */
3565ca02815Sjsg psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
3575ca02815Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
3585ca02815Sjsg
3595ca02815Sjsg /* Write the ring initialization command to C2PMSG_101 */
3605ca02815Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
3615ca02815Sjsg GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
3625ca02815Sjsg
3635ca02815Sjsg /* there might be handshake issue with hardware which needs delay */
3645ca02815Sjsg mdelay(20);
3655ca02815Sjsg
3665ca02815Sjsg /* Wait for response flag (bit 31) in C2PMSG_101 */
3675ca02815Sjsg ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
3685ca02815Sjsg 0x80000000, 0x8000FFFF, false);
3695ca02815Sjsg
3705ca02815Sjsg } else {
3715ca02815Sjsg /* Wait for sOS ready for ring creation */
3725ca02815Sjsg ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
3735ca02815Sjsg 0x80000000, 0x80000000, false);
3745ca02815Sjsg if (ret) {
3755ca02815Sjsg DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
3765ca02815Sjsg return ret;
3775ca02815Sjsg }
3785ca02815Sjsg
3795ca02815Sjsg /* Write low address of the ring to C2PMSG_69 */
3805ca02815Sjsg psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
3815ca02815Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
3825ca02815Sjsg /* Write high address of the ring to C2PMSG_70 */
3835ca02815Sjsg psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
3845ca02815Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
3855ca02815Sjsg /* Write size of ring to C2PMSG_71 */
3865ca02815Sjsg psp_ring_reg = ring->ring_size;
3875ca02815Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
3885ca02815Sjsg /* Write the ring initialization command to C2PMSG_64 */
3895ca02815Sjsg psp_ring_reg = ring_type;
3905ca02815Sjsg psp_ring_reg = psp_ring_reg << 16;
3915ca02815Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
3925ca02815Sjsg
3935ca02815Sjsg /* there might be handshake issue with hardware which needs delay */
3945ca02815Sjsg mdelay(20);
3955ca02815Sjsg
3965ca02815Sjsg /* Wait for response flag (bit 31) in C2PMSG_64 */
3975ca02815Sjsg ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
3985ca02815Sjsg 0x80000000, 0x8000FFFF, false);
3995ca02815Sjsg }
4005ca02815Sjsg
4015ca02815Sjsg return ret;
4025ca02815Sjsg }
4035ca02815Sjsg
psp_v13_0_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)4045ca02815Sjsg static int psp_v13_0_ring_destroy(struct psp_context *psp,
4055ca02815Sjsg enum psp_ring_type ring_type)
4065ca02815Sjsg {
4075ca02815Sjsg int ret = 0;
4085ca02815Sjsg struct psp_ring *ring = &psp->km_ring;
4095ca02815Sjsg struct amdgpu_device *adev = psp->adev;
4105ca02815Sjsg
4115ca02815Sjsg ret = psp_v13_0_ring_stop(psp, ring_type);
4125ca02815Sjsg if (ret)
4135ca02815Sjsg DRM_ERROR("Fail to stop psp ring\n");
4145ca02815Sjsg
4155ca02815Sjsg amdgpu_bo_free_kernel(&adev->firmware.rbuf,
4165ca02815Sjsg &ring->ring_mem_mc_addr,
4175ca02815Sjsg (void **)&ring->ring_mem);
4185ca02815Sjsg
4195ca02815Sjsg return ret;
4205ca02815Sjsg }
4215ca02815Sjsg
psp_v13_0_ring_get_wptr(struct psp_context * psp)4225ca02815Sjsg static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)
4235ca02815Sjsg {
4245ca02815Sjsg uint32_t data;
4255ca02815Sjsg struct amdgpu_device *adev = psp->adev;
4265ca02815Sjsg
4275ca02815Sjsg if (amdgpu_sriov_vf(adev))
4285ca02815Sjsg data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
4295ca02815Sjsg else
4305ca02815Sjsg data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
4315ca02815Sjsg
4325ca02815Sjsg return data;
4335ca02815Sjsg }
4345ca02815Sjsg
psp_v13_0_ring_set_wptr(struct psp_context * psp,uint32_t value)4355ca02815Sjsg static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
4365ca02815Sjsg {
4375ca02815Sjsg struct amdgpu_device *adev = psp->adev;
4385ca02815Sjsg
4395ca02815Sjsg if (amdgpu_sriov_vf(adev)) {
4405ca02815Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
4415ca02815Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
4425ca02815Sjsg GFX_CTRL_CMD_ID_CONSUME_CMD);
4435ca02815Sjsg } else
4445ca02815Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
4455ca02815Sjsg }
4465ca02815Sjsg
psp_v13_0_memory_training_send_msg(struct psp_context * psp,int msg)4471bb76ff1Sjsg static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg)
4481bb76ff1Sjsg {
4491bb76ff1Sjsg int ret;
4501bb76ff1Sjsg int i;
4511bb76ff1Sjsg uint32_t data_32;
4521bb76ff1Sjsg int max_wait;
4531bb76ff1Sjsg struct amdgpu_device *adev = psp->adev;
4541bb76ff1Sjsg
4551bb76ff1Sjsg data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
4561bb76ff1Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32);
4571bb76ff1Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg);
4581bb76ff1Sjsg
4591bb76ff1Sjsg max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
4601bb76ff1Sjsg for (i = 0; i < max_wait; i++) {
4611bb76ff1Sjsg ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
4621bb76ff1Sjsg 0x80000000, 0x80000000, false);
4631bb76ff1Sjsg if (ret == 0)
4641bb76ff1Sjsg break;
4651bb76ff1Sjsg }
4661bb76ff1Sjsg if (i < max_wait)
4671bb76ff1Sjsg ret = 0;
4681bb76ff1Sjsg else
4691bb76ff1Sjsg ret = -ETIME;
4701bb76ff1Sjsg
4711bb76ff1Sjsg dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
4721bb76ff1Sjsg (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
4731bb76ff1Sjsg (ret == 0) ? "succeed" : "failed",
4741bb76ff1Sjsg i, adev->usec_timeout/1000);
4751bb76ff1Sjsg return ret;
4761bb76ff1Sjsg }
4771bb76ff1Sjsg
4781bb76ff1Sjsg
psp_v13_0_memory_training(struct psp_context * psp,uint32_t ops)4791bb76ff1Sjsg static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)
4801bb76ff1Sjsg {
4811bb76ff1Sjsg struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
4821bb76ff1Sjsg uint32_t *pcache = (uint32_t *)ctx->sys_cache;
4831bb76ff1Sjsg struct amdgpu_device *adev = psp->adev;
4841bb76ff1Sjsg uint32_t p2c_header[4];
4851bb76ff1Sjsg uint32_t sz;
4861bb76ff1Sjsg void *buf;
4871bb76ff1Sjsg int ret, idx;
4881bb76ff1Sjsg
4891bb76ff1Sjsg if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
4901bb76ff1Sjsg dev_dbg(adev->dev, "Memory training is not supported.\n");
4911bb76ff1Sjsg return 0;
4921bb76ff1Sjsg } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
4931bb76ff1Sjsg dev_err(adev->dev, "Memory training initialization failure.\n");
4941bb76ff1Sjsg return -EINVAL;
4951bb76ff1Sjsg }
4961bb76ff1Sjsg
4971bb76ff1Sjsg if (psp_v13_0_is_sos_alive(psp)) {
4981bb76ff1Sjsg dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
4991bb76ff1Sjsg return 0;
5001bb76ff1Sjsg }
5011bb76ff1Sjsg
5021bb76ff1Sjsg amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
5031bb76ff1Sjsg dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
5041bb76ff1Sjsg pcache[0], pcache[1], pcache[2], pcache[3],
5051bb76ff1Sjsg p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
5061bb76ff1Sjsg
5071bb76ff1Sjsg if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
5081bb76ff1Sjsg dev_dbg(adev->dev, "Short training depends on restore.\n");
5091bb76ff1Sjsg ops |= PSP_MEM_TRAIN_RESTORE;
5101bb76ff1Sjsg }
5111bb76ff1Sjsg
5121bb76ff1Sjsg if ((ops & PSP_MEM_TRAIN_RESTORE) &&
5131bb76ff1Sjsg pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
5141bb76ff1Sjsg dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n");
5151bb76ff1Sjsg ops |= PSP_MEM_TRAIN_SAVE;
5161bb76ff1Sjsg }
5171bb76ff1Sjsg
5181bb76ff1Sjsg if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
5191bb76ff1Sjsg !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
5201bb76ff1Sjsg pcache[3] == p2c_header[3])) {
5211bb76ff1Sjsg dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
5221bb76ff1Sjsg ops |= PSP_MEM_TRAIN_SAVE;
5231bb76ff1Sjsg }
5241bb76ff1Sjsg
5251bb76ff1Sjsg if ((ops & PSP_MEM_TRAIN_SAVE) &&
5261bb76ff1Sjsg p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
5271bb76ff1Sjsg dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n");
5281bb76ff1Sjsg ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
5291bb76ff1Sjsg }
5301bb76ff1Sjsg
5311bb76ff1Sjsg if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
5321bb76ff1Sjsg ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
5331bb76ff1Sjsg ops |= PSP_MEM_TRAIN_SAVE;
5341bb76ff1Sjsg }
5351bb76ff1Sjsg
5361bb76ff1Sjsg dev_dbg(adev->dev, "Memory training ops:%x.\n", ops);
5371bb76ff1Sjsg
5381bb76ff1Sjsg if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
5391bb76ff1Sjsg /*
5401bb76ff1Sjsg * Long training will encroach a certain amount on the bottom of VRAM;
5411bb76ff1Sjsg * save the content from the bottom of VRAM to system memory
5421bb76ff1Sjsg * before training, and restore it after training to avoid
5431bb76ff1Sjsg * VRAM corruption.
5441bb76ff1Sjsg */
5451bb76ff1Sjsg sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
5461bb76ff1Sjsg
5471bb76ff1Sjsg if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
5481bb76ff1Sjsg dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
5491bb76ff1Sjsg adev->gmc.visible_vram_size,
5501bb76ff1Sjsg adev->mman.aper_base_kaddr);
5511bb76ff1Sjsg return -EINVAL;
5521bb76ff1Sjsg }
5531bb76ff1Sjsg
5541bb76ff1Sjsg buf = vmalloc(sz);
5551bb76ff1Sjsg if (!buf) {
5561bb76ff1Sjsg dev_err(adev->dev, "failed to allocate system memory.\n");
5571bb76ff1Sjsg return -ENOMEM;
5581bb76ff1Sjsg }
5591bb76ff1Sjsg
5601bb76ff1Sjsg if (drm_dev_enter(adev_to_drm(adev), &idx)) {
5611bb76ff1Sjsg memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
5621bb76ff1Sjsg ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
5631bb76ff1Sjsg if (ret) {
5641bb76ff1Sjsg DRM_ERROR("Send long training msg failed.\n");
5651bb76ff1Sjsg vfree(buf);
5661bb76ff1Sjsg drm_dev_exit(idx);
5671bb76ff1Sjsg return ret;
5681bb76ff1Sjsg }
5691bb76ff1Sjsg
5701bb76ff1Sjsg memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
5711bb76ff1Sjsg adev->hdp.funcs->flush_hdp(adev, NULL);
5721bb76ff1Sjsg vfree(buf);
5731bb76ff1Sjsg drm_dev_exit(idx);
5741bb76ff1Sjsg } else {
5751bb76ff1Sjsg vfree(buf);
5761bb76ff1Sjsg return -ENODEV;
5771bb76ff1Sjsg }
5781bb76ff1Sjsg }
5791bb76ff1Sjsg
5801bb76ff1Sjsg if (ops & PSP_MEM_TRAIN_SAVE) {
5811bb76ff1Sjsg amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
5821bb76ff1Sjsg }
5831bb76ff1Sjsg
5841bb76ff1Sjsg if (ops & PSP_MEM_TRAIN_RESTORE) {
5851bb76ff1Sjsg amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
5861bb76ff1Sjsg }
5871bb76ff1Sjsg
5881bb76ff1Sjsg if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
5891bb76ff1Sjsg ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
5901bb76ff1Sjsg PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
5911bb76ff1Sjsg if (ret) {
5921bb76ff1Sjsg dev_err(adev->dev, "send training msg failed.\n");
5931bb76ff1Sjsg return ret;
5941bb76ff1Sjsg }
5951bb76ff1Sjsg }
5961bb76ff1Sjsg ctx->training_cnt++;
5971bb76ff1Sjsg return 0;
5981bb76ff1Sjsg }
5991bb76ff1Sjsg
psp_v13_0_load_usbc_pd_fw(struct psp_context * psp,uint64_t fw_pri_mc_addr)6005ca02815Sjsg static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
6015ca02815Sjsg {
6025ca02815Sjsg struct amdgpu_device *adev = psp->adev;
6035ca02815Sjsg uint32_t reg_status;
6045ca02815Sjsg int ret, i = 0;
6055ca02815Sjsg
6065ca02815Sjsg /*
6075ca02815Sjsg * LFB address which is aligned to 1MB address and has to be
6085ca02815Sjsg * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
6095ca02815Sjsg * register
6105ca02815Sjsg */
6115ca02815Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
6125ca02815Sjsg
6135ca02815Sjsg ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
6145ca02815Sjsg 0x80000000, 0x80000000, false);
6155ca02815Sjsg if (ret)
6165ca02815Sjsg return ret;
6175ca02815Sjsg
6185ca02815Sjsg /* Fireup interrupt so PSP can pick up the address */
6195ca02815Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
6205ca02815Sjsg
6215ca02815Sjsg /* FW load takes very long time */
6225ca02815Sjsg do {
6235ca02815Sjsg drm_msleep(1000);
6245ca02815Sjsg reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);
6255ca02815Sjsg
6265ca02815Sjsg if (reg_status & 0x80000000)
6275ca02815Sjsg goto done;
6285ca02815Sjsg
6295ca02815Sjsg } while (++i < USBC_PD_POLLING_LIMIT_S);
6305ca02815Sjsg
6315ca02815Sjsg return -ETIME;
6325ca02815Sjsg done:
6335ca02815Sjsg
6345ca02815Sjsg if ((reg_status & 0xFFFF) != 0) {
6355ca02815Sjsg DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
6365ca02815Sjsg reg_status & 0xFFFF);
6375ca02815Sjsg return -EIO;
6385ca02815Sjsg }
6395ca02815Sjsg
6405ca02815Sjsg return 0;
6415ca02815Sjsg }
6425ca02815Sjsg
psp_v13_0_read_usbc_pd_fw(struct psp_context * psp,uint32_t * fw_ver)6435ca02815Sjsg static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
6445ca02815Sjsg {
6455ca02815Sjsg struct amdgpu_device *adev = psp->adev;
6465ca02815Sjsg int ret;
6475ca02815Sjsg
6485ca02815Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
6495ca02815Sjsg
6505ca02815Sjsg ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
6515ca02815Sjsg 0x80000000, 0x80000000, false);
6525ca02815Sjsg if (!ret)
6535ca02815Sjsg *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);
6545ca02815Sjsg
6555ca02815Sjsg return ret;
6565ca02815Sjsg }
6575ca02815Sjsg
psp_v13_0_exec_spi_cmd(struct psp_context * psp,int cmd)6581bb76ff1Sjsg static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)
6591bb76ff1Sjsg {
6601bb76ff1Sjsg uint32_t reg_status = 0, reg_val = 0;
6611bb76ff1Sjsg struct amdgpu_device *adev = psp->adev;
6621bb76ff1Sjsg int ret;
6631bb76ff1Sjsg
6641bb76ff1Sjsg /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
6651bb76ff1Sjsg reg_val |= (cmd << 16);
6661bb76ff1Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val);
6671bb76ff1Sjsg
6681bb76ff1Sjsg /* Ring the doorbell */
6691bb76ff1Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
6701bb76ff1Sjsg
6711bb76ff1Sjsg if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)
672*f005ef32Sjsg ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
673*f005ef32Sjsg MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT);
674*f005ef32Sjsg else
6751bb76ff1Sjsg ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
6761bb76ff1Sjsg MBOX_READY_FLAG, MBOX_READY_MASK, false);
6771bb76ff1Sjsg if (ret) {
6781bb76ff1Sjsg dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
6791bb76ff1Sjsg return ret;
6801bb76ff1Sjsg }
6811bb76ff1Sjsg
6821bb76ff1Sjsg reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
6831bb76ff1Sjsg if ((reg_status & 0xFFFF) != 0) {
6841bb76ff1Sjsg dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
6851bb76ff1Sjsg cmd, reg_status & 0xFFFF);
6861bb76ff1Sjsg return -EIO;
6871bb76ff1Sjsg }
6881bb76ff1Sjsg
6891bb76ff1Sjsg return 0;
6901bb76ff1Sjsg }
6911bb76ff1Sjsg
psp_v13_0_update_spirom(struct psp_context * psp,uint64_t fw_pri_mc_addr)6921bb76ff1Sjsg static int psp_v13_0_update_spirom(struct psp_context *psp,
6931bb76ff1Sjsg uint64_t fw_pri_mc_addr)
6941bb76ff1Sjsg {
6951bb76ff1Sjsg struct amdgpu_device *adev = psp->adev;
6961bb76ff1Sjsg int ret;
6971bb76ff1Sjsg
6981bb76ff1Sjsg /* Confirm PSP is ready to start */
6991bb76ff1Sjsg ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
7001bb76ff1Sjsg MBOX_READY_FLAG, MBOX_READY_MASK, false);
7011bb76ff1Sjsg if (ret) {
7021bb76ff1Sjsg dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
7031bb76ff1Sjsg return ret;
7041bb76ff1Sjsg }
7051bb76ff1Sjsg
7061bb76ff1Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
7071bb76ff1Sjsg
7081bb76ff1Sjsg ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
7091bb76ff1Sjsg if (ret)
7101bb76ff1Sjsg return ret;
7111bb76ff1Sjsg
7121bb76ff1Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
7131bb76ff1Sjsg
7141bb76ff1Sjsg ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
7151bb76ff1Sjsg if (ret)
7161bb76ff1Sjsg return ret;
7171bb76ff1Sjsg
7181bb76ff1Sjsg psp->vbflash_done = true;
7191bb76ff1Sjsg
7201bb76ff1Sjsg ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
7211bb76ff1Sjsg if (ret)
7221bb76ff1Sjsg return ret;
7231bb76ff1Sjsg
7241bb76ff1Sjsg return 0;
7251bb76ff1Sjsg }
7261bb76ff1Sjsg
psp_v13_0_vbflash_status(struct psp_context * psp)7271bb76ff1Sjsg static int psp_v13_0_vbflash_status(struct psp_context *psp)
7281bb76ff1Sjsg {
7291bb76ff1Sjsg struct amdgpu_device *adev = psp->adev;
7301bb76ff1Sjsg
7311bb76ff1Sjsg return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
7321bb76ff1Sjsg }
7331bb76ff1Sjsg
psp_v13_0_fatal_error_recovery_quirk(struct psp_context * psp)734*f005ef32Sjsg static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp)
735*f005ef32Sjsg {
736*f005ef32Sjsg struct amdgpu_device *adev = psp->adev;
737*f005ef32Sjsg
738*f005ef32Sjsg if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 10)) {
739*f005ef32Sjsg uint32_t reg_data;
740*f005ef32Sjsg /* MP1 fatal error: trigger PSP dram read to unhalt PSP
741*f005ef32Sjsg * during MP1 triggered sync flood.
742*f005ef32Sjsg */
743*f005ef32Sjsg reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
744*f005ef32Sjsg WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10);
745*f005ef32Sjsg
746*f005ef32Sjsg /* delay 1000ms for the mode1 reset for fatal error
747*f005ef32Sjsg * to be recovered back.
748*f005ef32Sjsg */
749*f005ef32Sjsg drm_msleep(1000);
750*f005ef32Sjsg }
751*f005ef32Sjsg
752*f005ef32Sjsg return 0;
753*f005ef32Sjsg }
754*f005ef32Sjsg
7555ca02815Sjsg static const struct psp_funcs psp_v13_0_funcs = {
7565ca02815Sjsg .init_microcode = psp_v13_0_init_microcode,
757*f005ef32Sjsg .wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state,
7585ca02815Sjsg .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
7591bb76ff1Sjsg .bootloader_load_spl = psp_v13_0_bootloader_load_spl,
7605ca02815Sjsg .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,
7615ca02815Sjsg .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv,
7625ca02815Sjsg .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv,
7635ca02815Sjsg .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv,
7641bb76ff1Sjsg .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv,
7655ca02815Sjsg .bootloader_load_sos = psp_v13_0_bootloader_load_sos,
7665ca02815Sjsg .ring_create = psp_v13_0_ring_create,
7675ca02815Sjsg .ring_stop = psp_v13_0_ring_stop,
7685ca02815Sjsg .ring_destroy = psp_v13_0_ring_destroy,
7695ca02815Sjsg .ring_get_wptr = psp_v13_0_ring_get_wptr,
7705ca02815Sjsg .ring_set_wptr = psp_v13_0_ring_set_wptr,
7711bb76ff1Sjsg .mem_training = psp_v13_0_memory_training,
7725ca02815Sjsg .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
7731bb76ff1Sjsg .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
7741bb76ff1Sjsg .update_spirom = psp_v13_0_update_spirom,
775*f005ef32Sjsg .vbflash_stat = psp_v13_0_vbflash_status,
776*f005ef32Sjsg .fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk,
7775ca02815Sjsg };
7785ca02815Sjsg
psp_v13_0_set_psp_funcs(struct psp_context * psp)7795ca02815Sjsg void psp_v13_0_set_psp_funcs(struct psp_context *psp)
7805ca02815Sjsg {
7815ca02815Sjsg psp->funcs = &psp_v13_0_funcs;
7825ca02815Sjsg }
783