1fb4d8502Sjsg /* 2fb4d8502Sjsg * Copyright 2011 Advanced Micro Devices, Inc. 3fb4d8502Sjsg * 4fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"), 6fb4d8502Sjsg * to deal in the Software without restriction, including without limitation 7fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions: 10fb4d8502Sjsg * 11fb4d8502Sjsg * The above copyright notice and this permission notice shall be included in 12fb4d8502Sjsg * all copies or substantial portions of the Software. 13fb4d8502Sjsg * 14fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15fb4d8502Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18fb4d8502Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19fb4d8502Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20fb4d8502Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21fb4d8502Sjsg * 22fb4d8502Sjsg * Authors: Alex Deucher 23fb4d8502Sjsg */ 24fb4d8502Sjsg #ifndef SI_H 25fb4d8502Sjsg #define SI_H 26fb4d8502Sjsg 27fb4d8502Sjsg #define TAHITI_RB_BITMAP_WIDTH_PER_SH 2 28fb4d8502Sjsg 29fb4d8502Sjsg #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 30fb4d8502Sjsg #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 31fb4d8502Sjsg #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001 32fb4d8502Sjsg 33fb4d8502Sjsg #define SI_MAX_SH_GPRS 256 34fb4d8502Sjsg #define SI_MAX_TEMP_GPRS 16 35fb4d8502Sjsg #define SI_MAX_SH_THREADS 256 36fb4d8502Sjsg #define SI_MAX_SH_STACK_ENTRIES 4096 37fb4d8502Sjsg #define SI_MAX_FRC_EOV_CNT 16384 38fb4d8502Sjsg #define SI_MAX_BACKENDS 8 39fb4d8502Sjsg #define SI_MAX_BACKENDS_MASK 0xFF 40fb4d8502Sjsg #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F 41fb4d8502Sjsg #define SI_MAX_SIMDS 12 42fb4d8502Sjsg #define SI_MAX_SIMDS_MASK 0x0FFF 43fb4d8502Sjsg #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF 44fb4d8502Sjsg #define SI_MAX_PIPES 8 45fb4d8502Sjsg #define SI_MAX_PIPES_MASK 0xFF 46fb4d8502Sjsg #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F 47fb4d8502Sjsg #define SI_MAX_LDS_NUM 0xFFFF 48fb4d8502Sjsg #define SI_MAX_TCC 16 49fb4d8502Sjsg #define SI_MAX_TCC_MASK 0xFFFF 50*ad8b1aafSjsg #define SI_MAX_CTLACKS_ASSERTION_WAIT 100 51fb4d8502Sjsg 52fb4d8502Sjsg /* SMC IND accessor regs */ 53fb4d8502Sjsg #define SMC_IND_INDEX_0 0x80 54fb4d8502Sjsg #define SMC_IND_DATA_0 0x81 55fb4d8502Sjsg 56fb4d8502Sjsg #define SMC_IND_ACCESS_CNTL 0x8A 57fb4d8502Sjsg # define AUTO_INCREMENT_IND_0 (1 << 0) 58fb4d8502Sjsg #define SMC_MESSAGE_0 0x8B 59fb4d8502Sjsg #define SMC_RESP_0 0x8C 60fb4d8502Sjsg 61fb4d8502Sjsg /* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */ 62fb4d8502Sjsg #define SMC_CG_IND_START 0xc0030000 63fb4d8502Sjsg #define SMC_CG_IND_END 0xc0040000 64fb4d8502Sjsg 65fb4d8502Sjsg #define CG_CGTT_LOCAL_0 0x400 66fb4d8502Sjsg #define CG_CGTT_LOCAL_1 0x401 67fb4d8502Sjsg 68fb4d8502Sjsg /* SMC IND registers */ 69fb4d8502Sjsg #define SMC_SYSCON_RESET_CNTL 0x80000000 70fb4d8502Sjsg # define RST_REG (1 << 0) 71fb4d8502Sjsg #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004 72fb4d8502Sjsg # define CK_DISABLE (1 << 0) 73fb4d8502Sjsg # define CKEN (1 << 24) 74fb4d8502Sjsg 75fb4d8502Sjsg #define VGA_HDP_CONTROL 0xCA 76fb4d8502Sjsg #define VGA_MEMORY_DISABLE (1 << 4) 77fb4d8502Sjsg 78fb4d8502Sjsg #define DCCG_DISP_SLOW_SELECT_REG 0x13F 79fb4d8502Sjsg #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0) 80fb4d8502Sjsg #define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0) 81fb4d8502Sjsg #define DCCG_DISP1_SLOW_SELECT_SHIFT 0 82fb4d8502Sjsg #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4) 83fb4d8502Sjsg #define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4) 84fb4d8502Sjsg #define DCCG_DISP2_SLOW_SELECT_SHIFT 4 85fb4d8502Sjsg 86fb4d8502Sjsg #define CG_SPLL_FUNC_CNTL 0x180 87fb4d8502Sjsg #define SPLL_RESET (1 << 0) 88fb4d8502Sjsg #define SPLL_SLEEP (1 << 1) 89fb4d8502Sjsg #define SPLL_BYPASS_EN (1 << 3) 90fb4d8502Sjsg #define SPLL_REF_DIV(x) ((x) << 4) 91fb4d8502Sjsg #define SPLL_REF_DIV_MASK (0x3f << 4) 92fb4d8502Sjsg #define SPLL_PDIV_A(x) ((x) << 20) 93fb4d8502Sjsg #define SPLL_PDIV_A_MASK (0x7f << 20) 94fb4d8502Sjsg #define SPLL_PDIV_A_SHIFT 20 95fb4d8502Sjsg #define CG_SPLL_FUNC_CNTL_2 0x181 96fb4d8502Sjsg #define SCLK_MUX_SEL(x) ((x) << 0) 97fb4d8502Sjsg #define SCLK_MUX_SEL_MASK (0x1ff << 0) 98fb4d8502Sjsg #define SPLL_CTLREQ_CHG (1 << 23) 99fb4d8502Sjsg #define SCLK_MUX_UPDATE (1 << 26) 100fb4d8502Sjsg #define CG_SPLL_FUNC_CNTL_3 0x182 101fb4d8502Sjsg #define SPLL_FB_DIV(x) ((x) << 0) 102fb4d8502Sjsg #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 103fb4d8502Sjsg #define SPLL_FB_DIV_SHIFT 0 104fb4d8502Sjsg #define SPLL_DITHEN (1 << 28) 105fb4d8502Sjsg #define CG_SPLL_FUNC_CNTL_4 0x183 106fb4d8502Sjsg 107fb4d8502Sjsg #define SPLL_STATUS 0x185 108fb4d8502Sjsg #define SPLL_CHG_STATUS (1 << 1) 109fb4d8502Sjsg #define SPLL_CNTL_MODE 0x186 110fb4d8502Sjsg #define SPLL_SW_DIR_CONTROL (1 << 0) 111fb4d8502Sjsg # define SPLL_REFCLK_SEL(x) ((x) << 26) 112fb4d8502Sjsg # define SPLL_REFCLK_SEL_MASK (3 << 26) 113fb4d8502Sjsg 114fb4d8502Sjsg #define CG_SPLL_SPREAD_SPECTRUM 0x188 115fb4d8502Sjsg #define SSEN (1 << 0) 116fb4d8502Sjsg #define CLK_S(x) ((x) << 4) 117fb4d8502Sjsg #define CLK_S_MASK (0xfff << 4) 118fb4d8502Sjsg #define CLK_S_SHIFT 4 119fb4d8502Sjsg #define CG_SPLL_SPREAD_SPECTRUM_2 0x189 120fb4d8502Sjsg #define CLK_V(x) ((x) << 0) 121fb4d8502Sjsg #define CLK_V_MASK (0x3ffffff << 0) 122fb4d8502Sjsg #define CLK_V_SHIFT 0 123fb4d8502Sjsg 124fb4d8502Sjsg #define CG_SPLL_AUTOSCALE_CNTL 0x18b 125fb4d8502Sjsg # define AUTOSCALE_ON_SS_CLEAR (1 << 9) 126fb4d8502Sjsg 127fb4d8502Sjsg /* discrete uvd clocks */ 128fb4d8502Sjsg #define CG_UPLL_FUNC_CNTL 0x18d 129fb4d8502Sjsg # define UPLL_RESET_MASK 0x00000001 130fb4d8502Sjsg # define UPLL_SLEEP_MASK 0x00000002 131fb4d8502Sjsg # define UPLL_BYPASS_EN_MASK 0x00000004 132fb4d8502Sjsg # define UPLL_CTLREQ_MASK 0x00000008 133fb4d8502Sjsg # define UPLL_VCO_MODE_MASK 0x00000600 134fb4d8502Sjsg # define UPLL_REF_DIV_MASK 0x003F0000 135fb4d8502Sjsg # define UPLL_CTLACK_MASK 0x40000000 136fb4d8502Sjsg # define UPLL_CTLACK2_MASK 0x80000000 137fb4d8502Sjsg #define CG_UPLL_FUNC_CNTL_2 0x18e 138fb4d8502Sjsg # define UPLL_PDIV_A(x) ((x) << 0) 139fb4d8502Sjsg # define UPLL_PDIV_A_MASK 0x0000007F 140fb4d8502Sjsg # define UPLL_PDIV_B(x) ((x) << 8) 141fb4d8502Sjsg # define UPLL_PDIV_B_MASK 0x00007F00 142fb4d8502Sjsg # define VCLK_SRC_SEL(x) ((x) << 20) 143fb4d8502Sjsg # define VCLK_SRC_SEL_MASK 0x01F00000 144fb4d8502Sjsg # define DCLK_SRC_SEL(x) ((x) << 25) 145fb4d8502Sjsg # define DCLK_SRC_SEL_MASK 0x3E000000 146fb4d8502Sjsg #define CG_UPLL_FUNC_CNTL_3 0x18f 147fb4d8502Sjsg # define UPLL_FB_DIV(x) ((x) << 0) 148fb4d8502Sjsg # define UPLL_FB_DIV_MASK 0x01FFFFFF 149fb4d8502Sjsg #define CG_UPLL_FUNC_CNTL_4 0x191 150fb4d8502Sjsg # define UPLL_SPARE_ISPARE9 0x00020000 151fb4d8502Sjsg #define CG_UPLL_FUNC_CNTL_5 0x192 152fb4d8502Sjsg # define RESET_ANTI_MUX_MASK 0x00000200 153fb4d8502Sjsg #define CG_UPLL_SPREAD_SPECTRUM 0x194 154fb4d8502Sjsg # define SSEN_MASK 0x00000001 155fb4d8502Sjsg 156fb4d8502Sjsg #define MPLL_BYPASSCLK_SEL 0x197 157fb4d8502Sjsg # define MPLL_CLKOUT_SEL(x) ((x) << 8) 158fb4d8502Sjsg # define MPLL_CLKOUT_SEL_MASK 0xFF00 159fb4d8502Sjsg 160fb4d8502Sjsg #define CG_CLKPIN_CNTL 0x198 161fb4d8502Sjsg # define XTALIN_DIVIDE (1 << 1) 162fb4d8502Sjsg # define BCLK_AS_XCLK (1 << 2) 163fb4d8502Sjsg #define CG_CLKPIN_CNTL_2 0x199 164fb4d8502Sjsg # define FORCE_BIF_REFCLK_EN (1 << 3) 165fb4d8502Sjsg # define MUX_TCLK_TO_XCLK (1 << 8) 166fb4d8502Sjsg 167fb4d8502Sjsg #define THM_CLK_CNTL 0x19b 168fb4d8502Sjsg # define CMON_CLK_SEL(x) ((x) << 0) 169fb4d8502Sjsg # define CMON_CLK_SEL_MASK 0xFF 170fb4d8502Sjsg # define TMON_CLK_SEL(x) ((x) << 8) 171fb4d8502Sjsg # define TMON_CLK_SEL_MASK 0xFF00 172fb4d8502Sjsg #define MISC_CLK_CNTL 0x19c 173fb4d8502Sjsg # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0) 174fb4d8502Sjsg # define DEEP_SLEEP_CLK_SEL_MASK 0xFF 175fb4d8502Sjsg # define ZCLK_SEL(x) ((x) << 8) 176fb4d8502Sjsg # define ZCLK_SEL_MASK 0xFF00 177fb4d8502Sjsg 178fb4d8502Sjsg #define CG_THERMAL_CTRL 0x1c0 179fb4d8502Sjsg #define DPM_EVENT_SRC(x) ((x) << 0) 180fb4d8502Sjsg #define DPM_EVENT_SRC_MASK (7 << 0) 181fb4d8502Sjsg #define DIG_THERM_DPM(x) ((x) << 14) 182fb4d8502Sjsg #define DIG_THERM_DPM_MASK 0x003FC000 183fb4d8502Sjsg #define DIG_THERM_DPM_SHIFT 14 184fb4d8502Sjsg #define CG_THERMAL_STATUS 0x1c1 185fb4d8502Sjsg #define FDO_PWM_DUTY(x) ((x) << 9) 186fb4d8502Sjsg #define FDO_PWM_DUTY_MASK (0xff << 9) 187fb4d8502Sjsg #define FDO_PWM_DUTY_SHIFT 9 188fb4d8502Sjsg #define CG_THERMAL_INT 0x1c2 189fb4d8502Sjsg #define DIG_THERM_INTH(x) ((x) << 8) 190fb4d8502Sjsg #define DIG_THERM_INTH_MASK 0x0000FF00 191fb4d8502Sjsg #define DIG_THERM_INTH_SHIFT 8 192fb4d8502Sjsg #define DIG_THERM_INTL(x) ((x) << 16) 193fb4d8502Sjsg #define DIG_THERM_INTL_MASK 0x00FF0000 194fb4d8502Sjsg #define DIG_THERM_INTL_SHIFT 16 195fb4d8502Sjsg #define THERM_INT_MASK_HIGH (1 << 24) 196fb4d8502Sjsg #define THERM_INT_MASK_LOW (1 << 25) 197fb4d8502Sjsg 198fb4d8502Sjsg #define CG_MULT_THERMAL_CTRL 0x1c4 199fb4d8502Sjsg #define TEMP_SEL(x) ((x) << 20) 200fb4d8502Sjsg #define TEMP_SEL_MASK (0xff << 20) 201fb4d8502Sjsg #define TEMP_SEL_SHIFT 20 202fb4d8502Sjsg #define CG_MULT_THERMAL_STATUS 0x1c5 203fb4d8502Sjsg #define ASIC_MAX_TEMP(x) ((x) << 0) 204fb4d8502Sjsg #define ASIC_MAX_TEMP_MASK 0x000001ff 205fb4d8502Sjsg #define ASIC_MAX_TEMP_SHIFT 0 206fb4d8502Sjsg #define CTF_TEMP(x) ((x) << 9) 207fb4d8502Sjsg #define CTF_TEMP_MASK 0x0003fe00 208fb4d8502Sjsg #define CTF_TEMP_SHIFT 9 209fb4d8502Sjsg 210fb4d8502Sjsg #define CG_FDO_CTRL0 0x1d5 211fb4d8502Sjsg #define FDO_STATIC_DUTY(x) ((x) << 0) 212fb4d8502Sjsg #define FDO_STATIC_DUTY_MASK 0x000000FF 213fb4d8502Sjsg #define FDO_STATIC_DUTY_SHIFT 0 214fb4d8502Sjsg #define CG_FDO_CTRL1 0x1d6 215fb4d8502Sjsg #define FMAX_DUTY100(x) ((x) << 0) 216fb4d8502Sjsg #define FMAX_DUTY100_MASK 0x000000FF 217fb4d8502Sjsg #define FMAX_DUTY100_SHIFT 0 218fb4d8502Sjsg #define CG_FDO_CTRL2 0x1d7 219fb4d8502Sjsg #define TMIN(x) ((x) << 0) 220fb4d8502Sjsg #define TMIN_MASK 0x000000FF 221fb4d8502Sjsg #define TMIN_SHIFT 0 222fb4d8502Sjsg #define FDO_PWM_MODE(x) ((x) << 11) 223fb4d8502Sjsg #define FDO_PWM_MODE_MASK (7 << 11) 224fb4d8502Sjsg #define FDO_PWM_MODE_SHIFT 11 225fb4d8502Sjsg #define TACH_PWM_RESP_RATE(x) ((x) << 25) 226fb4d8502Sjsg #define TACH_PWM_RESP_RATE_MASK (0x7f << 25) 227fb4d8502Sjsg #define TACH_PWM_RESP_RATE_SHIFT 25 228fb4d8502Sjsg 229fb4d8502Sjsg #define CG_TACH_CTRL 0x1dc 230fb4d8502Sjsg # define EDGE_PER_REV(x) ((x) << 0) 231fb4d8502Sjsg # define EDGE_PER_REV_MASK (0x7 << 0) 232fb4d8502Sjsg # define EDGE_PER_REV_SHIFT 0 233fb4d8502Sjsg # define TARGET_PERIOD(x) ((x) << 3) 234fb4d8502Sjsg # define TARGET_PERIOD_MASK 0xfffffff8 235fb4d8502Sjsg # define TARGET_PERIOD_SHIFT 3 236fb4d8502Sjsg #define CG_TACH_STATUS 0x1dd 237fb4d8502Sjsg # define TACH_PERIOD(x) ((x) << 0) 238fb4d8502Sjsg # define TACH_PERIOD_MASK 0xffffffff 239fb4d8502Sjsg # define TACH_PERIOD_SHIFT 0 240fb4d8502Sjsg 241fb4d8502Sjsg #define GENERAL_PWRMGT 0x1e0 242fb4d8502Sjsg # define GLOBAL_PWRMGT_EN (1 << 0) 243fb4d8502Sjsg # define STATIC_PM_EN (1 << 1) 244fb4d8502Sjsg # define THERMAL_PROTECTION_DIS (1 << 2) 245fb4d8502Sjsg # define THERMAL_PROTECTION_TYPE (1 << 3) 246fb4d8502Sjsg # define SW_SMIO_INDEX(x) ((x) << 6) 247fb4d8502Sjsg # define SW_SMIO_INDEX_MASK (1 << 6) 248fb4d8502Sjsg # define SW_SMIO_INDEX_SHIFT 6 249fb4d8502Sjsg # define VOLT_PWRMGT_EN (1 << 10) 250fb4d8502Sjsg # define DYN_SPREAD_SPECTRUM_EN (1 << 23) 251fb4d8502Sjsg #define CG_TPC 0x1e1 252fb4d8502Sjsg #define SCLK_PWRMGT_CNTL 0x1e2 253fb4d8502Sjsg # define SCLK_PWRMGT_OFF (1 << 0) 254fb4d8502Sjsg # define SCLK_LOW_D1 (1 << 1) 255fb4d8502Sjsg # define FIR_RESET (1 << 4) 256fb4d8502Sjsg # define FIR_FORCE_TREND_SEL (1 << 5) 257fb4d8502Sjsg # define FIR_TREND_MODE (1 << 6) 258fb4d8502Sjsg # define DYN_GFX_CLK_OFF_EN (1 << 7) 259fb4d8502Sjsg # define GFX_CLK_FORCE_ON (1 << 8) 260fb4d8502Sjsg # define GFX_CLK_REQUEST_OFF (1 << 9) 261fb4d8502Sjsg # define GFX_CLK_FORCE_OFF (1 << 10) 262fb4d8502Sjsg # define GFX_CLK_OFF_ACPI_D1 (1 << 11) 263fb4d8502Sjsg # define GFX_CLK_OFF_ACPI_D2 (1 << 12) 264fb4d8502Sjsg # define GFX_CLK_OFF_ACPI_D3 (1 << 13) 265fb4d8502Sjsg # define DYN_LIGHT_SLEEP_EN (1 << 14) 266fb4d8502Sjsg 267fb4d8502Sjsg #define TARGET_AND_CURRENT_PROFILE_INDEX 0x1e6 268fb4d8502Sjsg # define CURRENT_STATE_INDEX_MASK (0xf << 4) 269fb4d8502Sjsg # define CURRENT_STATE_INDEX_SHIFT 4 270fb4d8502Sjsg 271fb4d8502Sjsg #define CG_FTV 0x1ef 272fb4d8502Sjsg 273fb4d8502Sjsg #define CG_FFCT_0 0x1f0 274fb4d8502Sjsg # define UTC_0(x) ((x) << 0) 275fb4d8502Sjsg # define UTC_0_MASK (0x3ff << 0) 276fb4d8502Sjsg # define DTC_0(x) ((x) << 10) 277fb4d8502Sjsg # define DTC_0_MASK (0x3ff << 10) 278fb4d8502Sjsg 279fb4d8502Sjsg #define CG_BSP 0x1ff 280fb4d8502Sjsg # define BSP(x) ((x) << 0) 281fb4d8502Sjsg # define BSP_MASK (0xffff << 0) 282fb4d8502Sjsg # define BSU(x) ((x) << 16) 283fb4d8502Sjsg # define BSU_MASK (0xf << 16) 284fb4d8502Sjsg #define CG_AT 0x200 285fb4d8502Sjsg # define CG_R(x) ((x) << 0) 286fb4d8502Sjsg # define CG_R_MASK (0xffff << 0) 287fb4d8502Sjsg # define CG_L(x) ((x) << 16) 288fb4d8502Sjsg # define CG_L_MASK (0xffff << 16) 289fb4d8502Sjsg 290fb4d8502Sjsg #define CG_GIT 0x201 291fb4d8502Sjsg # define CG_GICST(x) ((x) << 0) 292fb4d8502Sjsg # define CG_GICST_MASK (0xffff << 0) 293fb4d8502Sjsg # define CG_GIPOT(x) ((x) << 16) 294fb4d8502Sjsg # define CG_GIPOT_MASK (0xffff << 16) 295fb4d8502Sjsg 296fb4d8502Sjsg #define CG_SSP 0x203 297fb4d8502Sjsg # define SST(x) ((x) << 0) 298fb4d8502Sjsg # define SST_MASK (0xffff << 0) 299fb4d8502Sjsg # define SSTU(x) ((x) << 16) 300fb4d8502Sjsg # define SSTU_MASK (0xf << 16) 301fb4d8502Sjsg 302fb4d8502Sjsg #define CG_DISPLAY_GAP_CNTL 0x20a 303fb4d8502Sjsg # define DISP1_GAP(x) ((x) << 0) 304fb4d8502Sjsg # define DISP1_GAP_MASK (3 << 0) 305fb4d8502Sjsg # define DISP2_GAP(x) ((x) << 2) 306fb4d8502Sjsg # define DISP2_GAP_MASK (3 << 2) 307fb4d8502Sjsg # define VBI_TIMER_COUNT(x) ((x) << 4) 308fb4d8502Sjsg # define VBI_TIMER_COUNT_MASK (0x3fff << 4) 309fb4d8502Sjsg # define VBI_TIMER_UNIT(x) ((x) << 20) 310fb4d8502Sjsg # define VBI_TIMER_UNIT_MASK (7 << 20) 311fb4d8502Sjsg # define DISP1_GAP_MCHG(x) ((x) << 24) 312fb4d8502Sjsg # define DISP1_GAP_MCHG_MASK (3 << 24) 313fb4d8502Sjsg # define DISP2_GAP_MCHG(x) ((x) << 26) 314fb4d8502Sjsg # define DISP2_GAP_MCHG_MASK (3 << 26) 315fb4d8502Sjsg 316fb4d8502Sjsg #define CG_ULV_CONTROL 0x21e 317fb4d8502Sjsg #define CG_ULV_PARAMETER 0x21f 318fb4d8502Sjsg 319fb4d8502Sjsg #define SMC_SCRATCH0 0x221 320fb4d8502Sjsg 321fb4d8502Sjsg #define CG_CAC_CTRL 0x22e 322fb4d8502Sjsg # define CAC_WINDOW(x) ((x) << 0) 323fb4d8502Sjsg # define CAC_WINDOW_MASK 0x00ffffff 324fb4d8502Sjsg 325fb4d8502Sjsg #define DMIF_ADDR_CONFIG 0x2F5 326fb4d8502Sjsg 327fb4d8502Sjsg #define DMIF_ADDR_CALC 0x300 328fb4d8502Sjsg 329fb4d8502Sjsg #define PIPE0_DMIF_BUFFER_CONTROL 0x0328 330fb4d8502Sjsg # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) 331fb4d8502Sjsg # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4) 332fb4d8502Sjsg 333fb4d8502Sjsg #define SRBM_STATUS 0x394 334fb4d8502Sjsg #define GRBM_RQ_PENDING (1 << 5) 335fb4d8502Sjsg #define VMC_BUSY (1 << 8) 336fb4d8502Sjsg #define MCB_BUSY (1 << 9) 337fb4d8502Sjsg #define MCB_NON_DISPLAY_BUSY (1 << 10) 338fb4d8502Sjsg #define MCC_BUSY (1 << 11) 339fb4d8502Sjsg #define MCD_BUSY (1 << 12) 340fb4d8502Sjsg #define SEM_BUSY (1 << 14) 341fb4d8502Sjsg #define IH_BUSY (1 << 17) 342fb4d8502Sjsg 343fb4d8502Sjsg #define SRBM_SOFT_RESET 0x398 344fb4d8502Sjsg #define SOFT_RESET_BIF (1 << 1) 345fb4d8502Sjsg #define SOFT_RESET_DC (1 << 5) 346fb4d8502Sjsg #define SOFT_RESET_DMA1 (1 << 6) 347fb4d8502Sjsg #define SOFT_RESET_GRBM (1 << 8) 348fb4d8502Sjsg #define SOFT_RESET_HDP (1 << 9) 349fb4d8502Sjsg #define SOFT_RESET_IH (1 << 10) 350fb4d8502Sjsg #define SOFT_RESET_MC (1 << 11) 351fb4d8502Sjsg #define SOFT_RESET_ROM (1 << 14) 352fb4d8502Sjsg #define SOFT_RESET_SEM (1 << 15) 353fb4d8502Sjsg #define SOFT_RESET_VMC (1 << 17) 354fb4d8502Sjsg #define SOFT_RESET_DMA (1 << 20) 355fb4d8502Sjsg #define SOFT_RESET_TST (1 << 21) 356fb4d8502Sjsg #define SOFT_RESET_REGBB (1 << 22) 357fb4d8502Sjsg #define SOFT_RESET_ORB (1 << 23) 358fb4d8502Sjsg 359fb4d8502Sjsg #define CC_SYS_RB_BACKEND_DISABLE 0x3A0 360fb4d8502Sjsg #define GC_USER_SYS_RB_BACKEND_DISABLE 0x3A1 361fb4d8502Sjsg 362fb4d8502Sjsg #define SRBM_READ_ERROR 0x3A6 363fb4d8502Sjsg #define SRBM_INT_CNTL 0x3A8 364fb4d8502Sjsg #define SRBM_INT_ACK 0x3AA 365fb4d8502Sjsg 366fb4d8502Sjsg #define SRBM_STATUS2 0x3B1 367fb4d8502Sjsg #define DMA_BUSY (1 << 5) 368fb4d8502Sjsg #define DMA1_BUSY (1 << 6) 369fb4d8502Sjsg 370fb4d8502Sjsg #define VM_L2_CNTL 0x500 371fb4d8502Sjsg #define ENABLE_L2_CACHE (1 << 0) 372fb4d8502Sjsg #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 373fb4d8502Sjsg #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 374fb4d8502Sjsg #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 375fb4d8502Sjsg #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 376fb4d8502Sjsg #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 377fb4d8502Sjsg #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 378fb4d8502Sjsg #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 379fb4d8502Sjsg #define VM_L2_CNTL2 0x501 380fb4d8502Sjsg #define INVALIDATE_ALL_L1_TLBS (1 << 0) 381fb4d8502Sjsg #define INVALIDATE_L2_CACHE (1 << 1) 382fb4d8502Sjsg #define INVALIDATE_CACHE_MODE(x) ((x) << 26) 383fb4d8502Sjsg #define INVALIDATE_PTE_AND_PDE_CACHES 0 384fb4d8502Sjsg #define INVALIDATE_ONLY_PTE_CACHES 1 385fb4d8502Sjsg #define INVALIDATE_ONLY_PDE_CACHES 2 386fb4d8502Sjsg #define VM_L2_CNTL3 0x502 387fb4d8502Sjsg #define BANK_SELECT(x) ((x) << 0) 388fb4d8502Sjsg #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 389fb4d8502Sjsg #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 390fb4d8502Sjsg #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 391fb4d8502Sjsg #define VM_L2_STATUS 0x503 392fb4d8502Sjsg #define L2_BUSY (1 << 0) 393fb4d8502Sjsg #define VM_CONTEXT0_CNTL 0x504 394fb4d8502Sjsg #define ENABLE_CONTEXT (1 << 0) 395fb4d8502Sjsg #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 396fb4d8502Sjsg #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 397fb4d8502Sjsg #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 398fb4d8502Sjsg #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 399fb4d8502Sjsg #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 400fb4d8502Sjsg #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 401fb4d8502Sjsg #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 402fb4d8502Sjsg #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 403fb4d8502Sjsg #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 404fb4d8502Sjsg #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 405fb4d8502Sjsg #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 406fb4d8502Sjsg #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 407fb4d8502Sjsg #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 408fb4d8502Sjsg #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24) 409fb4d8502Sjsg #define VM_CONTEXT1_CNTL 0x505 410fb4d8502Sjsg #define VM_CONTEXT0_CNTL2 0x50C 411fb4d8502Sjsg #define VM_CONTEXT1_CNTL2 0x50D 412fb4d8502Sjsg #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x50E 413fb4d8502Sjsg #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x50F 414fb4d8502Sjsg #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x510 415fb4d8502Sjsg #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x511 416fb4d8502Sjsg #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x512 417fb4d8502Sjsg #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x513 418fb4d8502Sjsg #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x514 419fb4d8502Sjsg #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x515 420fb4d8502Sjsg 421fb4d8502Sjsg #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x53f 422fb4d8502Sjsg #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x537 423fb4d8502Sjsg #define PROTECTIONS_MASK (0xf << 0) 424fb4d8502Sjsg #define PROTECTIONS_SHIFT 0 425fb4d8502Sjsg /* bit 0: range 426fb4d8502Sjsg * bit 1: pde0 427fb4d8502Sjsg * bit 2: valid 428fb4d8502Sjsg * bit 3: read 429fb4d8502Sjsg * bit 4: write 430fb4d8502Sjsg */ 431fb4d8502Sjsg #define MEMORY_CLIENT_ID_MASK (0xff << 12) 432fb4d8502Sjsg #define MEMORY_CLIENT_ID_SHIFT 12 433fb4d8502Sjsg #define MEMORY_CLIENT_RW_MASK (1 << 24) 434fb4d8502Sjsg #define MEMORY_CLIENT_RW_SHIFT 24 435fb4d8502Sjsg #define FAULT_VMID_MASK (0xf << 25) 436fb4d8502Sjsg #define FAULT_VMID_SHIFT 25 437fb4d8502Sjsg 438fb4d8502Sjsg #define VM_INVALIDATE_REQUEST 0x51E 439fb4d8502Sjsg #define VM_INVALIDATE_RESPONSE 0x51F 440fb4d8502Sjsg 441fb4d8502Sjsg #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x546 442fb4d8502Sjsg #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x547 443fb4d8502Sjsg 444fb4d8502Sjsg #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54F 445fb4d8502Sjsg #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x550 446fb4d8502Sjsg #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x551 447fb4d8502Sjsg #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x552 448fb4d8502Sjsg #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x553 449fb4d8502Sjsg #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x554 450fb4d8502Sjsg #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x555 451fb4d8502Sjsg #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x556 452fb4d8502Sjsg #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x557 453fb4d8502Sjsg #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x558 454fb4d8502Sjsg 455fb4d8502Sjsg #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x55F 456fb4d8502Sjsg #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x560 457fb4d8502Sjsg 458fb4d8502Sjsg #define VM_L2_CG 0x570 459fb4d8502Sjsg #define MC_CG_ENABLE (1 << 18) 460fb4d8502Sjsg #define MC_LS_ENABLE (1 << 19) 461fb4d8502Sjsg 462fb4d8502Sjsg #define MC_SHARED_CHMAP 0x801 463fb4d8502Sjsg #define NOOFCHAN_SHIFT 12 464fb4d8502Sjsg #define NOOFCHAN_MASK 0x0000f000 465fb4d8502Sjsg #define MC_SHARED_CHREMAP 0x802 466fb4d8502Sjsg 467fb4d8502Sjsg #define MC_VM_FB_LOCATION 0x809 468fb4d8502Sjsg #define MC_VM_AGP_TOP 0x80A 469fb4d8502Sjsg #define MC_VM_AGP_BOT 0x80B 470fb4d8502Sjsg #define MC_VM_AGP_BASE 0x80C 471fb4d8502Sjsg #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80D 472fb4d8502Sjsg #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80E 473fb4d8502Sjsg #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80F 474fb4d8502Sjsg 475fb4d8502Sjsg #define MC_VM_MX_L1_TLB_CNTL 0x819 476fb4d8502Sjsg #define ENABLE_L1_TLB (1 << 0) 477fb4d8502Sjsg #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 478fb4d8502Sjsg #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 479fb4d8502Sjsg #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 480fb4d8502Sjsg #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 481fb4d8502Sjsg #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 482fb4d8502Sjsg #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 483fb4d8502Sjsg #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 484fb4d8502Sjsg 485fb4d8502Sjsg #define MC_SHARED_BLACKOUT_CNTL 0x82B 486fb4d8502Sjsg 487fb4d8502Sjsg #define MC_HUB_MISC_HUB_CG 0x82E 488fb4d8502Sjsg #define MC_HUB_MISC_VM_CG 0x82F 489fb4d8502Sjsg 490fb4d8502Sjsg #define MC_HUB_MISC_SIP_CG 0x830 491fb4d8502Sjsg 492fb4d8502Sjsg #define MC_XPB_CLK_GAT 0x91E 493fb4d8502Sjsg 494fb4d8502Sjsg #define MC_CITF_MISC_RD_CG 0x992 495fb4d8502Sjsg #define MC_CITF_MISC_WR_CG 0x993 496fb4d8502Sjsg #define MC_CITF_MISC_VM_CG 0x994 497fb4d8502Sjsg 498fb4d8502Sjsg #define MC_ARB_RAMCFG 0x9D8 499fb4d8502Sjsg #define NOOFBANK_SHIFT 0 500fb4d8502Sjsg #define NOOFBANK_MASK 0x00000003 501fb4d8502Sjsg #define NOOFRANK_SHIFT 2 502fb4d8502Sjsg #define NOOFRANK_MASK 0x00000004 503fb4d8502Sjsg #define NOOFROWS_SHIFT 3 504fb4d8502Sjsg #define NOOFROWS_MASK 0x00000038 505fb4d8502Sjsg #define NOOFCOLS_SHIFT 6 506fb4d8502Sjsg #define NOOFCOLS_MASK 0x000000C0 507fb4d8502Sjsg #define CHANSIZE_SHIFT 8 508fb4d8502Sjsg #define CHANSIZE_MASK 0x00000100 509fb4d8502Sjsg #define CHANSIZE_OVERRIDE (1 << 11) 510fb4d8502Sjsg #define NOOFGROUPS_SHIFT 12 511fb4d8502Sjsg #define NOOFGROUPS_MASK 0x00001000 512fb4d8502Sjsg 513fb4d8502Sjsg #define MC_ARB_DRAM_TIMING 0x9DD 514fb4d8502Sjsg #define MC_ARB_DRAM_TIMING2 0x9DE 515fb4d8502Sjsg 516fb4d8502Sjsg #define MC_ARB_BURST_TIME 0xA02 517fb4d8502Sjsg #define STATE0(x) ((x) << 0) 518fb4d8502Sjsg #define STATE0_MASK (0x1f << 0) 519fb4d8502Sjsg #define STATE0_SHIFT 0 520fb4d8502Sjsg #define STATE1(x) ((x) << 5) 521fb4d8502Sjsg #define STATE1_MASK (0x1f << 5) 522fb4d8502Sjsg #define STATE1_SHIFT 5 523fb4d8502Sjsg #define STATE2(x) ((x) << 10) 524fb4d8502Sjsg #define STATE2_MASK (0x1f << 10) 525fb4d8502Sjsg #define STATE2_SHIFT 10 526fb4d8502Sjsg #define STATE3(x) ((x) << 15) 527fb4d8502Sjsg #define STATE3_MASK (0x1f << 15) 528fb4d8502Sjsg #define STATE3_SHIFT 15 529fb4d8502Sjsg 530fb4d8502Sjsg #define MC_SEQ_TRAIN_WAKEUP_CNTL 0xA3A 531fb4d8502Sjsg #define TRAIN_DONE_D0 (1 << 30) 532fb4d8502Sjsg #define TRAIN_DONE_D1 (1 << 31) 533fb4d8502Sjsg 534fb4d8502Sjsg #define MC_SEQ_SUP_CNTL 0xA32 535fb4d8502Sjsg #define RUN_MASK (1 << 0) 536fb4d8502Sjsg #define MC_SEQ_SUP_PGM 0xA33 537fb4d8502Sjsg #define MC_PMG_AUTO_CMD 0xA34 538fb4d8502Sjsg 539fb4d8502Sjsg #define MC_IO_PAD_CNTL_D0 0xA74 540fb4d8502Sjsg #define MEM_FALL_OUT_CMD (1 << 8) 541fb4d8502Sjsg 542fb4d8502Sjsg #define MC_SEQ_RAS_TIMING 0xA28 543fb4d8502Sjsg #define MC_SEQ_CAS_TIMING 0xA29 544fb4d8502Sjsg #define MC_SEQ_MISC_TIMING 0xA2A 545fb4d8502Sjsg #define MC_SEQ_MISC_TIMING2 0xA2B 546fb4d8502Sjsg #define MC_SEQ_PMG_TIMING 0xA2C 547fb4d8502Sjsg #define MC_SEQ_RD_CTL_D0 0xA2D 548fb4d8502Sjsg #define MC_SEQ_RD_CTL_D1 0xA2E 549fb4d8502Sjsg #define MC_SEQ_WR_CTL_D0 0xA2F 550fb4d8502Sjsg #define MC_SEQ_WR_CTL_D1 0xA30 551fb4d8502Sjsg 552fb4d8502Sjsg #define MC_SEQ_MISC0 0xA80 553fb4d8502Sjsg #define MC_SEQ_MISC0_VEN_ID_SHIFT 8 554fb4d8502Sjsg #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00 555fb4d8502Sjsg #define MC_SEQ_MISC0_VEN_ID_VALUE 3 556fb4d8502Sjsg #define MC_SEQ_MISC0_REV_ID_SHIFT 12 557fb4d8502Sjsg #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000 558fb4d8502Sjsg #define MC_SEQ_MISC0_REV_ID_VALUE 1 559fb4d8502Sjsg #define MC_SEQ_MISC0_GDDR5_SHIFT 28 560fb4d8502Sjsg #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 561fb4d8502Sjsg #define MC_SEQ_MISC0_GDDR5_VALUE 5 562fb4d8502Sjsg #define MC_SEQ_MISC1 0xA81 563fb4d8502Sjsg #define MC_SEQ_RESERVE_M 0xA82 564fb4d8502Sjsg #define MC_PMG_CMD_EMRS 0xA83 565fb4d8502Sjsg 566fb4d8502Sjsg #define MC_SEQ_IO_DEBUG_INDEX 0xA91 567fb4d8502Sjsg #define MC_SEQ_IO_DEBUG_DATA 0xA92 568fb4d8502Sjsg 569fb4d8502Sjsg #define MC_SEQ_MISC5 0xA95 570fb4d8502Sjsg #define MC_SEQ_MISC6 0xA96 571fb4d8502Sjsg 572fb4d8502Sjsg #define MC_SEQ_MISC7 0xA99 573fb4d8502Sjsg 574fb4d8502Sjsg #define MC_SEQ_RAS_TIMING_LP 0xA9B 575fb4d8502Sjsg #define MC_SEQ_CAS_TIMING_LP 0xA9C 576fb4d8502Sjsg #define MC_SEQ_MISC_TIMING_LP 0xA9D 577fb4d8502Sjsg #define MC_SEQ_MISC_TIMING2_LP 0xA9E 578fb4d8502Sjsg #define MC_SEQ_WR_CTL_D0_LP 0xA9F 579fb4d8502Sjsg #define MC_SEQ_WR_CTL_D1_LP 0xAA0 580fb4d8502Sjsg #define MC_SEQ_PMG_CMD_EMRS_LP 0xAA1 581fb4d8502Sjsg #define MC_SEQ_PMG_CMD_MRS_LP 0xAA2 582fb4d8502Sjsg 583fb4d8502Sjsg #define MC_PMG_CMD_MRS 0xAAB 584fb4d8502Sjsg 585fb4d8502Sjsg #define MC_SEQ_RD_CTL_D0_LP 0xAC7 586fb4d8502Sjsg #define MC_SEQ_RD_CTL_D1_LP 0xAC8 587fb4d8502Sjsg 588fb4d8502Sjsg #define MC_PMG_CMD_MRS1 0xAD1 589fb4d8502Sjsg #define MC_SEQ_PMG_CMD_MRS1_LP 0xAD2 590fb4d8502Sjsg #define MC_SEQ_PMG_TIMING_LP 0xAD3 591fb4d8502Sjsg 592fb4d8502Sjsg #define MC_SEQ_WR_CTL_2 0xAD5 593fb4d8502Sjsg #define MC_SEQ_WR_CTL_2_LP 0xAD6 594fb4d8502Sjsg #define MC_PMG_CMD_MRS2 0xAD7 595fb4d8502Sjsg #define MC_SEQ_PMG_CMD_MRS2_LP 0xAD8 596fb4d8502Sjsg 597fb4d8502Sjsg #define MCLK_PWRMGT_CNTL 0xAE8 598fb4d8502Sjsg # define DLL_SPEED(x) ((x) << 0) 599fb4d8502Sjsg # define DLL_SPEED_MASK (0x1f << 0) 600fb4d8502Sjsg # define DLL_READY (1 << 6) 601fb4d8502Sjsg # define MC_INT_CNTL (1 << 7) 602fb4d8502Sjsg # define MRDCK0_PDNB (1 << 8) 603fb4d8502Sjsg # define MRDCK1_PDNB (1 << 9) 604fb4d8502Sjsg # define MRDCK0_RESET (1 << 16) 605fb4d8502Sjsg # define MRDCK1_RESET (1 << 17) 606fb4d8502Sjsg # define DLL_READY_READ (1 << 24) 607fb4d8502Sjsg #define DLL_CNTL 0xAE9 608fb4d8502Sjsg # define MRDCK0_BYPASS (1 << 24) 609fb4d8502Sjsg # define MRDCK1_BYPASS (1 << 25) 610fb4d8502Sjsg 611fb4d8502Sjsg #define MPLL_CNTL_MODE 0xAEC 612fb4d8502Sjsg # define MPLL_MCLK_SEL (1 << 11) 613fb4d8502Sjsg #define MPLL_FUNC_CNTL 0xAED 614fb4d8502Sjsg #define BWCTRL(x) ((x) << 20) 615fb4d8502Sjsg #define BWCTRL_MASK (0xff << 20) 616fb4d8502Sjsg #define MPLL_FUNC_CNTL_1 0xAEE 617fb4d8502Sjsg #define VCO_MODE(x) ((x) << 0) 618fb4d8502Sjsg #define VCO_MODE_MASK (3 << 0) 619fb4d8502Sjsg #define CLKFRAC(x) ((x) << 4) 620fb4d8502Sjsg #define CLKFRAC_MASK (0xfff << 4) 621fb4d8502Sjsg #define CLKF(x) ((x) << 16) 622fb4d8502Sjsg #define CLKF_MASK (0xfff << 16) 623fb4d8502Sjsg #define MPLL_FUNC_CNTL_2 0xAEF 624fb4d8502Sjsg #define MPLL_AD_FUNC_CNTL 0xAF0 625fb4d8502Sjsg #define YCLK_POST_DIV(x) ((x) << 0) 626fb4d8502Sjsg #define YCLK_POST_DIV_MASK (7 << 0) 627fb4d8502Sjsg #define MPLL_DQ_FUNC_CNTL 0xAF1 628fb4d8502Sjsg #define YCLK_SEL(x) ((x) << 4) 629fb4d8502Sjsg #define YCLK_SEL_MASK (1 << 4) 630fb4d8502Sjsg 631fb4d8502Sjsg #define MPLL_SS1 0xAF3 632fb4d8502Sjsg #define CLKV(x) ((x) << 0) 633fb4d8502Sjsg #define CLKV_MASK (0x3ffffff << 0) 634fb4d8502Sjsg #define MPLL_SS2 0xAF4 635fb4d8502Sjsg #define CLKS(x) ((x) << 0) 636fb4d8502Sjsg #define CLKS_MASK (0xfff << 0) 637fb4d8502Sjsg 638fb4d8502Sjsg #define HDP_HOST_PATH_CNTL 0xB00 639fb4d8502Sjsg #define CLOCK_GATING_DIS (1 << 23) 640fb4d8502Sjsg #define HDP_NONSURFACE_BASE 0xB01 641fb4d8502Sjsg #define HDP_NONSURFACE_INFO 0xB02 642fb4d8502Sjsg #define HDP_NONSURFACE_SIZE 0xB03 643fb4d8502Sjsg 644fb4d8502Sjsg #define HDP_DEBUG0 0xBCC 645fb4d8502Sjsg 646fb4d8502Sjsg #define HDP_ADDR_CONFIG 0xBD2 647fb4d8502Sjsg #define HDP_MISC_CNTL 0xBD3 648fb4d8502Sjsg #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 649fb4d8502Sjsg #define HDP_MEM_POWER_LS 0xBD4 650fb4d8502Sjsg #define HDP_LS_ENABLE (1 << 0) 651fb4d8502Sjsg 652fb4d8502Sjsg #define ATC_MISC_CG 0xCD4 653fb4d8502Sjsg 654fb4d8502Sjsg #define IH_RB_CNTL 0xF80 655fb4d8502Sjsg # define IH_RB_ENABLE (1 << 0) 656fb4d8502Sjsg # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 657fb4d8502Sjsg # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 658fb4d8502Sjsg # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 659fb4d8502Sjsg # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 660fb4d8502Sjsg # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 661fb4d8502Sjsg # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 662fb4d8502Sjsg #define IH_RB_BASE 0xF81 663fb4d8502Sjsg #define IH_RB_RPTR 0xF82 664fb4d8502Sjsg #define IH_RB_WPTR 0xF83 665fb4d8502Sjsg # define RB_OVERFLOW (1 << 0) 666fb4d8502Sjsg # define WPTR_OFFSET_MASK 0x3fffc 667fb4d8502Sjsg #define IH_RB_WPTR_ADDR_HI 0xF84 668fb4d8502Sjsg #define IH_RB_WPTR_ADDR_LO 0xF85 669fb4d8502Sjsg #define IH_CNTL 0xF86 670fb4d8502Sjsg # define ENABLE_INTR (1 << 0) 671fb4d8502Sjsg # define IH_MC_SWAP(x) ((x) << 1) 672fb4d8502Sjsg # define IH_MC_SWAP_NONE 0 673fb4d8502Sjsg # define IH_MC_SWAP_16BIT 1 674fb4d8502Sjsg # define IH_MC_SWAP_32BIT 2 675fb4d8502Sjsg # define IH_MC_SWAP_64BIT 3 676fb4d8502Sjsg # define RPTR_REARM (1 << 4) 677fb4d8502Sjsg # define MC_WRREQ_CREDIT(x) ((x) << 15) 678fb4d8502Sjsg # define MC_WR_CLEAN_CNT(x) ((x) << 20) 679fb4d8502Sjsg # define MC_VMID(x) ((x) << 25) 680fb4d8502Sjsg 681fb4d8502Sjsg #define CONFIG_MEMSIZE 0x150A 682fb4d8502Sjsg 683fb4d8502Sjsg #define INTERRUPT_CNTL 0x151A 684fb4d8502Sjsg # define IH_DUMMY_RD_OVERRIDE (1 << 0) 685fb4d8502Sjsg # define IH_DUMMY_RD_EN (1 << 1) 686fb4d8502Sjsg # define IH_REQ_NONSNOOP_EN (1 << 3) 687fb4d8502Sjsg # define GEN_IH_INT_EN (1 << 8) 688fb4d8502Sjsg #define INTERRUPT_CNTL2 0x151B 689fb4d8502Sjsg 690fb4d8502Sjsg #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x1520 691fb4d8502Sjsg 692fb4d8502Sjsg #define BIF_FB_EN 0x1524 693fb4d8502Sjsg #define FB_READ_EN (1 << 0) 694fb4d8502Sjsg #define FB_WRITE_EN (1 << 1) 695fb4d8502Sjsg 696fb4d8502Sjsg #define HDP_REG_COHERENCY_FLUSH_CNTL 0x1528 697fb4d8502Sjsg 698fb4d8502Sjsg /* DCE6 ELD audio interface */ 699fb4d8502Sjsg #define AZ_F0_CODEC_ENDPOINT_INDEX 0x1780 700fb4d8502Sjsg # define AZ_ENDPOINT_REG_INDEX(x) (((x) & 0xff) << 0) 701fb4d8502Sjsg # define AZ_ENDPOINT_REG_WRITE_EN (1 << 8) 702fb4d8502Sjsg #define AZ_F0_CODEC_ENDPOINT_DATA 0x1781 703fb4d8502Sjsg 704fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25 705fb4d8502Sjsg #define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0) 706fb4d8502Sjsg #define SPEAKER_ALLOCATION_MASK (0x7f << 0) 707fb4d8502Sjsg #define SPEAKER_ALLOCATION_SHIFT 0 708fb4d8502Sjsg #define HDMI_CONNECTION (1 << 16) 709fb4d8502Sjsg #define DP_CONNECTION (1 << 17) 710fb4d8502Sjsg 711fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 /* LPCM */ 712fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 /* AC3 */ 713fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2A /* MPEG1 */ 714fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2B /* MP3 */ 715fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2C /* MPEG2 */ 716fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2D /* AAC */ 717fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2E /* DTS */ 718fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2F /* ATRAC */ 719fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 /* one bit audio - leave at 0 (default) */ 720fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 /* Dolby Digital */ 721fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 /* DTS-HD */ 722fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 /* MAT-MLP */ 723fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 /* DTS */ 724fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 /* WMA Pro */ 725fb4d8502Sjsg # define MAX_CHANNELS(x) (((x) & 0x7) << 0) 726fb4d8502Sjsg /* max channels minus one. 7 = 8 channels */ 727fb4d8502Sjsg # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) 728fb4d8502Sjsg # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) 729fb4d8502Sjsg # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ 730fb4d8502Sjsg /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO 731fb4d8502Sjsg * bit0 = 32 kHz 732fb4d8502Sjsg * bit1 = 44.1 kHz 733fb4d8502Sjsg * bit2 = 48 kHz 734fb4d8502Sjsg * bit3 = 88.2 kHz 735fb4d8502Sjsg * bit4 = 96 kHz 736fb4d8502Sjsg * bit5 = 176.4 kHz 737fb4d8502Sjsg * bit6 = 192 kHz 738fb4d8502Sjsg */ 739fb4d8502Sjsg 740fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37 741fb4d8502Sjsg # define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0) 742fb4d8502Sjsg # define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8) 743fb4d8502Sjsg /* VIDEO_LIPSYNC, AUDIO_LIPSYNC 744fb4d8502Sjsg * 0 = invalid 745fb4d8502Sjsg * x = legal delay value 746fb4d8502Sjsg * 255 = sync not supported 747fb4d8502Sjsg */ 748fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38 749fb4d8502Sjsg # define HBR_CAPABLE (1 << 0) /* enabled by default */ 750fb4d8502Sjsg 751fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a 752fb4d8502Sjsg # define MANUFACTURER_ID(x) (((x) & 0xffff) << 0) 753fb4d8502Sjsg # define PRODUCT_ID(x) (((x) & 0xffff) << 16) 754fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b 755fb4d8502Sjsg # define SINK_DESCRIPTION_LEN(x) (((x) & 0xff) << 0) 756fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c 757fb4d8502Sjsg # define PORT_ID0(x) (((x) & 0xffffffff) << 0) 758fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d 759fb4d8502Sjsg # define PORT_ID1(x) (((x) & 0xffffffff) << 0) 760fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e 761fb4d8502Sjsg # define DESCRIPTION0(x) (((x) & 0xff) << 0) 762fb4d8502Sjsg # define DESCRIPTION1(x) (((x) & 0xff) << 8) 763fb4d8502Sjsg # define DESCRIPTION2(x) (((x) & 0xff) << 16) 764fb4d8502Sjsg # define DESCRIPTION3(x) (((x) & 0xff) << 24) 765fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f 766fb4d8502Sjsg # define DESCRIPTION4(x) (((x) & 0xff) << 0) 767fb4d8502Sjsg # define DESCRIPTION5(x) (((x) & 0xff) << 8) 768fb4d8502Sjsg # define DESCRIPTION6(x) (((x) & 0xff) << 16) 769fb4d8502Sjsg # define DESCRIPTION7(x) (((x) & 0xff) << 24) 770fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40 771fb4d8502Sjsg # define DESCRIPTION8(x) (((x) & 0xff) << 0) 772fb4d8502Sjsg # define DESCRIPTION9(x) (((x) & 0xff) << 8) 773fb4d8502Sjsg # define DESCRIPTION10(x) (((x) & 0xff) << 16) 774fb4d8502Sjsg # define DESCRIPTION11(x) (((x) & 0xff) << 24) 775fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41 776fb4d8502Sjsg # define DESCRIPTION12(x) (((x) & 0xff) << 0) 777fb4d8502Sjsg # define DESCRIPTION13(x) (((x) & 0xff) << 8) 778fb4d8502Sjsg # define DESCRIPTION14(x) (((x) & 0xff) << 16) 779fb4d8502Sjsg # define DESCRIPTION15(x) (((x) & 0xff) << 24) 780fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42 781fb4d8502Sjsg # define DESCRIPTION16(x) (((x) & 0xff) << 0) 782fb4d8502Sjsg # define DESCRIPTION17(x) (((x) & 0xff) << 8) 783fb4d8502Sjsg 784fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 785fb4d8502Sjsg # define AUDIO_ENABLED (1 << 31) 786fb4d8502Sjsg 787fb4d8502Sjsg #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 788fb4d8502Sjsg #define PORT_CONNECTIVITY_MASK (3 << 30) 789fb4d8502Sjsg #define PORT_CONNECTIVITY_SHIFT 30 790fb4d8502Sjsg 791fb4d8502Sjsg #define DC_LB_MEMORY_SPLIT 0x1AC3 792fb4d8502Sjsg #define DC_LB_MEMORY_CONFIG(x) ((x) << 20) 793fb4d8502Sjsg 794fb4d8502Sjsg #define PRIORITY_A_CNT 0x1AC6 795fb4d8502Sjsg #define PRIORITY_MARK_MASK 0x7fff 796fb4d8502Sjsg #define PRIORITY_OFF (1 << 16) 797fb4d8502Sjsg #define PRIORITY_ALWAYS_ON (1 << 20) 798fb4d8502Sjsg #define PRIORITY_B_CNT 0x1AC7 799fb4d8502Sjsg 800fb4d8502Sjsg #define DPG_PIPE_ARBITRATION_CONTROL3 0x1B32 801fb4d8502Sjsg # define LATENCY_WATERMARK_MASK(x) ((x) << 16) 802fb4d8502Sjsg #define DPG_PIPE_LATENCY_CONTROL 0x1B33 803fb4d8502Sjsg # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 804fb4d8502Sjsg # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 805fb4d8502Sjsg 806fb4d8502Sjsg /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 807fb4d8502Sjsg #define VLINE_STATUS 0x1AEE 808fb4d8502Sjsg # define VLINE_OCCURRED (1 << 0) 809fb4d8502Sjsg # define VLINE_ACK (1 << 4) 810fb4d8502Sjsg # define VLINE_STAT (1 << 12) 811fb4d8502Sjsg # define VLINE_INTERRUPT (1 << 16) 812fb4d8502Sjsg # define VLINE_INTERRUPT_TYPE (1 << 17) 813fb4d8502Sjsg /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 814fb4d8502Sjsg #define VBLANK_STATUS 0x1AEF 815fb4d8502Sjsg # define VBLANK_OCCURRED (1 << 0) 816fb4d8502Sjsg # define VBLANK_ACK (1 << 4) 817fb4d8502Sjsg # define VBLANK_STAT (1 << 12) 818fb4d8502Sjsg # define VBLANK_INTERRUPT (1 << 16) 819fb4d8502Sjsg # define VBLANK_INTERRUPT_TYPE (1 << 17) 820fb4d8502Sjsg 821fb4d8502Sjsg /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 822fb4d8502Sjsg #define INT_MASK 0x1AD0 823fb4d8502Sjsg # define VBLANK_INT_MASK (1 << 0) 824fb4d8502Sjsg # define VLINE_INT_MASK (1 << 4) 825fb4d8502Sjsg 826fb4d8502Sjsg #define DISP_INTERRUPT_STATUS 0x183D 827fb4d8502Sjsg # define LB_D1_VLINE_INTERRUPT (1 << 2) 828fb4d8502Sjsg # define LB_D1_VBLANK_INTERRUPT (1 << 3) 829fb4d8502Sjsg # define DC_HPD1_INTERRUPT (1 << 17) 830fb4d8502Sjsg # define DC_HPD1_RX_INTERRUPT (1 << 18) 831fb4d8502Sjsg # define DACA_AUTODETECT_INTERRUPT (1 << 22) 832fb4d8502Sjsg # define DACB_AUTODETECT_INTERRUPT (1 << 23) 833fb4d8502Sjsg # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 834fb4d8502Sjsg # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 835fb4d8502Sjsg #define DISP_INTERRUPT_STATUS_CONTINUE 0x183E 836fb4d8502Sjsg # define LB_D2_VLINE_INTERRUPT (1 << 2) 837fb4d8502Sjsg # define LB_D2_VBLANK_INTERRUPT (1 << 3) 838fb4d8502Sjsg # define DC_HPD2_INTERRUPT (1 << 17) 839fb4d8502Sjsg # define DC_HPD2_RX_INTERRUPT (1 << 18) 840fb4d8502Sjsg # define DISP_TIMER_INTERRUPT (1 << 24) 841fb4d8502Sjsg #define DISP_INTERRUPT_STATUS_CONTINUE2 0x183F 842fb4d8502Sjsg # define LB_D3_VLINE_INTERRUPT (1 << 2) 843fb4d8502Sjsg # define LB_D3_VBLANK_INTERRUPT (1 << 3) 844fb4d8502Sjsg # define DC_HPD3_INTERRUPT (1 << 17) 845fb4d8502Sjsg # define DC_HPD3_RX_INTERRUPT (1 << 18) 846fb4d8502Sjsg #define DISP_INTERRUPT_STATUS_CONTINUE3 0x1840 847fb4d8502Sjsg # define LB_D4_VLINE_INTERRUPT (1 << 2) 848fb4d8502Sjsg # define LB_D4_VBLANK_INTERRUPT (1 << 3) 849fb4d8502Sjsg # define DC_HPD4_INTERRUPT (1 << 17) 850fb4d8502Sjsg # define DC_HPD4_RX_INTERRUPT (1 << 18) 851fb4d8502Sjsg #define DISP_INTERRUPT_STATUS_CONTINUE4 0x1853 852fb4d8502Sjsg # define LB_D5_VLINE_INTERRUPT (1 << 2) 853fb4d8502Sjsg # define LB_D5_VBLANK_INTERRUPT (1 << 3) 854fb4d8502Sjsg # define DC_HPD5_INTERRUPT (1 << 17) 855fb4d8502Sjsg # define DC_HPD5_RX_INTERRUPT (1 << 18) 856fb4d8502Sjsg #define DISP_INTERRUPT_STATUS_CONTINUE5 0x1854 857fb4d8502Sjsg # define LB_D6_VLINE_INTERRUPT (1 << 2) 858fb4d8502Sjsg # define LB_D6_VBLANK_INTERRUPT (1 << 3) 859fb4d8502Sjsg # define DC_HPD6_INTERRUPT (1 << 17) 860fb4d8502Sjsg # define DC_HPD6_RX_INTERRUPT (1 << 18) 861fb4d8502Sjsg 862fb4d8502Sjsg /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 863fb4d8502Sjsg #define GRPH_INT_STATUS 0x1A16 864fb4d8502Sjsg # define GRPH_PFLIP_INT_OCCURRED (1 << 0) 865fb4d8502Sjsg # define GRPH_PFLIP_INT_CLEAR (1 << 8) 866fb4d8502Sjsg /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 867fb4d8502Sjsg #define GRPH_INT_CONTROL 0x1A17 868fb4d8502Sjsg # define GRPH_PFLIP_INT_MASK (1 << 0) 869fb4d8502Sjsg # define GRPH_PFLIP_INT_TYPE (1 << 8) 870fb4d8502Sjsg 871fb4d8502Sjsg #define DAC_AUTODETECT_INT_CONTROL 0x19F2 872fb4d8502Sjsg 873fb4d8502Sjsg #define DC_HPD1_INT_STATUS 0x1807 874fb4d8502Sjsg #define DC_HPD2_INT_STATUS 0x180A 875fb4d8502Sjsg #define DC_HPD3_INT_STATUS 0x180D 876fb4d8502Sjsg #define DC_HPD4_INT_STATUS 0x1810 877fb4d8502Sjsg #define DC_HPD5_INT_STATUS 0x1813 878fb4d8502Sjsg #define DC_HPD6_INT_STATUS 0x1816 879fb4d8502Sjsg # define DC_HPDx_INT_STATUS (1 << 0) 880fb4d8502Sjsg # define DC_HPDx_SENSE (1 << 1) 881fb4d8502Sjsg # define DC_HPDx_RX_INT_STATUS (1 << 8) 882fb4d8502Sjsg 883fb4d8502Sjsg #define DC_HPD1_INT_CONTROL 0x1808 884fb4d8502Sjsg #define DC_HPD2_INT_CONTROL 0x180B 885fb4d8502Sjsg #define DC_HPD3_INT_CONTROL 0x180E 886fb4d8502Sjsg #define DC_HPD4_INT_CONTROL 0x1811 887fb4d8502Sjsg #define DC_HPD5_INT_CONTROL 0x1814 888fb4d8502Sjsg #define DC_HPD6_INT_CONTROL 0x1817 889fb4d8502Sjsg # define DC_HPDx_INT_ACK (1 << 0) 890fb4d8502Sjsg # define DC_HPDx_INT_POLARITY (1 << 8) 891fb4d8502Sjsg # define DC_HPDx_INT_EN (1 << 16) 892fb4d8502Sjsg # define DC_HPDx_RX_INT_ACK (1 << 20) 893fb4d8502Sjsg # define DC_HPDx_RX_INT_EN (1 << 24) 894fb4d8502Sjsg 895fb4d8502Sjsg #define DC_HPD1_CONTROL 0x1809 896fb4d8502Sjsg #define DC_HPD2_CONTROL 0x180C 897fb4d8502Sjsg #define DC_HPD3_CONTROL 0x180F 898fb4d8502Sjsg #define DC_HPD4_CONTROL 0x1812 899fb4d8502Sjsg #define DC_HPD5_CONTROL 0x1815 900fb4d8502Sjsg #define DC_HPD6_CONTROL 0x1818 901fb4d8502Sjsg # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 902fb4d8502Sjsg # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 903fb4d8502Sjsg # define DC_HPDx_EN (1 << 28) 904fb4d8502Sjsg 905fb4d8502Sjsg #define DPG_PIPE_STUTTER_CONTROL 0x1B35 906fb4d8502Sjsg # define STUTTER_ENABLE (1 << 0) 907fb4d8502Sjsg 908fb4d8502Sjsg /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 909fb4d8502Sjsg #define CRTC_STATUS_FRAME_COUNT 0x1BA6 910fb4d8502Sjsg 911fb4d8502Sjsg /* Audio clocks */ 912fb4d8502Sjsg #define DCCG_AUDIO_DTO_SOURCE 0x05ac 913fb4d8502Sjsg # define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */ 914fb4d8502Sjsg # define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */ 915fb4d8502Sjsg 916fb4d8502Sjsg #define DCCG_AUDIO_DTO0_PHASE 0x05b0 917fb4d8502Sjsg #define DCCG_AUDIO_DTO0_MODULE 0x05b4 918fb4d8502Sjsg #define DCCG_AUDIO_DTO1_PHASE 0x05c0 919fb4d8502Sjsg #define DCCG_AUDIO_DTO1_MODULE 0x05c4 920fb4d8502Sjsg 921fb4d8502Sjsg #define AFMT_AUDIO_SRC_CONTROL 0x1c4f 922fb4d8502Sjsg #define AFMT_AUDIO_SRC_SELECT(x) (((x) & 7) << 0) 923fb4d8502Sjsg /* AFMT_AUDIO_SRC_SELECT 924fb4d8502Sjsg * 0 = stream0 925fb4d8502Sjsg * 1 = stream1 926fb4d8502Sjsg * 2 = stream2 927fb4d8502Sjsg * 3 = stream3 928fb4d8502Sjsg * 4 = stream4 929fb4d8502Sjsg * 5 = stream5 930fb4d8502Sjsg */ 931fb4d8502Sjsg 932fb4d8502Sjsg #define GRBM_CNTL 0x2000 933fb4d8502Sjsg #define GRBM_READ_TIMEOUT(x) ((x) << 0) 934fb4d8502Sjsg 935fb4d8502Sjsg #define GRBM_STATUS2 0x2002 936fb4d8502Sjsg #define RLC_RQ_PENDING (1 << 0) 937fb4d8502Sjsg #define RLC_BUSY (1 << 8) 938fb4d8502Sjsg #define TC_BUSY (1 << 9) 939fb4d8502Sjsg 940fb4d8502Sjsg #define GRBM_STATUS 0x2004 941fb4d8502Sjsg #define CMDFIFO_AVAIL_MASK 0x0000000F 942fb4d8502Sjsg #define RING2_RQ_PENDING (1 << 4) 943fb4d8502Sjsg #define SRBM_RQ_PENDING (1 << 5) 944fb4d8502Sjsg #define RING1_RQ_PENDING (1 << 6) 945fb4d8502Sjsg #define CF_RQ_PENDING (1 << 7) 946fb4d8502Sjsg #define PF_RQ_PENDING (1 << 8) 947fb4d8502Sjsg #define GDS_DMA_RQ_PENDING (1 << 9) 948fb4d8502Sjsg #define GRBM_EE_BUSY (1 << 10) 949fb4d8502Sjsg #define DB_CLEAN (1 << 12) 950fb4d8502Sjsg #define CB_CLEAN (1 << 13) 951fb4d8502Sjsg #define TA_BUSY (1 << 14) 952fb4d8502Sjsg #define GDS_BUSY (1 << 15) 953fb4d8502Sjsg #define VGT_BUSY (1 << 17) 954fb4d8502Sjsg #define IA_BUSY_NO_DMA (1 << 18) 955fb4d8502Sjsg #define IA_BUSY (1 << 19) 956fb4d8502Sjsg #define SX_BUSY (1 << 20) 957fb4d8502Sjsg #define SPI_BUSY (1 << 22) 958fb4d8502Sjsg #define BCI_BUSY (1 << 23) 959fb4d8502Sjsg #define SC_BUSY (1 << 24) 960fb4d8502Sjsg #define PA_BUSY (1 << 25) 961fb4d8502Sjsg #define DB_BUSY (1 << 26) 962fb4d8502Sjsg #define CP_COHERENCY_BUSY (1 << 28) 963fb4d8502Sjsg #define CP_BUSY (1 << 29) 964fb4d8502Sjsg #define CB_BUSY (1 << 30) 965fb4d8502Sjsg #define GUI_ACTIVE (1 << 31) 966fb4d8502Sjsg #define GRBM_STATUS_SE0 0x2005 967fb4d8502Sjsg #define GRBM_STATUS_SE1 0x2006 968fb4d8502Sjsg #define SE_DB_CLEAN (1 << 1) 969fb4d8502Sjsg #define SE_CB_CLEAN (1 << 2) 970fb4d8502Sjsg #define SE_BCI_BUSY (1 << 22) 971fb4d8502Sjsg #define SE_VGT_BUSY (1 << 23) 972fb4d8502Sjsg #define SE_PA_BUSY (1 << 24) 973fb4d8502Sjsg #define SE_TA_BUSY (1 << 25) 974fb4d8502Sjsg #define SE_SX_BUSY (1 << 26) 975fb4d8502Sjsg #define SE_SPI_BUSY (1 << 27) 976fb4d8502Sjsg #define SE_SC_BUSY (1 << 29) 977fb4d8502Sjsg #define SE_DB_BUSY (1 << 30) 978fb4d8502Sjsg #define SE_CB_BUSY (1 << 31) 979fb4d8502Sjsg 980fb4d8502Sjsg #define GRBM_SOFT_RESET 0x2008 981fb4d8502Sjsg #define SOFT_RESET_CP (1 << 0) 982fb4d8502Sjsg #define SOFT_RESET_CB (1 << 1) 983fb4d8502Sjsg #define SOFT_RESET_RLC (1 << 2) 984fb4d8502Sjsg #define SOFT_RESET_DB (1 << 3) 985fb4d8502Sjsg #define SOFT_RESET_GDS (1 << 4) 986fb4d8502Sjsg #define SOFT_RESET_PA (1 << 5) 987fb4d8502Sjsg #define SOFT_RESET_SC (1 << 6) 988fb4d8502Sjsg #define SOFT_RESET_BCI (1 << 7) 989fb4d8502Sjsg #define SOFT_RESET_SPI (1 << 8) 990fb4d8502Sjsg #define SOFT_RESET_SX (1 << 10) 991fb4d8502Sjsg #define SOFT_RESET_TC (1 << 11) 992fb4d8502Sjsg #define SOFT_RESET_TA (1 << 12) 993fb4d8502Sjsg #define SOFT_RESET_VGT (1 << 14) 994fb4d8502Sjsg #define SOFT_RESET_IA (1 << 15) 995fb4d8502Sjsg 996fb4d8502Sjsg #define GRBM_GFX_INDEX 0x200B 997fb4d8502Sjsg #define INSTANCE_INDEX(x) ((x) << 0) 998fb4d8502Sjsg #define SH_INDEX(x) ((x) << 8) 999fb4d8502Sjsg #define SE_INDEX(x) ((x) << 16) 1000fb4d8502Sjsg #define SH_BROADCAST_WRITES (1 << 29) 1001fb4d8502Sjsg #define INSTANCE_BROADCAST_WRITES (1 << 30) 1002fb4d8502Sjsg #define SE_BROADCAST_WRITES (1 << 31) 1003fb4d8502Sjsg 1004fb4d8502Sjsg #define GRBM_INT_CNTL 0x2018 1005fb4d8502Sjsg # define RDERR_INT_ENABLE (1 << 0) 1006fb4d8502Sjsg # define GUI_IDLE_INT_ENABLE (1 << 19) 1007fb4d8502Sjsg 1008fb4d8502Sjsg #define CP_STRMOUT_CNTL 0x213F 1009fb4d8502Sjsg #define SCRATCH_REG0 0x2140 1010fb4d8502Sjsg #define SCRATCH_REG1 0x2141 1011fb4d8502Sjsg #define SCRATCH_REG2 0x2142 1012fb4d8502Sjsg #define SCRATCH_REG3 0x2143 1013fb4d8502Sjsg #define SCRATCH_REG4 0x2144 1014fb4d8502Sjsg #define SCRATCH_REG5 0x2145 1015fb4d8502Sjsg #define SCRATCH_REG6 0x2146 1016fb4d8502Sjsg #define SCRATCH_REG7 0x2147 1017fb4d8502Sjsg 1018fb4d8502Sjsg #define SCRATCH_UMSK 0x2150 1019fb4d8502Sjsg #define SCRATCH_ADDR 0x2151 1020fb4d8502Sjsg 1021fb4d8502Sjsg #define CP_SEM_WAIT_TIMER 0x216F 1022fb4d8502Sjsg 1023fb4d8502Sjsg #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x2172 1024fb4d8502Sjsg 1025fb4d8502Sjsg #define CP_ME_CNTL 0x21B6 1026fb4d8502Sjsg #define CP_CE_HALT (1 << 24) 1027fb4d8502Sjsg #define CP_PFP_HALT (1 << 26) 1028fb4d8502Sjsg #define CP_ME_HALT (1 << 28) 1029fb4d8502Sjsg 1030fb4d8502Sjsg #define CP_COHER_CNTL2 0x217A 1031fb4d8502Sjsg 1032fb4d8502Sjsg #define CP_RB2_RPTR 0x21BE 1033fb4d8502Sjsg #define CP_RB1_RPTR 0x21BF 1034fb4d8502Sjsg #define CP_RB0_RPTR 0x21C0 1035fb4d8502Sjsg #define CP_RB_WPTR_DELAY 0x21C1 1036fb4d8502Sjsg 1037fb4d8502Sjsg #define CP_QUEUE_THRESHOLDS 0x21D8 1038fb4d8502Sjsg #define ROQ_IB1_START(x) ((x) << 0) 1039fb4d8502Sjsg #define ROQ_IB2_START(x) ((x) << 8) 1040fb4d8502Sjsg #define CP_MEQ_THRESHOLDS 0x21D9 1041fb4d8502Sjsg #define MEQ1_START(x) ((x) << 0) 1042fb4d8502Sjsg #define MEQ2_START(x) ((x) << 8) 1043fb4d8502Sjsg 1044fb4d8502Sjsg #define CP_PERFMON_CNTL 0x21FF 1045fb4d8502Sjsg 1046fb4d8502Sjsg #define VGT_VTX_VECT_EJECT_REG 0x222C 1047fb4d8502Sjsg 1048fb4d8502Sjsg #define VGT_CACHE_INVALIDATION 0x2231 1049fb4d8502Sjsg #define CACHE_INVALIDATION(x) ((x) << 0) 1050fb4d8502Sjsg #define VC_ONLY 0 1051fb4d8502Sjsg #define TC_ONLY 1 1052fb4d8502Sjsg #define VC_AND_TC 2 1053fb4d8502Sjsg #define AUTO_INVLD_EN(x) ((x) << 6) 1054fb4d8502Sjsg #define NO_AUTO 0 1055fb4d8502Sjsg #define ES_AUTO 1 1056fb4d8502Sjsg #define GS_AUTO 2 1057fb4d8502Sjsg #define ES_AND_GS_AUTO 3 1058fb4d8502Sjsg #define VGT_ESGS_RING_SIZE 0x2232 1059fb4d8502Sjsg #define VGT_GSVS_RING_SIZE 0x2233 1060fb4d8502Sjsg 1061fb4d8502Sjsg #define VGT_GS_VERTEX_REUSE 0x2235 1062fb4d8502Sjsg 1063fb4d8502Sjsg #define VGT_PRIMITIVE_TYPE 0x2256 1064fb4d8502Sjsg #define VGT_INDEX_TYPE 0x2257 1065fb4d8502Sjsg 1066fb4d8502Sjsg #define VGT_NUM_INDICES 0x225C 1067fb4d8502Sjsg #define VGT_NUM_INSTANCES 0x225D 1068fb4d8502Sjsg 1069fb4d8502Sjsg #define VGT_TF_RING_SIZE 0x2262 1070fb4d8502Sjsg 1071fb4d8502Sjsg #define VGT_HS_OFFCHIP_PARAM 0x226C 1072fb4d8502Sjsg 1073fb4d8502Sjsg #define VGT_TF_MEMORY_BASE 0x226E 1074fb4d8502Sjsg 1075fb4d8502Sjsg #define CC_GC_SHADER_ARRAY_CONFIG 0x226F 1076fb4d8502Sjsg #define INACTIVE_CUS_MASK 0xFFFF0000 1077fb4d8502Sjsg #define INACTIVE_CUS_SHIFT 16 1078fb4d8502Sjsg #define GC_USER_SHADER_ARRAY_CONFIG 0x2270 1079fb4d8502Sjsg 1080fb4d8502Sjsg #define PA_CL_ENHANCE 0x2285 1081fb4d8502Sjsg #define CLIP_VTX_REORDER_ENA (1 << 0) 1082fb4d8502Sjsg #define NUM_CLIP_SEQ(x) ((x) << 1) 1083fb4d8502Sjsg 1084fb4d8502Sjsg #define PA_SU_LINE_STIPPLE_VALUE 0x2298 1085fb4d8502Sjsg 1086fb4d8502Sjsg #define PA_SC_LINE_STIPPLE_STATE 0x22C4 1087fb4d8502Sjsg 1088fb4d8502Sjsg #define PA_SC_FORCE_EOV_MAX_CNTS 0x22C9 1089fb4d8502Sjsg #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1090fb4d8502Sjsg #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 1091fb4d8502Sjsg 1092fb4d8502Sjsg #define PA_SC_FIFO_SIZE 0x22F3 1093fb4d8502Sjsg #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 1094fb4d8502Sjsg #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 1095fb4d8502Sjsg #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 1096fb4d8502Sjsg #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 1097fb4d8502Sjsg 1098fb4d8502Sjsg #define PA_SC_ENHANCE 0x22FC 1099fb4d8502Sjsg 1100fb4d8502Sjsg #define SQ_CONFIG 0x2300 1101fb4d8502Sjsg 1102fb4d8502Sjsg #define SQC_CACHES 0x2302 1103fb4d8502Sjsg 1104fb4d8502Sjsg #define SQ_POWER_THROTTLE 0x2396 1105fb4d8502Sjsg #define MIN_POWER(x) ((x) << 0) 1106fb4d8502Sjsg #define MIN_POWER_MASK (0x3fff << 0) 1107fb4d8502Sjsg #define MIN_POWER_SHIFT 0 1108fb4d8502Sjsg #define MAX_POWER(x) ((x) << 16) 1109fb4d8502Sjsg #define MAX_POWER_MASK (0x3fff << 16) 1110fb4d8502Sjsg #define MAX_POWER_SHIFT 0 1111fb4d8502Sjsg #define SQ_POWER_THROTTLE2 0x2397 1112fb4d8502Sjsg #define MAX_POWER_DELTA(x) ((x) << 0) 1113fb4d8502Sjsg #define MAX_POWER_DELTA_MASK (0x3fff << 0) 1114fb4d8502Sjsg #define MAX_POWER_DELTA_SHIFT 0 1115fb4d8502Sjsg #define STI_SIZE(x) ((x) << 16) 1116fb4d8502Sjsg #define STI_SIZE_MASK (0x3ff << 16) 1117fb4d8502Sjsg #define STI_SIZE_SHIFT 16 1118fb4d8502Sjsg #define LTI_RATIO(x) ((x) << 27) 1119fb4d8502Sjsg #define LTI_RATIO_MASK (0xf << 27) 1120fb4d8502Sjsg #define LTI_RATIO_SHIFT 27 1121fb4d8502Sjsg 1122fb4d8502Sjsg #define SX_DEBUG_1 0x2418 1123fb4d8502Sjsg 1124fb4d8502Sjsg #define SPI_STATIC_THREAD_MGMT_1 0x2438 1125fb4d8502Sjsg #define SPI_STATIC_THREAD_MGMT_2 0x2439 1126fb4d8502Sjsg #define SPI_STATIC_THREAD_MGMT_3 0x243A 1127fb4d8502Sjsg #define SPI_PS_MAX_WAVE_ID 0x243B 1128fb4d8502Sjsg 1129fb4d8502Sjsg #define SPI_CONFIG_CNTL 0x2440 1130fb4d8502Sjsg 1131fb4d8502Sjsg #define SPI_CONFIG_CNTL_1 0x244F 1132fb4d8502Sjsg #define VTX_DONE_DELAY(x) ((x) << 0) 1133fb4d8502Sjsg #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 1134fb4d8502Sjsg 1135fb4d8502Sjsg #define CGTS_TCC_DISABLE 0x2452 1136fb4d8502Sjsg #define CGTS_USER_TCC_DISABLE 0x2453 1137fb4d8502Sjsg #define TCC_DISABLE_MASK 0xFFFF0000 1138fb4d8502Sjsg #define TCC_DISABLE_SHIFT 16 1139fb4d8502Sjsg #define CGTS_SM_CTRL_REG 0x2454 1140fb4d8502Sjsg #define OVERRIDE (1 << 21) 1141fb4d8502Sjsg #define LS_OVERRIDE (1 << 22) 1142fb4d8502Sjsg 1143fb4d8502Sjsg #define SPI_LB_CU_MASK 0x24D5 1144fb4d8502Sjsg 1145fb4d8502Sjsg #define TA_CNTL_AUX 0x2542 1146fb4d8502Sjsg 1147fb4d8502Sjsg #define CC_RB_BACKEND_DISABLE 0x263D 1148fb4d8502Sjsg #define BACKEND_DISABLE(x) ((x) << 16) 1149fb4d8502Sjsg #define GB_ADDR_CONFIG 0x263E 1150fb4d8502Sjsg #define NUM_PIPES(x) ((x) << 0) 1151fb4d8502Sjsg #define NUM_PIPES_MASK 0x00000007 1152fb4d8502Sjsg #define NUM_PIPES_SHIFT 0 1153fb4d8502Sjsg #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 1154fb4d8502Sjsg #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 1155fb4d8502Sjsg #define PIPE_INTERLEAVE_SIZE_SHIFT 4 1156fb4d8502Sjsg #define NUM_SHADER_ENGINES(x) ((x) << 12) 1157fb4d8502Sjsg #define NUM_SHADER_ENGINES_MASK 0x00003000 1158fb4d8502Sjsg #define NUM_SHADER_ENGINES_SHIFT 12 1159fb4d8502Sjsg #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 1160fb4d8502Sjsg #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 1161fb4d8502Sjsg #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 1162fb4d8502Sjsg #define NUM_GPUS(x) ((x) << 20) 1163fb4d8502Sjsg #define NUM_GPUS_MASK 0x00700000 1164fb4d8502Sjsg #define NUM_GPUS_SHIFT 20 1165fb4d8502Sjsg #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 1166fb4d8502Sjsg #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 1167fb4d8502Sjsg #define MULTI_GPU_TILE_SIZE_SHIFT 24 1168fb4d8502Sjsg #define ROW_SIZE(x) ((x) << 28) 1169fb4d8502Sjsg #define ROW_SIZE_MASK 0x30000000 1170fb4d8502Sjsg #define ROW_SIZE_SHIFT 28 1171fb4d8502Sjsg 1172fb4d8502Sjsg #define GB_TILE_MODE0 0x2644 1173fb4d8502Sjsg # define MICRO_TILE_MODE(x) ((x) << 0) 1174fb4d8502Sjsg # define ADDR_SURF_DISPLAY_MICRO_TILING 0 1175fb4d8502Sjsg # define ADDR_SURF_THIN_MICRO_TILING 1 1176fb4d8502Sjsg # define ADDR_SURF_DEPTH_MICRO_TILING 2 1177fb4d8502Sjsg # define ARRAY_MODE(x) ((x) << 2) 1178fb4d8502Sjsg # define ARRAY_LINEAR_GENERAL 0 1179fb4d8502Sjsg # define ARRAY_LINEAR_ALIGNED 1 1180fb4d8502Sjsg # define ARRAY_1D_TILED_THIN1 2 1181fb4d8502Sjsg # define ARRAY_2D_TILED_THIN1 4 1182fb4d8502Sjsg # define PIPE_CONFIG(x) ((x) << 6) 1183fb4d8502Sjsg # define ADDR_SURF_P2 0 1184fb4d8502Sjsg # define ADDR_SURF_P4_8x16 4 1185fb4d8502Sjsg # define ADDR_SURF_P4_16x16 5 1186fb4d8502Sjsg # define ADDR_SURF_P4_16x32 6 1187fb4d8502Sjsg # define ADDR_SURF_P4_32x32 7 1188fb4d8502Sjsg # define ADDR_SURF_P8_16x16_8x16 8 1189fb4d8502Sjsg # define ADDR_SURF_P8_16x32_8x16 9 1190fb4d8502Sjsg # define ADDR_SURF_P8_32x32_8x16 10 1191fb4d8502Sjsg # define ADDR_SURF_P8_16x32_16x16 11 1192fb4d8502Sjsg # define ADDR_SURF_P8_32x32_16x16 12 1193fb4d8502Sjsg # define ADDR_SURF_P8_32x32_16x32 13 1194fb4d8502Sjsg # define ADDR_SURF_P8_32x64_32x32 14 1195fb4d8502Sjsg # define TILE_SPLIT(x) ((x) << 11) 1196fb4d8502Sjsg # define ADDR_SURF_TILE_SPLIT_64B 0 1197fb4d8502Sjsg # define ADDR_SURF_TILE_SPLIT_128B 1 1198fb4d8502Sjsg # define ADDR_SURF_TILE_SPLIT_256B 2 1199fb4d8502Sjsg # define ADDR_SURF_TILE_SPLIT_512B 3 1200fb4d8502Sjsg # define ADDR_SURF_TILE_SPLIT_1KB 4 1201fb4d8502Sjsg # define ADDR_SURF_TILE_SPLIT_2KB 5 1202fb4d8502Sjsg # define ADDR_SURF_TILE_SPLIT_4KB 6 1203fb4d8502Sjsg # define BANK_WIDTH(x) ((x) << 14) 1204fb4d8502Sjsg # define ADDR_SURF_BANK_WIDTH_1 0 1205fb4d8502Sjsg # define ADDR_SURF_BANK_WIDTH_2 1 1206fb4d8502Sjsg # define ADDR_SURF_BANK_WIDTH_4 2 1207fb4d8502Sjsg # define ADDR_SURF_BANK_WIDTH_8 3 1208fb4d8502Sjsg # define BANK_HEIGHT(x) ((x) << 16) 1209fb4d8502Sjsg # define ADDR_SURF_BANK_HEIGHT_1 0 1210fb4d8502Sjsg # define ADDR_SURF_BANK_HEIGHT_2 1 1211fb4d8502Sjsg # define ADDR_SURF_BANK_HEIGHT_4 2 1212fb4d8502Sjsg # define ADDR_SURF_BANK_HEIGHT_8 3 1213fb4d8502Sjsg # define MACRO_TILE_ASPECT(x) ((x) << 18) 1214fb4d8502Sjsg # define ADDR_SURF_MACRO_ASPECT_1 0 1215fb4d8502Sjsg # define ADDR_SURF_MACRO_ASPECT_2 1 1216fb4d8502Sjsg # define ADDR_SURF_MACRO_ASPECT_4 2 1217fb4d8502Sjsg # define ADDR_SURF_MACRO_ASPECT_8 3 1218fb4d8502Sjsg # define NUM_BANKS(x) ((x) << 20) 1219fb4d8502Sjsg # define ADDR_SURF_2_BANK 0 1220fb4d8502Sjsg # define ADDR_SURF_4_BANK 1 1221fb4d8502Sjsg # define ADDR_SURF_8_BANK 2 1222fb4d8502Sjsg # define ADDR_SURF_16_BANK 3 1223fb4d8502Sjsg #define GB_TILE_MODE1 0x2645 1224fb4d8502Sjsg #define GB_TILE_MODE2 0x2646 1225fb4d8502Sjsg #define GB_TILE_MODE3 0x2647 1226fb4d8502Sjsg #define GB_TILE_MODE4 0x2648 1227fb4d8502Sjsg #define GB_TILE_MODE5 0x2649 1228fb4d8502Sjsg #define GB_TILE_MODE6 0x264a 1229fb4d8502Sjsg #define GB_TILE_MODE7 0x264b 1230fb4d8502Sjsg #define GB_TILE_MODE8 0x264c 1231fb4d8502Sjsg #define GB_TILE_MODE9 0x264d 1232fb4d8502Sjsg #define GB_TILE_MODE10 0x264e 1233fb4d8502Sjsg #define GB_TILE_MODE11 0x264f 1234fb4d8502Sjsg #define GB_TILE_MODE12 0x2650 1235fb4d8502Sjsg #define GB_TILE_MODE13 0x2651 1236fb4d8502Sjsg #define GB_TILE_MODE14 0x2652 1237fb4d8502Sjsg #define GB_TILE_MODE15 0x2653 1238fb4d8502Sjsg #define GB_TILE_MODE16 0x2654 1239fb4d8502Sjsg #define GB_TILE_MODE17 0x2655 1240fb4d8502Sjsg #define GB_TILE_MODE18 0x2656 1241fb4d8502Sjsg #define GB_TILE_MODE19 0x2657 1242fb4d8502Sjsg #define GB_TILE_MODE20 0x2658 1243fb4d8502Sjsg #define GB_TILE_MODE21 0x2659 1244fb4d8502Sjsg #define GB_TILE_MODE22 0x265a 1245fb4d8502Sjsg #define GB_TILE_MODE23 0x265b 1246fb4d8502Sjsg #define GB_TILE_MODE24 0x265c 1247fb4d8502Sjsg #define GB_TILE_MODE25 0x265d 1248fb4d8502Sjsg #define GB_TILE_MODE26 0x265e 1249fb4d8502Sjsg #define GB_TILE_MODE27 0x265f 1250fb4d8502Sjsg #define GB_TILE_MODE28 0x2660 1251fb4d8502Sjsg #define GB_TILE_MODE29 0x2661 1252fb4d8502Sjsg #define GB_TILE_MODE30 0x2662 1253fb4d8502Sjsg #define GB_TILE_MODE31 0x2663 1254fb4d8502Sjsg 1255fb4d8502Sjsg #define CB_PERFCOUNTER0_SELECT0 0x2688 1256fb4d8502Sjsg #define CB_PERFCOUNTER0_SELECT1 0x2689 1257fb4d8502Sjsg #define CB_PERFCOUNTER1_SELECT0 0x268A 1258fb4d8502Sjsg #define CB_PERFCOUNTER1_SELECT1 0x268B 1259fb4d8502Sjsg #define CB_PERFCOUNTER2_SELECT0 0x268C 1260fb4d8502Sjsg #define CB_PERFCOUNTER2_SELECT1 0x268D 1261fb4d8502Sjsg #define CB_PERFCOUNTER3_SELECT0 0x268E 1262fb4d8502Sjsg #define CB_PERFCOUNTER3_SELECT1 0x268F 1263fb4d8502Sjsg 1264fb4d8502Sjsg #define CB_CGTT_SCLK_CTRL 0x2698 1265fb4d8502Sjsg 1266fb4d8502Sjsg #define GC_USER_RB_BACKEND_DISABLE 0x26DF 1267fb4d8502Sjsg #define BACKEND_DISABLE_MASK 0x00FF0000 1268fb4d8502Sjsg #define BACKEND_DISABLE_SHIFT 16 1269fb4d8502Sjsg 1270fb4d8502Sjsg #define TCP_CHAN_STEER_LO 0x2B03 1271fb4d8502Sjsg #define TCP_CHAN_STEER_HI 0x2B94 1272fb4d8502Sjsg 1273fb4d8502Sjsg #define CP_RB0_BASE 0x3040 1274fb4d8502Sjsg #define CP_RB0_CNTL 0x3041 1275fb4d8502Sjsg #define RB_BUFSZ(x) ((x) << 0) 1276fb4d8502Sjsg #define RB_BLKSZ(x) ((x) << 8) 1277fb4d8502Sjsg #define BUF_SWAP_32BIT (2 << 16) 1278fb4d8502Sjsg #define RB_NO_UPDATE (1 << 27) 1279fb4d8502Sjsg #define RB_RPTR_WR_ENA (1 << 31) 1280fb4d8502Sjsg 1281fb4d8502Sjsg #define CP_RB0_RPTR_ADDR 0x3043 1282fb4d8502Sjsg #define CP_RB0_RPTR_ADDR_HI 0x3044 1283fb4d8502Sjsg #define CP_RB0_WPTR 0x3045 1284fb4d8502Sjsg 1285fb4d8502Sjsg #define CP_PFP_UCODE_ADDR 0x3054 1286fb4d8502Sjsg #define CP_PFP_UCODE_DATA 0x3055 1287fb4d8502Sjsg #define CP_ME_RAM_RADDR 0x3056 1288fb4d8502Sjsg #define CP_ME_RAM_WADDR 0x3057 1289fb4d8502Sjsg #define CP_ME_RAM_DATA 0x3058 1290fb4d8502Sjsg 1291fb4d8502Sjsg #define CP_CE_UCODE_ADDR 0x305A 1292fb4d8502Sjsg #define CP_CE_UCODE_DATA 0x305B 1293fb4d8502Sjsg 1294fb4d8502Sjsg #define CP_RB1_BASE 0x3060 1295fb4d8502Sjsg #define CP_RB1_CNTL 0x3061 1296fb4d8502Sjsg #define CP_RB1_RPTR_ADDR 0x3062 1297fb4d8502Sjsg #define CP_RB1_RPTR_ADDR_HI 0x3063 1298fb4d8502Sjsg #define CP_RB1_WPTR 0x3064 1299fb4d8502Sjsg #define CP_RB2_BASE 0x3065 1300fb4d8502Sjsg #define CP_RB2_CNTL 0x3066 1301fb4d8502Sjsg #define CP_RB2_RPTR_ADDR 0x3067 1302fb4d8502Sjsg #define CP_RB2_RPTR_ADDR_HI 0x3068 1303fb4d8502Sjsg #define CP_RB2_WPTR 0x3069 1304fb4d8502Sjsg #define CP_INT_CNTL_RING0 0x306A 1305fb4d8502Sjsg #define CP_INT_CNTL_RING1 0x306B 1306fb4d8502Sjsg #define CP_INT_CNTL_RING2 0x306C 1307fb4d8502Sjsg # define CNTX_BUSY_INT_ENABLE (1 << 19) 1308fb4d8502Sjsg # define CNTX_EMPTY_INT_ENABLE (1 << 20) 1309fb4d8502Sjsg # define WAIT_MEM_SEM_INT_ENABLE (1 << 21) 1310fb4d8502Sjsg # define TIME_STAMP_INT_ENABLE (1 << 26) 1311fb4d8502Sjsg # define CP_RINGID2_INT_ENABLE (1 << 29) 1312fb4d8502Sjsg # define CP_RINGID1_INT_ENABLE (1 << 30) 1313fb4d8502Sjsg # define CP_RINGID0_INT_ENABLE (1 << 31) 1314fb4d8502Sjsg #define CP_INT_STATUS_RING0 0x306D 1315fb4d8502Sjsg #define CP_INT_STATUS_RING1 0x306E 1316fb4d8502Sjsg #define CP_INT_STATUS_RING2 0x306F 1317fb4d8502Sjsg # define WAIT_MEM_SEM_INT_STAT (1 << 21) 1318fb4d8502Sjsg # define TIME_STAMP_INT_STAT (1 << 26) 1319fb4d8502Sjsg # define CP_RINGID2_INT_STAT (1 << 29) 1320fb4d8502Sjsg # define CP_RINGID1_INT_STAT (1 << 30) 1321fb4d8502Sjsg # define CP_RINGID0_INT_STAT (1 << 31) 1322fb4d8502Sjsg 1323fb4d8502Sjsg #define CP_MEM_SLP_CNTL 0x3079 1324fb4d8502Sjsg # define CP_MEM_LS_EN (1 << 0) 1325fb4d8502Sjsg 1326fb4d8502Sjsg #define CP_DEBUG 0x307F 1327fb4d8502Sjsg 1328fb4d8502Sjsg #define RLC_CNTL 0x30C0 1329fb4d8502Sjsg # define RLC_ENABLE (1 << 0) 1330fb4d8502Sjsg #define RLC_RL_BASE 0x30C1 1331fb4d8502Sjsg #define RLC_RL_SIZE 0x30C2 1332fb4d8502Sjsg #define RLC_LB_CNTL 0x30C3 1333fb4d8502Sjsg # define LOAD_BALANCE_ENABLE (1 << 0) 1334fb4d8502Sjsg #define RLC_SAVE_AND_RESTORE_BASE 0x30C4 1335fb4d8502Sjsg #define RLC_LB_CNTR_MAX 0x30C5 1336fb4d8502Sjsg #define RLC_LB_CNTR_INIT 0x30C6 1337fb4d8502Sjsg 1338fb4d8502Sjsg #define RLC_CLEAR_STATE_RESTORE_BASE 0x30C8 1339fb4d8502Sjsg 1340fb4d8502Sjsg #define RLC_UCODE_ADDR 0x30CB 1341fb4d8502Sjsg #define RLC_UCODE_DATA 0x30CC 1342fb4d8502Sjsg 1343fb4d8502Sjsg #define RLC_GPU_CLOCK_COUNT_LSB 0x30CE 1344fb4d8502Sjsg #define RLC_GPU_CLOCK_COUNT_MSB 0x30CF 1345fb4d8502Sjsg #define RLC_CAPTURE_GPU_CLOCK_COUNT 0x30D0 1346fb4d8502Sjsg #define RLC_MC_CNTL 0x30D1 1347fb4d8502Sjsg #define RLC_UCODE_CNTL 0x30D2 1348fb4d8502Sjsg #define RLC_STAT 0x30D3 1349fb4d8502Sjsg # define RLC_BUSY_STATUS (1 << 0) 1350fb4d8502Sjsg # define GFX_POWER_STATUS (1 << 1) 1351fb4d8502Sjsg # define GFX_CLOCK_STATUS (1 << 2) 1352fb4d8502Sjsg # define GFX_LS_STATUS (1 << 3) 1353fb4d8502Sjsg 1354fb4d8502Sjsg #define RLC_PG_CNTL 0x30D7 1355fb4d8502Sjsg # define GFX_PG_ENABLE (1 << 0) 1356fb4d8502Sjsg # define GFX_PG_SRC (1 << 1) 1357fb4d8502Sjsg 1358fb4d8502Sjsg #define RLC_CGTT_MGCG_OVERRIDE 0x3100 1359fb4d8502Sjsg #define RLC_CGCG_CGLS_CTRL 0x3101 1360fb4d8502Sjsg # define CGCG_EN (1 << 0) 1361fb4d8502Sjsg # define CGLS_EN (1 << 1) 1362fb4d8502Sjsg 1363fb4d8502Sjsg #define RLC_TTOP_D 0x3105 1364fb4d8502Sjsg # define RLC_PUD(x) ((x) << 0) 1365fb4d8502Sjsg # define RLC_PUD_MASK (0xff << 0) 1366fb4d8502Sjsg # define RLC_PDD(x) ((x) << 8) 1367fb4d8502Sjsg # define RLC_PDD_MASK (0xff << 8) 1368fb4d8502Sjsg # define RLC_TTPD(x) ((x) << 16) 1369fb4d8502Sjsg # define RLC_TTPD_MASK (0xff << 16) 1370fb4d8502Sjsg # define RLC_MSD(x) ((x) << 24) 1371fb4d8502Sjsg # define RLC_MSD_MASK (0xff << 24) 1372fb4d8502Sjsg 1373fb4d8502Sjsg #define RLC_LB_INIT_CU_MASK 0x3107 1374fb4d8502Sjsg 1375fb4d8502Sjsg #define RLC_PG_AO_CU_MASK 0x310B 1376fb4d8502Sjsg #define RLC_MAX_PG_CU 0x310C 1377fb4d8502Sjsg # define MAX_PU_CU(x) ((x) << 0) 1378fb4d8502Sjsg # define MAX_PU_CU_MASK (0xff << 0) 1379fb4d8502Sjsg #define RLC_AUTO_PG_CTRL 0x310C 1380fb4d8502Sjsg # define AUTO_PG_EN (1 << 0) 1381fb4d8502Sjsg # define GRBM_REG_SGIT(x) ((x) << 3) 1382fb4d8502Sjsg # define GRBM_REG_SGIT_MASK (0xffff << 3) 1383fb4d8502Sjsg # define PG_AFTER_GRBM_REG_ST(x) ((x) << 19) 1384fb4d8502Sjsg # define PG_AFTER_GRBM_REG_ST_MASK (0x1fff << 19) 1385fb4d8502Sjsg 1386fb4d8502Sjsg #define RLC_SERDES_WR_MASTER_MASK_0 0x3115 1387fb4d8502Sjsg #define RLC_SERDES_WR_MASTER_MASK_1 0x3116 1388fb4d8502Sjsg #define RLC_SERDES_WR_CTRL 0x3117 1389fb4d8502Sjsg 1390fb4d8502Sjsg #define RLC_SERDES_MASTER_BUSY_0 0x3119 1391fb4d8502Sjsg #define RLC_SERDES_MASTER_BUSY_1 0x311A 1392fb4d8502Sjsg 1393fb4d8502Sjsg #define RLC_GCPM_GENERAL_3 0x311E 1394fb4d8502Sjsg 1395fb4d8502Sjsg #define DB_RENDER_CONTROL 0xA000 1396fb4d8502Sjsg 1397fb4d8502Sjsg #define DB_DEPTH_INFO 0xA00F 1398fb4d8502Sjsg 1399fb4d8502Sjsg #define PA_SC_RASTER_CONFIG 0xA0D4 1400fb4d8502Sjsg # define RB_MAP_PKR0(x) ((x) << 0) 1401fb4d8502Sjsg # define RB_MAP_PKR0_MASK (0x3 << 0) 1402fb4d8502Sjsg # define RB_MAP_PKR1(x) ((x) << 2) 1403fb4d8502Sjsg # define RB_MAP_PKR1_MASK (0x3 << 2) 1404fb4d8502Sjsg # define RASTER_CONFIG_RB_MAP_0 0 1405fb4d8502Sjsg # define RASTER_CONFIG_RB_MAP_1 1 1406fb4d8502Sjsg # define RASTER_CONFIG_RB_MAP_2 2 1407fb4d8502Sjsg # define RASTER_CONFIG_RB_MAP_3 3 1408fb4d8502Sjsg # define RB_XSEL2(x) ((x) << 4) 1409fb4d8502Sjsg # define RB_XSEL2_MASK (0x3 << 4) 1410fb4d8502Sjsg # define RB_XSEL (1 << 6) 1411fb4d8502Sjsg # define RB_YSEL (1 << 7) 1412fb4d8502Sjsg # define PKR_MAP(x) ((x) << 8) 1413fb4d8502Sjsg # define PKR_MAP_MASK (0x3 << 8) 1414fb4d8502Sjsg # define RASTER_CONFIG_PKR_MAP_0 0 1415fb4d8502Sjsg # define RASTER_CONFIG_PKR_MAP_1 1 1416fb4d8502Sjsg # define RASTER_CONFIG_PKR_MAP_2 2 1417fb4d8502Sjsg # define RASTER_CONFIG_PKR_MAP_3 3 1418fb4d8502Sjsg # define PKR_XSEL(x) ((x) << 10) 1419fb4d8502Sjsg # define PKR_XSEL_MASK (0x3 << 10) 1420fb4d8502Sjsg # define PKR_YSEL(x) ((x) << 12) 1421fb4d8502Sjsg # define PKR_YSEL_MASK (0x3 << 12) 1422fb4d8502Sjsg # define SC_MAP(x) ((x) << 16) 1423fb4d8502Sjsg # define SC_MAP_MASK (0x3 << 16) 1424fb4d8502Sjsg # define SC_XSEL(x) ((x) << 18) 1425fb4d8502Sjsg # define SC_XSEL_MASK (0x3 << 18) 1426fb4d8502Sjsg # define SC_YSEL(x) ((x) << 20) 1427fb4d8502Sjsg # define SC_YSEL_MASK (0x3 << 20) 1428fb4d8502Sjsg # define SE_MAP(x) ((x) << 24) 1429fb4d8502Sjsg # define SE_MAP_MASK (0x3 << 24) 1430fb4d8502Sjsg # define RASTER_CONFIG_SE_MAP_0 0 1431fb4d8502Sjsg # define RASTER_CONFIG_SE_MAP_1 1 1432fb4d8502Sjsg # define RASTER_CONFIG_SE_MAP_2 2 1433fb4d8502Sjsg # define RASTER_CONFIG_SE_MAP_3 3 1434fb4d8502Sjsg # define SE_XSEL(x) ((x) << 26) 1435fb4d8502Sjsg # define SE_XSEL_MASK (0x3 << 26) 1436fb4d8502Sjsg # define SE_YSEL(x) ((x) << 28) 1437fb4d8502Sjsg # define SE_YSEL_MASK (0x3 << 28) 1438fb4d8502Sjsg 1439fb4d8502Sjsg 1440fb4d8502Sjsg #define VGT_EVENT_INITIATOR 0xA2A4 1441fb4d8502Sjsg # define SAMPLE_STREAMOUTSTATS1 (1 << 0) 1442fb4d8502Sjsg # define SAMPLE_STREAMOUTSTATS2 (2 << 0) 1443fb4d8502Sjsg # define SAMPLE_STREAMOUTSTATS3 (3 << 0) 1444fb4d8502Sjsg # define CACHE_FLUSH_TS (4 << 0) 1445fb4d8502Sjsg # define CACHE_FLUSH (6 << 0) 1446fb4d8502Sjsg # define CS_PARTIAL_FLUSH (7 << 0) 1447fb4d8502Sjsg # define VGT_STREAMOUT_RESET (10 << 0) 1448fb4d8502Sjsg # define END_OF_PIPE_INCR_DE (11 << 0) 1449fb4d8502Sjsg # define END_OF_PIPE_IB_END (12 << 0) 1450fb4d8502Sjsg # define RST_PIX_CNT (13 << 0) 1451fb4d8502Sjsg # define VS_PARTIAL_FLUSH (15 << 0) 1452fb4d8502Sjsg # define PS_PARTIAL_FLUSH (16 << 0) 1453fb4d8502Sjsg # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) 1454fb4d8502Sjsg # define ZPASS_DONE (21 << 0) 1455fb4d8502Sjsg # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) 1456fb4d8502Sjsg # define PERFCOUNTER_START (23 << 0) 1457fb4d8502Sjsg # define PERFCOUNTER_STOP (24 << 0) 1458fb4d8502Sjsg # define PIPELINESTAT_START (25 << 0) 1459fb4d8502Sjsg # define PIPELINESTAT_STOP (26 << 0) 1460fb4d8502Sjsg # define PERFCOUNTER_SAMPLE (27 << 0) 1461fb4d8502Sjsg # define SAMPLE_PIPELINESTAT (30 << 0) 1462fb4d8502Sjsg # define SAMPLE_STREAMOUTSTATS (32 << 0) 1463fb4d8502Sjsg # define RESET_VTX_CNT (33 << 0) 1464fb4d8502Sjsg # define VGT_FLUSH (36 << 0) 1465fb4d8502Sjsg # define BOTTOM_OF_PIPE_TS (40 << 0) 1466fb4d8502Sjsg # define DB_CACHE_FLUSH_AND_INV (42 << 0) 1467fb4d8502Sjsg # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) 1468fb4d8502Sjsg # define FLUSH_AND_INV_DB_META (44 << 0) 1469fb4d8502Sjsg # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) 1470fb4d8502Sjsg # define FLUSH_AND_INV_CB_META (46 << 0) 1471fb4d8502Sjsg # define CS_DONE (47 << 0) 1472fb4d8502Sjsg # define PS_DONE (48 << 0) 1473fb4d8502Sjsg # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) 1474fb4d8502Sjsg # define THREAD_TRACE_START (51 << 0) 1475fb4d8502Sjsg # define THREAD_TRACE_STOP (52 << 0) 1476fb4d8502Sjsg # define THREAD_TRACE_FLUSH (54 << 0) 1477fb4d8502Sjsg # define THREAD_TRACE_FINISH (55 << 0) 1478fb4d8502Sjsg 1479fb4d8502Sjsg /* PIF PHY0 registers idx/data 0x8/0xc */ 1480fb4d8502Sjsg #define PB0_PIF_CNTL 0x10 1481fb4d8502Sjsg # define LS2_EXIT_TIME(x) ((x) << 17) 1482fb4d8502Sjsg # define LS2_EXIT_TIME_MASK (0x7 << 17) 1483fb4d8502Sjsg # define LS2_EXIT_TIME_SHIFT 17 1484fb4d8502Sjsg #define PB0_PIF_PAIRING 0x11 1485fb4d8502Sjsg # define MULTI_PIF (1 << 25) 1486fb4d8502Sjsg #define PB0_PIF_PWRDOWN_0 0x12 1487fb4d8502Sjsg # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) 1488fb4d8502Sjsg # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7) 1489fb4d8502Sjsg # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7 1490fb4d8502Sjsg # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) 1491fb4d8502Sjsg # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10) 1492fb4d8502Sjsg # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10 1493fb4d8502Sjsg # define PLL_RAMP_UP_TIME_0(x) ((x) << 24) 1494fb4d8502Sjsg # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24) 1495fb4d8502Sjsg # define PLL_RAMP_UP_TIME_0_SHIFT 24 1496fb4d8502Sjsg #define PB0_PIF_PWRDOWN_1 0x13 1497fb4d8502Sjsg # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) 1498fb4d8502Sjsg # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7) 1499fb4d8502Sjsg # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7 1500fb4d8502Sjsg # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) 1501fb4d8502Sjsg # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10) 1502fb4d8502Sjsg # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10 1503fb4d8502Sjsg # define PLL_RAMP_UP_TIME_1(x) ((x) << 24) 1504fb4d8502Sjsg # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24) 1505fb4d8502Sjsg # define PLL_RAMP_UP_TIME_1_SHIFT 24 1506fb4d8502Sjsg 1507fb4d8502Sjsg #define PB0_PIF_PWRDOWN_2 0x17 1508fb4d8502Sjsg # define PLL_POWER_STATE_IN_TXS2_2(x) ((x) << 7) 1509fb4d8502Sjsg # define PLL_POWER_STATE_IN_TXS2_2_MASK (0x7 << 7) 1510fb4d8502Sjsg # define PLL_POWER_STATE_IN_TXS2_2_SHIFT 7 1511fb4d8502Sjsg # define PLL_POWER_STATE_IN_OFF_2(x) ((x) << 10) 1512fb4d8502Sjsg # define PLL_POWER_STATE_IN_OFF_2_MASK (0x7 << 10) 1513fb4d8502Sjsg # define PLL_POWER_STATE_IN_OFF_2_SHIFT 10 1514fb4d8502Sjsg # define PLL_RAMP_UP_TIME_2(x) ((x) << 24) 1515fb4d8502Sjsg # define PLL_RAMP_UP_TIME_2_MASK (0x7 << 24) 1516fb4d8502Sjsg # define PLL_RAMP_UP_TIME_2_SHIFT 24 1517fb4d8502Sjsg #define PB0_PIF_PWRDOWN_3 0x18 1518fb4d8502Sjsg # define PLL_POWER_STATE_IN_TXS2_3(x) ((x) << 7) 1519fb4d8502Sjsg # define PLL_POWER_STATE_IN_TXS2_3_MASK (0x7 << 7) 1520fb4d8502Sjsg # define PLL_POWER_STATE_IN_TXS2_3_SHIFT 7 1521fb4d8502Sjsg # define PLL_POWER_STATE_IN_OFF_3(x) ((x) << 10) 1522fb4d8502Sjsg # define PLL_POWER_STATE_IN_OFF_3_MASK (0x7 << 10) 1523fb4d8502Sjsg # define PLL_POWER_STATE_IN_OFF_3_SHIFT 10 1524fb4d8502Sjsg # define PLL_RAMP_UP_TIME_3(x) ((x) << 24) 1525fb4d8502Sjsg # define PLL_RAMP_UP_TIME_3_MASK (0x7 << 24) 1526fb4d8502Sjsg # define PLL_RAMP_UP_TIME_3_SHIFT 24 1527fb4d8502Sjsg /* PIF PHY1 registers idx/data 0x10/0x14 */ 1528fb4d8502Sjsg #define PB1_PIF_CNTL 0x10 1529fb4d8502Sjsg #define PB1_PIF_PAIRING 0x11 1530fb4d8502Sjsg #define PB1_PIF_PWRDOWN_0 0x12 1531fb4d8502Sjsg #define PB1_PIF_PWRDOWN_1 0x13 1532fb4d8502Sjsg 1533fb4d8502Sjsg #define PB1_PIF_PWRDOWN_2 0x17 1534fb4d8502Sjsg #define PB1_PIF_PWRDOWN_3 0x18 1535fb4d8502Sjsg /* PCIE registers idx/data 0x30/0x34 */ 1536fb4d8502Sjsg #define PCIE_CNTL2 0x1c /* PCIE */ 1537fb4d8502Sjsg # define SLV_MEM_LS_EN (1 << 16) 1538fb4d8502Sjsg # define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17) 1539fb4d8502Sjsg # define MST_MEM_LS_EN (1 << 18) 1540fb4d8502Sjsg # define REPLAY_MEM_LS_EN (1 << 19) 1541fb4d8502Sjsg #define PCIE_LC_STATUS1 0x28 /* PCIE */ 1542fb4d8502Sjsg # define LC_REVERSE_RCVR (1 << 0) 1543fb4d8502Sjsg # define LC_REVERSE_XMIT (1 << 1) 1544fb4d8502Sjsg # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2) 1545fb4d8502Sjsg # define LC_OPERATING_LINK_WIDTH_SHIFT 2 1546fb4d8502Sjsg # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5) 1547fb4d8502Sjsg # define LC_DETECTED_LINK_WIDTH_SHIFT 5 1548fb4d8502Sjsg 1549fb4d8502Sjsg #define PCIE_P_CNTL 0x40 /* PCIE */ 1550fb4d8502Sjsg # define P_IGNORE_EDB_ERR (1 << 6) 1551fb4d8502Sjsg 1552fb4d8502Sjsg /* PCIE PORT registers idx/data 0x38/0x3c */ 1553fb4d8502Sjsg #define PCIE_LC_CNTL 0xa0 1554fb4d8502Sjsg # define LC_L0S_INACTIVITY(x) ((x) << 8) 1555fb4d8502Sjsg # define LC_L0S_INACTIVITY_MASK (0xf << 8) 1556fb4d8502Sjsg # define LC_L0S_INACTIVITY_SHIFT 8 1557fb4d8502Sjsg # define LC_L1_INACTIVITY(x) ((x) << 12) 1558fb4d8502Sjsg # define LC_L1_INACTIVITY_MASK (0xf << 12) 1559fb4d8502Sjsg # define LC_L1_INACTIVITY_SHIFT 12 1560fb4d8502Sjsg # define LC_PMI_TO_L1_DIS (1 << 16) 1561fb4d8502Sjsg # define LC_ASPM_TO_L1_DIS (1 << 24) 1562fb4d8502Sjsg #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 1563fb4d8502Sjsg # define LC_LINK_WIDTH_SHIFT 0 1564fb4d8502Sjsg # define LC_LINK_WIDTH_MASK 0x7 1565fb4d8502Sjsg # define LC_LINK_WIDTH_X0 0 1566fb4d8502Sjsg # define LC_LINK_WIDTH_X1 1 1567fb4d8502Sjsg # define LC_LINK_WIDTH_X2 2 1568fb4d8502Sjsg # define LC_LINK_WIDTH_X4 3 1569fb4d8502Sjsg # define LC_LINK_WIDTH_X8 4 1570fb4d8502Sjsg # define LC_LINK_WIDTH_X16 6 1571fb4d8502Sjsg # define LC_LINK_WIDTH_RD_SHIFT 4 1572fb4d8502Sjsg # define LC_LINK_WIDTH_RD_MASK 0x70 1573fb4d8502Sjsg # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 1574fb4d8502Sjsg # define LC_RECONFIG_NOW (1 << 8) 1575fb4d8502Sjsg # define LC_RENEGOTIATION_SUPPORT (1 << 9) 1576fb4d8502Sjsg # define LC_RENEGOTIATE_EN (1 << 10) 1577fb4d8502Sjsg # define LC_SHORT_RECONFIG_EN (1 << 11) 1578fb4d8502Sjsg # define LC_UPCONFIGURE_SUPPORT (1 << 12) 1579fb4d8502Sjsg # define LC_UPCONFIGURE_DIS (1 << 13) 1580fb4d8502Sjsg # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) 1581fb4d8502Sjsg # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21) 1582fb4d8502Sjsg # define LC_DYN_LANES_PWR_STATE_SHIFT 21 1583fb4d8502Sjsg #define PCIE_LC_N_FTS_CNTL 0xa3 /* PCIE_P */ 1584fb4d8502Sjsg # define LC_XMIT_N_FTS(x) ((x) << 0) 1585fb4d8502Sjsg # define LC_XMIT_N_FTS_MASK (0xff << 0) 1586fb4d8502Sjsg # define LC_XMIT_N_FTS_SHIFT 0 1587fb4d8502Sjsg # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8) 1588fb4d8502Sjsg # define LC_N_FTS_MASK (0xff << 24) 1589fb4d8502Sjsg #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 1590fb4d8502Sjsg # define LC_GEN2_EN_STRAP (1 << 0) 1591fb4d8502Sjsg # define LC_GEN3_EN_STRAP (1 << 1) 1592fb4d8502Sjsg # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2) 1593fb4d8502Sjsg # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3) 1594fb4d8502Sjsg # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3 1595fb4d8502Sjsg # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5) 1596fb4d8502Sjsg # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6) 1597fb4d8502Sjsg # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7) 1598fb4d8502Sjsg # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8) 1599fb4d8502Sjsg # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9) 1600fb4d8502Sjsg # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10) 1601fb4d8502Sjsg # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10 1602fb4d8502Sjsg # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */ 1603fb4d8502Sjsg # define LC_CURRENT_DATA_RATE_SHIFT 13 1604fb4d8502Sjsg # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16) 1605fb4d8502Sjsg # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18) 1606fb4d8502Sjsg # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19) 1607fb4d8502Sjsg # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20) 1608fb4d8502Sjsg # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21) 1609fb4d8502Sjsg 1610fb4d8502Sjsg #define PCIE_LC_CNTL2 0xb1 1611fb4d8502Sjsg # define LC_ALLOW_PDWN_IN_L1 (1 << 17) 1612fb4d8502Sjsg # define LC_ALLOW_PDWN_IN_L23 (1 << 18) 1613fb4d8502Sjsg 1614fb4d8502Sjsg #define PCIE_LC_CNTL3 0xb5 /* PCIE_P */ 1615fb4d8502Sjsg # define LC_GO_TO_RECOVERY (1 << 30) 1616fb4d8502Sjsg #define PCIE_LC_CNTL4 0xb6 /* PCIE_P */ 1617fb4d8502Sjsg # define LC_REDO_EQ (1 << 5) 1618fb4d8502Sjsg # define LC_SET_QUIESCE (1 << 13) 1619fb4d8502Sjsg 1620fb4d8502Sjsg /* 1621fb4d8502Sjsg * UVD 1622fb4d8502Sjsg */ 1623fb4d8502Sjsg #define UVD_UDEC_ADDR_CONFIG 0x3bd3 1624fb4d8502Sjsg #define UVD_UDEC_DB_ADDR_CONFIG 0x3bd4 1625fb4d8502Sjsg #define UVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 1626fb4d8502Sjsg #define UVD_RBC_RB_RPTR 0x3da4 1627fb4d8502Sjsg #define UVD_RBC_RB_WPTR 0x3da5 1628fb4d8502Sjsg #define UVD_STATUS 0x3daf 1629fb4d8502Sjsg 1630fb4d8502Sjsg #define UVD_CGC_CTRL 0x3dc2 1631fb4d8502Sjsg # define DCM (1 << 0) 1632fb4d8502Sjsg # define CG_DT(x) ((x) << 2) 1633fb4d8502Sjsg # define CG_DT_MASK (0xf << 2) 1634fb4d8502Sjsg # define CLK_OD(x) ((x) << 6) 1635fb4d8502Sjsg # define CLK_OD_MASK (0x1f << 6) 1636fb4d8502Sjsg 1637fb4d8502Sjsg /* UVD CTX indirect */ 1638fb4d8502Sjsg #define UVD_CGC_MEM_CTRL 0xC0 1639fb4d8502Sjsg #define UVD_CGC_CTRL2 0xC1 1640fb4d8502Sjsg # define DYN_OR_EN (1 << 0) 1641fb4d8502Sjsg # define DYN_RR_EN (1 << 1) 1642fb4d8502Sjsg # define G_DIV_ID(x) ((x) << 2) 1643fb4d8502Sjsg # define G_DIV_ID_MASK (0x7 << 2) 1644fb4d8502Sjsg 1645fb4d8502Sjsg /* 1646fb4d8502Sjsg * PM4 1647fb4d8502Sjsg */ 1648*ad8b1aafSjsg #define PACKET_TYPE0 0 1649*ad8b1aafSjsg #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 1650*ad8b1aafSjsg ((reg) & 0xFFFF) | \ 1651fb4d8502Sjsg ((n) & 0x3FFF) << 16) 1652fb4d8502Sjsg #define CP_PACKET2 0x80000000 1653fb4d8502Sjsg #define PACKET2_PAD_SHIFT 0 1654fb4d8502Sjsg #define PACKET2_PAD_MASK (0x3fffffff << 0) 1655fb4d8502Sjsg 1656fb4d8502Sjsg #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 1657fb4d8502Sjsg #define RADEON_PACKET_TYPE3 3 1658fb4d8502Sjsg #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 1659fb4d8502Sjsg (((op) & 0xFF) << 8) | \ 1660fb4d8502Sjsg ((n) & 0x3FFF) << 16) 1661fb4d8502Sjsg 1662fb4d8502Sjsg #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 1663fb4d8502Sjsg 1664fb4d8502Sjsg /* Packet 3 types */ 1665fb4d8502Sjsg #define PACKET3_NOP 0x10 1666fb4d8502Sjsg #define PACKET3_SET_BASE 0x11 1667fb4d8502Sjsg #define PACKET3_BASE_INDEX(x) ((x) << 0) 1668fb4d8502Sjsg #define GDS_PARTITION_BASE 2 1669fb4d8502Sjsg #define CE_PARTITION_BASE 3 1670fb4d8502Sjsg #define PACKET3_CLEAR_STATE 0x12 1671fb4d8502Sjsg #define PACKET3_INDEX_BUFFER_SIZE 0x13 1672fb4d8502Sjsg #define PACKET3_DISPATCH_DIRECT 0x15 1673fb4d8502Sjsg #define PACKET3_DISPATCH_INDIRECT 0x16 1674fb4d8502Sjsg #define PACKET3_ALLOC_GDS 0x1B 1675fb4d8502Sjsg #define PACKET3_WRITE_GDS_RAM 0x1C 1676fb4d8502Sjsg #define PACKET3_ATOMIC_GDS 0x1D 1677fb4d8502Sjsg #define PACKET3_ATOMIC 0x1E 1678fb4d8502Sjsg #define PACKET3_OCCLUSION_QUERY 0x1F 1679fb4d8502Sjsg #define PACKET3_SET_PREDICATION 0x20 1680fb4d8502Sjsg #define PACKET3_REG_RMW 0x21 1681fb4d8502Sjsg #define PACKET3_COND_EXEC 0x22 1682fb4d8502Sjsg #define PACKET3_PRED_EXEC 0x23 1683fb4d8502Sjsg #define PACKET3_DRAW_INDIRECT 0x24 1684fb4d8502Sjsg #define PACKET3_DRAW_INDEX_INDIRECT 0x25 1685fb4d8502Sjsg #define PACKET3_INDEX_BASE 0x26 1686fb4d8502Sjsg #define PACKET3_DRAW_INDEX_2 0x27 1687fb4d8502Sjsg #define PACKET3_CONTEXT_CONTROL 0x28 1688fb4d8502Sjsg #define PACKET3_INDEX_TYPE 0x2A 1689fb4d8502Sjsg #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 1690fb4d8502Sjsg #define PACKET3_DRAW_INDEX_AUTO 0x2D 1691fb4d8502Sjsg #define PACKET3_DRAW_INDEX_IMMD 0x2E 1692fb4d8502Sjsg #define PACKET3_NUM_INSTANCES 0x2F 1693fb4d8502Sjsg #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 1694fb4d8502Sjsg #define PACKET3_INDIRECT_BUFFER_CONST 0x31 1695fb4d8502Sjsg #define PACKET3_INDIRECT_BUFFER 0x3F 1696fb4d8502Sjsg #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1697fb4d8502Sjsg #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 1698fb4d8502Sjsg #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 1699fb4d8502Sjsg #define PACKET3_WRITE_DATA 0x37 1700fb4d8502Sjsg #define WRITE_DATA_DST_SEL(x) ((x) << 8) 1701fb4d8502Sjsg /* 0 - register 1702fb4d8502Sjsg * 1 - memory (sync - via GRBM) 1703fb4d8502Sjsg * 2 - tc/l2 1704fb4d8502Sjsg * 3 - gds 1705fb4d8502Sjsg * 4 - reserved 1706fb4d8502Sjsg * 5 - memory (async - direct) 1707fb4d8502Sjsg */ 1708fb4d8502Sjsg #define WR_ONE_ADDR (1 << 16) 1709fb4d8502Sjsg #define WR_CONFIRM (1 << 20) 1710fb4d8502Sjsg #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 1711fb4d8502Sjsg /* 0 - me 1712fb4d8502Sjsg * 1 - pfp 1713fb4d8502Sjsg * 2 - ce 1714fb4d8502Sjsg */ 1715fb4d8502Sjsg #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 1716fb4d8502Sjsg #define PACKET3_MEM_SEMAPHORE 0x39 1717fb4d8502Sjsg #define PACKET3_MPEG_INDEX 0x3A 1718fb4d8502Sjsg #define PACKET3_COPY_DW 0x3B 1719fb4d8502Sjsg #define PACKET3_WAIT_REG_MEM 0x3C 1720fb4d8502Sjsg #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 1721fb4d8502Sjsg /* 0 - always 1722fb4d8502Sjsg * 1 - < 1723fb4d8502Sjsg * 2 - <= 1724fb4d8502Sjsg * 3 - == 1725fb4d8502Sjsg * 4 - != 1726fb4d8502Sjsg * 5 - >= 1727fb4d8502Sjsg * 6 - > 1728fb4d8502Sjsg */ 1729fb4d8502Sjsg #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 1730fb4d8502Sjsg /* 0 - reg 1731fb4d8502Sjsg * 1 - mem 1732fb4d8502Sjsg */ 1733fb4d8502Sjsg #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 1734fb4d8502Sjsg /* 0 - me 1735fb4d8502Sjsg * 1 - pfp 1736fb4d8502Sjsg */ 1737fb4d8502Sjsg #define PACKET3_MEM_WRITE 0x3D 1738fb4d8502Sjsg #define PACKET3_COPY_DATA 0x40 1739fb4d8502Sjsg #define PACKET3_CP_DMA 0x41 1740fb4d8502Sjsg /* 1. header 1741fb4d8502Sjsg * 2. SRC_ADDR_LO or DATA [31:0] 1742fb4d8502Sjsg * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | 1743fb4d8502Sjsg * SRC_ADDR_HI [7:0] 1744fb4d8502Sjsg * 4. DST_ADDR_LO [31:0] 1745fb4d8502Sjsg * 5. DST_ADDR_HI [7:0] 1746fb4d8502Sjsg * 6. COMMAND [30:21] | BYTE_COUNT [20:0] 1747fb4d8502Sjsg */ 1748fb4d8502Sjsg # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 1749fb4d8502Sjsg /* 0 - DST_ADDR 1750fb4d8502Sjsg * 1 - GDS 1751fb4d8502Sjsg */ 1752fb4d8502Sjsg # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) 1753fb4d8502Sjsg /* 0 - ME 1754fb4d8502Sjsg * 1 - PFP 1755fb4d8502Sjsg */ 1756fb4d8502Sjsg # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) 1757fb4d8502Sjsg /* 0 - SRC_ADDR 1758fb4d8502Sjsg * 1 - GDS 1759fb4d8502Sjsg * 2 - DATA 1760fb4d8502Sjsg */ 1761fb4d8502Sjsg # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 1762fb4d8502Sjsg /* COMMAND */ 1763fb4d8502Sjsg # define PACKET3_CP_DMA_DIS_WC (1 << 21) 1764fb4d8502Sjsg # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) 1765fb4d8502Sjsg /* 0 - none 1766fb4d8502Sjsg * 1 - 8 in 16 1767fb4d8502Sjsg * 2 - 8 in 32 1768fb4d8502Sjsg * 3 - 8 in 64 1769fb4d8502Sjsg */ 1770fb4d8502Sjsg # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 1771fb4d8502Sjsg /* 0 - none 1772fb4d8502Sjsg * 1 - 8 in 16 1773fb4d8502Sjsg * 2 - 8 in 32 1774fb4d8502Sjsg * 3 - 8 in 64 1775fb4d8502Sjsg */ 1776fb4d8502Sjsg # define PACKET3_CP_DMA_CMD_SAS (1 << 26) 1777fb4d8502Sjsg /* 0 - memory 1778fb4d8502Sjsg * 1 - register 1779fb4d8502Sjsg */ 1780fb4d8502Sjsg # define PACKET3_CP_DMA_CMD_DAS (1 << 27) 1781fb4d8502Sjsg /* 0 - memory 1782fb4d8502Sjsg * 1 - register 1783fb4d8502Sjsg */ 1784fb4d8502Sjsg # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 1785fb4d8502Sjsg # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 1786fb4d8502Sjsg # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) 1787fb4d8502Sjsg #define PACKET3_PFP_SYNC_ME 0x42 1788fb4d8502Sjsg #define PACKET3_SURFACE_SYNC 0x43 1789fb4d8502Sjsg # define PACKET3_DEST_BASE_0_ENA (1 << 0) 1790fb4d8502Sjsg # define PACKET3_DEST_BASE_1_ENA (1 << 1) 1791fb4d8502Sjsg # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1792fb4d8502Sjsg # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 1793fb4d8502Sjsg # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 1794fb4d8502Sjsg # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 1795fb4d8502Sjsg # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 1796fb4d8502Sjsg # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 1797fb4d8502Sjsg # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 1798fb4d8502Sjsg # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 1799fb4d8502Sjsg # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 1800fb4d8502Sjsg # define PACKET3_DEST_BASE_2_ENA (1 << 19) 1801fb4d8502Sjsg # define PACKET3_DEST_BASE_3_ENA (1 << 21) 1802fb4d8502Sjsg # define PACKET3_TCL1_ACTION_ENA (1 << 22) 1803fb4d8502Sjsg # define PACKET3_TC_ACTION_ENA (1 << 23) 1804fb4d8502Sjsg # define PACKET3_CB_ACTION_ENA (1 << 25) 1805fb4d8502Sjsg # define PACKET3_DB_ACTION_ENA (1 << 26) 1806fb4d8502Sjsg # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 1807fb4d8502Sjsg # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 1808fb4d8502Sjsg #define PACKET3_ME_INITIALIZE 0x44 1809fb4d8502Sjsg #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1810fb4d8502Sjsg #define PACKET3_COND_WRITE 0x45 1811fb4d8502Sjsg #define PACKET3_EVENT_WRITE 0x46 1812fb4d8502Sjsg #define EVENT_TYPE(x) ((x) << 0) 1813fb4d8502Sjsg #define EVENT_INDEX(x) ((x) << 8) 1814fb4d8502Sjsg /* 0 - any non-TS event 1815fb4d8502Sjsg * 1 - ZPASS_DONE 1816fb4d8502Sjsg * 2 - SAMPLE_PIPELINESTAT 1817fb4d8502Sjsg * 3 - SAMPLE_STREAMOUTSTAT* 1818fb4d8502Sjsg * 4 - *S_PARTIAL_FLUSH 1819fb4d8502Sjsg * 5 - EOP events 1820fb4d8502Sjsg * 6 - EOS events 1821fb4d8502Sjsg * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT 1822fb4d8502Sjsg */ 1823fb4d8502Sjsg #define INV_L2 (1 << 20) 1824fb4d8502Sjsg /* INV TC L2 cache when EVENT_INDEX = 7 */ 1825fb4d8502Sjsg #define PACKET3_EVENT_WRITE_EOP 0x47 1826fb4d8502Sjsg #define DATA_SEL(x) ((x) << 29) 1827fb4d8502Sjsg /* 0 - discard 1828fb4d8502Sjsg * 1 - send low 32bit data 1829fb4d8502Sjsg * 2 - send 64bit data 1830fb4d8502Sjsg * 3 - send 64bit counter value 1831fb4d8502Sjsg */ 1832fb4d8502Sjsg #define INT_SEL(x) ((x) << 24) 1833fb4d8502Sjsg /* 0 - none 1834fb4d8502Sjsg * 1 - interrupt only (DATA_SEL = 0) 1835fb4d8502Sjsg * 2 - interrupt when data write is confirmed 1836fb4d8502Sjsg */ 1837fb4d8502Sjsg #define PACKET3_EVENT_WRITE_EOS 0x48 1838fb4d8502Sjsg #define PACKET3_PREAMBLE_CNTL 0x4A 1839fb4d8502Sjsg # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 1840fb4d8502Sjsg # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 1841fb4d8502Sjsg #define PACKET3_ONE_REG_WRITE 0x57 1842fb4d8502Sjsg #define PACKET3_LOAD_CONFIG_REG 0x5F 1843fb4d8502Sjsg #define PACKET3_LOAD_CONTEXT_REG 0x60 1844fb4d8502Sjsg #define PACKET3_LOAD_SH_REG 0x61 1845fb4d8502Sjsg #define PACKET3_SET_CONFIG_REG 0x68 1846fb4d8502Sjsg #define PACKET3_SET_CONFIG_REG_START 0x00002000 1847fb4d8502Sjsg #define PACKET3_SET_CONFIG_REG_END 0x00002c00 1848fb4d8502Sjsg #define PACKET3_SET_CONTEXT_REG 0x69 1849fb4d8502Sjsg #define PACKET3_SET_CONTEXT_REG_START 0x000a000 1850fb4d8502Sjsg #define PACKET3_SET_CONTEXT_REG_END 0x000a400 1851fb4d8502Sjsg #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 1852fb4d8502Sjsg #define PACKET3_SET_RESOURCE_INDIRECT 0x74 1853fb4d8502Sjsg #define PACKET3_SET_SH_REG 0x76 1854fb4d8502Sjsg #define PACKET3_SET_SH_REG_START 0x00002c00 1855fb4d8502Sjsg #define PACKET3_SET_SH_REG_END 0x00003000 1856fb4d8502Sjsg #define PACKET3_SET_SH_REG_OFFSET 0x77 1857fb4d8502Sjsg #define PACKET3_ME_WRITE 0x7A 1858fb4d8502Sjsg #define PACKET3_SCRATCH_RAM_WRITE 0x7D 1859fb4d8502Sjsg #define PACKET3_SCRATCH_RAM_READ 0x7E 1860fb4d8502Sjsg #define PACKET3_CE_WRITE 0x7F 1861fb4d8502Sjsg #define PACKET3_LOAD_CONST_RAM 0x80 1862fb4d8502Sjsg #define PACKET3_WRITE_CONST_RAM 0x81 1863fb4d8502Sjsg #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 1864fb4d8502Sjsg #define PACKET3_DUMP_CONST_RAM 0x83 1865fb4d8502Sjsg #define PACKET3_INCREMENT_CE_COUNTER 0x84 1866fb4d8502Sjsg #define PACKET3_INCREMENT_DE_COUNTER 0x85 1867fb4d8502Sjsg #define PACKET3_WAIT_ON_CE_COUNTER 0x86 1868fb4d8502Sjsg #define PACKET3_WAIT_ON_DE_COUNTER 0x87 1869fb4d8502Sjsg #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 1870fb4d8502Sjsg #define PACKET3_SET_CE_DE_COUNTERS 0x89 1871fb4d8502Sjsg #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A 1872fb4d8502Sjsg #define PACKET3_SWITCH_BUFFER 0x8B 1873fb4d8502Sjsg 1874fb4d8502Sjsg /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ 1875fb4d8502Sjsg #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ 1876fb4d8502Sjsg #define DMA1_REGISTER_OFFSET 0x200 /* not a register */ 1877fb4d8502Sjsg 1878fb4d8502Sjsg #define DMA_RB_CNTL 0x3400 1879fb4d8502Sjsg # define DMA_RB_ENABLE (1 << 0) 1880fb4d8502Sjsg # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 1881fb4d8502Sjsg # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 1882fb4d8502Sjsg # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 1883fb4d8502Sjsg # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 1884fb4d8502Sjsg # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 1885fb4d8502Sjsg #define DMA_RB_BASE 0x3401 1886fb4d8502Sjsg #define DMA_RB_RPTR 0x3402 1887fb4d8502Sjsg #define DMA_RB_WPTR 0x3403 1888fb4d8502Sjsg 1889fb4d8502Sjsg #define DMA_RB_RPTR_ADDR_HI 0x3407 1890fb4d8502Sjsg #define DMA_RB_RPTR_ADDR_LO 0x3408 1891fb4d8502Sjsg 1892fb4d8502Sjsg #define DMA_IB_CNTL 0x3409 1893fb4d8502Sjsg # define DMA_IB_ENABLE (1 << 0) 1894fb4d8502Sjsg # define DMA_IB_SWAP_ENABLE (1 << 4) 1895fb4d8502Sjsg # define CMD_VMID_FORCE (1 << 31) 1896fb4d8502Sjsg #define DMA_IB_RPTR 0x340a 1897fb4d8502Sjsg #define DMA_CNTL 0x340b 1898fb4d8502Sjsg # define TRAP_ENABLE (1 << 0) 1899fb4d8502Sjsg # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 1900fb4d8502Sjsg # define SEM_WAIT_INT_ENABLE (1 << 2) 1901fb4d8502Sjsg # define DATA_SWAP_ENABLE (1 << 3) 1902fb4d8502Sjsg # define FENCE_SWAP_ENABLE (1 << 4) 1903fb4d8502Sjsg # define CTXEMPTY_INT_ENABLE (1 << 28) 1904fb4d8502Sjsg #define DMA_STATUS_REG 0x340d 1905fb4d8502Sjsg # define DMA_IDLE (1 << 0) 1906fb4d8502Sjsg #define DMA_TILING_CONFIG 0x342e 1907fb4d8502Sjsg 1908fb4d8502Sjsg #define DMA_POWER_CNTL 0x342f 1909fb4d8502Sjsg # define MEM_POWER_OVERRIDE (1 << 8) 1910fb4d8502Sjsg #define DMA_CLK_CTRL 0x3430 1911fb4d8502Sjsg 1912fb4d8502Sjsg #define DMA_PG 0x3435 1913fb4d8502Sjsg # define PG_CNTL_ENABLE (1 << 0) 1914fb4d8502Sjsg #define DMA_PGFSM_CONFIG 0x3436 1915fb4d8502Sjsg #define DMA_PGFSM_WRITE 0x3437 1916fb4d8502Sjsg 1917fb4d8502Sjsg #define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \ 1918fb4d8502Sjsg (((b) & 0x1) << 26) | \ 1919fb4d8502Sjsg (((t) & 0x1) << 23) | \ 1920fb4d8502Sjsg (((s) & 0x1) << 22) | \ 1921fb4d8502Sjsg (((n) & 0xFFFFF) << 0)) 1922fb4d8502Sjsg 1923fb4d8502Sjsg #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ 1924fb4d8502Sjsg (((vmid) & 0xF) << 20) | \ 1925fb4d8502Sjsg (((n) & 0xFFFFF) << 0)) 1926fb4d8502Sjsg 1927fb4d8502Sjsg #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \ 1928fb4d8502Sjsg (1 << 26) | \ 1929fb4d8502Sjsg (1 << 21) | \ 1930fb4d8502Sjsg (((n) & 0xFFFFF) << 0)) 1931fb4d8502Sjsg 1932fb4d8502Sjsg /* async DMA Packet types */ 1933fb4d8502Sjsg #define DMA_PACKET_WRITE 0x2 1934fb4d8502Sjsg #define DMA_PACKET_COPY 0x3 1935fb4d8502Sjsg #define DMA_PACKET_INDIRECT_BUFFER 0x4 1936fb4d8502Sjsg #define DMA_PACKET_SEMAPHORE 0x5 1937fb4d8502Sjsg #define DMA_PACKET_FENCE 0x6 1938fb4d8502Sjsg #define DMA_PACKET_TRAP 0x7 1939fb4d8502Sjsg #define DMA_PACKET_SRBM_WRITE 0x9 1940fb4d8502Sjsg #define DMA_PACKET_CONSTANT_FILL 0xd 1941fb4d8502Sjsg #define DMA_PACKET_POLL_REG_MEM 0xe 1942fb4d8502Sjsg #define DMA_PACKET_NOP 0xf 1943fb4d8502Sjsg 1944fb4d8502Sjsg #define VCE_STATUS 0x20004 1945fb4d8502Sjsg #define VCE_VCPU_CNTL 0x20014 1946fb4d8502Sjsg #define VCE_CLK_EN (1 << 0) 1947fb4d8502Sjsg #define VCE_VCPU_CACHE_OFFSET0 0x20024 1948fb4d8502Sjsg #define VCE_VCPU_CACHE_SIZE0 0x20028 1949fb4d8502Sjsg #define VCE_VCPU_CACHE_OFFSET1 0x2002c 1950fb4d8502Sjsg #define VCE_VCPU_CACHE_SIZE1 0x20030 1951fb4d8502Sjsg #define VCE_VCPU_CACHE_OFFSET2 0x20034 1952fb4d8502Sjsg #define VCE_VCPU_CACHE_SIZE2 0x20038 1953fb4d8502Sjsg #define VCE_SOFT_RESET 0x20120 1954fb4d8502Sjsg #define VCE_ECPU_SOFT_RESET (1 << 0) 1955fb4d8502Sjsg #define VCE_FME_SOFT_RESET (1 << 2) 1956fb4d8502Sjsg #define VCE_RB_BASE_LO2 0x2016c 1957fb4d8502Sjsg #define VCE_RB_BASE_HI2 0x20170 1958fb4d8502Sjsg #define VCE_RB_SIZE2 0x20174 1959fb4d8502Sjsg #define VCE_RB_RPTR2 0x20178 1960fb4d8502Sjsg #define VCE_RB_WPTR2 0x2017c 1961fb4d8502Sjsg #define VCE_RB_BASE_LO 0x20180 1962fb4d8502Sjsg #define VCE_RB_BASE_HI 0x20184 1963fb4d8502Sjsg #define VCE_RB_SIZE 0x20188 1964fb4d8502Sjsg #define VCE_RB_RPTR 0x2018c 1965fb4d8502Sjsg #define VCE_RB_WPTR 0x20190 1966fb4d8502Sjsg #define VCE_CLOCK_GATING_A 0x202f8 1967fb4d8502Sjsg #define VCE_CLOCK_GATING_B 0x202fc 1968fb4d8502Sjsg #define VCE_UENC_CLOCK_GATING 0x205bc 1969fb4d8502Sjsg #define VCE_UENC_REG_CLOCK_GATING 0x205c0 1970fb4d8502Sjsg #define VCE_FW_REG_STATUS 0x20e10 1971fb4d8502Sjsg # define VCE_FW_REG_STATUS_BUSY (1 << 0) 1972fb4d8502Sjsg # define VCE_FW_REG_STATUS_PASS (1 << 3) 1973fb4d8502Sjsg # define VCE_FW_REG_STATUS_DONE (1 << 11) 1974fb4d8502Sjsg #define VCE_LMI_FW_START_KEYSEL 0x20e18 1975fb4d8502Sjsg #define VCE_LMI_FW_PERIODIC_CTRL 0x20e20 1976fb4d8502Sjsg #define VCE_LMI_CTRL2 0x20e74 1977fb4d8502Sjsg #define VCE_LMI_CTRL 0x20e98 1978fb4d8502Sjsg #define VCE_LMI_VM_CTRL 0x20ea0 1979fb4d8502Sjsg #define VCE_LMI_SWAP_CNTL 0x20eb4 1980fb4d8502Sjsg #define VCE_LMI_SWAP_CNTL1 0x20eb8 1981fb4d8502Sjsg #define VCE_LMI_CACHE_CTRL 0x20ef4 1982fb4d8502Sjsg 1983fb4d8502Sjsg #define VCE_CMD_NO_OP 0x00000000 1984fb4d8502Sjsg #define VCE_CMD_END 0x00000001 1985fb4d8502Sjsg #define VCE_CMD_IB 0x00000002 1986fb4d8502Sjsg #define VCE_CMD_FENCE 0x00000003 1987fb4d8502Sjsg #define VCE_CMD_TRAP 0x00000004 1988fb4d8502Sjsg #define VCE_CMD_IB_AUTO 0x00000005 1989fb4d8502Sjsg #define VCE_CMD_SEMAPHORE 0x00000006 1990fb4d8502Sjsg 1991fb4d8502Sjsg 1992fb4d8502Sjsg //#dce stupp 1993fb4d8502Sjsg /* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ 1994fb4d8502Sjsg #define SI_CRTC0_REGISTER_OFFSET 0 //(0x6df0 - 0x6df0)/4 1995fb4d8502Sjsg #define SI_CRTC1_REGISTER_OFFSET 0x300 //(0x79f0 - 0x6df0)/4 1996fb4d8502Sjsg #define SI_CRTC2_REGISTER_OFFSET 0x2600 //(0x105f0 - 0x6df0)/4 1997fb4d8502Sjsg #define SI_CRTC3_REGISTER_OFFSET 0x2900 //(0x111f0 - 0x6df0)/4 1998fb4d8502Sjsg #define SI_CRTC4_REGISTER_OFFSET 0x2c00 //(0x11df0 - 0x6df0)/4 1999fb4d8502Sjsg #define SI_CRTC5_REGISTER_OFFSET 0x2f00 //(0x129f0 - 0x6df0)/4 2000fb4d8502Sjsg 2001fb4d8502Sjsg #define CURSOR_WIDTH 64 2002fb4d8502Sjsg #define CURSOR_HEIGHT 64 2003fb4d8502Sjsg #define AMDGPU_MM_INDEX 0x0000 2004fb4d8502Sjsg #define AMDGPU_MM_DATA 0x0001 2005fb4d8502Sjsg 2006fb4d8502Sjsg #define VERDE_NUM_CRTC 6 2007fb4d8502Sjsg #define BLACKOUT_MODE_MASK 0x00000007 2008fb4d8502Sjsg #define VGA_RENDER_CONTROL 0xC0 2009fb4d8502Sjsg #define R_000300_VGA_RENDER_CONTROL 0xC0 2010fb4d8502Sjsg #define C_000300_VGA_VSTATUS_CNTL 0xFFFCFFFF 2011fb4d8502Sjsg #define EVERGREEN_CRTC_STATUS 0x1BA3 2012fb4d8502Sjsg #define EVERGREEN_CRTC_V_BLANK (1 << 0) 2013fb4d8502Sjsg #define EVERGREEN_CRTC_STATUS_POSITION 0x1BA4 2014fb4d8502Sjsg /* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */ 2015fb4d8502Sjsg #define EVERGREEN_CRTC_V_BLANK_START_END 0x1b8d 2016fb4d8502Sjsg #define EVERGREEN_CRTC_CONTROL 0x1b9c 2017fb4d8502Sjsg #define EVERGREEN_CRTC_MASTER_EN (1 << 0) 2018fb4d8502Sjsg #define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24) 2019fb4d8502Sjsg #define EVERGREEN_CRTC_BLANK_CONTROL 0x1b9d 2020fb4d8502Sjsg #define EVERGREEN_CRTC_BLANK_DATA_EN (1 << 8) 2021fb4d8502Sjsg #define EVERGREEN_CRTC_V_BLANK (1 << 0) 2022fb4d8502Sjsg #define EVERGREEN_CRTC_STATUS_HV_COUNT 0x1ba8 2023fb4d8502Sjsg #define EVERGREEN_CRTC_UPDATE_LOCK 0x1bb5 2024fb4d8502Sjsg #define EVERGREEN_MASTER_UPDATE_LOCK 0x1bbd 2025fb4d8502Sjsg #define EVERGREEN_MASTER_UPDATE_MODE 0x1bbe 2026fb4d8502Sjsg #define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16) 2027fb4d8502Sjsg #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 2028fb4d8502Sjsg #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 2029fb4d8502Sjsg #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 2030fb4d8502Sjsg #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 2031fb4d8502Sjsg #define EVERGREEN_GRPH_UPDATE 0x1a11 2032fb4d8502Sjsg #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0xc4 2033fb4d8502Sjsg #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0xc9 2034fb4d8502Sjsg #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2) 2035fb4d8502Sjsg 2036fb4d8502Sjsg #define EVERGREEN_DATA_FORMAT 0x1ac0 2037fb4d8502Sjsg # define EVERGREEN_INTERLEAVE_EN (1 << 0) 2038fb4d8502Sjsg 2039fb4d8502Sjsg #define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000 2040fb4d8502Sjsg #define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc 2041fb4d8502Sjsg 2042fb4d8502Sjsg #define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL (0 << 20) 2043fb4d8502Sjsg #define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED (1 << 20) 2044fb4d8502Sjsg #define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1 (2 << 20) 2045fb4d8502Sjsg #define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1 (4 << 20) 2046fb4d8502Sjsg 2047fb4d8502Sjsg #define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a45 2048fb4d8502Sjsg #define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1845 2049fb4d8502Sjsg 2050fb4d8502Sjsg #define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1847 2051fb4d8502Sjsg #define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a47 2052fb4d8502Sjsg 2053fb4d8502Sjsg #define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x8 2054fb4d8502Sjsg #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x8 2055fb4d8502Sjsg #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x8 2056fb4d8502Sjsg #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x8 2057fb4d8502Sjsg #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x8 2058fb4d8502Sjsg #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x8 2059fb4d8502Sjsg 2060fb4d8502Sjsg #define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x4 2061fb4d8502Sjsg #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x4 2062fb4d8502Sjsg #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x4 2063fb4d8502Sjsg #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x4 2064fb4d8502Sjsg #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x4 2065fb4d8502Sjsg #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x4 2066fb4d8502Sjsg 2067fb4d8502Sjsg #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000 2068fb4d8502Sjsg #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x20000 2069fb4d8502Sjsg #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x20000 2070fb4d8502Sjsg #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000 2071fb4d8502Sjsg #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x20000 2072fb4d8502Sjsg #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x20000 2073fb4d8502Sjsg 2074fb4d8502Sjsg #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1 2075fb4d8502Sjsg #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100 2076fb4d8502Sjsg 2077fb4d8502Sjsg #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK 0x1 2078fb4d8502Sjsg 2079fb4d8502Sjsg #define R600_D1GRPH_SWAP_CONTROL 0x1843 2080fb4d8502Sjsg #define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0) 2081fb4d8502Sjsg #define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0) 2082fb4d8502Sjsg #define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0) 2083fb4d8502Sjsg #define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0) 2084fb4d8502Sjsg 2085fb4d8502Sjsg #define AVIVO_D1VGA_CONTROL 0x00cc 2086fb4d8502Sjsg # define AVIVO_DVGA_CONTROL_MODE_ENABLE (1 << 0) 2087fb4d8502Sjsg # define AVIVO_DVGA_CONTROL_TIMING_SELECT (1 << 8) 2088fb4d8502Sjsg # define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1 << 9) 2089fb4d8502Sjsg # define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 << 10) 2090fb4d8502Sjsg # define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1 << 16) 2091fb4d8502Sjsg # define AVIVO_DVGA_CONTROL_ROTATE (1 << 24) 2092fb4d8502Sjsg #define AVIVO_D2VGA_CONTROL 0x00ce 2093fb4d8502Sjsg 2094fb4d8502Sjsg #define R600_BUS_CNTL 0x1508 2095fb4d8502Sjsg # define R600_BIOS_ROM_DIS (1 << 1) 2096fb4d8502Sjsg 2097fb4d8502Sjsg #define R600_ROM_CNTL 0x580 2098fb4d8502Sjsg # define R600_SCK_OVERWRITE (1 << 1) 2099fb4d8502Sjsg # define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 2100fb4d8502Sjsg # define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) 2101fb4d8502Sjsg 2102fb4d8502Sjsg #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1 2103fb4d8502Sjsg 2104fb4d8502Sjsg #define FMT_BIT_DEPTH_CONTROL 0x1bf2 2105fb4d8502Sjsg #define FMT_TRUNCATE_EN (1 << 0) 2106fb4d8502Sjsg #define FMT_TRUNCATE_DEPTH (1 << 4) 2107fb4d8502Sjsg #define FMT_SPATIAL_DITHER_EN (1 << 8) 2108fb4d8502Sjsg #define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9) 2109fb4d8502Sjsg #define FMT_SPATIAL_DITHER_DEPTH (1 << 12) 2110fb4d8502Sjsg #define FMT_FRAME_RANDOM_ENABLE (1 << 13) 2111fb4d8502Sjsg #define FMT_RGB_RANDOM_ENABLE (1 << 14) 2112fb4d8502Sjsg #define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15) 2113fb4d8502Sjsg #define FMT_TEMPORAL_DITHER_EN (1 << 16) 2114fb4d8502Sjsg #define FMT_TEMPORAL_DITHER_DEPTH (1 << 20) 2115fb4d8502Sjsg #define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21) 2116fb4d8502Sjsg #define FMT_TEMPORAL_LEVEL (1 << 24) 2117fb4d8502Sjsg #define FMT_TEMPORAL_DITHER_RESET (1 << 25) 2118fb4d8502Sjsg #define FMT_25FRC_SEL(x) ((x) << 26) 2119fb4d8502Sjsg #define FMT_50FRC_SEL(x) ((x) << 28) 2120fb4d8502Sjsg #define FMT_75FRC_SEL(x) ((x) << 30) 2121fb4d8502Sjsg 2122fb4d8502Sjsg #define EVERGREEN_DC_LUT_CONTROL 0x1a80 2123fb4d8502Sjsg #define EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE 0x1a81 2124fb4d8502Sjsg #define EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN 0x1a82 2125fb4d8502Sjsg #define EVERGREEN_DC_LUT_BLACK_OFFSET_RED 0x1a83 2126fb4d8502Sjsg #define EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE 0x1a84 2127fb4d8502Sjsg #define EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN 0x1a85 2128fb4d8502Sjsg #define EVERGREEN_DC_LUT_WHITE_OFFSET_RED 0x1a86 2129fb4d8502Sjsg #define EVERGREEN_DC_LUT_30_COLOR 0x1a7c 2130fb4d8502Sjsg #define EVERGREEN_DC_LUT_RW_INDEX 0x1a79 2131fb4d8502Sjsg #define EVERGREEN_DC_LUT_WRITE_EN_MASK 0x1a7e 2132fb4d8502Sjsg #define EVERGREEN_DC_LUT_RW_MODE 0x1a78 2133fb4d8502Sjsg 2134fb4d8502Sjsg #define EVERGREEN_GRPH_ENABLE 0x1a00 2135fb4d8502Sjsg #define EVERGREEN_GRPH_CONTROL 0x1a01 2136fb4d8502Sjsg #define EVERGREEN_GRPH_DEPTH(x) (((x) & 0x3) << 0) 2137fb4d8502Sjsg #define EVERGREEN_GRPH_DEPTH_8BPP 0 2138fb4d8502Sjsg #define EVERGREEN_GRPH_DEPTH_16BPP 1 2139fb4d8502Sjsg #define EVERGREEN_GRPH_DEPTH_32BPP 2 2140fb4d8502Sjsg #define EVERGREEN_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2) 2141fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_2_BANK 0 2142fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_4_BANK 1 2143fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_8_BANK 2 2144fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_16_BANK 3 2145fb4d8502Sjsg #define EVERGREEN_GRPH_Z(x) (((x) & 0x3) << 4) 2146fb4d8502Sjsg #define EVERGREEN_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6) 2147fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_BANK_WIDTH_1 0 2148fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_BANK_WIDTH_2 1 2149fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_BANK_WIDTH_4 2 2150fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_BANK_WIDTH_8 3 2151fb4d8502Sjsg #define EVERGREEN_GRPH_FORMAT(x) (((x) & 0x7) << 8) 2152fb4d8502Sjsg 2153fb4d8502Sjsg #define EVERGREEN_GRPH_FORMAT_INDEXED 0 2154fb4d8502Sjsg #define EVERGREEN_GRPH_FORMAT_ARGB1555 0 2155fb4d8502Sjsg #define EVERGREEN_GRPH_FORMAT_ARGB565 1 2156fb4d8502Sjsg #define EVERGREEN_GRPH_FORMAT_ARGB4444 2 2157fb4d8502Sjsg #define EVERGREEN_GRPH_FORMAT_AI88 3 2158fb4d8502Sjsg #define EVERGREEN_GRPH_FORMAT_MONO16 4 2159fb4d8502Sjsg #define EVERGREEN_GRPH_FORMAT_BGRA5551 5 2160fb4d8502Sjsg 2161fb4d8502Sjsg /* 32 BPP */ 2162fb4d8502Sjsg #define EVERGREEN_GRPH_FORMAT_ARGB8888 0 2163fb4d8502Sjsg #define EVERGREEN_GRPH_FORMAT_ARGB2101010 1 2164fb4d8502Sjsg #define EVERGREEN_GRPH_FORMAT_32BPP_DIG 2 2165fb4d8502Sjsg #define EVERGREEN_GRPH_FORMAT_8B_ARGB2101010 3 2166fb4d8502Sjsg #define EVERGREEN_GRPH_FORMAT_BGRA1010102 4 2167fb4d8502Sjsg #define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 5 2168fb4d8502Sjsg #define EVERGREEN_GRPH_FORMAT_RGB111110 6 2169fb4d8502Sjsg #define EVERGREEN_GRPH_FORMAT_BGR101111 7 2170fb4d8502Sjsg #define EVERGREEN_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11) 2171fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_BANK_HEIGHT_1 0 2172fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_BANK_HEIGHT_2 1 2173fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_BANK_HEIGHT_4 2 2174fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_BANK_HEIGHT_8 3 2175fb4d8502Sjsg #define EVERGREEN_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13) 2176fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_TILE_SPLIT_64B 0 2177fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_TILE_SPLIT_128B 1 2178fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_TILE_SPLIT_256B 2 2179fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_TILE_SPLIT_512B 3 2180fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_TILE_SPLIT_1KB 4 2181fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_TILE_SPLIT_2KB 5 2182fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_TILE_SPLIT_4KB 6 2183fb4d8502Sjsg #define EVERGREEN_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18) 2184fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1 0 2185fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2 1 2186fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4 2 2187fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8 3 2188fb4d8502Sjsg #define EVERGREEN_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20) 2189fb4d8502Sjsg #define EVERGREEN_GRPH_ARRAY_LINEAR_GENERAL 0 2190fb4d8502Sjsg #define EVERGREEN_GRPH_ARRAY_LINEAR_ALIGNED 1 2191fb4d8502Sjsg #define EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1 2 2192fb4d8502Sjsg #define EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1 4 2193fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1 0 2194fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2 1 2195fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4 2 2196fb4d8502Sjsg #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8 3 2197fb4d8502Sjsg 2198fb4d8502Sjsg #define EVERGREEN_GRPH_SWAP_CONTROL 0x1a03 2199fb4d8502Sjsg #define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) 2200fb4d8502Sjsg # define EVERGREEN_GRPH_ENDIAN_NONE 0 2201fb4d8502Sjsg # define EVERGREEN_GRPH_ENDIAN_8IN16 1 2202fb4d8502Sjsg # define EVERGREEN_GRPH_ENDIAN_8IN32 2 2203fb4d8502Sjsg # define EVERGREEN_GRPH_ENDIAN_8IN64 3 2204c349dbc7Sjsg #define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) 2205c349dbc7Sjsg # define EVERGREEN_GRPH_RED_SEL_R 0 2206c349dbc7Sjsg # define EVERGREEN_GRPH_RED_SEL_G 1 2207c349dbc7Sjsg # define EVERGREEN_GRPH_RED_SEL_B 2 2208c349dbc7Sjsg # define EVERGREEN_GRPH_RED_SEL_A 3 2209c349dbc7Sjsg #define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) 2210c349dbc7Sjsg # define EVERGREEN_GRPH_GREEN_SEL_G 0 2211c349dbc7Sjsg # define EVERGREEN_GRPH_GREEN_SEL_B 1 2212c349dbc7Sjsg # define EVERGREEN_GRPH_GREEN_SEL_A 2 2213c349dbc7Sjsg # define EVERGREEN_GRPH_GREEN_SEL_R 3 2214c349dbc7Sjsg #define EVERGREEN_GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) 2215c349dbc7Sjsg # define EVERGREEN_GRPH_BLUE_SEL_B 0 2216c349dbc7Sjsg # define EVERGREEN_GRPH_BLUE_SEL_A 1 2217c349dbc7Sjsg # define EVERGREEN_GRPH_BLUE_SEL_R 2 2218c349dbc7Sjsg # define EVERGREEN_GRPH_BLUE_SEL_G 3 2219c349dbc7Sjsg #define EVERGREEN_GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) 2220c349dbc7Sjsg # define EVERGREEN_GRPH_ALPHA_SEL_A 0 2221c349dbc7Sjsg # define EVERGREEN_GRPH_ALPHA_SEL_R 1 2222c349dbc7Sjsg # define EVERGREEN_GRPH_ALPHA_SEL_G 2 2223c349dbc7Sjsg # define EVERGREEN_GRPH_ALPHA_SEL_B 3 2224fb4d8502Sjsg 2225fb4d8502Sjsg #define EVERGREEN_D3VGA_CONTROL 0xf8 2226fb4d8502Sjsg #define EVERGREEN_D4VGA_CONTROL 0xf9 2227fb4d8502Sjsg #define EVERGREEN_D5VGA_CONTROL 0xfa 2228fb4d8502Sjsg #define EVERGREEN_D6VGA_CONTROL 0xfb 2229fb4d8502Sjsg 2230fb4d8502Sjsg #define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK 0xffffff00 2231fb4d8502Sjsg 2232fb4d8502Sjsg #define EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL 0x1a02 2233fb4d8502Sjsg #define EVERGREEN_LUT_10BIT_BYPASS_EN (1 << 8) 2234fb4d8502Sjsg 2235fb4d8502Sjsg #define EVERGREEN_GRPH_PITCH 0x1a06 2236fb4d8502Sjsg #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 2237fb4d8502Sjsg #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 2238fb4d8502Sjsg #define EVERGREEN_GRPH_SURFACE_OFFSET_X 0x1a09 2239fb4d8502Sjsg #define EVERGREEN_GRPH_SURFACE_OFFSET_Y 0x1a0a 2240fb4d8502Sjsg #define EVERGREEN_GRPH_X_START 0x1a0b 2241fb4d8502Sjsg #define EVERGREEN_GRPH_Y_START 0x1a0c 2242fb4d8502Sjsg #define EVERGREEN_GRPH_X_END 0x1a0d 2243fb4d8502Sjsg #define EVERGREEN_GRPH_Y_END 0x1a0e 2244fb4d8502Sjsg #define EVERGREEN_GRPH_UPDATE 0x1a11 2245fb4d8502Sjsg #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2) 2246fb4d8502Sjsg #define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16) 2247fb4d8502Sjsg #define EVERGREEN_GRPH_FLIP_CONTROL 0x1a12 2248fb4d8502Sjsg #define EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN (1 << 0) 2249fb4d8502Sjsg 2250fb4d8502Sjsg #define EVERGREEN_VIEWPORT_START 0x1b5c 2251fb4d8502Sjsg #define EVERGREEN_VIEWPORT_SIZE 0x1b5d 2252fb4d8502Sjsg #define EVERGREEN_DESKTOP_HEIGHT 0x1ac1 2253fb4d8502Sjsg 2254fb4d8502Sjsg /* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */ 2255fb4d8502Sjsg #define EVERGREEN_CUR_CONTROL 0x1a66 2256fb4d8502Sjsg # define EVERGREEN_CURSOR_EN (1 << 0) 2257fb4d8502Sjsg # define EVERGREEN_CURSOR_MODE(x) (((x) & 0x3) << 8) 2258fb4d8502Sjsg # define EVERGREEN_CURSOR_MONO 0 2259fb4d8502Sjsg # define EVERGREEN_CURSOR_24_1 1 2260fb4d8502Sjsg # define EVERGREEN_CURSOR_24_8_PRE_MULT 2 2261fb4d8502Sjsg # define EVERGREEN_CURSOR_24_8_UNPRE_MULT 3 2262fb4d8502Sjsg # define EVERGREEN_CURSOR_2X_MAGNIFY (1 << 16) 2263fb4d8502Sjsg # define EVERGREEN_CURSOR_FORCE_MC_ON (1 << 20) 2264fb4d8502Sjsg # define EVERGREEN_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) 2265fb4d8502Sjsg # define EVERGREEN_CURSOR_URGENT_ALWAYS 0 2266fb4d8502Sjsg # define EVERGREEN_CURSOR_URGENT_1_8 1 2267fb4d8502Sjsg # define EVERGREEN_CURSOR_URGENT_1_4 2 2268fb4d8502Sjsg # define EVERGREEN_CURSOR_URGENT_3_8 3 2269fb4d8502Sjsg # define EVERGREEN_CURSOR_URGENT_1_2 4 2270fb4d8502Sjsg #define EVERGREEN_CUR_SURFACE_ADDRESS 0x1a67 2271fb4d8502Sjsg # define EVERGREEN_CUR_SURFACE_ADDRESS_MASK 0xfffff000 2272fb4d8502Sjsg #define EVERGREEN_CUR_SIZE 0x1a68 2273fb4d8502Sjsg #define EVERGREEN_CUR_SURFACE_ADDRESS_HIGH 0x1a69 2274fb4d8502Sjsg #define EVERGREEN_CUR_POSITION 0x1a6a 2275fb4d8502Sjsg #define EVERGREEN_CUR_HOT_SPOT 0x1a6b 2276fb4d8502Sjsg #define EVERGREEN_CUR_COLOR1 0x1a6c 2277fb4d8502Sjsg #define EVERGREEN_CUR_COLOR2 0x1a6d 2278fb4d8502Sjsg #define EVERGREEN_CUR_UPDATE 0x1a6e 2279fb4d8502Sjsg # define EVERGREEN_CURSOR_UPDATE_PENDING (1 << 0) 2280fb4d8502Sjsg # define EVERGREEN_CURSOR_UPDATE_TAKEN (1 << 1) 2281fb4d8502Sjsg # define EVERGREEN_CURSOR_UPDATE_LOCK (1 << 16) 2282fb4d8502Sjsg # define EVERGREEN_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24) 2283fb4d8502Sjsg 2284fb4d8502Sjsg 2285fb4d8502Sjsg #define NI_INPUT_CSC_CONTROL 0x1a35 2286fb4d8502Sjsg # define NI_INPUT_CSC_GRPH_MODE(x) (((x) & 0x3) << 0) 2287fb4d8502Sjsg # define NI_INPUT_CSC_BYPASS 0 2288fb4d8502Sjsg # define NI_INPUT_CSC_PROG_COEFF 1 2289fb4d8502Sjsg # define NI_INPUT_CSC_PROG_SHARED_MATRIXA 2 2290fb4d8502Sjsg # define NI_INPUT_CSC_OVL_MODE(x) (((x) & 0x3) << 4) 2291fb4d8502Sjsg 2292fb4d8502Sjsg #define NI_OUTPUT_CSC_CONTROL 0x1a3c 2293fb4d8502Sjsg # define NI_OUTPUT_CSC_GRPH_MODE(x) (((x) & 0x7) << 0) 2294fb4d8502Sjsg # define NI_OUTPUT_CSC_BYPASS 0 2295fb4d8502Sjsg # define NI_OUTPUT_CSC_TV_RGB 1 2296fb4d8502Sjsg # define NI_OUTPUT_CSC_YCBCR_601 2 2297fb4d8502Sjsg # define NI_OUTPUT_CSC_YCBCR_709 3 2298fb4d8502Sjsg # define NI_OUTPUT_CSC_PROG_COEFF 4 2299fb4d8502Sjsg # define NI_OUTPUT_CSC_PROG_SHARED_MATRIXB 5 2300fb4d8502Sjsg # define NI_OUTPUT_CSC_OVL_MODE(x) (((x) & 0x7) << 4) 2301fb4d8502Sjsg 2302fb4d8502Sjsg #define NI_DEGAMMA_CONTROL 0x1a58 2303fb4d8502Sjsg # define NI_GRPH_DEGAMMA_MODE(x) (((x) & 0x3) << 0) 2304fb4d8502Sjsg # define NI_DEGAMMA_BYPASS 0 2305fb4d8502Sjsg # define NI_DEGAMMA_SRGB_24 1 2306fb4d8502Sjsg # define NI_DEGAMMA_XVYCC_222 2 2307fb4d8502Sjsg # define NI_OVL_DEGAMMA_MODE(x) (((x) & 0x3) << 4) 2308fb4d8502Sjsg # define NI_ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8) 2309fb4d8502Sjsg # define NI_CURSOR_DEGAMMA_MODE(x) (((x) & 0x3) << 12) 2310fb4d8502Sjsg 2311fb4d8502Sjsg #define NI_GAMUT_REMAP_CONTROL 0x1a59 2312fb4d8502Sjsg # define NI_GRPH_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 0) 2313fb4d8502Sjsg # define NI_GAMUT_REMAP_BYPASS 0 2314fb4d8502Sjsg # define NI_GAMUT_REMAP_PROG_COEFF 1 2315fb4d8502Sjsg # define NI_GAMUT_REMAP_PROG_SHARED_MATRIXA 2 2316fb4d8502Sjsg # define NI_GAMUT_REMAP_PROG_SHARED_MATRIXB 3 2317fb4d8502Sjsg # define NI_OVL_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 4) 2318fb4d8502Sjsg 2319fb4d8502Sjsg #define NI_REGAMMA_CONTROL 0x1aa0 2320fb4d8502Sjsg # define NI_GRPH_REGAMMA_MODE(x) (((x) & 0x7) << 0) 2321fb4d8502Sjsg # define NI_REGAMMA_BYPASS 0 2322fb4d8502Sjsg # define NI_REGAMMA_SRGB_24 1 2323fb4d8502Sjsg # define NI_REGAMMA_XVYCC_222 2 2324fb4d8502Sjsg # define NI_REGAMMA_PROG_A 3 2325fb4d8502Sjsg # define NI_REGAMMA_PROG_B 4 2326fb4d8502Sjsg # define NI_OVL_REGAMMA_MODE(x) (((x) & 0x7) << 4) 2327fb4d8502Sjsg 2328fb4d8502Sjsg 2329fb4d8502Sjsg #define NI_PRESCALE_GRPH_CONTROL 0x1a2d 2330fb4d8502Sjsg # define NI_GRPH_PRESCALE_BYPASS (1 << 4) 2331fb4d8502Sjsg 2332fb4d8502Sjsg #define NI_PRESCALE_OVL_CONTROL 0x1a31 2333fb4d8502Sjsg # define NI_OVL_PRESCALE_BYPASS (1 << 4) 2334fb4d8502Sjsg 2335fb4d8502Sjsg #define NI_INPUT_GAMMA_CONTROL 0x1a10 2336fb4d8502Sjsg # define NI_GRPH_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 0) 2337fb4d8502Sjsg # define NI_INPUT_GAMMA_USE_LUT 0 2338fb4d8502Sjsg # define NI_INPUT_GAMMA_BYPASS 1 2339fb4d8502Sjsg # define NI_INPUT_GAMMA_SRGB_24 2 2340fb4d8502Sjsg # define NI_INPUT_GAMMA_XVYCC_222 3 2341fb4d8502Sjsg # define NI_OVL_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 4) 2342fb4d8502Sjsg 2343fb4d8502Sjsg #define BLACKOUT_MODE_MASK 0x00000007 2344fb4d8502Sjsg #define VGA_RENDER_CONTROL 0xC0 2345fb4d8502Sjsg #define R_000300_VGA_RENDER_CONTROL 0xC0 2346fb4d8502Sjsg #define C_000300_VGA_VSTATUS_CNTL 0xFFFCFFFF 2347fb4d8502Sjsg #define EVERGREEN_CRTC_STATUS 0x1BA3 2348fb4d8502Sjsg #define EVERGREEN_CRTC_V_BLANK (1 << 0) 2349fb4d8502Sjsg #define EVERGREEN_CRTC_STATUS_POSITION 0x1BA4 2350fb4d8502Sjsg /* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */ 2351fb4d8502Sjsg #define EVERGREEN_CRTC_V_BLANK_START_END 0x1b8d 2352fb4d8502Sjsg #define EVERGREEN_CRTC_CONTROL 0x1b9c 2353fb4d8502Sjsg # define EVERGREEN_CRTC_MASTER_EN (1 << 0) 2354fb4d8502Sjsg # define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24) 2355fb4d8502Sjsg #define EVERGREEN_CRTC_BLANK_CONTROL 0x1b9d 2356fb4d8502Sjsg # define EVERGREEN_CRTC_BLANK_DATA_EN (1 << 8) 2357fb4d8502Sjsg # define EVERGREEN_CRTC_V_BLANK (1 << 0) 2358fb4d8502Sjsg #define EVERGREEN_CRTC_STATUS_HV_COUNT 0x1ba8 2359fb4d8502Sjsg #define EVERGREEN_CRTC_UPDATE_LOCK 0x1bb5 2360fb4d8502Sjsg #define EVERGREEN_MASTER_UPDATE_LOCK 0x1bbd 2361fb4d8502Sjsg #define EVERGREEN_MASTER_UPDATE_MODE 0x1bbe 2362fb4d8502Sjsg #define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16) 2363fb4d8502Sjsg #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 2364fb4d8502Sjsg #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 2365fb4d8502Sjsg #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 2366fb4d8502Sjsg #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 2367fb4d8502Sjsg #define EVERGREEN_GRPH_UPDATE 0x1a11 2368fb4d8502Sjsg #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0xc4 2369fb4d8502Sjsg #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0xc9 2370fb4d8502Sjsg #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2) 2371fb4d8502Sjsg 2372fb4d8502Sjsg #define mmVM_CONTEXT1_CNTL__xxRANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10 2373fb4d8502Sjsg #define mmVM_CONTEXT1_CNTL__xxRANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 2374fb4d8502Sjsg #define mmVM_CONTEXT1_CNTL__xxDUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80 2375fb4d8502Sjsg #define mmVM_CONTEXT1_CNTL__xxDUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 2376fb4d8502Sjsg #define mmVM_CONTEXT1_CNTL__xxPDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400 2377fb4d8502Sjsg #define mmVM_CONTEXT1_CNTL__xxPDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 2378fb4d8502Sjsg #define mmVM_CONTEXT1_CNTL__xxVALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000 2379fb4d8502Sjsg #define mmVM_CONTEXT1_CNTL__xxVALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 2380fb4d8502Sjsg #define mmVM_CONTEXT1_CNTL__xxREAD_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000 2381fb4d8502Sjsg #define mmVM_CONTEXT1_CNTL__xxREAD_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 2382fb4d8502Sjsg #define mmVM_CONTEXT1_CNTL__xxWRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000 2383fb4d8502Sjsg #define mmVM_CONTEXT1_CNTL__xxWRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 2384fb4d8502Sjsg 2385fb4d8502Sjsg #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxVMID_MASK 0x1e000000 2386fb4d8502Sjsg #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxVMID__SHIFT 0x19 2387fb4d8502Sjsg #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxPROTECTIONS_MASK 0xff 2388fb4d8502Sjsg #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxPROTECTIONS__SHIFT 0x0 2389fb4d8502Sjsg #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_ID_MASK 0xff000 2390fb4d8502Sjsg #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_ID__SHIFT 0xc 2391fb4d8502Sjsg #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_RW_MASK 0x1000000 2392fb4d8502Sjsg #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_RW__SHIFT 0x18 2393fb4d8502Sjsg 2394fb4d8502Sjsg #define mmMC_SHARED_BLACKOUT_CNTL__xxBLACKOUT_MODE_MASK 0x7 2395fb4d8502Sjsg #define mmMC_SHARED_BLACKOUT_CNTL__xxBLACKOUT_MODE__SHIFT 0x0 2396fb4d8502Sjsg 2397fb4d8502Sjsg #define mmBIF_FB_EN__xxFB_READ_EN_MASK 0x1 2398fb4d8502Sjsg #define mmBIF_FB_EN__xxFB_READ_EN__SHIFT 0x0 2399fb4d8502Sjsg #define mmBIF_FB_EN__xxFB_WRITE_EN_MASK 0x2 2400fb4d8502Sjsg #define mmBIF_FB_EN__xxFB_WRITE_EN__SHIFT 0x1 2401fb4d8502Sjsg 2402fb4d8502Sjsg #define mmSRBM_SOFT_RESET__xxSOFT_RESET_VMC_MASK 0x20000 2403fb4d8502Sjsg #define mmSRBM_SOFT_RESET__xxSOFT_RESET_VMC__SHIFT 0x11 2404fb4d8502Sjsg #define mmSRBM_SOFT_RESET__xxSOFT_RESET_MC_MASK 0x800 2405fb4d8502Sjsg #define mmSRBM_SOFT_RESET__xxSOFT_RESET_MC__SHIFT 0xb 2406fb4d8502Sjsg 2407fb4d8502Sjsg #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8 2408fb4d8502Sjsg #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 2409fb4d8502Sjsg #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40 2410fb4d8502Sjsg #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6 2411fb4d8502Sjsg #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200 2412fb4d8502Sjsg #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 2413fb4d8502Sjsg #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000 2414fb4d8502Sjsg #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 2415fb4d8502Sjsg #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000 2416fb4d8502Sjsg #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 2417fb4d8502Sjsg #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000 2418fb4d8502Sjsg #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 2419fb4d8502Sjsg 2420fb4d8502Sjsg #define MC_SEQ_MISC0__MT__MASK 0xf0000000 2421fb4d8502Sjsg #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 2422fb4d8502Sjsg #define MC_SEQ_MISC0__MT__DDR2 0x20000000 2423fb4d8502Sjsg #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 2424fb4d8502Sjsg #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 2425fb4d8502Sjsg #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 2426fb4d8502Sjsg #define MC_SEQ_MISC0__MT__HBM 0x60000000 2427fb4d8502Sjsg #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 2428fb4d8502Sjsg 2429fb4d8502Sjsg #define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000 2430fb4d8502Sjsg #define CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK 0x4000000 2431fb4d8502Sjsg #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000 2432fb4d8502Sjsg #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 2433fb4d8502Sjsg #define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) 2434fb4d8502Sjsg #define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 2435fb4d8502Sjsg #define PACKET3_SEM_SEL_WAIT (0x7 << 29) 2436fb4d8502Sjsg 2437fb4d8502Sjsg #define CONFIG_CNTL 0x1509 2438fb4d8502Sjsg #define CC_DRM_ID_STRAPS 0X1559 2439fb4d8502Sjsg #define AMDGPU_PCIE_INDEX 0xc 2440fb4d8502Sjsg #define AMDGPU_PCIE_DATA 0xd 2441fb4d8502Sjsg 2442fb4d8502Sjsg #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0x3411 2443fb4d8502Sjsg #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0x3412 2444fb4d8502Sjsg #define DMA_MODE 0x342f 2445fb4d8502Sjsg #define DMA_RB_RPTR_ADDR_HI 0x3407 2446fb4d8502Sjsg #define DMA_RB_RPTR_ADDR_LO 0x3408 2447fb4d8502Sjsg #define DMA_BUSY_MASK 0x20 2448fb4d8502Sjsg #define DMA1_BUSY_MASK 0X40 2449fb4d8502Sjsg #define SDMA_MAX_INSTANCE 2 2450fb4d8502Sjsg 2451fb4d8502Sjsg #define PCIE_BUS_CLK 10000 2452fb4d8502Sjsg #define TCLK (PCIE_BUS_CLK / 10) 2453fb4d8502Sjsg #define PCIE_PORT_INDEX 0xe 2454fb4d8502Sjsg #define PCIE_PORT_DATA 0xf 2455fb4d8502Sjsg #define EVERGREEN_PIF_PHY0_INDEX 0x8 2456fb4d8502Sjsg #define EVERGREEN_PIF_PHY0_DATA 0xc 2457fb4d8502Sjsg #define EVERGREEN_PIF_PHY1_INDEX 0x10 2458fb4d8502Sjsg #define EVERGREEN_PIF_PHY1_DATA 0x14 2459fb4d8502Sjsg 2460fb4d8502Sjsg #define MC_VM_FB_OFFSET 0x81a 2461fb4d8502Sjsg 2462*ad8b1aafSjsg /* Discrete VCE clocks */ 2463*ad8b1aafSjsg #define CG_VCEPLL_FUNC_CNTL 0xc0030600 2464*ad8b1aafSjsg #define VCEPLL_RESET_MASK 0x00000001 2465*ad8b1aafSjsg #define VCEPLL_SLEEP_MASK 0x00000002 2466*ad8b1aafSjsg #define VCEPLL_BYPASS_EN_MASK 0x00000004 2467*ad8b1aafSjsg #define VCEPLL_CTLREQ_MASK 0x00000008 2468*ad8b1aafSjsg #define VCEPLL_VCO_MODE_MASK 0x00000600 2469*ad8b1aafSjsg #define VCEPLL_REF_DIV_MASK 0x003F0000 2470*ad8b1aafSjsg #define VCEPLL_CTLACK_MASK 0x40000000 2471*ad8b1aafSjsg #define VCEPLL_CTLACK2_MASK 0x80000000 2472*ad8b1aafSjsg 2473*ad8b1aafSjsg #define CG_VCEPLL_FUNC_CNTL_2 0xc0030601 2474*ad8b1aafSjsg #define VCEPLL_PDIV_A(x) ((x) << 0) 2475*ad8b1aafSjsg #define VCEPLL_PDIV_A_MASK 0x0000007F 2476*ad8b1aafSjsg #define VCEPLL_PDIV_B(x) ((x) << 8) 2477*ad8b1aafSjsg #define VCEPLL_PDIV_B_MASK 0x00007F00 2478*ad8b1aafSjsg #define EVCLK_SRC_SEL(x) ((x) << 20) 2479*ad8b1aafSjsg #define EVCLK_SRC_SEL_MASK 0x01F00000 2480*ad8b1aafSjsg #define ECCLK_SRC_SEL(x) ((x) << 25) 2481*ad8b1aafSjsg #define ECCLK_SRC_SEL_MASK 0x3E000000 2482*ad8b1aafSjsg 2483*ad8b1aafSjsg #define CG_VCEPLL_FUNC_CNTL_3 0xc0030602 2484*ad8b1aafSjsg #define VCEPLL_FB_DIV(x) ((x) << 0) 2485*ad8b1aafSjsg #define VCEPLL_FB_DIV_MASK 0x01FFFFFF 2486*ad8b1aafSjsg 2487*ad8b1aafSjsg #define CG_VCEPLL_FUNC_CNTL_4 0xc0030603 2488*ad8b1aafSjsg 2489*ad8b1aafSjsg #define CG_VCEPLL_FUNC_CNTL_5 0xc0030604 2490*ad8b1aafSjsg #define CG_VCEPLL_SPREAD_SPECTRUM 0xc0030606 2491*ad8b1aafSjsg #define VCEPLL_SSEN_MASK 0x00000001 2492*ad8b1aafSjsg 2493*ad8b1aafSjsg 2494fb4d8502Sjsg #endif 2495