1fb4d8502Sjsg /* 2fb4d8502Sjsg * Copyright 2014 Advanced Micro Devices, Inc. 3fb4d8502Sjsg * 4fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"), 6fb4d8502Sjsg * to deal in the Software without restriction, including without limitation 7fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions: 10fb4d8502Sjsg * 11fb4d8502Sjsg * The above copyright notice and this permission notice shall be included in 12fb4d8502Sjsg * all copies or substantial portions of the Software. 13fb4d8502Sjsg * 14fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15fb4d8502Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18fb4d8502Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19fb4d8502Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20fb4d8502Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21fb4d8502Sjsg * 22fb4d8502Sjsg */ 23fb4d8502Sjsg #ifndef VI_H 24fb4d8502Sjsg #define VI_H 25fb4d8502Sjsg 26fb4d8502Sjsg #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ 27fb4d8502Sjsg #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ 28fb4d8502Sjsg #define SDMA_MAX_INSTANCE 2 29fb4d8502Sjsg 30fb4d8502Sjsg #define KFD_VI_SDMA_QUEUE_OFFSET 0x80 /* not a register */ 31fb4d8502Sjsg 32fb4d8502Sjsg /* crtc instance offsets */ 33fb4d8502Sjsg #define CRTC0_REGISTER_OFFSET (0x1b9c - 0x1b9c) 34fb4d8502Sjsg #define CRTC1_REGISTER_OFFSET (0x1d9c - 0x1b9c) 35fb4d8502Sjsg #define CRTC2_REGISTER_OFFSET (0x1f9c - 0x1b9c) 36fb4d8502Sjsg #define CRTC3_REGISTER_OFFSET (0x419c - 0x1b9c) 37fb4d8502Sjsg #define CRTC4_REGISTER_OFFSET (0x439c - 0x1b9c) 38fb4d8502Sjsg #define CRTC5_REGISTER_OFFSET (0x459c - 0x1b9c) 39fb4d8502Sjsg #define CRTC6_REGISTER_OFFSET (0x479c - 0x1b9c) 40fb4d8502Sjsg 41fb4d8502Sjsg /* dig instance offsets */ 42fb4d8502Sjsg #define DIG0_REGISTER_OFFSET (0x4a00 - 0x4a00) 43fb4d8502Sjsg #define DIG1_REGISTER_OFFSET (0x4b00 - 0x4a00) 44fb4d8502Sjsg #define DIG2_REGISTER_OFFSET (0x4c00 - 0x4a00) 45fb4d8502Sjsg #define DIG3_REGISTER_OFFSET (0x4d00 - 0x4a00) 46fb4d8502Sjsg #define DIG4_REGISTER_OFFSET (0x4e00 - 0x4a00) 47fb4d8502Sjsg #define DIG5_REGISTER_OFFSET (0x4f00 - 0x4a00) 48fb4d8502Sjsg #define DIG6_REGISTER_OFFSET (0x5400 - 0x4a00) 49fb4d8502Sjsg #define DIG7_REGISTER_OFFSET (0x5600 - 0x4a00) 50fb4d8502Sjsg #define DIG8_REGISTER_OFFSET (0x5700 - 0x4a00) 51fb4d8502Sjsg 52fb4d8502Sjsg /* audio endpt instance offsets */ 53fb4d8502Sjsg #define AUD0_REGISTER_OFFSET (0x17a8 - 0x17a8) 54fb4d8502Sjsg #define AUD1_REGISTER_OFFSET (0x17ac - 0x17a8) 55fb4d8502Sjsg #define AUD2_REGISTER_OFFSET (0x17b0 - 0x17a8) 56fb4d8502Sjsg #define AUD3_REGISTER_OFFSET (0x17b4 - 0x17a8) 57fb4d8502Sjsg #define AUD4_REGISTER_OFFSET (0x17b8 - 0x17a8) 58fb4d8502Sjsg #define AUD5_REGISTER_OFFSET (0x17bc - 0x17a8) 59fb4d8502Sjsg #define AUD6_REGISTER_OFFSET (0x17c0 - 0x17a8) 60fb4d8502Sjsg #define AUD7_REGISTER_OFFSET (0x17c4 - 0x17a8) 61fb4d8502Sjsg 62fb4d8502Sjsg /* hpd instance offsets */ 63fb4d8502Sjsg #define HPD0_REGISTER_OFFSET (0x1898 - 0x1898) 64fb4d8502Sjsg #define HPD1_REGISTER_OFFSET (0x18a0 - 0x1898) 65fb4d8502Sjsg #define HPD2_REGISTER_OFFSET (0x18a8 - 0x1898) 66fb4d8502Sjsg #define HPD3_REGISTER_OFFSET (0x18b0 - 0x1898) 67fb4d8502Sjsg #define HPD4_REGISTER_OFFSET (0x18b8 - 0x1898) 68fb4d8502Sjsg #define HPD5_REGISTER_OFFSET (0x18c0 - 0x1898) 69fb4d8502Sjsg 70fb4d8502Sjsg #define PIPEID(x) ((x) << 0) 71fb4d8502Sjsg #define MEID(x) ((x) << 2) 72fb4d8502Sjsg #define VMID(x) ((x) << 4) 73fb4d8502Sjsg #define QUEUEID(x) ((x) << 8) 74fb4d8502Sjsg 75fb4d8502Sjsg #define MC_SEQ_MISC0__MT__MASK 0xf0000000 76fb4d8502Sjsg #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 77fb4d8502Sjsg #define MC_SEQ_MISC0__MT__DDR2 0x20000000 78fb4d8502Sjsg #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 79fb4d8502Sjsg #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 80fb4d8502Sjsg #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 81fb4d8502Sjsg #define MC_SEQ_MISC0__MT__HBM 0x60000000 82fb4d8502Sjsg #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 83fb4d8502Sjsg 84fb4d8502Sjsg /* 85fb4d8502Sjsg * PM4 86fb4d8502Sjsg */ 87fb4d8502Sjsg #define PACKET_TYPE0 0 88fb4d8502Sjsg #define PACKET_TYPE1 1 89fb4d8502Sjsg #define PACKET_TYPE2 2 90fb4d8502Sjsg #define PACKET_TYPE3 3 91fb4d8502Sjsg 92fb4d8502Sjsg #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 93fb4d8502Sjsg #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 94fb4d8502Sjsg #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) 95fb4d8502Sjsg #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 96fb4d8502Sjsg #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 97fb4d8502Sjsg ((reg) & 0xFFFF) | \ 98fb4d8502Sjsg ((n) & 0x3FFF) << 16) 99fb4d8502Sjsg #define CP_PACKET2 0x80000000 100fb4d8502Sjsg #define PACKET2_PAD_SHIFT 0 101fb4d8502Sjsg #define PACKET2_PAD_MASK (0x3fffffff << 0) 102fb4d8502Sjsg 103fb4d8502Sjsg #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 104fb4d8502Sjsg 105fb4d8502Sjsg #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 106fb4d8502Sjsg (((op) & 0xFF) << 8) | \ 107fb4d8502Sjsg ((n) & 0x3FFF) << 16) 108fb4d8502Sjsg 109fb4d8502Sjsg #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 110fb4d8502Sjsg 111fb4d8502Sjsg /* Packet 3 types */ 112fb4d8502Sjsg #define PACKET3_NOP 0x10 113fb4d8502Sjsg #define PACKET3_SET_BASE 0x11 114fb4d8502Sjsg #define PACKET3_BASE_INDEX(x) ((x) << 0) 115fb4d8502Sjsg #define CE_PARTITION_BASE 3 116fb4d8502Sjsg #define PACKET3_CLEAR_STATE 0x12 117fb4d8502Sjsg #define PACKET3_INDEX_BUFFER_SIZE 0x13 118fb4d8502Sjsg #define PACKET3_DISPATCH_DIRECT 0x15 119fb4d8502Sjsg #define PACKET3_DISPATCH_INDIRECT 0x16 120fb4d8502Sjsg #define PACKET3_ATOMIC_GDS 0x1D 121fb4d8502Sjsg #define PACKET3_ATOMIC_MEM 0x1E 122fb4d8502Sjsg #define PACKET3_OCCLUSION_QUERY 0x1F 123fb4d8502Sjsg #define PACKET3_SET_PREDICATION 0x20 124fb4d8502Sjsg #define PACKET3_REG_RMW 0x21 125fb4d8502Sjsg #define PACKET3_COND_EXEC 0x22 126fb4d8502Sjsg #define PACKET3_PRED_EXEC 0x23 127fb4d8502Sjsg #define PACKET3_DRAW_INDIRECT 0x24 128fb4d8502Sjsg #define PACKET3_DRAW_INDEX_INDIRECT 0x25 129fb4d8502Sjsg #define PACKET3_INDEX_BASE 0x26 130fb4d8502Sjsg #define PACKET3_DRAW_INDEX_2 0x27 131fb4d8502Sjsg #define PACKET3_CONTEXT_CONTROL 0x28 132fb4d8502Sjsg #define PACKET3_INDEX_TYPE 0x2A 133fb4d8502Sjsg #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 134fb4d8502Sjsg #define PACKET3_DRAW_INDEX_AUTO 0x2D 135fb4d8502Sjsg #define PACKET3_NUM_INSTANCES 0x2F 136fb4d8502Sjsg #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 137fb4d8502Sjsg #define PACKET3_INDIRECT_BUFFER_CONST 0x33 138fb4d8502Sjsg #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 139fb4d8502Sjsg #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 140fb4d8502Sjsg #define PACKET3_DRAW_PREAMBLE 0x36 141fb4d8502Sjsg #define PACKET3_WRITE_DATA 0x37 142fb4d8502Sjsg #define WRITE_DATA_DST_SEL(x) ((x) << 8) 143fb4d8502Sjsg /* 0 - register 144fb4d8502Sjsg * 1 - memory (sync - via GRBM) 145fb4d8502Sjsg * 2 - gl2 146fb4d8502Sjsg * 3 - gds 147fb4d8502Sjsg * 4 - reserved 148fb4d8502Sjsg * 5 - memory (async - direct) 149fb4d8502Sjsg */ 150fb4d8502Sjsg #define WR_ONE_ADDR (1 << 16) 151fb4d8502Sjsg #define WR_CONFIRM (1 << 20) 152fb4d8502Sjsg #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 153fb4d8502Sjsg /* 0 - LRU 154fb4d8502Sjsg * 1 - Stream 155fb4d8502Sjsg */ 156fb4d8502Sjsg #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 157fb4d8502Sjsg /* 0 - me 158fb4d8502Sjsg * 1 - pfp 159fb4d8502Sjsg * 2 - ce 160fb4d8502Sjsg */ 161fb4d8502Sjsg #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 162fb4d8502Sjsg #define PACKET3_MEM_SEMAPHORE 0x39 163fb4d8502Sjsg # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 164fb4d8502Sjsg # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 165fb4d8502Sjsg # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ 166fb4d8502Sjsg # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 167fb4d8502Sjsg # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 168fb4d8502Sjsg #define PACKET3_WAIT_REG_MEM 0x3C 169fb4d8502Sjsg #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 170fb4d8502Sjsg /* 0 - always 171fb4d8502Sjsg * 1 - < 172fb4d8502Sjsg * 2 - <= 173fb4d8502Sjsg * 3 - == 174fb4d8502Sjsg * 4 - != 175fb4d8502Sjsg * 5 - >= 176fb4d8502Sjsg * 6 - > 177fb4d8502Sjsg */ 178fb4d8502Sjsg #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 179fb4d8502Sjsg /* 0 - reg 180fb4d8502Sjsg * 1 - mem 181fb4d8502Sjsg */ 182fb4d8502Sjsg #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 183fb4d8502Sjsg /* 0 - wait_reg_mem 184fb4d8502Sjsg * 1 - wr_wait_wr_reg 185fb4d8502Sjsg */ 186fb4d8502Sjsg #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 187fb4d8502Sjsg /* 0 - me 188fb4d8502Sjsg * 1 - pfp 189fb4d8502Sjsg */ 190fb4d8502Sjsg #define PACKET3_INDIRECT_BUFFER 0x3F 191fb4d8502Sjsg #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) 192fb4d8502Sjsg #define INDIRECT_BUFFER_VALID (1 << 23) 193fb4d8502Sjsg #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 194fb4d8502Sjsg /* 0 - LRU 195fb4d8502Sjsg * 1 - Stream 196fb4d8502Sjsg * 2 - Bypass 197fb4d8502Sjsg */ 198fb4d8502Sjsg #define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) 199fb4d8502Sjsg #define PACKET3_COPY_DATA 0x40 200fb4d8502Sjsg #define PACKET3_PFP_SYNC_ME 0x42 201fb4d8502Sjsg #define PACKET3_SURFACE_SYNC 0x43 202fb4d8502Sjsg # define PACKET3_DEST_BASE_0_ENA (1 << 0) 203fb4d8502Sjsg # define PACKET3_DEST_BASE_1_ENA (1 << 1) 204fb4d8502Sjsg # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 205fb4d8502Sjsg # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 206fb4d8502Sjsg # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 207fb4d8502Sjsg # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 208fb4d8502Sjsg # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 209fb4d8502Sjsg # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 210fb4d8502Sjsg # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 211fb4d8502Sjsg # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 212fb4d8502Sjsg # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 213fb4d8502Sjsg # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) 214fb4d8502Sjsg # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ 215fb4d8502Sjsg # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ 216fb4d8502Sjsg # define PACKET3_DEST_BASE_2_ENA (1 << 19) 217fb4d8502Sjsg # define PACKET3_DEST_BASE_3_ENA (1 << 21) 218fb4d8502Sjsg # define PACKET3_TCL1_ACTION_ENA (1 << 22) 219fb4d8502Sjsg # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ 220fb4d8502Sjsg # define PACKET3_CB_ACTION_ENA (1 << 25) 221fb4d8502Sjsg # define PACKET3_DB_ACTION_ENA (1 << 26) 222fb4d8502Sjsg # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 223fb4d8502Sjsg # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) 224fb4d8502Sjsg # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 225fb4d8502Sjsg #define PACKET3_COND_WRITE 0x45 226fb4d8502Sjsg #define PACKET3_EVENT_WRITE 0x46 227fb4d8502Sjsg #define EVENT_TYPE(x) ((x) << 0) 228fb4d8502Sjsg #define EVENT_INDEX(x) ((x) << 8) 229fb4d8502Sjsg /* 0 - any non-TS event 230fb4d8502Sjsg * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 231fb4d8502Sjsg * 2 - SAMPLE_PIPELINESTAT 232fb4d8502Sjsg * 3 - SAMPLE_STREAMOUTSTAT* 233fb4d8502Sjsg * 4 - *S_PARTIAL_FLUSH 234fb4d8502Sjsg * 5 - EOP events 235fb4d8502Sjsg * 6 - EOS events 236fb4d8502Sjsg */ 237fb4d8502Sjsg #define PACKET3_EVENT_WRITE_EOP 0x47 238fb4d8502Sjsg #define EOP_TCL1_VOL_ACTION_EN (1 << 12) 239fb4d8502Sjsg #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 240fb4d8502Sjsg #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 241fb4d8502Sjsg #define EOP_TCL1_ACTION_EN (1 << 16) 242fb4d8502Sjsg #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 243fb4d8502Sjsg #define EOP_TCL2_VOLATILE (1 << 24) 244fb4d8502Sjsg #define EOP_CACHE_POLICY(x) ((x) << 25) 245fb4d8502Sjsg /* 0 - LRU 246fb4d8502Sjsg * 1 - Stream 247fb4d8502Sjsg * 2 - Bypass 248fb4d8502Sjsg */ 249fb4d8502Sjsg #define DATA_SEL(x) ((x) << 29) 250fb4d8502Sjsg /* 0 - discard 251fb4d8502Sjsg * 1 - send low 32bit data 252fb4d8502Sjsg * 2 - send 64bit data 253fb4d8502Sjsg * 3 - send 64bit GPU counter value 254fb4d8502Sjsg * 4 - send 64bit sys counter value 255fb4d8502Sjsg */ 256fb4d8502Sjsg #define INT_SEL(x) ((x) << 24) 257fb4d8502Sjsg /* 0 - none 258fb4d8502Sjsg * 1 - interrupt only (DATA_SEL = 0) 259fb4d8502Sjsg * 2 - interrupt when data write is confirmed 260fb4d8502Sjsg */ 261fb4d8502Sjsg #define DST_SEL(x) ((x) << 16) 262fb4d8502Sjsg /* 0 - MC 263fb4d8502Sjsg * 1 - TC/L2 264fb4d8502Sjsg */ 265fb4d8502Sjsg #define PACKET3_EVENT_WRITE_EOS 0x48 266fb4d8502Sjsg #define PACKET3_RELEASE_MEM 0x49 267fb4d8502Sjsg #define PACKET3_PREAMBLE_CNTL 0x4A 268fb4d8502Sjsg # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 269fb4d8502Sjsg # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 270fb4d8502Sjsg #define PACKET3_DMA_DATA 0x50 271fb4d8502Sjsg /* 1. header 272fb4d8502Sjsg * 2. CONTROL 273fb4d8502Sjsg * 3. SRC_ADDR_LO or DATA [31:0] 274fb4d8502Sjsg * 4. SRC_ADDR_HI [31:0] 275fb4d8502Sjsg * 5. DST_ADDR_LO [31:0] 276fb4d8502Sjsg * 6. DST_ADDR_HI [7:0] 277fb4d8502Sjsg * 7. COMMAND [30:21] | BYTE_COUNT [20:0] 278fb4d8502Sjsg */ 279fb4d8502Sjsg /* CONTROL */ 280fb4d8502Sjsg # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 281fb4d8502Sjsg /* 0 - ME 282fb4d8502Sjsg * 1 - PFP 283fb4d8502Sjsg */ 284fb4d8502Sjsg # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 285fb4d8502Sjsg /* 0 - LRU 286fb4d8502Sjsg * 1 - Stream 287fb4d8502Sjsg * 2 - Bypass 288fb4d8502Sjsg */ 289fb4d8502Sjsg # define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15) 290fb4d8502Sjsg # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 291fb4d8502Sjsg /* 0 - DST_ADDR using DAS 292fb4d8502Sjsg * 1 - GDS 293fb4d8502Sjsg * 3 - DST_ADDR using L2 294fb4d8502Sjsg */ 295fb4d8502Sjsg # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 296fb4d8502Sjsg /* 0 - LRU 297fb4d8502Sjsg * 1 - Stream 298fb4d8502Sjsg * 2 - Bypass 299fb4d8502Sjsg */ 300fb4d8502Sjsg # define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27) 301fb4d8502Sjsg # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 302fb4d8502Sjsg /* 0 - SRC_ADDR using SAS 303fb4d8502Sjsg * 1 - GDS 304fb4d8502Sjsg * 2 - DATA 305fb4d8502Sjsg * 3 - SRC_ADDR using L2 306fb4d8502Sjsg */ 307fb4d8502Sjsg # define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 308fb4d8502Sjsg /* COMMAND */ 309fb4d8502Sjsg # define PACKET3_DMA_DATA_DIS_WC (1 << 21) 310fb4d8502Sjsg # define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) 311fb4d8502Sjsg /* 0 - none 312fb4d8502Sjsg * 1 - 8 in 16 313fb4d8502Sjsg * 2 - 8 in 32 314fb4d8502Sjsg * 3 - 8 in 64 315fb4d8502Sjsg */ 316fb4d8502Sjsg # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) 317fb4d8502Sjsg /* 0 - none 318fb4d8502Sjsg * 1 - 8 in 16 319fb4d8502Sjsg * 2 - 8 in 32 320fb4d8502Sjsg * 3 - 8 in 64 321fb4d8502Sjsg */ 322fb4d8502Sjsg # define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 323fb4d8502Sjsg /* 0 - memory 324fb4d8502Sjsg * 1 - register 325fb4d8502Sjsg */ 326fb4d8502Sjsg # define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 327fb4d8502Sjsg /* 0 - memory 328fb4d8502Sjsg * 1 - register 329fb4d8502Sjsg */ 330fb4d8502Sjsg # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 331fb4d8502Sjsg # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 332fb4d8502Sjsg # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 333*ad8b1aafSjsg #define PACKET3_ACQUIRE_MEM 0x58 334fb4d8502Sjsg #define PACKET3_REWIND 0x59 335fb4d8502Sjsg #define PACKET3_LOAD_UCONFIG_REG 0x5E 336fb4d8502Sjsg #define PACKET3_LOAD_SH_REG 0x5F 337fb4d8502Sjsg #define PACKET3_LOAD_CONFIG_REG 0x60 338fb4d8502Sjsg #define PACKET3_LOAD_CONTEXT_REG 0x61 339fb4d8502Sjsg #define PACKET3_SET_CONFIG_REG 0x68 340fb4d8502Sjsg #define PACKET3_SET_CONFIG_REG_START 0x00002000 341fb4d8502Sjsg #define PACKET3_SET_CONFIG_REG_END 0x00002c00 342fb4d8502Sjsg #define PACKET3_SET_CONTEXT_REG 0x69 343fb4d8502Sjsg #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 344fb4d8502Sjsg #define PACKET3_SET_CONTEXT_REG_END 0x0000a400 345fb4d8502Sjsg #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 346fb4d8502Sjsg #define PACKET3_SET_SH_REG 0x76 347fb4d8502Sjsg #define PACKET3_SET_SH_REG_START 0x00002c00 348fb4d8502Sjsg #define PACKET3_SET_SH_REG_END 0x00003000 349fb4d8502Sjsg #define PACKET3_SET_SH_REG_OFFSET 0x77 350fb4d8502Sjsg #define PACKET3_SET_QUEUE_REG 0x78 351fb4d8502Sjsg #define PACKET3_SET_UCONFIG_REG 0x79 352fb4d8502Sjsg #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 353fb4d8502Sjsg #define PACKET3_SET_UCONFIG_REG_END 0x0000c400 354fb4d8502Sjsg #define PACKET3_SCRATCH_RAM_WRITE 0x7D 355fb4d8502Sjsg #define PACKET3_SCRATCH_RAM_READ 0x7E 356fb4d8502Sjsg #define PACKET3_LOAD_CONST_RAM 0x80 357fb4d8502Sjsg #define PACKET3_WRITE_CONST_RAM 0x81 358fb4d8502Sjsg #define PACKET3_DUMP_CONST_RAM 0x83 359fb4d8502Sjsg #define PACKET3_INCREMENT_CE_COUNTER 0x84 360fb4d8502Sjsg #define PACKET3_INCREMENT_DE_COUNTER 0x85 361fb4d8502Sjsg #define PACKET3_WAIT_ON_CE_COUNTER 0x86 362fb4d8502Sjsg #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 363fb4d8502Sjsg #define PACKET3_SWITCH_BUFFER 0x8B 364fb4d8502Sjsg #define PACKET3_FRAME_CONTROL 0x90 365fb4d8502Sjsg # define FRAME_CMD(x) ((x) << 28) 366fb4d8502Sjsg /* 367fb4d8502Sjsg * x=0: tmz_begin 368fb4d8502Sjsg * x=1: tmz_end 369fb4d8502Sjsg */ 370fb4d8502Sjsg #define PACKET3_SET_RESOURCES 0xA0 371fb4d8502Sjsg /* 1. header 372fb4d8502Sjsg * 2. CONTROL 373fb4d8502Sjsg * 3. QUEUE_MASK_LO [31:0] 374fb4d8502Sjsg * 4. QUEUE_MASK_HI [31:0] 375fb4d8502Sjsg * 5. GWS_MASK_LO [31:0] 376fb4d8502Sjsg * 6. GWS_MASK_HI [31:0] 377fb4d8502Sjsg * 7. OAC_MASK [15:0] 378fb4d8502Sjsg * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0] 379fb4d8502Sjsg */ 380fb4d8502Sjsg # define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) 381fb4d8502Sjsg # define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) 382fb4d8502Sjsg # define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) 383fb4d8502Sjsg #define PACKET3_MAP_QUEUES 0xA2 384fb4d8502Sjsg /* 1. header 385fb4d8502Sjsg * 2. CONTROL 386fb4d8502Sjsg * 3. CONTROL2 387fb4d8502Sjsg * 4. MQD_ADDR_LO [31:0] 388fb4d8502Sjsg * 5. MQD_ADDR_HI [31:0] 389fb4d8502Sjsg * 6. WPTR_ADDR_LO [31:0] 390fb4d8502Sjsg * 7. WPTR_ADDR_HI [31:0] 391fb4d8502Sjsg */ 392fb4d8502Sjsg /* CONTROL */ 393fb4d8502Sjsg # define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 394fb4d8502Sjsg # define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8) 395fb4d8502Sjsg # define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) 396fb4d8502Sjsg # define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24) 397fb4d8502Sjsg # define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 398fb4d8502Sjsg # define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 399fb4d8502Sjsg /* CONTROL2 */ 400fb4d8502Sjsg # define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1) 401fb4d8502Sjsg # define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) 402fb4d8502Sjsg # define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 26) 403fb4d8502Sjsg # define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 29) 404fb4d8502Sjsg # define PACKET3_MAP_QUEUES_ME(x) ((x) << 31) 405fb4d8502Sjsg #define PACKET3_UNMAP_QUEUES 0xA3 406fb4d8502Sjsg /* 1. header 407fb4d8502Sjsg * 2. CONTROL 408fb4d8502Sjsg * 3. CONTROL2 409fb4d8502Sjsg * 4. CONTROL3 410fb4d8502Sjsg * 5. CONTROL4 411fb4d8502Sjsg * 6. CONTROL5 412fb4d8502Sjsg */ 413fb4d8502Sjsg /* CONTROL */ 414fb4d8502Sjsg # define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0) 415fb4d8502Sjsg /* 0 - PREEMPT_QUEUES 416fb4d8502Sjsg * 1 - RESET_QUEUES 417fb4d8502Sjsg * 2 - DISABLE_PROCESS_QUEUES 418fb4d8502Sjsg * 3 - PREEMPT_QUEUES_NO_UNMAP 419fb4d8502Sjsg */ 420fb4d8502Sjsg # define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 421fb4d8502Sjsg # define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 422fb4d8502Sjsg # define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 423fb4d8502Sjsg /* CONTROL2a */ 424fb4d8502Sjsg # define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0) 425fb4d8502Sjsg /* CONTROL2b */ 426fb4d8502Sjsg # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2) 427fb4d8502Sjsg /* CONTROL3a */ 428fb4d8502Sjsg # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2) 429fb4d8502Sjsg /* CONTROL3b */ 430fb4d8502Sjsg # define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0) 431fb4d8502Sjsg /* CONTROL4 */ 432fb4d8502Sjsg # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2) 433fb4d8502Sjsg /* CONTROL5 */ 434fb4d8502Sjsg # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2) 435fb4d8502Sjsg #define PACKET3_QUERY_STATUS 0xA4 436fb4d8502Sjsg /* 1. header 437fb4d8502Sjsg * 2. CONTROL 438fb4d8502Sjsg * 3. CONTROL2 439fb4d8502Sjsg * 4. ADDR_LO [31:0] 440fb4d8502Sjsg * 5. ADDR_HI [31:0] 441fb4d8502Sjsg * 6. DATA_LO [31:0] 442fb4d8502Sjsg * 7. DATA_HI [31:0] 443fb4d8502Sjsg */ 444fb4d8502Sjsg /* CONTROL */ 445fb4d8502Sjsg # define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0) 446fb4d8502Sjsg # define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28) 447fb4d8502Sjsg # define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30) 448fb4d8502Sjsg /* CONTROL2a */ 449fb4d8502Sjsg # define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) 450fb4d8502Sjsg /* CONTROL2b */ 451fb4d8502Sjsg # define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) 452fb4d8502Sjsg # define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25) 453fb4d8502Sjsg 454fb4d8502Sjsg 455fb4d8502Sjsg #define VCE_CMD_NO_OP 0x00000000 456fb4d8502Sjsg #define VCE_CMD_END 0x00000001 457fb4d8502Sjsg #define VCE_CMD_IB 0x00000002 458fb4d8502Sjsg #define VCE_CMD_FENCE 0x00000003 459fb4d8502Sjsg #define VCE_CMD_TRAP 0x00000004 460fb4d8502Sjsg #define VCE_CMD_IB_AUTO 0x00000005 461fb4d8502Sjsg #define VCE_CMD_SEMAPHORE 0x00000006 462fb4d8502Sjsg 463fb4d8502Sjsg #define VCE_CMD_IB_VM 0x00000102 464fb4d8502Sjsg #define VCE_CMD_WAIT_GE 0x00000106 465fb4d8502Sjsg #define VCE_CMD_UPDATE_PTB 0x00000107 466fb4d8502Sjsg #define VCE_CMD_FLUSH_TLB 0x00000108 467fb4d8502Sjsg 468fb4d8502Sjsg /* HEVC ENC */ 469fb4d8502Sjsg #define HEVC_ENC_CMD_NO_OP 0x00000000 470fb4d8502Sjsg #define HEVC_ENC_CMD_END 0x00000001 471fb4d8502Sjsg #define HEVC_ENC_CMD_FENCE 0x00000003 472fb4d8502Sjsg #define HEVC_ENC_CMD_TRAP 0x00000004 473fb4d8502Sjsg #define HEVC_ENC_CMD_IB_VM 0x00000102 474fb4d8502Sjsg #define HEVC_ENC_CMD_WAIT_GE 0x00000106 475fb4d8502Sjsg #define HEVC_ENC_CMD_UPDATE_PTB 0x00000107 476fb4d8502Sjsg #define HEVC_ENC_CMD_FLUSH_TLB 0x00000108 477fb4d8502Sjsg 478fb4d8502Sjsg /* mmPA_SC_RASTER_CONFIG mask */ 479fb4d8502Sjsg #define RB_MAP_PKR0(x) ((x) << 0) 480fb4d8502Sjsg #define RB_MAP_PKR0_MASK (0x3 << 0) 481fb4d8502Sjsg #define RB_MAP_PKR1(x) ((x) << 2) 482fb4d8502Sjsg #define RB_MAP_PKR1_MASK (0x3 << 2) 483fb4d8502Sjsg #define RB_XSEL2(x) ((x) << 4) 484fb4d8502Sjsg #define RB_XSEL2_MASK (0x3 << 4) 485fb4d8502Sjsg #define RB_XSEL (1 << 6) 486fb4d8502Sjsg #define RB_YSEL (1 << 7) 487fb4d8502Sjsg #define PKR_MAP(x) ((x) << 8) 488fb4d8502Sjsg #define PKR_MAP_MASK (0x3 << 8) 489fb4d8502Sjsg #define PKR_XSEL(x) ((x) << 10) 490fb4d8502Sjsg #define PKR_XSEL_MASK (0x3 << 10) 491fb4d8502Sjsg #define PKR_YSEL(x) ((x) << 12) 492fb4d8502Sjsg #define PKR_YSEL_MASK (0x3 << 12) 493fb4d8502Sjsg #define SC_MAP(x) ((x) << 16) 494fb4d8502Sjsg #define SC_MAP_MASK (0x3 << 16) 495fb4d8502Sjsg #define SC_XSEL(x) ((x) << 18) 496fb4d8502Sjsg #define SC_XSEL_MASK (0x3 << 18) 497fb4d8502Sjsg #define SC_YSEL(x) ((x) << 20) 498fb4d8502Sjsg #define SC_YSEL_MASK (0x3 << 20) 499fb4d8502Sjsg #define SE_MAP(x) ((x) << 24) 500fb4d8502Sjsg #define SE_MAP_MASK (0x3 << 24) 501fb4d8502Sjsg #define SE_XSEL(x) ((x) << 26) 502fb4d8502Sjsg #define SE_XSEL_MASK (0x3 << 26) 503fb4d8502Sjsg #define SE_YSEL(x) ((x) << 28) 504fb4d8502Sjsg #define SE_YSEL_MASK (0x3 << 28) 505fb4d8502Sjsg 506fb4d8502Sjsg /* mmPA_SC_RASTER_CONFIG_1 mask */ 507fb4d8502Sjsg #define SE_PAIR_MAP(x) ((x) << 0) 508fb4d8502Sjsg #define SE_PAIR_MAP_MASK (0x3 << 0) 509fb4d8502Sjsg #define SE_PAIR_XSEL(x) ((x) << 2) 510fb4d8502Sjsg #define SE_PAIR_XSEL_MASK (0x3 << 2) 511fb4d8502Sjsg #define SE_PAIR_YSEL(x) ((x) << 4) 512fb4d8502Sjsg #define SE_PAIR_YSEL_MASK (0x3 << 4) 513fb4d8502Sjsg 514fb4d8502Sjsg #endif 515