1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/bsearch.h> 24 #include <linux/pci.h> 25 #include <linux/slab.h> 26 #include "kfd_priv.h" 27 #include "kfd_device_queue_manager.h" 28 #include "kfd_pm4_headers_vi.h" 29 #include "cwsr_trap_handler.h" 30 #include "kfd_iommu.h" 31 32 #define MQD_SIZE_ALIGNED 768 33 34 /* 35 * kfd_locked is used to lock the kfd driver during suspend or reset 36 * once locked, kfd driver will stop any further GPU execution. 37 * create process (open) will return -EAGAIN. 38 */ 39 static atomic_t kfd_locked = ATOMIC_INIT(0); 40 41 #ifdef KFD_SUPPORT_IOMMU_V2 42 static const struct kfd_device_info kaveri_device_info = { 43 .asic_family = CHIP_KAVERI, 44 .max_pasid_bits = 16, 45 /* max num of queues for KV.TODO should be a dynamic value */ 46 .max_no_of_hqd = 24, 47 .doorbell_size = 4, 48 .ih_ring_entry_size = 4 * sizeof(uint32_t), 49 .event_interrupt_class = &event_interrupt_class_cik, 50 .num_of_watch_points = 4, 51 .mqd_size_aligned = MQD_SIZE_ALIGNED, 52 .supports_cwsr = false, 53 .needs_iommu_device = true, 54 .needs_pci_atomics = false, 55 .num_sdma_engines = 2, 56 }; 57 58 static const struct kfd_device_info carrizo_device_info = { 59 .asic_family = CHIP_CARRIZO, 60 .max_pasid_bits = 16, 61 /* max num of queues for CZ.TODO should be a dynamic value */ 62 .max_no_of_hqd = 24, 63 .doorbell_size = 4, 64 .ih_ring_entry_size = 4 * sizeof(uint32_t), 65 .event_interrupt_class = &event_interrupt_class_cik, 66 .num_of_watch_points = 4, 67 .mqd_size_aligned = MQD_SIZE_ALIGNED, 68 .supports_cwsr = true, 69 .needs_iommu_device = true, 70 .needs_pci_atomics = false, 71 .num_sdma_engines = 2, 72 }; 73 74 static const struct kfd_device_info raven_device_info = { 75 .asic_family = CHIP_RAVEN, 76 .max_pasid_bits = 16, 77 .max_no_of_hqd = 24, 78 .doorbell_size = 8, 79 .ih_ring_entry_size = 8 * sizeof(uint32_t), 80 .event_interrupt_class = &event_interrupt_class_v9, 81 .num_of_watch_points = 4, 82 .mqd_size_aligned = MQD_SIZE_ALIGNED, 83 .supports_cwsr = true, 84 .needs_iommu_device = true, 85 .needs_pci_atomics = true, 86 .num_sdma_engines = 1, 87 }; 88 #endif 89 90 static const struct kfd_device_info hawaii_device_info = { 91 .asic_family = CHIP_HAWAII, 92 .max_pasid_bits = 16, 93 /* max num of queues for KV.TODO should be a dynamic value */ 94 .max_no_of_hqd = 24, 95 .doorbell_size = 4, 96 .ih_ring_entry_size = 4 * sizeof(uint32_t), 97 .event_interrupt_class = &event_interrupt_class_cik, 98 .num_of_watch_points = 4, 99 .mqd_size_aligned = MQD_SIZE_ALIGNED, 100 .supports_cwsr = false, 101 .needs_iommu_device = false, 102 .needs_pci_atomics = false, 103 .num_sdma_engines = 2, 104 }; 105 106 static const struct kfd_device_info tonga_device_info = { 107 .asic_family = CHIP_TONGA, 108 .max_pasid_bits = 16, 109 .max_no_of_hqd = 24, 110 .doorbell_size = 4, 111 .ih_ring_entry_size = 4 * sizeof(uint32_t), 112 .event_interrupt_class = &event_interrupt_class_cik, 113 .num_of_watch_points = 4, 114 .mqd_size_aligned = MQD_SIZE_ALIGNED, 115 .supports_cwsr = false, 116 .needs_iommu_device = false, 117 .needs_pci_atomics = true, 118 .num_sdma_engines = 2, 119 }; 120 121 static const struct kfd_device_info tonga_vf_device_info = { 122 .asic_family = CHIP_TONGA, 123 .max_pasid_bits = 16, 124 .max_no_of_hqd = 24, 125 .doorbell_size = 4, 126 .ih_ring_entry_size = 4 * sizeof(uint32_t), 127 .event_interrupt_class = &event_interrupt_class_cik, 128 .num_of_watch_points = 4, 129 .mqd_size_aligned = MQD_SIZE_ALIGNED, 130 .supports_cwsr = false, 131 .needs_iommu_device = false, 132 .needs_pci_atomics = false, 133 .num_sdma_engines = 2, 134 }; 135 136 static const struct kfd_device_info fiji_device_info = { 137 .asic_family = CHIP_FIJI, 138 .max_pasid_bits = 16, 139 .max_no_of_hqd = 24, 140 .doorbell_size = 4, 141 .ih_ring_entry_size = 4 * sizeof(uint32_t), 142 .event_interrupt_class = &event_interrupt_class_cik, 143 .num_of_watch_points = 4, 144 .mqd_size_aligned = MQD_SIZE_ALIGNED, 145 .supports_cwsr = true, 146 .needs_iommu_device = false, 147 .needs_pci_atomics = true, 148 .num_sdma_engines = 2, 149 }; 150 151 static const struct kfd_device_info fiji_vf_device_info = { 152 .asic_family = CHIP_FIJI, 153 .max_pasid_bits = 16, 154 .max_no_of_hqd = 24, 155 .doorbell_size = 4, 156 .ih_ring_entry_size = 4 * sizeof(uint32_t), 157 .event_interrupt_class = &event_interrupt_class_cik, 158 .num_of_watch_points = 4, 159 .mqd_size_aligned = MQD_SIZE_ALIGNED, 160 .supports_cwsr = true, 161 .needs_iommu_device = false, 162 .needs_pci_atomics = false, 163 .num_sdma_engines = 2, 164 }; 165 166 167 static const struct kfd_device_info polaris10_device_info = { 168 .asic_family = CHIP_POLARIS10, 169 .max_pasid_bits = 16, 170 .max_no_of_hqd = 24, 171 .doorbell_size = 4, 172 .ih_ring_entry_size = 4 * sizeof(uint32_t), 173 .event_interrupt_class = &event_interrupt_class_cik, 174 .num_of_watch_points = 4, 175 .mqd_size_aligned = MQD_SIZE_ALIGNED, 176 .supports_cwsr = true, 177 .needs_iommu_device = false, 178 .needs_pci_atomics = true, 179 .num_sdma_engines = 2, 180 }; 181 182 static const struct kfd_device_info polaris10_vf_device_info = { 183 .asic_family = CHIP_POLARIS10, 184 .max_pasid_bits = 16, 185 .max_no_of_hqd = 24, 186 .doorbell_size = 4, 187 .ih_ring_entry_size = 4 * sizeof(uint32_t), 188 .event_interrupt_class = &event_interrupt_class_cik, 189 .num_of_watch_points = 4, 190 .mqd_size_aligned = MQD_SIZE_ALIGNED, 191 .supports_cwsr = true, 192 .needs_iommu_device = false, 193 .needs_pci_atomics = false, 194 .num_sdma_engines = 2, 195 }; 196 197 static const struct kfd_device_info polaris11_device_info = { 198 .asic_family = CHIP_POLARIS11, 199 .max_pasid_bits = 16, 200 .max_no_of_hqd = 24, 201 .doorbell_size = 4, 202 .ih_ring_entry_size = 4 * sizeof(uint32_t), 203 .event_interrupt_class = &event_interrupt_class_cik, 204 .num_of_watch_points = 4, 205 .mqd_size_aligned = MQD_SIZE_ALIGNED, 206 .supports_cwsr = true, 207 .needs_iommu_device = false, 208 .needs_pci_atomics = true, 209 .num_sdma_engines = 2, 210 }; 211 212 static const struct kfd_device_info vega10_device_info = { 213 .asic_family = CHIP_VEGA10, 214 .max_pasid_bits = 16, 215 .max_no_of_hqd = 24, 216 .doorbell_size = 8, 217 .ih_ring_entry_size = 8 * sizeof(uint32_t), 218 .event_interrupt_class = &event_interrupt_class_v9, 219 .num_of_watch_points = 4, 220 .mqd_size_aligned = MQD_SIZE_ALIGNED, 221 .supports_cwsr = true, 222 .needs_iommu_device = false, 223 .needs_pci_atomics = false, 224 .num_sdma_engines = 2, 225 }; 226 227 static const struct kfd_device_info vega10_vf_device_info = { 228 .asic_family = CHIP_VEGA10, 229 .max_pasid_bits = 16, 230 .max_no_of_hqd = 24, 231 .doorbell_size = 8, 232 .ih_ring_entry_size = 8 * sizeof(uint32_t), 233 .event_interrupt_class = &event_interrupt_class_v9, 234 .num_of_watch_points = 4, 235 .mqd_size_aligned = MQD_SIZE_ALIGNED, 236 .supports_cwsr = true, 237 .needs_iommu_device = false, 238 .needs_pci_atomics = false, 239 .num_sdma_engines = 2, 240 }; 241 242 243 struct kfd_deviceid { 244 unsigned short did; 245 const struct kfd_device_info *device_info; 246 }; 247 248 static const struct kfd_deviceid supported_devices[] = { 249 #ifdef KFD_SUPPORT_IOMMU_V2 250 { 0x1304, &kaveri_device_info }, /* Kaveri */ 251 { 0x1305, &kaveri_device_info }, /* Kaveri */ 252 { 0x1306, &kaveri_device_info }, /* Kaveri */ 253 { 0x1307, &kaveri_device_info }, /* Kaveri */ 254 { 0x1309, &kaveri_device_info }, /* Kaveri */ 255 { 0x130A, &kaveri_device_info }, /* Kaveri */ 256 { 0x130B, &kaveri_device_info }, /* Kaveri */ 257 { 0x130C, &kaveri_device_info }, /* Kaveri */ 258 { 0x130D, &kaveri_device_info }, /* Kaveri */ 259 { 0x130E, &kaveri_device_info }, /* Kaveri */ 260 { 0x130F, &kaveri_device_info }, /* Kaveri */ 261 { 0x1310, &kaveri_device_info }, /* Kaveri */ 262 { 0x1311, &kaveri_device_info }, /* Kaveri */ 263 { 0x1312, &kaveri_device_info }, /* Kaveri */ 264 { 0x1313, &kaveri_device_info }, /* Kaveri */ 265 { 0x1315, &kaveri_device_info }, /* Kaveri */ 266 { 0x1316, &kaveri_device_info }, /* Kaveri */ 267 { 0x1317, &kaveri_device_info }, /* Kaveri */ 268 { 0x1318, &kaveri_device_info }, /* Kaveri */ 269 { 0x131B, &kaveri_device_info }, /* Kaveri */ 270 { 0x131C, &kaveri_device_info }, /* Kaveri */ 271 { 0x131D, &kaveri_device_info }, /* Kaveri */ 272 { 0x9870, &carrizo_device_info }, /* Carrizo */ 273 { 0x9874, &carrizo_device_info }, /* Carrizo */ 274 { 0x9875, &carrizo_device_info }, /* Carrizo */ 275 { 0x9876, &carrizo_device_info }, /* Carrizo */ 276 { 0x9877, &carrizo_device_info }, /* Carrizo */ 277 { 0x15DD, &raven_device_info }, /* Raven */ 278 #endif 279 { 0x67A0, &hawaii_device_info }, /* Hawaii */ 280 { 0x67A1, &hawaii_device_info }, /* Hawaii */ 281 { 0x67A2, &hawaii_device_info }, /* Hawaii */ 282 { 0x67A8, &hawaii_device_info }, /* Hawaii */ 283 { 0x67A9, &hawaii_device_info }, /* Hawaii */ 284 { 0x67AA, &hawaii_device_info }, /* Hawaii */ 285 { 0x67B0, &hawaii_device_info }, /* Hawaii */ 286 { 0x67B1, &hawaii_device_info }, /* Hawaii */ 287 { 0x67B8, &hawaii_device_info }, /* Hawaii */ 288 { 0x67B9, &hawaii_device_info }, /* Hawaii */ 289 { 0x67BA, &hawaii_device_info }, /* Hawaii */ 290 { 0x67BE, &hawaii_device_info }, /* Hawaii */ 291 { 0x6920, &tonga_device_info }, /* Tonga */ 292 { 0x6921, &tonga_device_info }, /* Tonga */ 293 { 0x6928, &tonga_device_info }, /* Tonga */ 294 { 0x6929, &tonga_device_info }, /* Tonga */ 295 { 0x692B, &tonga_device_info }, /* Tonga */ 296 { 0x692F, &tonga_vf_device_info }, /* Tonga vf */ 297 { 0x6938, &tonga_device_info }, /* Tonga */ 298 { 0x6939, &tonga_device_info }, /* Tonga */ 299 { 0x7300, &fiji_device_info }, /* Fiji */ 300 { 0x730F, &fiji_vf_device_info }, /* Fiji vf*/ 301 { 0x67C0, &polaris10_device_info }, /* Polaris10 */ 302 { 0x67C1, &polaris10_device_info }, /* Polaris10 */ 303 { 0x67C2, &polaris10_device_info }, /* Polaris10 */ 304 { 0x67C4, &polaris10_device_info }, /* Polaris10 */ 305 { 0x67C7, &polaris10_device_info }, /* Polaris10 */ 306 { 0x67C8, &polaris10_device_info }, /* Polaris10 */ 307 { 0x67C9, &polaris10_device_info }, /* Polaris10 */ 308 { 0x67CA, &polaris10_device_info }, /* Polaris10 */ 309 { 0x67CC, &polaris10_device_info }, /* Polaris10 */ 310 { 0x67CF, &polaris10_device_info }, /* Polaris10 */ 311 { 0x67D0, &polaris10_vf_device_info }, /* Polaris10 vf*/ 312 { 0x67DF, &polaris10_device_info }, /* Polaris10 */ 313 { 0x67E0, &polaris11_device_info }, /* Polaris11 */ 314 { 0x67E1, &polaris11_device_info }, /* Polaris11 */ 315 { 0x67E3, &polaris11_device_info }, /* Polaris11 */ 316 { 0x67E7, &polaris11_device_info }, /* Polaris11 */ 317 { 0x67E8, &polaris11_device_info }, /* Polaris11 */ 318 { 0x67E9, &polaris11_device_info }, /* Polaris11 */ 319 { 0x67EB, &polaris11_device_info }, /* Polaris11 */ 320 { 0x67EF, &polaris11_device_info }, /* Polaris11 */ 321 { 0x67FF, &polaris11_device_info }, /* Polaris11 */ 322 { 0x6860, &vega10_device_info }, /* Vega10 */ 323 { 0x6861, &vega10_device_info }, /* Vega10 */ 324 { 0x6862, &vega10_device_info }, /* Vega10 */ 325 { 0x6863, &vega10_device_info }, /* Vega10 */ 326 { 0x6864, &vega10_device_info }, /* Vega10 */ 327 { 0x6867, &vega10_device_info }, /* Vega10 */ 328 { 0x6868, &vega10_device_info }, /* Vega10 */ 329 { 0x6869, &vega10_device_info }, /* Vega10 */ 330 { 0x686A, &vega10_device_info }, /* Vega10 */ 331 { 0x686B, &vega10_device_info }, /* Vega10 */ 332 { 0x686C, &vega10_vf_device_info }, /* Vega10 vf*/ 333 { 0x686D, &vega10_device_info }, /* Vega10 */ 334 { 0x686E, &vega10_device_info }, /* Vega10 */ 335 { 0x686F, &vega10_device_info }, /* Vega10 */ 336 { 0x687F, &vega10_device_info }, /* Vega10 */ 337 }; 338 339 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 340 unsigned int chunk_size); 341 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 342 343 static int kfd_resume(struct kfd_dev *kfd); 344 345 static const struct kfd_device_info *lookup_device_info(unsigned short did) 346 { 347 size_t i; 348 349 for (i = 0; i < ARRAY_SIZE(supported_devices); i++) { 350 if (supported_devices[i].did == did) { 351 WARN_ON(!supported_devices[i].device_info); 352 return supported_devices[i].device_info; 353 } 354 } 355 356 dev_warn(kfd_device, "DID %04x is missing in supported_devices\n", 357 did); 358 359 return NULL; 360 } 361 362 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, 363 struct pci_dev *pdev, const struct kfd2kgd_calls *f2g) 364 { 365 struct kfd_dev *kfd; 366 int ret; 367 const struct kfd_device_info *device_info = 368 lookup_device_info(pdev->device); 369 370 if (!device_info) { 371 dev_err(kfd_device, "kgd2kfd_probe failed\n"); 372 return NULL; 373 } 374 375 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 376 * 32 and 64-bit requests are possible and must be 377 * supported. 378 */ 379 ret = pci_enable_atomic_ops_to_root(pdev, 380 PCI_EXP_DEVCAP2_ATOMIC_COMP32 | 381 PCI_EXP_DEVCAP2_ATOMIC_COMP64); 382 if (device_info->needs_pci_atomics && ret < 0) { 383 dev_info(kfd_device, 384 "skipped device %x:%x, PCI rejects atomics\n", 385 pdev->vendor, pdev->device); 386 return NULL; 387 } 388 389 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 390 if (!kfd) 391 return NULL; 392 393 kfd->kgd = kgd; 394 kfd->device_info = device_info; 395 kfd->pdev = pdev; 396 kfd->init_complete = false; 397 kfd->kfd2kgd = f2g; 398 399 rw_init(&kfd->doorbell_mutex, "kfddb"); 400 memset(&kfd->doorbell_available_index, 0, 401 sizeof(kfd->doorbell_available_index)); 402 403 return kfd; 404 } 405 406 static void kfd_cwsr_init(struct kfd_dev *kfd) 407 { 408 if (cwsr_enable && kfd->device_info->supports_cwsr) { 409 if (kfd->device_info->asic_family < CHIP_VEGA10) { 410 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 411 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 412 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 413 } else { 414 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 415 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 416 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 417 } 418 419 kfd->cwsr_enabled = true; 420 } 421 } 422 423 bool kgd2kfd_device_init(struct kfd_dev *kfd, 424 const struct kgd2kfd_shared_resources *gpu_resources) 425 { 426 unsigned int size; 427 428 kfd->shared_resources = *gpu_resources; 429 430 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 431 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 432 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 433 - kfd->vm_info.first_vmid_kfd + 1; 434 435 /* Verify module parameters regarding mapped process number*/ 436 if ((hws_max_conc_proc < 0) 437 || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) { 438 dev_err(kfd_device, 439 "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n", 440 hws_max_conc_proc, kfd->vm_info.vmid_num_kfd, 441 kfd->vm_info.vmid_num_kfd); 442 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 443 } else 444 kfd->max_proc_per_quantum = hws_max_conc_proc; 445 446 /* calculate max size of mqds needed for queues */ 447 size = max_num_of_queues_per_device * 448 kfd->device_info->mqd_size_aligned; 449 450 /* 451 * calculate max size of runlist packet. 452 * There can be only 2 packets at once 453 */ 454 size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_mes_map_process) + 455 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 456 + sizeof(struct pm4_mes_runlist)) * 2; 457 458 /* Add size of HIQ & DIQ */ 459 size += KFD_KERNEL_QUEUE_SIZE * 2; 460 461 /* add another 512KB for all other allocations on gart (HPD, fences) */ 462 size += 512 * 1024; 463 464 if (kfd->kfd2kgd->init_gtt_mem_allocation( 465 kfd->kgd, size, &kfd->gtt_mem, 466 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 467 false)) { 468 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 469 goto out; 470 } 471 472 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 473 474 /* Initialize GTT sa with 512 byte chunk size */ 475 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 476 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 477 goto kfd_gtt_sa_init_error; 478 } 479 480 if (kfd_doorbell_init(kfd)) { 481 dev_err(kfd_device, 482 "Error initializing doorbell aperture\n"); 483 goto kfd_doorbell_error; 484 } 485 486 if (kfd_topology_add_device(kfd)) { 487 dev_err(kfd_device, "Error adding device to topology\n"); 488 goto kfd_topology_add_device_error; 489 } 490 491 if (kfd_interrupt_init(kfd)) { 492 dev_err(kfd_device, "Error initializing interrupts\n"); 493 goto kfd_interrupt_error; 494 } 495 496 kfd->dqm = device_queue_manager_init(kfd); 497 if (!kfd->dqm) { 498 dev_err(kfd_device, "Error initializing queue manager\n"); 499 goto device_queue_manager_error; 500 } 501 502 if (kfd_iommu_device_init(kfd)) { 503 dev_err(kfd_device, "Error initializing iommuv2\n"); 504 goto device_iommu_error; 505 } 506 507 kfd_cwsr_init(kfd); 508 509 if (kfd_resume(kfd)) 510 goto kfd_resume_error; 511 512 kfd->dbgmgr = NULL; 513 514 kfd->init_complete = true; 515 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor, 516 kfd->pdev->device); 517 518 pr_debug("Starting kfd with the following scheduling policy %d\n", 519 kfd->dqm->sched_policy); 520 521 goto out; 522 523 kfd_resume_error: 524 device_iommu_error: 525 device_queue_manager_uninit(kfd->dqm); 526 device_queue_manager_error: 527 kfd_interrupt_exit(kfd); 528 kfd_interrupt_error: 529 kfd_topology_remove_device(kfd); 530 kfd_topology_add_device_error: 531 kfd_doorbell_fini(kfd); 532 kfd_doorbell_error: 533 kfd_gtt_sa_fini(kfd); 534 kfd_gtt_sa_init_error: 535 kfd->kfd2kgd->free_gtt_mem(kfd->kgd, kfd->gtt_mem); 536 dev_err(kfd_device, 537 "device %x:%x NOT added due to errors\n", 538 kfd->pdev->vendor, kfd->pdev->device); 539 out: 540 return kfd->init_complete; 541 } 542 543 void kgd2kfd_device_exit(struct kfd_dev *kfd) 544 { 545 if (kfd->init_complete) { 546 kgd2kfd_suspend(kfd); 547 device_queue_manager_uninit(kfd->dqm); 548 kfd_interrupt_exit(kfd); 549 kfd_topology_remove_device(kfd); 550 kfd_doorbell_fini(kfd); 551 kfd_gtt_sa_fini(kfd); 552 kfd->kfd2kgd->free_gtt_mem(kfd->kgd, kfd->gtt_mem); 553 } 554 555 kfree(kfd); 556 } 557 558 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 559 { 560 if (!kfd->init_complete) 561 return 0; 562 kgd2kfd_suspend(kfd); 563 564 /* hold dqm->lock to prevent further execution*/ 565 dqm_lock(kfd->dqm); 566 567 kfd_signal_reset_event(kfd); 568 return 0; 569 } 570 571 /* 572 * Fix me. KFD won't be able to resume existing process for now. 573 * We will keep all existing process in a evicted state and 574 * wait the process to be terminated. 575 */ 576 577 int kgd2kfd_post_reset(struct kfd_dev *kfd) 578 { 579 int ret, count; 580 581 if (!kfd->init_complete) 582 return 0; 583 584 dqm_unlock(kfd->dqm); 585 586 ret = kfd_resume(kfd); 587 if (ret) 588 return ret; 589 count = atomic_dec_return(&kfd_locked); 590 WARN_ONCE(count != 0, "KFD reset ref. error"); 591 return 0; 592 } 593 594 bool kfd_is_locked(void) 595 { 596 return (atomic_read(&kfd_locked) > 0); 597 } 598 599 void kgd2kfd_suspend(struct kfd_dev *kfd) 600 { 601 if (!kfd->init_complete) 602 return; 603 604 /* For first KFD device suspend all the KFD processes */ 605 if (atomic_inc_return(&kfd_locked) == 1) 606 kfd_suspend_all_processes(); 607 608 kfd->dqm->ops.stop(kfd->dqm); 609 610 kfd_iommu_suspend(kfd); 611 } 612 613 int kgd2kfd_resume(struct kfd_dev *kfd) 614 { 615 int ret, count; 616 617 if (!kfd->init_complete) 618 return 0; 619 620 ret = kfd_resume(kfd); 621 if (ret) 622 return ret; 623 624 count = atomic_dec_return(&kfd_locked); 625 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 626 if (count == 0) 627 ret = kfd_resume_all_processes(); 628 629 return ret; 630 } 631 632 static int kfd_resume(struct kfd_dev *kfd) 633 { 634 int err = 0; 635 636 err = kfd_iommu_resume(kfd); 637 if (err) { 638 dev_err(kfd_device, 639 "Failed to resume IOMMU for device %x:%x\n", 640 kfd->pdev->vendor, kfd->pdev->device); 641 return err; 642 } 643 644 err = kfd->dqm->ops.start(kfd->dqm); 645 if (err) { 646 dev_err(kfd_device, 647 "Error starting queue manager for device %x:%x\n", 648 kfd->pdev->vendor, kfd->pdev->device); 649 goto dqm_start_error; 650 } 651 652 return err; 653 654 dqm_start_error: 655 kfd_iommu_suspend(kfd); 656 return err; 657 } 658 659 /* This is called directly from KGD at ISR. */ 660 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 661 { 662 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 663 bool is_patched = false; 664 unsigned long flags; 665 666 if (!kfd->init_complete) 667 return; 668 669 if (kfd->device_info->ih_ring_entry_size > sizeof(patched_ihre)) { 670 dev_err_once(kfd_device, "Ring entry too small\n"); 671 return; 672 } 673 674 spin_lock_irqsave(&kfd->interrupt_lock, flags); 675 676 if (kfd->interrupts_active 677 && interrupt_is_wanted(kfd, ih_ring_entry, 678 patched_ihre, &is_patched) 679 && enqueue_ih_ring_entry(kfd, 680 is_patched ? patched_ihre : ih_ring_entry)) 681 queue_work(kfd->ih_wq, &kfd->interrupt_work); 682 683 spin_unlock_irqrestore(&kfd->interrupt_lock, flags); 684 } 685 686 int kgd2kfd_quiesce_mm(struct mm_struct *mm) 687 { 688 struct kfd_process *p; 689 int r; 690 691 /* Because we are called from arbitrary context (workqueue) as opposed 692 * to process context, kfd_process could attempt to exit while we are 693 * running so the lookup function increments the process ref count. 694 */ 695 p = kfd_lookup_process_by_mm(mm); 696 if (!p) 697 return -ESRCH; 698 699 r = kfd_process_evict_queues(p); 700 701 kfd_unref_process(p); 702 return r; 703 } 704 705 int kgd2kfd_resume_mm(struct mm_struct *mm) 706 { 707 struct kfd_process *p; 708 int r; 709 710 /* Because we are called from arbitrary context (workqueue) as opposed 711 * to process context, kfd_process could attempt to exit while we are 712 * running so the lookup function increments the process ref count. 713 */ 714 p = kfd_lookup_process_by_mm(mm); 715 if (!p) 716 return -ESRCH; 717 718 r = kfd_process_restore_queues(p); 719 720 kfd_unref_process(p); 721 return r; 722 } 723 724 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 725 * prepare for safe eviction of KFD BOs that belong to the specified 726 * process. 727 * 728 * @mm: mm_struct that identifies the specified KFD process 729 * @fence: eviction fence attached to KFD process BOs 730 * 731 */ 732 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 733 struct dma_fence *fence) 734 { 735 struct kfd_process *p; 736 unsigned long active_time; 737 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 738 739 if (!fence) 740 return -EINVAL; 741 742 if (dma_fence_is_signaled(fence)) 743 return 0; 744 745 p = kfd_lookup_process_by_mm(mm); 746 if (!p) 747 return -ENODEV; 748 749 if (fence->seqno == p->last_eviction_seqno) 750 goto out; 751 752 p->last_eviction_seqno = fence->seqno; 753 754 /* Avoid KFD process starvation. Wait for at least 755 * PROCESS_ACTIVE_TIME_MS before evicting the process again 756 */ 757 active_time = get_jiffies_64() - p->last_restore_timestamp; 758 if (delay_jiffies > active_time) 759 delay_jiffies -= active_time; 760 else 761 delay_jiffies = 0; 762 763 /* During process initialization eviction_work.dwork is initialized 764 * to kfd_evict_bo_worker 765 */ 766 schedule_delayed_work(&p->eviction_work, delay_jiffies); 767 out: 768 kfd_unref_process(p); 769 return 0; 770 } 771 772 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 773 unsigned int chunk_size) 774 { 775 unsigned int num_of_longs; 776 777 if (WARN_ON(buf_size < chunk_size)) 778 return -EINVAL; 779 if (WARN_ON(buf_size == 0)) 780 return -EINVAL; 781 if (WARN_ON(chunk_size == 0)) 782 return -EINVAL; 783 784 kfd->gtt_sa_chunk_size = chunk_size; 785 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 786 787 num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) / 788 BITS_PER_LONG; 789 790 kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL); 791 792 if (!kfd->gtt_sa_bitmap) 793 return -ENOMEM; 794 795 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 796 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 797 798 rw_init(&kfd->gtt_sa_lock, "gttsa"); 799 800 return 0; 801 802 } 803 804 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 805 { 806 mutex_destroy(&kfd->gtt_sa_lock); 807 kfree(kfd->gtt_sa_bitmap); 808 } 809 810 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 811 unsigned int bit_num, 812 unsigned int chunk_size) 813 { 814 return start_addr + bit_num * chunk_size; 815 } 816 817 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 818 unsigned int bit_num, 819 unsigned int chunk_size) 820 { 821 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 822 } 823 824 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 825 struct kfd_mem_obj **mem_obj) 826 { 827 unsigned int found, start_search, cur_size; 828 829 if (size == 0) 830 return -EINVAL; 831 832 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 833 return -ENOMEM; 834 835 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 836 if (!(*mem_obj)) 837 return -ENOMEM; 838 839 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 840 841 start_search = 0; 842 843 mutex_lock(&kfd->gtt_sa_lock); 844 845 kfd_gtt_restart_search: 846 /* Find the first chunk that is free */ 847 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 848 kfd->gtt_sa_num_of_chunks, 849 start_search); 850 851 pr_debug("Found = %d\n", found); 852 853 /* If there wasn't any free chunk, bail out */ 854 if (found == kfd->gtt_sa_num_of_chunks) 855 goto kfd_gtt_no_free_chunk; 856 857 /* Update fields of mem_obj */ 858 (*mem_obj)->range_start = found; 859 (*mem_obj)->range_end = found; 860 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 861 kfd->gtt_start_gpu_addr, 862 found, 863 kfd->gtt_sa_chunk_size); 864 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 865 kfd->gtt_start_cpu_ptr, 866 found, 867 kfd->gtt_sa_chunk_size); 868 869 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 870 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 871 872 /* If we need only one chunk, mark it as allocated and get out */ 873 if (size <= kfd->gtt_sa_chunk_size) { 874 pr_debug("Single bit\n"); 875 set_bit(found, kfd->gtt_sa_bitmap); 876 goto kfd_gtt_out; 877 } 878 879 /* Otherwise, try to see if we have enough contiguous chunks */ 880 cur_size = size - kfd->gtt_sa_chunk_size; 881 do { 882 (*mem_obj)->range_end = 883 find_next_zero_bit(kfd->gtt_sa_bitmap, 884 kfd->gtt_sa_num_of_chunks, ++found); 885 /* 886 * If next free chunk is not contiguous than we need to 887 * restart our search from the last free chunk we found (which 888 * wasn't contiguous to the previous ones 889 */ 890 if ((*mem_obj)->range_end != found) { 891 start_search = found; 892 goto kfd_gtt_restart_search; 893 } 894 895 /* 896 * If we reached end of buffer, bail out with error 897 */ 898 if (found == kfd->gtt_sa_num_of_chunks) 899 goto kfd_gtt_no_free_chunk; 900 901 /* Check if we don't need another chunk */ 902 if (cur_size <= kfd->gtt_sa_chunk_size) 903 cur_size = 0; 904 else 905 cur_size -= kfd->gtt_sa_chunk_size; 906 907 } while (cur_size > 0); 908 909 pr_debug("range_start = %d, range_end = %d\n", 910 (*mem_obj)->range_start, (*mem_obj)->range_end); 911 912 /* Mark the chunks as allocated */ 913 for (found = (*mem_obj)->range_start; 914 found <= (*mem_obj)->range_end; 915 found++) 916 set_bit(found, kfd->gtt_sa_bitmap); 917 918 kfd_gtt_out: 919 mutex_unlock(&kfd->gtt_sa_lock); 920 return 0; 921 922 kfd_gtt_no_free_chunk: 923 pr_debug("Allocation failed with mem_obj = %p\n", mem_obj); 924 mutex_unlock(&kfd->gtt_sa_lock); 925 kfree(mem_obj); 926 return -ENOMEM; 927 } 928 929 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 930 { 931 unsigned int bit; 932 933 /* Act like kfree when trying to free a NULL object */ 934 if (!mem_obj) 935 return 0; 936 937 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 938 mem_obj, mem_obj->range_start, mem_obj->range_end); 939 940 mutex_lock(&kfd->gtt_sa_lock); 941 942 /* Mark the chunks as free */ 943 for (bit = mem_obj->range_start; 944 bit <= mem_obj->range_end; 945 bit++) 946 clear_bit(bit, kfd->gtt_sa_bitmap); 947 948 mutex_unlock(&kfd->gtt_sa_lock); 949 950 kfree(mem_obj); 951 return 0; 952 } 953 954 #if defined(CONFIG_DEBUG_FS) 955 956 /* This function will send a package to HIQ to hang the HWS 957 * which will trigger a GPU reset and bring the HWS back to normal state 958 */ 959 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 960 { 961 int r = 0; 962 963 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 964 pr_err("HWS is not enabled"); 965 return -EINVAL; 966 } 967 968 r = pm_debugfs_hang_hws(&dev->dqm->packets); 969 if (!r) 970 r = dqm_debugfs_execute_queues(dev->dqm); 971 972 return r; 973 } 974 975 #endif 976