1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 */ 24 25 #include "dm_services.h" 26 27 #include "dc.h" 28 29 #include "core_status.h" 30 #include "core_types.h" 31 #include "hw_sequencer.h" 32 #include "dce/dce_hwseq.h" 33 34 #include "resource.h" 35 36 #include "clk_mgr.h" 37 #include "clock_source.h" 38 #include "dc_bios_types.h" 39 40 #include "bios_parser_interface.h" 41 #include "bios/bios_parser_helper.h" 42 #include "include/irq_service_interface.h" 43 #include "transform.h" 44 #include "dmcu.h" 45 #include "dpp.h" 46 #include "timing_generator.h" 47 #include "abm.h" 48 #include "virtual/virtual_link_encoder.h" 49 #include "hubp.h" 50 51 #include "link_hwss.h" 52 #include "link_encoder.h" 53 #include "link_enc_cfg.h" 54 55 #include "dc_link.h" 56 #include "dc_link_ddc.h" 57 #include "dm_helpers.h" 58 #include "mem_input.h" 59 60 #include "dc_link_dp.h" 61 #include "dc_dmub_srv.h" 62 63 #include "dsc.h" 64 65 #include "vm_helper.h" 66 67 #include "dce/dce_i2c.h" 68 69 #include "dmub/dmub_srv.h" 70 71 #include "i2caux_interface.h" 72 73 #include "dce/dmub_psr.h" 74 75 #include "dce/dmub_hw_lock_mgr.h" 76 77 #include "dc_trace.h" 78 79 #include "dce/dmub_outbox.h" 80 81 #define CTX \ 82 dc->ctx 83 84 #define DC_LOGGER \ 85 dc->ctx->logger 86 87 static const char DC_BUILD_ID[] = "production-build"; 88 89 /** 90 * DOC: Overview 91 * 92 * DC is the OS-agnostic component of the amdgpu DC driver. 93 * 94 * DC maintains and validates a set of structs representing the state of the 95 * driver and writes that state to AMD hardware 96 * 97 * Main DC HW structs: 98 * 99 * struct dc - The central struct. One per driver. Created on driver load, 100 * destroyed on driver unload. 101 * 102 * struct dc_context - One per driver. 103 * Used as a backpointer by most other structs in dc. 104 * 105 * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP 106 * plugpoints). Created on driver load, destroyed on driver unload. 107 * 108 * struct dc_sink - One per display. Created on boot or hotplug. 109 * Destroyed on shutdown or hotunplug. A dc_link can have a local sink 110 * (the display directly attached). It may also have one or more remote 111 * sinks (in the Multi-Stream Transport case) 112 * 113 * struct resource_pool - One per driver. Represents the hw blocks not in the 114 * main pipeline. Not directly accessible by dm. 115 * 116 * Main dc state structs: 117 * 118 * These structs can be created and destroyed as needed. There is a full set of 119 * these structs in dc->current_state representing the currently programmed state. 120 * 121 * struct dc_state - The global DC state to track global state information, 122 * such as bandwidth values. 123 * 124 * struct dc_stream_state - Represents the hw configuration for the pipeline from 125 * a framebuffer to a display. Maps one-to-one with dc_sink. 126 * 127 * struct dc_plane_state - Represents a framebuffer. Each stream has at least one, 128 * and may have more in the Multi-Plane Overlay case. 129 * 130 * struct resource_context - Represents the programmable state of everything in 131 * the resource_pool. Not directly accessible by dm. 132 * 133 * struct pipe_ctx - A member of struct resource_context. Represents the 134 * internal hardware pipeline components. Each dc_plane_state has either 135 * one or two (in the pipe-split case). 136 */ 137 138 /******************************************************************************* 139 * Private functions 140 ******************************************************************************/ 141 142 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new) 143 { 144 if (new > *original) 145 *original = new; 146 } 147 148 static void destroy_links(struct dc *dc) 149 { 150 uint32_t i; 151 152 for (i = 0; i < dc->link_count; i++) { 153 if (NULL != dc->links[i]) 154 link_destroy(&dc->links[i]); 155 } 156 } 157 158 static uint32_t get_num_of_internal_disp(struct dc_link **links, uint32_t num_links) 159 { 160 int i; 161 uint32_t count = 0; 162 163 for (i = 0; i < num_links; i++) { 164 if (links[i]->connector_signal == SIGNAL_TYPE_EDP || 165 links[i]->is_internal_display) 166 count++; 167 } 168 169 return count; 170 } 171 172 static int get_seamless_boot_stream_count(struct dc_state *ctx) 173 { 174 uint8_t i; 175 uint8_t seamless_boot_stream_count = 0; 176 177 for (i = 0; i < ctx->stream_count; i++) 178 if (ctx->streams[i]->apply_seamless_boot_optimization) 179 seamless_boot_stream_count++; 180 181 return seamless_boot_stream_count; 182 } 183 184 static bool create_links( 185 struct dc *dc, 186 uint32_t num_virtual_links) 187 { 188 int i; 189 int connectors_num; 190 struct dc_bios *bios = dc->ctx->dc_bios; 191 192 dc->link_count = 0; 193 194 connectors_num = bios->funcs->get_connectors_number(bios); 195 196 DC_LOG_DC("BIOS object table - number of connectors: %d", connectors_num); 197 198 if (connectors_num > ENUM_ID_COUNT) { 199 dm_error( 200 "DC: Number of connectors %d exceeds maximum of %d!\n", 201 connectors_num, 202 ENUM_ID_COUNT); 203 return false; 204 } 205 206 dm_output_to_console( 207 "DC: %s: connectors_num: physical:%d, virtual:%d\n", 208 __func__, 209 connectors_num, 210 num_virtual_links); 211 212 for (i = 0; i < connectors_num; i++) { 213 struct link_init_data link_init_params = {0}; 214 struct dc_link *link; 215 216 DC_LOG_DC("BIOS object table - printing link object info for connector number: %d, link_index: %d", i, dc->link_count); 217 218 link_init_params.ctx = dc->ctx; 219 /* next BIOS object table connector */ 220 link_init_params.connector_index = i; 221 link_init_params.link_index = dc->link_count; 222 link_init_params.dc = dc; 223 link = link_create(&link_init_params); 224 225 if (link) { 226 dc->links[dc->link_count] = link; 227 link->dc = dc; 228 ++dc->link_count; 229 } 230 } 231 232 DC_LOG_DC("BIOS object table - end"); 233 234 /* Create a link for each usb4 dpia port */ 235 for (i = 0; i < dc->res_pool->usb4_dpia_count; i++) { 236 struct link_init_data link_init_params = {0}; 237 struct dc_link *link; 238 239 link_init_params.ctx = dc->ctx; 240 link_init_params.connector_index = i; 241 link_init_params.link_index = dc->link_count; 242 link_init_params.dc = dc; 243 link_init_params.is_dpia_link = true; 244 245 link = link_create(&link_init_params); 246 if (link) { 247 dc->links[dc->link_count] = link; 248 link->dc = dc; 249 ++dc->link_count; 250 } 251 } 252 253 for (i = 0; i < num_virtual_links; i++) { 254 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL); 255 struct encoder_init_data enc_init = {0}; 256 257 if (link == NULL) { 258 BREAK_TO_DEBUGGER(); 259 goto failed_alloc; 260 } 261 262 link->link_index = dc->link_count; 263 dc->links[dc->link_count] = link; 264 dc->link_count++; 265 266 link->ctx = dc->ctx; 267 link->dc = dc; 268 link->connector_signal = SIGNAL_TYPE_VIRTUAL; 269 link->link_id.type = OBJECT_TYPE_CONNECTOR; 270 link->link_id.id = CONNECTOR_ID_VIRTUAL; 271 link->link_id.enum_id = ENUM_ID_1; 272 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL); 273 274 if (!link->link_enc) { 275 BREAK_TO_DEBUGGER(); 276 goto failed_alloc; 277 } 278 279 link->link_status.dpcd_caps = &link->dpcd_caps; 280 281 enc_init.ctx = dc->ctx; 282 enc_init.channel = CHANNEL_ID_UNKNOWN; 283 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN; 284 enc_init.transmitter = TRANSMITTER_UNKNOWN; 285 enc_init.connector = link->link_id; 286 enc_init.encoder.type = OBJECT_TYPE_ENCODER; 287 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL; 288 enc_init.encoder.enum_id = ENUM_ID_1; 289 virtual_link_encoder_construct(link->link_enc, &enc_init); 290 } 291 292 dc->caps.num_of_internal_disp = get_num_of_internal_disp(dc->links, dc->link_count); 293 294 return true; 295 296 failed_alloc: 297 return false; 298 } 299 300 /* Create additional DIG link encoder objects if fewer than the platform 301 * supports were created during link construction. This can happen if the 302 * number of physical connectors is less than the number of DIGs. 303 */ 304 static bool create_link_encoders(struct dc *dc) 305 { 306 bool res = true; 307 unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia; 308 unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc; 309 int i; 310 311 /* A platform without USB4 DPIA endpoints has a fixed mapping between DIG 312 * link encoders and physical display endpoints and does not require 313 * additional link encoder objects. 314 */ 315 if (num_usb4_dpia == 0) 316 return res; 317 318 /* Create as many link encoder objects as the platform supports. DPIA 319 * endpoints can be programmably mapped to any DIG. 320 */ 321 if (num_dig_link_enc > dc->res_pool->dig_link_enc_count) { 322 for (i = 0; i < num_dig_link_enc; i++) { 323 struct link_encoder *link_enc = dc->res_pool->link_encoders[i]; 324 325 if (!link_enc && dc->res_pool->funcs->link_enc_create_minimal) { 326 link_enc = dc->res_pool->funcs->link_enc_create_minimal(dc->ctx, 327 (enum engine_id)(ENGINE_ID_DIGA + i)); 328 if (link_enc) { 329 dc->res_pool->link_encoders[i] = link_enc; 330 dc->res_pool->dig_link_enc_count++; 331 } else { 332 res = false; 333 } 334 } 335 } 336 } 337 338 return res; 339 } 340 341 /* Destroy any additional DIG link encoder objects created by 342 * create_link_encoders(). 343 * NB: Must only be called after destroy_links(). 344 */ 345 static void destroy_link_encoders(struct dc *dc) 346 { 347 unsigned int num_usb4_dpia; 348 unsigned int num_dig_link_enc; 349 int i; 350 351 if (!dc->res_pool) 352 return; 353 354 num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia; 355 num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc; 356 357 /* A platform without USB4 DPIA endpoints has a fixed mapping between DIG 358 * link encoders and physical display endpoints and does not require 359 * additional link encoder objects. 360 */ 361 if (num_usb4_dpia == 0) 362 return; 363 364 for (i = 0; i < num_dig_link_enc; i++) { 365 struct link_encoder *link_enc = dc->res_pool->link_encoders[i]; 366 367 if (link_enc) { 368 link_enc->funcs->destroy(&link_enc); 369 dc->res_pool->link_encoders[i] = NULL; 370 dc->res_pool->dig_link_enc_count--; 371 } 372 } 373 } 374 375 static struct dc_perf_trace *dc_perf_trace_create(void) 376 { 377 return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL); 378 } 379 380 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace) 381 { 382 kfree(*perf_trace); 383 *perf_trace = NULL; 384 } 385 386 /** 387 * dc_stream_adjust_vmin_vmax: 388 * 389 * Looks up the pipe context of dc_stream_state and updates the 390 * vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh 391 * Rate, which is a power-saving feature that targets reducing panel 392 * refresh rate while the screen is static 393 * 394 * @dc: dc reference 395 * @stream: Initial dc stream state 396 * @adjust: Updated parameters for vertical_total_min and vertical_total_max 397 */ 398 bool dc_stream_adjust_vmin_vmax(struct dc *dc, 399 struct dc_stream_state *stream, 400 struct dc_crtc_timing_adjust *adjust) 401 { 402 int i; 403 404 /* 405 * Don't adjust DRR while there's bandwidth optimizations pending to 406 * avoid conflicting with firmware updates. 407 */ 408 if (dc->ctx->dce_version > DCE_VERSION_MAX) 409 if (dc->optimized_required || dc->wm_optimized_required) 410 return false; 411 412 stream->adjust.v_total_max = adjust->v_total_max; 413 stream->adjust.v_total_mid = adjust->v_total_mid; 414 stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num; 415 stream->adjust.v_total_min = adjust->v_total_min; 416 417 for (i = 0; i < MAX_PIPES; i++) { 418 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 419 420 if (pipe->stream == stream && pipe->stream_res.tg) { 421 dc->hwss.set_drr(&pipe, 422 1, 423 *adjust); 424 425 return true; 426 } 427 } 428 return false; 429 } 430 431 /** 432 ***************************************************************************** 433 * Function: dc_stream_get_last_vrr_vtotal 434 * 435 * @brief 436 * Looks up the pipe context of dc_stream_state and gets the 437 * last VTOTAL used by DRR (Dynamic Refresh Rate) 438 * 439 * @param [in] dc: dc reference 440 * @param [in] stream: Initial dc stream state 441 * @param [in] adjust: Updated parameters for vertical_total_min and 442 * vertical_total_max 443 ***************************************************************************** 444 */ 445 bool dc_stream_get_last_used_drr_vtotal(struct dc *dc, 446 struct dc_stream_state *stream, 447 uint32_t *refresh_rate) 448 { 449 bool status = false; 450 451 int i = 0; 452 453 for (i = 0; i < MAX_PIPES; i++) { 454 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 455 456 if (pipe->stream == stream && pipe->stream_res.tg) { 457 /* Only execute if a function pointer has been defined for 458 * the DC version in question 459 */ 460 if (pipe->stream_res.tg->funcs->get_last_used_drr_vtotal) { 461 pipe->stream_res.tg->funcs->get_last_used_drr_vtotal(pipe->stream_res.tg, refresh_rate); 462 463 status = true; 464 465 break; 466 } 467 } 468 } 469 470 return status; 471 } 472 473 bool dc_stream_get_crtc_position(struct dc *dc, 474 struct dc_stream_state **streams, int num_streams, 475 unsigned int *v_pos, unsigned int *nom_v_pos) 476 { 477 /* TODO: Support multiple streams */ 478 const struct dc_stream_state *stream = streams[0]; 479 int i; 480 bool ret = false; 481 struct crtc_position position; 482 483 for (i = 0; i < MAX_PIPES; i++) { 484 struct pipe_ctx *pipe = 485 &dc->current_state->res_ctx.pipe_ctx[i]; 486 487 if (pipe->stream == stream && pipe->stream_res.stream_enc) { 488 dc->hwss.get_position(&pipe, 1, &position); 489 490 *v_pos = position.vertical_count; 491 *nom_v_pos = position.nominal_vcount; 492 ret = true; 493 } 494 } 495 return ret; 496 } 497 498 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 499 bool dc_stream_forward_dmcu_crc_window(struct dc *dc, struct dc_stream_state *stream, 500 struct crc_params *crc_window) 501 { 502 int i; 503 struct dmcu *dmcu = dc->res_pool->dmcu; 504 struct pipe_ctx *pipe; 505 struct crc_region tmp_win, *crc_win; 506 struct otg_phy_mux mapping_tmp, *mux_mapping; 507 508 /*crc window can't be null*/ 509 if (!crc_window) 510 return false; 511 512 if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu))) { 513 crc_win = &tmp_win; 514 mux_mapping = &mapping_tmp; 515 /*set crc window*/ 516 tmp_win.x_start = crc_window->windowa_x_start; 517 tmp_win.y_start = crc_window->windowa_y_start; 518 tmp_win.x_end = crc_window->windowa_x_end; 519 tmp_win.y_end = crc_window->windowa_y_end; 520 521 for (i = 0; i < MAX_PIPES; i++) { 522 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 523 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe) 524 break; 525 } 526 527 /* Stream not found */ 528 if (i == MAX_PIPES) 529 return false; 530 531 532 /*set mux routing info*/ 533 mapping_tmp.phy_output_num = stream->link->link_enc_hw_inst; 534 mapping_tmp.otg_output_num = pipe->stream_res.tg->inst; 535 536 dmcu->funcs->forward_crc_window(dmcu, crc_win, mux_mapping); 537 } else { 538 DC_LOG_DC("dmcu is not initialized"); 539 return false; 540 } 541 542 return true; 543 } 544 545 bool dc_stream_stop_dmcu_crc_win_update(struct dc *dc, struct dc_stream_state *stream) 546 { 547 int i; 548 struct dmcu *dmcu = dc->res_pool->dmcu; 549 struct pipe_ctx *pipe; 550 struct otg_phy_mux mapping_tmp, *mux_mapping; 551 552 if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu))) { 553 mux_mapping = &mapping_tmp; 554 555 for (i = 0; i < MAX_PIPES; i++) { 556 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 557 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe) 558 break; 559 } 560 561 /* Stream not found */ 562 if (i == MAX_PIPES) 563 return false; 564 565 566 /*set mux routing info*/ 567 mapping_tmp.phy_output_num = stream->link->link_enc_hw_inst; 568 mapping_tmp.otg_output_num = pipe->stream_res.tg->inst; 569 570 dmcu->funcs->stop_crc_win_update(dmcu, mux_mapping); 571 } else { 572 DC_LOG_DC("dmcu is not initialized"); 573 return false; 574 } 575 576 return true; 577 } 578 #endif 579 580 /** 581 * dc_stream_configure_crc() - Configure CRC capture for the given stream. 582 * @dc: DC Object 583 * @stream: The stream to configure CRC on. 584 * @enable: Enable CRC if true, disable otherwise. 585 * @crc_window: CRC window (x/y start/end) information 586 * @continuous: Capture CRC on every frame if true. Otherwise, only capture 587 * once. 588 * 589 * By default, only CRC0 is configured, and the entire frame is used to 590 * calculate the crc. 591 */ 592 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream, 593 struct crc_params *crc_window, bool enable, bool continuous) 594 { 595 int i; 596 struct pipe_ctx *pipe; 597 struct crc_params param; 598 struct timing_generator *tg; 599 600 for (i = 0; i < MAX_PIPES; i++) { 601 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 602 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe) 603 break; 604 } 605 /* Stream not found */ 606 if (i == MAX_PIPES) 607 return false; 608 609 /* By default, capture the full frame */ 610 param.windowa_x_start = 0; 611 param.windowa_y_start = 0; 612 param.windowa_x_end = pipe->stream->timing.h_addressable; 613 param.windowa_y_end = pipe->stream->timing.v_addressable; 614 param.windowb_x_start = 0; 615 param.windowb_y_start = 0; 616 param.windowb_x_end = pipe->stream->timing.h_addressable; 617 param.windowb_y_end = pipe->stream->timing.v_addressable; 618 619 if (crc_window) { 620 param.windowa_x_start = crc_window->windowa_x_start; 621 param.windowa_y_start = crc_window->windowa_y_start; 622 param.windowa_x_end = crc_window->windowa_x_end; 623 param.windowa_y_end = crc_window->windowa_y_end; 624 param.windowb_x_start = crc_window->windowb_x_start; 625 param.windowb_y_start = crc_window->windowb_y_start; 626 param.windowb_x_end = crc_window->windowb_x_end; 627 param.windowb_y_end = crc_window->windowb_y_end; 628 } 629 630 param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0; 631 param.odm_mode = pipe->next_odm_pipe ? 1:0; 632 633 /* Default to the union of both windows */ 634 param.selection = UNION_WINDOW_A_B; 635 param.continuous_mode = continuous; 636 param.enable = enable; 637 638 tg = pipe->stream_res.tg; 639 640 /* Only call if supported */ 641 if (tg->funcs->configure_crc) 642 return tg->funcs->configure_crc(tg, ¶m); 643 DC_LOG_WARNING("CRC capture not supported."); 644 return false; 645 } 646 647 /** 648 * dc_stream_get_crc() - Get CRC values for the given stream. 649 * 650 * @dc: DC object. 651 * @stream: The DC stream state of the stream to get CRCs from. 652 * @r_cr: CRC value for the red component. 653 * @g_y: CRC value for the green component. 654 * @b_cb: CRC value for the blue component. 655 * 656 * dc_stream_configure_crc needs to be called beforehand to enable CRCs. 657 * 658 * Return: 659 * false if stream is not found, or if CRCs are not enabled. 660 */ 661 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream, 662 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) 663 { 664 int i; 665 struct pipe_ctx *pipe; 666 struct timing_generator *tg; 667 668 for (i = 0; i < MAX_PIPES; i++) { 669 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 670 if (pipe->stream == stream) 671 break; 672 } 673 /* Stream not found */ 674 if (i == MAX_PIPES) 675 return false; 676 677 tg = pipe->stream_res.tg; 678 679 if (tg->funcs->get_crc) 680 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb); 681 DC_LOG_WARNING("CRC capture not supported."); 682 return false; 683 } 684 685 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream, 686 enum dc_dynamic_expansion option) 687 { 688 /* OPP FMT dyn expansion updates*/ 689 int i; 690 struct pipe_ctx *pipe_ctx; 691 692 for (i = 0; i < MAX_PIPES; i++) { 693 if (dc->current_state->res_ctx.pipe_ctx[i].stream 694 == stream) { 695 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 696 pipe_ctx->stream_res.opp->dyn_expansion = option; 697 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 698 pipe_ctx->stream_res.opp, 699 COLOR_SPACE_YCBCR601, 700 stream->timing.display_color_depth, 701 stream->signal); 702 } 703 } 704 } 705 706 void dc_stream_set_dither_option(struct dc_stream_state *stream, 707 enum dc_dither_option option) 708 { 709 struct bit_depth_reduction_params params; 710 struct dc_link *link = stream->link; 711 struct pipe_ctx *pipes = NULL; 712 int i; 713 714 for (i = 0; i < MAX_PIPES; i++) { 715 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream == 716 stream) { 717 pipes = &link->dc->current_state->res_ctx.pipe_ctx[i]; 718 break; 719 } 720 } 721 722 if (!pipes) 723 return; 724 if (option > DITHER_OPTION_MAX) 725 return; 726 727 stream->dither_option = option; 728 729 memset(¶ms, 0, sizeof(params)); 730 resource_build_bit_depth_reduction_params(stream, ¶ms); 731 stream->bit_depth_params = params; 732 733 if (pipes->plane_res.xfm && 734 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) { 735 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth( 736 pipes->plane_res.xfm, 737 pipes->plane_res.scl_data.lb_params.depth, 738 &stream->bit_depth_params); 739 } 740 741 pipes->stream_res.opp->funcs-> 742 opp_program_bit_depth_reduction(pipes->stream_res.opp, ¶ms); 743 } 744 745 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) 746 { 747 int i; 748 bool ret = false; 749 struct pipe_ctx *pipes; 750 751 for (i = 0; i < MAX_PIPES; i++) { 752 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) { 753 pipes = &dc->current_state->res_ctx.pipe_ctx[i]; 754 dc->hwss.program_gamut_remap(pipes); 755 ret = true; 756 } 757 } 758 759 return ret; 760 } 761 762 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream) 763 { 764 int i; 765 bool ret = false; 766 struct pipe_ctx *pipes; 767 768 for (i = 0; i < MAX_PIPES; i++) { 769 if (dc->current_state->res_ctx.pipe_ctx[i].stream 770 == stream) { 771 772 pipes = &dc->current_state->res_ctx.pipe_ctx[i]; 773 dc->hwss.program_output_csc(dc, 774 pipes, 775 stream->output_color_space, 776 stream->csc_color_matrix.matrix, 777 pipes->stream_res.opp->inst); 778 ret = true; 779 } 780 } 781 782 return ret; 783 } 784 785 void dc_stream_set_static_screen_params(struct dc *dc, 786 struct dc_stream_state **streams, 787 int num_streams, 788 const struct dc_static_screen_params *params) 789 { 790 int i, j; 791 struct pipe_ctx *pipes_affected[MAX_PIPES]; 792 int num_pipes_affected = 0; 793 794 for (i = 0; i < num_streams; i++) { 795 struct dc_stream_state *stream = streams[i]; 796 797 for (j = 0; j < MAX_PIPES; j++) { 798 if (dc->current_state->res_ctx.pipe_ctx[j].stream 799 == stream) { 800 pipes_affected[num_pipes_affected++] = 801 &dc->current_state->res_ctx.pipe_ctx[j]; 802 } 803 } 804 } 805 806 dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params); 807 } 808 809 static void dc_destruct(struct dc *dc) 810 { 811 // reset link encoder assignment table on destruct 812 if (dc->res_pool && dc->res_pool->funcs->link_encs_assign) 813 link_enc_cfg_init(dc, dc->current_state); 814 815 if (dc->current_state) { 816 dc_release_state(dc->current_state); 817 dc->current_state = NULL; 818 } 819 820 destroy_links(dc); 821 822 destroy_link_encoders(dc); 823 824 if (dc->clk_mgr) { 825 dc_destroy_clk_mgr(dc->clk_mgr); 826 dc->clk_mgr = NULL; 827 } 828 829 dc_destroy_resource_pool(dc); 830 831 if (dc->ctx->gpio_service) 832 dal_gpio_service_destroy(&dc->ctx->gpio_service); 833 834 if (dc->ctx->created_bios) 835 dal_bios_parser_destroy(&dc->ctx->dc_bios); 836 837 dc_perf_trace_destroy(&dc->ctx->perf_trace); 838 839 kfree(dc->ctx); 840 dc->ctx = NULL; 841 842 kfree(dc->bw_vbios); 843 dc->bw_vbios = NULL; 844 845 kfree(dc->bw_dceip); 846 dc->bw_dceip = NULL; 847 848 kfree(dc->dcn_soc); 849 dc->dcn_soc = NULL; 850 851 kfree(dc->dcn_ip); 852 dc->dcn_ip = NULL; 853 854 kfree(dc->vm_helper); 855 dc->vm_helper = NULL; 856 857 } 858 859 static bool dc_construct_ctx(struct dc *dc, 860 const struct dc_init_data *init_params) 861 { 862 struct dc_context *dc_ctx; 863 enum dce_version dc_version = DCE_VERSION_UNKNOWN; 864 865 dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL); 866 if (!dc_ctx) 867 return false; 868 869 dc_ctx->cgs_device = init_params->cgs_device; 870 dc_ctx->driver_context = init_params->driver; 871 dc_ctx->dc = dc; 872 dc_ctx->asic_id = init_params->asic_id; 873 dc_ctx->dc_sink_id_count = 0; 874 dc_ctx->dc_stream_id_count = 0; 875 dc_ctx->dce_environment = init_params->dce_environment; 876 dc_ctx->dcn_reg_offsets = init_params->dcn_reg_offsets; 877 dc_ctx->nbio_reg_offsets = init_params->nbio_reg_offsets; 878 879 /* Create logger */ 880 881 dc_version = resource_parse_asic_id(init_params->asic_id); 882 dc_ctx->dce_version = dc_version; 883 884 dc_ctx->perf_trace = dc_perf_trace_create(); 885 if (!dc_ctx->perf_trace) { 886 kfree(dc_ctx); 887 ASSERT_CRITICAL(false); 888 return false; 889 } 890 891 dc->ctx = dc_ctx; 892 893 return true; 894 } 895 896 static bool dc_construct(struct dc *dc, 897 const struct dc_init_data *init_params) 898 { 899 struct dc_context *dc_ctx; 900 struct bw_calcs_dceip *dc_dceip; 901 struct bw_calcs_vbios *dc_vbios; 902 struct dcn_soc_bounding_box *dcn_soc; 903 struct dcn_ip_params *dcn_ip; 904 905 dc->config = init_params->flags; 906 907 // Allocate memory for the vm_helper 908 dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL); 909 if (!dc->vm_helper) { 910 dm_error("%s: failed to create dc->vm_helper\n", __func__); 911 goto fail; 912 } 913 914 memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides)); 915 916 dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL); 917 if (!dc_dceip) { 918 dm_error("%s: failed to create dceip\n", __func__); 919 goto fail; 920 } 921 922 dc->bw_dceip = dc_dceip; 923 924 dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL); 925 if (!dc_vbios) { 926 dm_error("%s: failed to create vbios\n", __func__); 927 goto fail; 928 } 929 930 dc->bw_vbios = dc_vbios; 931 dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL); 932 if (!dcn_soc) { 933 dm_error("%s: failed to create dcn_soc\n", __func__); 934 goto fail; 935 } 936 937 dc->dcn_soc = dcn_soc; 938 939 dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL); 940 if (!dcn_ip) { 941 dm_error("%s: failed to create dcn_ip\n", __func__); 942 goto fail; 943 } 944 945 dc->dcn_ip = dcn_ip; 946 947 if (!dc_construct_ctx(dc, init_params)) { 948 dm_error("%s: failed to create ctx\n", __func__); 949 goto fail; 950 } 951 952 dc_ctx = dc->ctx; 953 954 /* Resource should construct all asic specific resources. 955 * This should be the only place where we need to parse the asic id 956 */ 957 if (init_params->vbios_override) 958 dc_ctx->dc_bios = init_params->vbios_override; 959 else { 960 /* Create BIOS parser */ 961 struct bp_init_data bp_init_data; 962 963 bp_init_data.ctx = dc_ctx; 964 bp_init_data.bios = init_params->asic_id.atombios_base_address; 965 966 dc_ctx->dc_bios = dal_bios_parser_create( 967 &bp_init_data, dc_ctx->dce_version); 968 969 if (!dc_ctx->dc_bios) { 970 ASSERT_CRITICAL(false); 971 goto fail; 972 } 973 974 dc_ctx->created_bios = true; 975 } 976 977 dc->vendor_signature = init_params->vendor_signature; 978 979 /* Create GPIO service */ 980 dc_ctx->gpio_service = dal_gpio_service_create( 981 dc_ctx->dce_version, 982 dc_ctx->dce_environment, 983 dc_ctx); 984 985 if (!dc_ctx->gpio_service) { 986 ASSERT_CRITICAL(false); 987 goto fail; 988 } 989 990 dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version); 991 if (!dc->res_pool) 992 goto fail; 993 994 /* set i2c speed if not done by the respective dcnxxx__resource.c */ 995 if (dc->caps.i2c_speed_in_khz_hdcp == 0) 996 dc->caps.i2c_speed_in_khz_hdcp = dc->caps.i2c_speed_in_khz; 997 998 dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg); 999 if (!dc->clk_mgr) 1000 goto fail; 1001 #ifdef CONFIG_DRM_AMD_DC_DCN 1002 dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present; 1003 1004 if (dc->res_pool->funcs->update_bw_bounding_box) { 1005 DC_FP_START(); 1006 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); 1007 DC_FP_END(); 1008 } 1009 #endif 1010 1011 /* Creation of current_state must occur after dc->dml 1012 * is initialized in dc_create_resource_pool because 1013 * on creation it copies the contents of dc->dml 1014 */ 1015 1016 dc->current_state = dc_create_state(dc); 1017 1018 if (!dc->current_state) { 1019 dm_error("%s: failed to create validate ctx\n", __func__); 1020 goto fail; 1021 } 1022 1023 if (!create_links(dc, init_params->num_virtual_links)) 1024 goto fail; 1025 1026 /* Create additional DIG link encoder objects if fewer than the platform 1027 * supports were created during link construction. 1028 */ 1029 if (!create_link_encoders(dc)) 1030 goto fail; 1031 1032 dc_resource_state_construct(dc, dc->current_state); 1033 1034 return true; 1035 1036 fail: 1037 return false; 1038 } 1039 1040 static void disable_all_writeback_pipes_for_stream( 1041 const struct dc *dc, 1042 struct dc_stream_state *stream, 1043 struct dc_state *context) 1044 { 1045 int i; 1046 1047 for (i = 0; i < stream->num_wb_info; i++) 1048 stream->writeback_info[i].wb_enabled = false; 1049 } 1050 1051 static void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context, 1052 struct dc_stream_state *stream, bool lock) 1053 { 1054 int i; 1055 1056 /* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */ 1057 if (dc->hwss.interdependent_update_lock) 1058 dc->hwss.interdependent_update_lock(dc, context, lock); 1059 else { 1060 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1061 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1062 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 1063 1064 // Copied conditions that were previously in dce110_apply_ctx_for_surface 1065 if (stream == pipe_ctx->stream) { 1066 if (!pipe_ctx->top_pipe && 1067 (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) 1068 dc->hwss.pipe_control_lock(dc, pipe_ctx, lock); 1069 } 1070 } 1071 } 1072 } 1073 1074 static void disable_dangling_plane(struct dc *dc, struct dc_state *context) 1075 { 1076 int i, j; 1077 struct dc_state *dangling_context = dc_create_state(dc); 1078 struct dc_state *current_ctx; 1079 struct pipe_ctx *pipe; 1080 1081 if (dangling_context == NULL) 1082 return; 1083 1084 dc_resource_state_copy_construct(dc->current_state, dangling_context); 1085 1086 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1087 struct dc_stream_state *old_stream = 1088 dc->current_state->res_ctx.pipe_ctx[i].stream; 1089 bool should_disable = true; 1090 bool pipe_split_change = false; 1091 1092 if ((context->res_ctx.pipe_ctx[i].top_pipe) && 1093 (dc->current_state->res_ctx.pipe_ctx[i].top_pipe)) 1094 pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe->pipe_idx != 1095 dc->current_state->res_ctx.pipe_ctx[i].top_pipe->pipe_idx; 1096 else 1097 pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe != 1098 dc->current_state->res_ctx.pipe_ctx[i].top_pipe; 1099 1100 for (j = 0; j < context->stream_count; j++) { 1101 if (old_stream == context->streams[j]) { 1102 should_disable = false; 1103 break; 1104 } 1105 } 1106 if (!should_disable && pipe_split_change && 1107 dc->current_state->stream_count != context->stream_count) 1108 should_disable = true; 1109 1110 if (old_stream && !dc->current_state->res_ctx.pipe_ctx[i].top_pipe && 1111 !dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe) { 1112 struct pipe_ctx *old_pipe, *new_pipe; 1113 1114 old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 1115 new_pipe = &context->res_ctx.pipe_ctx[i]; 1116 1117 if (old_pipe->plane_state && !new_pipe->plane_state) 1118 should_disable = true; 1119 } 1120 1121 if (should_disable && old_stream) { 1122 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 1123 /* When disabling plane for a phantom pipe, we must turn on the 1124 * phantom OTG so the disable programming gets the double buffer 1125 * update. Otherwise the pipe will be left in a partially disabled 1126 * state that can result in underflow or hang when enabling it 1127 * again for different use. 1128 */ 1129 if (old_stream->mall_stream_config.type == SUBVP_PHANTOM) { 1130 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); 1131 } 1132 dc_rem_all_planes_for_stream(dc, old_stream, dangling_context); 1133 disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context); 1134 1135 if (dc->hwss.apply_ctx_for_surface) { 1136 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true); 1137 dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context); 1138 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false); 1139 dc->hwss.post_unlock_program_front_end(dc, dangling_context); 1140 } 1141 if (dc->hwss.program_front_end_for_ctx) { 1142 dc->hwss.interdependent_update_lock(dc, dc->current_state, true); 1143 dc->hwss.program_front_end_for_ctx(dc, dangling_context); 1144 dc->hwss.interdependent_update_lock(dc, dc->current_state, false); 1145 dc->hwss.post_unlock_program_front_end(dc, dangling_context); 1146 } 1147 } 1148 } 1149 1150 current_ctx = dc->current_state; 1151 dc->current_state = dangling_context; 1152 dc_release_state(current_ctx); 1153 } 1154 1155 static void disable_vbios_mode_if_required( 1156 struct dc *dc, 1157 struct dc_state *context) 1158 { 1159 unsigned int i, j; 1160 1161 /* check if timing_changed, disable stream*/ 1162 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1163 struct dc_stream_state *stream = NULL; 1164 struct dc_link *link = NULL; 1165 struct pipe_ctx *pipe = NULL; 1166 1167 pipe = &context->res_ctx.pipe_ctx[i]; 1168 stream = pipe->stream; 1169 if (stream == NULL) 1170 continue; 1171 1172 // only looking for first odm pipe 1173 if (pipe->prev_odm_pipe) 1174 continue; 1175 1176 if (stream->link->local_sink && 1177 stream->link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1178 link = stream->link; 1179 } 1180 1181 if (link != NULL && link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 1182 unsigned int enc_inst, tg_inst = 0; 1183 unsigned int pix_clk_100hz; 1184 1185 enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc); 1186 if (enc_inst != ENGINE_ID_UNKNOWN) { 1187 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 1188 if (dc->res_pool->stream_enc[j]->id == enc_inst) { 1189 tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg( 1190 dc->res_pool->stream_enc[j]); 1191 break; 1192 } 1193 } 1194 1195 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz( 1196 dc->res_pool->dp_clock_source, 1197 tg_inst, &pix_clk_100hz); 1198 1199 if (link->link_status.link_active) { 1200 uint32_t requested_pix_clk_100hz = 1201 pipe->stream_res.pix_clk_params.requested_pix_clk_100hz; 1202 1203 if (pix_clk_100hz != requested_pix_clk_100hz) { 1204 core_link_disable_stream(pipe); 1205 pipe->stream->dpms_off = false; 1206 } 1207 } 1208 } 1209 } 1210 } 1211 } 1212 1213 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context) 1214 { 1215 int i; 1216 PERF_TRACE(); 1217 for (i = 0; i < MAX_PIPES; i++) { 1218 int count = 0; 1219 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1220 1221 if (!pipe->plane_state || pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) 1222 continue; 1223 1224 /* Timeout 100 ms */ 1225 while (count < 100000) { 1226 /* Must set to false to start with, due to OR in update function */ 1227 pipe->plane_state->status.is_flip_pending = false; 1228 dc->hwss.update_pending_status(pipe); 1229 if (!pipe->plane_state->status.is_flip_pending) 1230 break; 1231 udelay(1); 1232 count++; 1233 } 1234 ASSERT(!pipe->plane_state->status.is_flip_pending); 1235 } 1236 PERF_TRACE(); 1237 } 1238 1239 /******************************************************************************* 1240 * Public functions 1241 ******************************************************************************/ 1242 1243 struct dc *dc_create(const struct dc_init_data *init_params) 1244 { 1245 struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL); 1246 unsigned int full_pipe_count; 1247 1248 if (!dc) 1249 return NULL; 1250 1251 if (init_params->dce_environment == DCE_ENV_VIRTUAL_HW) { 1252 if (!dc_construct_ctx(dc, init_params)) 1253 goto destruct_dc; 1254 } else { 1255 if (!dc_construct(dc, init_params)) 1256 goto destruct_dc; 1257 1258 full_pipe_count = dc->res_pool->pipe_count; 1259 if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE) 1260 full_pipe_count--; 1261 dc->caps.max_streams = min( 1262 full_pipe_count, 1263 dc->res_pool->stream_enc_count); 1264 1265 dc->caps.max_links = dc->link_count; 1266 dc->caps.max_audios = dc->res_pool->audio_count; 1267 dc->caps.linear_pitch_alignment = 64; 1268 1269 dc->caps.max_dp_protocol_version = DP_VERSION_1_4; 1270 1271 dc->caps.max_otg_num = dc->res_pool->res_cap->num_timing_generator; 1272 1273 if (dc->res_pool->dmcu != NULL) 1274 dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version; 1275 } 1276 1277 dc->dcn_reg_offsets = init_params->dcn_reg_offsets; 1278 dc->nbio_reg_offsets = init_params->nbio_reg_offsets; 1279 1280 /* Populate versioning information */ 1281 dc->versions.dc_ver = DC_VER; 1282 1283 dc->build_id = DC_BUILD_ID; 1284 1285 DC_LOG_DC("Display Core initialized\n"); 1286 1287 1288 1289 return dc; 1290 1291 destruct_dc: 1292 dc_destruct(dc); 1293 kfree(dc); 1294 return NULL; 1295 } 1296 1297 static void detect_edp_presence(struct dc *dc) 1298 { 1299 struct dc_link *edp_links[MAX_NUM_EDP]; 1300 struct dc_link *edp_link = NULL; 1301 enum dc_connection_type type; 1302 int i; 1303 int edp_num; 1304 1305 get_edp_links(dc, edp_links, &edp_num); 1306 if (!edp_num) 1307 return; 1308 1309 for (i = 0; i < edp_num; i++) { 1310 edp_link = edp_links[i]; 1311 if (dc->config.edp_not_connected) { 1312 edp_link->edp_sink_present = false; 1313 } else { 1314 dc_link_detect_sink(edp_link, &type); 1315 edp_link->edp_sink_present = (type != dc_connection_none); 1316 } 1317 } 1318 } 1319 1320 void dc_hardware_init(struct dc *dc) 1321 { 1322 1323 detect_edp_presence(dc); 1324 if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW) 1325 dc->hwss.init_hw(dc); 1326 } 1327 1328 void dc_init_callbacks(struct dc *dc, 1329 const struct dc_callback_init *init_params) 1330 { 1331 #ifdef CONFIG_DRM_AMD_DC_HDCP 1332 dc->ctx->cp_psp = init_params->cp_psp; 1333 #endif 1334 } 1335 1336 void dc_deinit_callbacks(struct dc *dc) 1337 { 1338 #ifdef CONFIG_DRM_AMD_DC_HDCP 1339 memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp)); 1340 #endif 1341 } 1342 1343 void dc_destroy(struct dc **dc) 1344 { 1345 dc_destruct(*dc); 1346 kfree(*dc); 1347 *dc = NULL; 1348 } 1349 1350 static void enable_timing_multisync( 1351 struct dc *dc, 1352 struct dc_state *ctx) 1353 { 1354 int i, multisync_count = 0; 1355 int pipe_count = dc->res_pool->pipe_count; 1356 struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL }; 1357 1358 for (i = 0; i < pipe_count; i++) { 1359 if (!ctx->res_ctx.pipe_ctx[i].stream || 1360 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled) 1361 continue; 1362 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source) 1363 continue; 1364 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i]; 1365 multisync_count++; 1366 } 1367 1368 if (multisync_count > 0) { 1369 dc->hwss.enable_per_frame_crtc_position_reset( 1370 dc, multisync_count, multisync_pipes); 1371 } 1372 } 1373 1374 static void program_timing_sync( 1375 struct dc *dc, 1376 struct dc_state *ctx) 1377 { 1378 int i, j, k; 1379 int group_index = 0; 1380 int num_group = 0; 1381 int pipe_count = dc->res_pool->pipe_count; 1382 struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL }; 1383 1384 for (i = 0; i < pipe_count; i++) { 1385 if (!ctx->res_ctx.pipe_ctx[i].stream 1386 || ctx->res_ctx.pipe_ctx[i].top_pipe 1387 || ctx->res_ctx.pipe_ctx[i].prev_odm_pipe) 1388 continue; 1389 1390 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i]; 1391 } 1392 1393 for (i = 0; i < pipe_count; i++) { 1394 int group_size = 1; 1395 enum timing_synchronization_type sync_type = NOT_SYNCHRONIZABLE; 1396 struct pipe_ctx *pipe_set[MAX_PIPES]; 1397 1398 if (!unsynced_pipes[i]) 1399 continue; 1400 1401 pipe_set[0] = unsynced_pipes[i]; 1402 unsynced_pipes[i] = NULL; 1403 1404 /* Add tg to the set, search rest of the tg's for ones with 1405 * same timing, add all tgs with same timing to the group 1406 */ 1407 for (j = i + 1; j < pipe_count; j++) { 1408 if (!unsynced_pipes[j]) 1409 continue; 1410 if (sync_type != TIMING_SYNCHRONIZABLE && 1411 dc->hwss.enable_vblanks_synchronization && 1412 unsynced_pipes[j]->stream_res.tg->funcs->align_vblanks && 1413 resource_are_vblanks_synchronizable( 1414 unsynced_pipes[j]->stream, 1415 pipe_set[0]->stream)) { 1416 sync_type = VBLANK_SYNCHRONIZABLE; 1417 pipe_set[group_size] = unsynced_pipes[j]; 1418 unsynced_pipes[j] = NULL; 1419 group_size++; 1420 } else 1421 if (sync_type != VBLANK_SYNCHRONIZABLE && 1422 resource_are_streams_timing_synchronizable( 1423 unsynced_pipes[j]->stream, 1424 pipe_set[0]->stream)) { 1425 sync_type = TIMING_SYNCHRONIZABLE; 1426 pipe_set[group_size] = unsynced_pipes[j]; 1427 unsynced_pipes[j] = NULL; 1428 group_size++; 1429 } 1430 } 1431 1432 /* set first unblanked pipe as master */ 1433 for (j = 0; j < group_size; j++) { 1434 bool is_blanked; 1435 1436 if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked) 1437 is_blanked = 1438 pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp); 1439 else 1440 is_blanked = 1441 pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg); 1442 if (!is_blanked) { 1443 if (j == 0) 1444 break; 1445 1446 swap(pipe_set[0], pipe_set[j]); 1447 break; 1448 } 1449 } 1450 1451 for (k = 0; k < group_size; k++) { 1452 struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream); 1453 1454 status->timing_sync_info.group_id = num_group; 1455 status->timing_sync_info.group_size = group_size; 1456 if (k == 0) 1457 status->timing_sync_info.master = true; 1458 else 1459 status->timing_sync_info.master = false; 1460 1461 } 1462 1463 /* remove any other pipes that are already been synced */ 1464 if (dc->config.use_pipe_ctx_sync_logic) { 1465 /* check pipe's syncd to decide which pipe to be removed */ 1466 for (j = 1; j < group_size; j++) { 1467 if (pipe_set[j]->pipe_idx_syncd == pipe_set[0]->pipe_idx_syncd) { 1468 group_size--; 1469 pipe_set[j] = pipe_set[group_size]; 1470 j--; 1471 } else 1472 /* link slave pipe's syncd with master pipe */ 1473 pipe_set[j]->pipe_idx_syncd = pipe_set[0]->pipe_idx_syncd; 1474 } 1475 } else { 1476 for (j = j + 1; j < group_size; j++) { 1477 bool is_blanked; 1478 1479 if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked) 1480 is_blanked = 1481 pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp); 1482 else 1483 is_blanked = 1484 pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg); 1485 if (!is_blanked) { 1486 group_size--; 1487 pipe_set[j] = pipe_set[group_size]; 1488 j--; 1489 } 1490 } 1491 } 1492 1493 if (group_size > 1) { 1494 if (sync_type == TIMING_SYNCHRONIZABLE) { 1495 dc->hwss.enable_timing_synchronization( 1496 dc, group_index, group_size, pipe_set); 1497 } else 1498 if (sync_type == VBLANK_SYNCHRONIZABLE) { 1499 dc->hwss.enable_vblanks_synchronization( 1500 dc, group_index, group_size, pipe_set); 1501 } 1502 group_index++; 1503 } 1504 num_group++; 1505 } 1506 } 1507 1508 static bool streams_changed(struct dc *dc, 1509 struct dc_stream_state *streams[], 1510 uint8_t stream_count) 1511 { 1512 uint8_t i; 1513 1514 if (stream_count != dc->current_state->stream_count) 1515 return true; 1516 1517 for (i = 0; i < dc->current_state->stream_count; i++) { 1518 if (dc->current_state->streams[i] != streams[i]) 1519 return true; 1520 if (!streams[i]->link->link_state_valid) 1521 return true; 1522 } 1523 1524 return false; 1525 } 1526 1527 bool dc_validate_boot_timing(const struct dc *dc, 1528 const struct dc_sink *sink, 1529 struct dc_crtc_timing *crtc_timing) 1530 { 1531 struct timing_generator *tg; 1532 struct stream_encoder *se = NULL; 1533 1534 struct dc_crtc_timing hw_crtc_timing = {0}; 1535 1536 struct dc_link *link = sink->link; 1537 unsigned int i, enc_inst, tg_inst = 0; 1538 1539 /* Support seamless boot on EDP displays only */ 1540 if (sink->sink_signal != SIGNAL_TYPE_EDP) { 1541 return false; 1542 } 1543 1544 if (dc->debug.force_odm_combine) 1545 return false; 1546 1547 /* Check for enabled DIG to identify enabled display */ 1548 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc)) 1549 return false; 1550 1551 enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc); 1552 1553 if (enc_inst == ENGINE_ID_UNKNOWN) 1554 return false; 1555 1556 for (i = 0; i < dc->res_pool->stream_enc_count; i++) { 1557 if (dc->res_pool->stream_enc[i]->id == enc_inst) { 1558 1559 se = dc->res_pool->stream_enc[i]; 1560 1561 tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg( 1562 dc->res_pool->stream_enc[i]); 1563 break; 1564 } 1565 } 1566 1567 // tg_inst not found 1568 if (i == dc->res_pool->stream_enc_count) 1569 return false; 1570 1571 if (tg_inst >= dc->res_pool->timing_generator_count) 1572 return false; 1573 1574 tg = dc->res_pool->timing_generators[tg_inst]; 1575 1576 if (!tg->funcs->get_hw_timing) 1577 return false; 1578 1579 if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing)) 1580 return false; 1581 1582 if (crtc_timing->h_total != hw_crtc_timing.h_total) 1583 return false; 1584 1585 if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left) 1586 return false; 1587 1588 if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable) 1589 return false; 1590 1591 if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right) 1592 return false; 1593 1594 if (crtc_timing->h_front_porch != hw_crtc_timing.h_front_porch) 1595 return false; 1596 1597 if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width) 1598 return false; 1599 1600 if (crtc_timing->v_total != hw_crtc_timing.v_total) 1601 return false; 1602 1603 if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top) 1604 return false; 1605 1606 if (crtc_timing->v_addressable != hw_crtc_timing.v_addressable) 1607 return false; 1608 1609 if (crtc_timing->v_border_bottom != hw_crtc_timing.v_border_bottom) 1610 return false; 1611 1612 if (crtc_timing->v_front_porch != hw_crtc_timing.v_front_porch) 1613 return false; 1614 1615 if (crtc_timing->v_sync_width != hw_crtc_timing.v_sync_width) 1616 return false; 1617 1618 /* block DSC for now, as VBIOS does not currently support DSC timings */ 1619 if (crtc_timing->flags.DSC) 1620 return false; 1621 1622 if (dc_is_dp_signal(link->connector_signal)) { 1623 unsigned int pix_clk_100hz; 1624 uint32_t numOdmPipes = 1; 1625 uint32_t id_src[4] = {0}; 1626 1627 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz( 1628 dc->res_pool->dp_clock_source, 1629 tg_inst, &pix_clk_100hz); 1630 1631 if (tg->funcs->get_optc_source) 1632 tg->funcs->get_optc_source(tg, 1633 &numOdmPipes, &id_src[0], &id_src[1]); 1634 1635 if (numOdmPipes == 2) 1636 pix_clk_100hz *= 2; 1637 if (numOdmPipes == 4) 1638 pix_clk_100hz *= 4; 1639 1640 // Note: In rare cases, HW pixclk may differ from crtc's pixclk 1641 // slightly due to rounding issues in 10 kHz units. 1642 if (crtc_timing->pix_clk_100hz != pix_clk_100hz) 1643 return false; 1644 1645 if (!se->funcs->dp_get_pixel_format) 1646 return false; 1647 1648 if (!se->funcs->dp_get_pixel_format( 1649 se, 1650 &hw_crtc_timing.pixel_encoding, 1651 &hw_crtc_timing.display_color_depth)) 1652 return false; 1653 1654 if (hw_crtc_timing.display_color_depth != crtc_timing->display_color_depth) 1655 return false; 1656 1657 if (hw_crtc_timing.pixel_encoding != crtc_timing->pixel_encoding) 1658 return false; 1659 } 1660 1661 if (link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) { 1662 return false; 1663 } 1664 1665 if (is_edp_ilr_optimization_required(link, crtc_timing)) { 1666 DC_LOG_EVENT_LINK_TRAINING("Seamless boot disabled to optimize eDP link rate\n"); 1667 return false; 1668 } 1669 1670 return true; 1671 } 1672 1673 static inline bool should_update_pipe_for_stream( 1674 struct dc_state *context, 1675 struct pipe_ctx *pipe_ctx, 1676 struct dc_stream_state *stream) 1677 { 1678 return (pipe_ctx->stream && pipe_ctx->stream == stream); 1679 } 1680 1681 static inline bool should_update_pipe_for_plane( 1682 struct dc_state *context, 1683 struct pipe_ctx *pipe_ctx, 1684 struct dc_plane_state *plane_state) 1685 { 1686 return (pipe_ctx->plane_state == plane_state); 1687 } 1688 1689 void dc_enable_stereo( 1690 struct dc *dc, 1691 struct dc_state *context, 1692 struct dc_stream_state *streams[], 1693 uint8_t stream_count) 1694 { 1695 int i, j; 1696 struct pipe_ctx *pipe; 1697 1698 for (i = 0; i < MAX_PIPES; i++) { 1699 if (context != NULL) { 1700 pipe = &context->res_ctx.pipe_ctx[i]; 1701 } else { 1702 context = dc->current_state; 1703 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 1704 } 1705 1706 for (j = 0; pipe && j < stream_count; j++) { 1707 if (should_update_pipe_for_stream(context, pipe, streams[j]) && 1708 dc->hwss.setup_stereo) 1709 dc->hwss.setup_stereo(pipe, dc); 1710 } 1711 } 1712 } 1713 1714 void dc_trigger_sync(struct dc *dc, struct dc_state *context) 1715 { 1716 if (context->stream_count > 1 && !dc->debug.disable_timing_sync) { 1717 enable_timing_multisync(dc, context); 1718 program_timing_sync(dc, context); 1719 } 1720 } 1721 1722 static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context) 1723 { 1724 int i; 1725 unsigned int stream_mask = 0; 1726 1727 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1728 if (context->res_ctx.pipe_ctx[i].stream) 1729 stream_mask |= 1 << i; 1730 } 1731 1732 return stream_mask; 1733 } 1734 1735 void dc_z10_restore(const struct dc *dc) 1736 { 1737 if (dc->hwss.z10_restore) 1738 dc->hwss.z10_restore(dc); 1739 } 1740 1741 void dc_z10_save_init(struct dc *dc) 1742 { 1743 if (dc->hwss.z10_save_init) 1744 dc->hwss.z10_save_init(dc); 1745 } 1746 1747 /* 1748 * Applies given context to HW and copy it into current context. 1749 * It's up to the user to release the src context afterwards. 1750 */ 1751 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context) 1752 { 1753 struct dc_bios *dcb = dc->ctx->dc_bios; 1754 enum dc_status result = DC_ERROR_UNEXPECTED; 1755 struct pipe_ctx *pipe; 1756 int i, k, l; 1757 struct dc_stream_state *dc_streams[MAX_STREAMS] = {0}; 1758 struct dc_state *old_state; 1759 bool subvp_prev_use = false; 1760 1761 dc_z10_restore(dc); 1762 dc_allow_idle_optimizations(dc, false); 1763 1764 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1765 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 1766 1767 /* Check old context for SubVP */ 1768 subvp_prev_use |= (old_pipe->stream && old_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM); 1769 if (subvp_prev_use) 1770 break; 1771 } 1772 1773 for (i = 0; i < context->stream_count; i++) 1774 dc_streams[i] = context->streams[i]; 1775 1776 if (!dcb->funcs->is_accelerated_mode(dcb)) { 1777 disable_vbios_mode_if_required(dc, context); 1778 dc->hwss.enable_accelerated_mode(dc, context); 1779 } 1780 1781 if (context->stream_count > get_seamless_boot_stream_count(context) || 1782 context->stream_count == 0) 1783 dc->hwss.prepare_bandwidth(dc, context); 1784 1785 /* When SubVP is active, all HW programming must be done while 1786 * SubVP lock is acquired 1787 */ 1788 if (dc->hwss.subvp_pipe_control_lock) 1789 dc->hwss.subvp_pipe_control_lock(dc, context, true, true, NULL, subvp_prev_use); 1790 1791 if (dc->debug.enable_double_buffered_dsc_pg_support) 1792 dc->hwss.update_dsc_pg(dc, context, false); 1793 1794 disable_dangling_plane(dc, context); 1795 /* re-program planes for existing stream, in case we need to 1796 * free up plane resource for later use 1797 */ 1798 if (dc->hwss.apply_ctx_for_surface) { 1799 for (i = 0; i < context->stream_count; i++) { 1800 if (context->streams[i]->mode_changed) 1801 continue; 1802 apply_ctx_interdependent_lock(dc, context, context->streams[i], true); 1803 dc->hwss.apply_ctx_for_surface( 1804 dc, context->streams[i], 1805 context->stream_status[i].plane_count, 1806 context); /* use new pipe config in new context */ 1807 apply_ctx_interdependent_lock(dc, context, context->streams[i], false); 1808 dc->hwss.post_unlock_program_front_end(dc, context); 1809 } 1810 } 1811 1812 /* Program hardware */ 1813 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1814 pipe = &context->res_ctx.pipe_ctx[i]; 1815 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe); 1816 } 1817 1818 result = dc->hwss.apply_ctx_to_hw(dc, context); 1819 1820 if (result != DC_OK) { 1821 /* Application of dc_state to hardware stopped. */ 1822 dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY; 1823 return result; 1824 } 1825 1826 dc_trigger_sync(dc, context); 1827 1828 /* Program all planes within new context*/ 1829 if (dc->hwss.program_front_end_for_ctx) { 1830 dc->hwss.interdependent_update_lock(dc, context, true); 1831 dc->hwss.program_front_end_for_ctx(dc, context); 1832 dc->hwss.interdependent_update_lock(dc, context, false); 1833 dc->hwss.post_unlock_program_front_end(dc, context); 1834 } 1835 1836 if (dc->hwss.commit_subvp_config) 1837 dc->hwss.commit_subvp_config(dc, context); 1838 if (dc->hwss.subvp_pipe_control_lock) 1839 dc->hwss.subvp_pipe_control_lock(dc, context, false, true, NULL, subvp_prev_use); 1840 1841 for (i = 0; i < context->stream_count; i++) { 1842 const struct dc_link *link = context->streams[i]->link; 1843 1844 if (!context->streams[i]->mode_changed) 1845 continue; 1846 1847 if (dc->hwss.apply_ctx_for_surface) { 1848 apply_ctx_interdependent_lock(dc, context, context->streams[i], true); 1849 dc->hwss.apply_ctx_for_surface( 1850 dc, context->streams[i], 1851 context->stream_status[i].plane_count, 1852 context); 1853 apply_ctx_interdependent_lock(dc, context, context->streams[i], false); 1854 dc->hwss.post_unlock_program_front_end(dc, context); 1855 } 1856 1857 /* 1858 * enable stereo 1859 * TODO rework dc_enable_stereo call to work with validation sets? 1860 */ 1861 for (k = 0; k < MAX_PIPES; k++) { 1862 pipe = &context->res_ctx.pipe_ctx[k]; 1863 1864 for (l = 0 ; pipe && l < context->stream_count; l++) { 1865 if (context->streams[l] && 1866 context->streams[l] == pipe->stream && 1867 dc->hwss.setup_stereo) 1868 dc->hwss.setup_stereo(pipe, dc); 1869 } 1870 } 1871 1872 CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}", 1873 context->streams[i]->timing.h_addressable, 1874 context->streams[i]->timing.v_addressable, 1875 context->streams[i]->timing.h_total, 1876 context->streams[i]->timing.v_total, 1877 context->streams[i]->timing.pix_clk_100hz / 10); 1878 } 1879 1880 dc_enable_stereo(dc, context, dc_streams, context->stream_count); 1881 1882 if (context->stream_count > get_seamless_boot_stream_count(context) || 1883 context->stream_count == 0) { 1884 /* Must wait for no flips to be pending before doing optimize bw */ 1885 wait_for_no_pipes_pending(dc, context); 1886 /* pplib is notified if disp_num changed */ 1887 dc->hwss.optimize_bandwidth(dc, context); 1888 } 1889 1890 if (dc->debug.enable_double_buffered_dsc_pg_support) 1891 dc->hwss.update_dsc_pg(dc, context, true); 1892 1893 if (dc->ctx->dce_version >= DCE_VERSION_MAX) 1894 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk); 1895 else 1896 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce); 1897 1898 context->stream_mask = get_stream_mask(dc, context); 1899 1900 if (context->stream_mask != dc->current_state->stream_mask) 1901 dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask); 1902 1903 for (i = 0; i < context->stream_count; i++) 1904 context->streams[i]->mode_changed = false; 1905 1906 old_state = dc->current_state; 1907 dc->current_state = context; 1908 1909 dc_release_state(old_state); 1910 1911 dc_retain_state(dc->current_state); 1912 1913 return result; 1914 } 1915 1916 /** 1917 * dc_commit_streams - Commit current stream state 1918 * 1919 * @dc: DC object with the commit state to be configured in the hardware 1920 * @streams: Array with a list of stream state 1921 * @stream_count: Total of streams 1922 * 1923 * Function responsible for commit streams change to the hardware. 1924 * 1925 * Return: 1926 * Return DC_OK if everything work as expected, otherwise, return a dc_status 1927 * code. 1928 */ 1929 enum dc_status dc_commit_streams(struct dc *dc, 1930 struct dc_stream_state *streams[], 1931 uint8_t stream_count) 1932 { 1933 int i, j; 1934 struct dc_state *context; 1935 enum dc_status res = DC_OK; 1936 struct dc_validation_set set[MAX_STREAMS] = {0}; 1937 1938 if (!streams_changed(dc, streams, stream_count)) 1939 return res; 1940 1941 DC_LOG_DC("%s: %d streams\n", __func__, stream_count); 1942 1943 for (i = 0; i < stream_count; i++) { 1944 struct dc_stream_state *stream = streams[i]; 1945 struct dc_stream_status *status = dc_stream_get_status(stream); 1946 1947 dc_stream_log(dc, stream); 1948 1949 set[i].stream = stream; 1950 1951 if (status) { 1952 set[i].plane_count = status->plane_count; 1953 for (j = 0; j < status->plane_count; j++) 1954 set[i].plane_states[j] = status->plane_states[j]; 1955 } 1956 } 1957 1958 context = dc_create_state(dc); 1959 if (!context) 1960 goto context_alloc_fail; 1961 1962 dc_resource_state_copy_construct_current(dc, context); 1963 1964 /* 1965 * Previous validation was perfomred with fast_validation = true and 1966 * the full DML state required for hardware programming was skipped. 1967 * 1968 * Re-validate here to calculate these parameters / watermarks. 1969 */ 1970 res = dc_validate_global_state(dc, context, false); 1971 if (res != DC_OK) { 1972 DC_LOG_ERROR("DC commit global validation failure: %s (%d)", 1973 dc_status_to_str(res), res); 1974 return res; 1975 } 1976 1977 res = dc_commit_state_no_check(dc, context); 1978 1979 context_alloc_fail: 1980 1981 DC_LOG_DC("%s Finished.\n", __func__); 1982 1983 return (res == DC_OK); 1984 } 1985 1986 /* TODO: When the transition to the new commit sequence is done, remove this 1987 * function in favor of dc_commit_streams. */ 1988 bool dc_commit_state(struct dc *dc, struct dc_state *context) 1989 { 1990 enum dc_status result = DC_ERROR_UNEXPECTED; 1991 int i; 1992 1993 /* TODO: Since change commit sequence can have a huge impact, 1994 * we decided to only enable it for DCN3x. However, as soon as 1995 * we get more confident about this change we'll need to enable 1996 * the new sequence for all ASICs. */ 1997 if (dc->ctx->dce_version >= DCN_VERSION_3_2) { 1998 result = dc_commit_streams(dc, context->streams, context->stream_count); 1999 return result == DC_OK; 2000 } 2001 2002 if (!streams_changed(dc, context->streams, context->stream_count)) 2003 return DC_OK; 2004 2005 DC_LOG_DC("%s: %d streams\n", 2006 __func__, context->stream_count); 2007 2008 for (i = 0; i < context->stream_count; i++) { 2009 struct dc_stream_state *stream = context->streams[i]; 2010 2011 dc_stream_log(dc, stream); 2012 } 2013 2014 /* 2015 * Previous validation was perfomred with fast_validation = true and 2016 * the full DML state required for hardware programming was skipped. 2017 * 2018 * Re-validate here to calculate these parameters / watermarks. 2019 */ 2020 result = dc_validate_global_state(dc, context, false); 2021 if (result != DC_OK) { 2022 DC_LOG_ERROR("DC commit global validation failure: %s (%d)", 2023 dc_status_to_str(result), result); 2024 return result; 2025 } 2026 2027 result = dc_commit_state_no_check(dc, context); 2028 2029 return (result == DC_OK); 2030 } 2031 2032 bool dc_acquire_release_mpc_3dlut( 2033 struct dc *dc, bool acquire, 2034 struct dc_stream_state *stream, 2035 struct dc_3dlut **lut, 2036 struct dc_transfer_func **shaper) 2037 { 2038 int pipe_idx; 2039 bool ret = false; 2040 bool found_pipe_idx = false; 2041 const struct resource_pool *pool = dc->res_pool; 2042 struct resource_context *res_ctx = &dc->current_state->res_ctx; 2043 int mpcc_id = 0; 2044 2045 if (pool && res_ctx) { 2046 if (acquire) { 2047 /*find pipe idx for the given stream*/ 2048 for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) { 2049 if (res_ctx->pipe_ctx[pipe_idx].stream == stream) { 2050 found_pipe_idx = true; 2051 mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst; 2052 break; 2053 } 2054 } 2055 } else 2056 found_pipe_idx = true;/*for release pipe_idx is not required*/ 2057 2058 if (found_pipe_idx) { 2059 if (acquire && pool->funcs->acquire_post_bldn_3dlut) 2060 ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper); 2061 else if (!acquire && pool->funcs->release_post_bldn_3dlut) 2062 ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper); 2063 } 2064 } 2065 return ret; 2066 } 2067 2068 static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context) 2069 { 2070 int i; 2071 struct pipe_ctx *pipe; 2072 2073 for (i = 0; i < MAX_PIPES; i++) { 2074 pipe = &context->res_ctx.pipe_ctx[i]; 2075 2076 // Don't check flip pending on phantom pipes 2077 if (!pipe->plane_state || (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM)) 2078 continue; 2079 2080 /* Must set to false to start with, due to OR in update function */ 2081 pipe->plane_state->status.is_flip_pending = false; 2082 dc->hwss.update_pending_status(pipe); 2083 if (pipe->plane_state->status.is_flip_pending) 2084 return true; 2085 } 2086 return false; 2087 } 2088 2089 /* Perform updates here which need to be deferred until next vupdate 2090 * 2091 * i.e. blnd lut, 3dlut, and shaper lut bypass regs are double buffered 2092 * but forcing lut memory to shutdown state is immediate. This causes 2093 * single frame corruption as lut gets disabled mid-frame unless shutdown 2094 * is deferred until after entering bypass. 2095 */ 2096 static void process_deferred_updates(struct dc *dc) 2097 { 2098 int i = 0; 2099 2100 if (dc->debug.enable_mem_low_power.bits.cm) { 2101 ASSERT(dc->dcn_ip->max_num_dpp); 2102 for (i = 0; i < dc->dcn_ip->max_num_dpp; i++) 2103 if (dc->res_pool->dpps[i]->funcs->dpp_deferred_update) 2104 dc->res_pool->dpps[i]->funcs->dpp_deferred_update(dc->res_pool->dpps[i]); 2105 } 2106 } 2107 2108 void dc_post_update_surfaces_to_stream(struct dc *dc) 2109 { 2110 int i; 2111 struct dc_state *context = dc->current_state; 2112 2113 if ((!dc->optimized_required) || get_seamless_boot_stream_count(context) > 0) 2114 return; 2115 2116 post_surface_trace(dc); 2117 2118 /* 2119 * Only relevant for DCN behavior where we can guarantee the optimization 2120 * is safe to apply - retain the legacy behavior for DCE. 2121 */ 2122 2123 if (dc->ctx->dce_version < DCE_VERSION_MAX) 2124 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce); 2125 else { 2126 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk); 2127 2128 if (is_flip_pending_in_pipes(dc, context)) 2129 return; 2130 2131 for (i = 0; i < dc->res_pool->pipe_count; i++) 2132 if (context->res_ctx.pipe_ctx[i].stream == NULL || 2133 context->res_ctx.pipe_ctx[i].plane_state == NULL) { 2134 context->res_ctx.pipe_ctx[i].pipe_idx = i; 2135 dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]); 2136 } 2137 2138 process_deferred_updates(dc); 2139 2140 dc->hwss.optimize_bandwidth(dc, context); 2141 2142 if (dc->debug.enable_double_buffered_dsc_pg_support) 2143 dc->hwss.update_dsc_pg(dc, context, true); 2144 } 2145 2146 dc->optimized_required = false; 2147 dc->wm_optimized_required = false; 2148 } 2149 2150 static void init_state(struct dc *dc, struct dc_state *context) 2151 { 2152 /* Each context must have their own instance of VBA and in order to 2153 * initialize and obtain IP and SOC the base DML instance from DC is 2154 * initially copied into every context 2155 */ 2156 memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib)); 2157 } 2158 2159 struct dc_state *dc_create_state(struct dc *dc) 2160 { 2161 struct dc_state *context = kvzalloc(sizeof(struct dc_state), 2162 GFP_KERNEL); 2163 2164 if (!context) 2165 return NULL; 2166 2167 init_state(dc, context); 2168 2169 kref_init(&context->refcount); 2170 2171 return context; 2172 } 2173 2174 struct dc_state *dc_copy_state(struct dc_state *src_ctx) 2175 { 2176 int i, j; 2177 struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL); 2178 2179 if (!new_ctx) 2180 return NULL; 2181 memcpy(new_ctx, src_ctx, sizeof(struct dc_state)); 2182 2183 for (i = 0; i < MAX_PIPES; i++) { 2184 struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i]; 2185 2186 if (cur_pipe->top_pipe) 2187 cur_pipe->top_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx]; 2188 2189 if (cur_pipe->bottom_pipe) 2190 cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx]; 2191 2192 if (cur_pipe->prev_odm_pipe) 2193 cur_pipe->prev_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx]; 2194 2195 if (cur_pipe->next_odm_pipe) 2196 cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx]; 2197 2198 } 2199 2200 for (i = 0; i < new_ctx->stream_count; i++) { 2201 dc_stream_retain(new_ctx->streams[i]); 2202 for (j = 0; j < new_ctx->stream_status[i].plane_count; j++) 2203 dc_plane_state_retain( 2204 new_ctx->stream_status[i].plane_states[j]); 2205 } 2206 2207 kref_init(&new_ctx->refcount); 2208 2209 return new_ctx; 2210 } 2211 2212 void dc_retain_state(struct dc_state *context) 2213 { 2214 kref_get(&context->refcount); 2215 } 2216 2217 static void dc_state_free(struct kref *kref) 2218 { 2219 struct dc_state *context = container_of(kref, struct dc_state, refcount); 2220 dc_resource_state_destruct(context); 2221 kvfree(context); 2222 } 2223 2224 void dc_release_state(struct dc_state *context) 2225 { 2226 kref_put(&context->refcount, dc_state_free); 2227 } 2228 2229 bool dc_set_generic_gpio_for_stereo(bool enable, 2230 struct gpio_service *gpio_service) 2231 { 2232 enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR; 2233 struct gpio_pin_info pin_info; 2234 struct gpio *generic; 2235 struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config), 2236 GFP_KERNEL); 2237 2238 if (!config) 2239 return false; 2240 pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0); 2241 2242 if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) { 2243 kfree(config); 2244 return false; 2245 } else { 2246 generic = dal_gpio_service_create_generic_mux( 2247 gpio_service, 2248 pin_info.offset, 2249 pin_info.mask); 2250 } 2251 2252 if (!generic) { 2253 kfree(config); 2254 return false; 2255 } 2256 2257 gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT); 2258 2259 config->enable_output_from_mux = enable; 2260 config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC; 2261 2262 if (gpio_result == GPIO_RESULT_OK) 2263 gpio_result = dal_mux_setup_config(generic, config); 2264 2265 if (gpio_result == GPIO_RESULT_OK) { 2266 dal_gpio_close(generic); 2267 dal_gpio_destroy_generic_mux(&generic); 2268 kfree(config); 2269 return true; 2270 } else { 2271 dal_gpio_close(generic); 2272 dal_gpio_destroy_generic_mux(&generic); 2273 kfree(config); 2274 return false; 2275 } 2276 } 2277 2278 static bool is_surface_in_context( 2279 const struct dc_state *context, 2280 const struct dc_plane_state *plane_state) 2281 { 2282 int j; 2283 2284 for (j = 0; j < MAX_PIPES; j++) { 2285 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; 2286 2287 if (plane_state == pipe_ctx->plane_state) { 2288 return true; 2289 } 2290 } 2291 2292 return false; 2293 } 2294 2295 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u) 2296 { 2297 union surface_update_flags *update_flags = &u->surface->update_flags; 2298 enum surface_update_type update_type = UPDATE_TYPE_FAST; 2299 2300 if (!u->plane_info) 2301 return UPDATE_TYPE_FAST; 2302 2303 if (u->plane_info->color_space != u->surface->color_space) { 2304 update_flags->bits.color_space_change = 1; 2305 elevate_update_type(&update_type, UPDATE_TYPE_MED); 2306 } 2307 2308 if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) { 2309 update_flags->bits.horizontal_mirror_change = 1; 2310 elevate_update_type(&update_type, UPDATE_TYPE_MED); 2311 } 2312 2313 if (u->plane_info->rotation != u->surface->rotation) { 2314 update_flags->bits.rotation_change = 1; 2315 elevate_update_type(&update_type, UPDATE_TYPE_FULL); 2316 } 2317 2318 if (u->plane_info->format != u->surface->format) { 2319 update_flags->bits.pixel_format_change = 1; 2320 elevate_update_type(&update_type, UPDATE_TYPE_FULL); 2321 } 2322 2323 if (u->plane_info->stereo_format != u->surface->stereo_format) { 2324 update_flags->bits.stereo_format_change = 1; 2325 elevate_update_type(&update_type, UPDATE_TYPE_FULL); 2326 } 2327 2328 if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) { 2329 update_flags->bits.per_pixel_alpha_change = 1; 2330 elevate_update_type(&update_type, UPDATE_TYPE_MED); 2331 } 2332 2333 if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) { 2334 update_flags->bits.global_alpha_change = 1; 2335 elevate_update_type(&update_type, UPDATE_TYPE_MED); 2336 } 2337 2338 if (u->plane_info->dcc.enable != u->surface->dcc.enable 2339 || u->plane_info->dcc.dcc_ind_blk != u->surface->dcc.dcc_ind_blk 2340 || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) { 2341 /* During DCC on/off, stutter period is calculated before 2342 * DCC has fully transitioned. This results in incorrect 2343 * stutter period calculation. Triggering a full update will 2344 * recalculate stutter period. 2345 */ 2346 update_flags->bits.dcc_change = 1; 2347 elevate_update_type(&update_type, UPDATE_TYPE_FULL); 2348 } 2349 2350 if (resource_pixel_format_to_bpp(u->plane_info->format) != 2351 resource_pixel_format_to_bpp(u->surface->format)) { 2352 /* different bytes per element will require full bandwidth 2353 * and DML calculation 2354 */ 2355 update_flags->bits.bpp_change = 1; 2356 elevate_update_type(&update_type, UPDATE_TYPE_FULL); 2357 } 2358 2359 if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch 2360 || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) { 2361 update_flags->bits.plane_size_change = 1; 2362 elevate_update_type(&update_type, UPDATE_TYPE_MED); 2363 } 2364 2365 2366 if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info, 2367 sizeof(union dc_tiling_info)) != 0) { 2368 update_flags->bits.swizzle_change = 1; 2369 elevate_update_type(&update_type, UPDATE_TYPE_MED); 2370 2371 /* todo: below are HW dependent, we should add a hook to 2372 * DCE/N resource and validated there. 2373 */ 2374 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) { 2375 /* swizzled mode requires RQ to be setup properly, 2376 * thus need to run DML to calculate RQ settings 2377 */ 2378 update_flags->bits.bandwidth_change = 1; 2379 elevate_update_type(&update_type, UPDATE_TYPE_FULL); 2380 } 2381 } 2382 2383 /* This should be UPDATE_TYPE_FAST if nothing has changed. */ 2384 return update_type; 2385 } 2386 2387 static enum surface_update_type get_scaling_info_update_type( 2388 const struct dc_surface_update *u) 2389 { 2390 union surface_update_flags *update_flags = &u->surface->update_flags; 2391 2392 if (!u->scaling_info) 2393 return UPDATE_TYPE_FAST; 2394 2395 if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width 2396 || u->scaling_info->clip_rect.height != u->surface->clip_rect.height 2397 || u->scaling_info->dst_rect.width != u->surface->dst_rect.width 2398 || u->scaling_info->dst_rect.height != u->surface->dst_rect.height 2399 || u->scaling_info->scaling_quality.integer_scaling != 2400 u->surface->scaling_quality.integer_scaling 2401 ) { 2402 update_flags->bits.scaling_change = 1; 2403 2404 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width 2405 || u->scaling_info->dst_rect.height < u->surface->dst_rect.height) 2406 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width 2407 || u->scaling_info->dst_rect.height < u->surface->src_rect.height)) 2408 /* Making dst rect smaller requires a bandwidth change */ 2409 update_flags->bits.bandwidth_change = 1; 2410 } 2411 2412 if (u->scaling_info->src_rect.width != u->surface->src_rect.width 2413 || u->scaling_info->src_rect.height != u->surface->src_rect.height) { 2414 2415 update_flags->bits.scaling_change = 1; 2416 if (u->scaling_info->src_rect.width > u->surface->src_rect.width 2417 || u->scaling_info->src_rect.height > u->surface->src_rect.height) 2418 /* Making src rect bigger requires a bandwidth change */ 2419 update_flags->bits.clock_change = 1; 2420 } 2421 2422 if (u->scaling_info->src_rect.x != u->surface->src_rect.x 2423 || u->scaling_info->src_rect.y != u->surface->src_rect.y 2424 || u->scaling_info->clip_rect.x != u->surface->clip_rect.x 2425 || u->scaling_info->clip_rect.y != u->surface->clip_rect.y 2426 || u->scaling_info->dst_rect.x != u->surface->dst_rect.x 2427 || u->scaling_info->dst_rect.y != u->surface->dst_rect.y) 2428 update_flags->bits.position_change = 1; 2429 2430 if (update_flags->bits.clock_change 2431 || update_flags->bits.bandwidth_change 2432 || update_flags->bits.scaling_change) 2433 return UPDATE_TYPE_FULL; 2434 2435 if (update_flags->bits.position_change) 2436 return UPDATE_TYPE_MED; 2437 2438 return UPDATE_TYPE_FAST; 2439 } 2440 2441 static enum surface_update_type det_surface_update(const struct dc *dc, 2442 const struct dc_surface_update *u) 2443 { 2444 const struct dc_state *context = dc->current_state; 2445 enum surface_update_type type; 2446 enum surface_update_type overall_type = UPDATE_TYPE_FAST; 2447 union surface_update_flags *update_flags = &u->surface->update_flags; 2448 2449 if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) { 2450 update_flags->raw = 0xFFFFFFFF; 2451 return UPDATE_TYPE_FULL; 2452 } 2453 2454 update_flags->raw = 0; // Reset all flags 2455 2456 type = get_plane_info_update_type(u); 2457 elevate_update_type(&overall_type, type); 2458 2459 type = get_scaling_info_update_type(u); 2460 elevate_update_type(&overall_type, type); 2461 2462 if (u->flip_addr) { 2463 update_flags->bits.addr_update = 1; 2464 if (u->flip_addr->address.tmz_surface != u->surface->address.tmz_surface) { 2465 update_flags->bits.tmz_changed = 1; 2466 elevate_update_type(&overall_type, UPDATE_TYPE_FULL); 2467 } 2468 } 2469 if (u->in_transfer_func) 2470 update_flags->bits.in_transfer_func_change = 1; 2471 2472 if (u->input_csc_color_matrix) 2473 update_flags->bits.input_csc_change = 1; 2474 2475 if (u->coeff_reduction_factor) 2476 update_flags->bits.coeff_reduction_change = 1; 2477 2478 if (u->gamut_remap_matrix) 2479 update_flags->bits.gamut_remap_change = 1; 2480 2481 if (u->gamma) { 2482 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN; 2483 2484 if (u->plane_info) 2485 format = u->plane_info->format; 2486 else if (u->surface) 2487 format = u->surface->format; 2488 2489 if (dce_use_lut(format)) 2490 update_flags->bits.gamma_change = 1; 2491 } 2492 2493 if (u->lut3d_func || u->func_shaper) 2494 update_flags->bits.lut_3d = 1; 2495 2496 if (u->hdr_mult.value) 2497 if (u->hdr_mult.value != u->surface->hdr_mult.value) { 2498 update_flags->bits.hdr_mult = 1; 2499 elevate_update_type(&overall_type, UPDATE_TYPE_MED); 2500 } 2501 2502 if (update_flags->bits.in_transfer_func_change) { 2503 type = UPDATE_TYPE_MED; 2504 elevate_update_type(&overall_type, type); 2505 } 2506 2507 if (update_flags->bits.input_csc_change 2508 || update_flags->bits.coeff_reduction_change 2509 || update_flags->bits.lut_3d 2510 || update_flags->bits.gamma_change 2511 || update_flags->bits.gamut_remap_change) { 2512 type = UPDATE_TYPE_FULL; 2513 elevate_update_type(&overall_type, type); 2514 } 2515 2516 return overall_type; 2517 } 2518 2519 static enum surface_update_type check_update_surfaces_for_stream( 2520 struct dc *dc, 2521 struct dc_surface_update *updates, 2522 int surface_count, 2523 struct dc_stream_update *stream_update, 2524 const struct dc_stream_status *stream_status) 2525 { 2526 int i; 2527 enum surface_update_type overall_type = UPDATE_TYPE_FAST; 2528 2529 if (dc->idle_optimizations_allowed) 2530 overall_type = UPDATE_TYPE_FULL; 2531 2532 if (stream_status == NULL || stream_status->plane_count != surface_count) 2533 overall_type = UPDATE_TYPE_FULL; 2534 2535 if (stream_update && stream_update->pending_test_pattern) { 2536 overall_type = UPDATE_TYPE_FULL; 2537 } 2538 2539 /* some stream updates require passive update */ 2540 if (stream_update) { 2541 union stream_update_flags *su_flags = &stream_update->stream->update_flags; 2542 2543 if ((stream_update->src.height != 0 && stream_update->src.width != 0) || 2544 (stream_update->dst.height != 0 && stream_update->dst.width != 0) || 2545 stream_update->integer_scaling_update) 2546 su_flags->bits.scaling = 1; 2547 2548 if (stream_update->out_transfer_func) 2549 su_flags->bits.out_tf = 1; 2550 2551 if (stream_update->abm_level) 2552 su_flags->bits.abm_level = 1; 2553 2554 if (stream_update->dpms_off) 2555 su_flags->bits.dpms_off = 1; 2556 2557 if (stream_update->gamut_remap) 2558 su_flags->bits.gamut_remap = 1; 2559 2560 if (stream_update->wb_update) 2561 su_flags->bits.wb_update = 1; 2562 2563 if (stream_update->dsc_config) 2564 su_flags->bits.dsc_changed = 1; 2565 2566 if (stream_update->mst_bw_update) 2567 su_flags->bits.mst_bw = 1; 2568 if (stream_update->crtc_timing_adjust && dc_extended_blank_supported(dc)) 2569 su_flags->bits.crtc_timing_adjust = 1; 2570 2571 if (su_flags->raw != 0) 2572 overall_type = UPDATE_TYPE_FULL; 2573 2574 if (stream_update->output_csc_transform || stream_update->output_color_space) 2575 su_flags->bits.out_csc = 1; 2576 } 2577 2578 for (i = 0 ; i < surface_count; i++) { 2579 enum surface_update_type type = 2580 det_surface_update(dc, &updates[i]); 2581 2582 elevate_update_type(&overall_type, type); 2583 } 2584 2585 return overall_type; 2586 } 2587 2588 static bool dc_check_is_fullscreen_video(struct rect src, struct rect clip_rect) 2589 { 2590 int view_height, view_width, clip_x, clip_y, clip_width, clip_height; 2591 2592 view_height = src.height; 2593 view_width = src.width; 2594 2595 clip_x = clip_rect.x; 2596 clip_y = clip_rect.y; 2597 2598 clip_width = clip_rect.width; 2599 clip_height = clip_rect.height; 2600 2601 /* check for centered video accounting for off by 1 scaling truncation */ 2602 if ((view_height - clip_y - clip_height <= clip_y + 1) && 2603 (view_width - clip_x - clip_width <= clip_x + 1) && 2604 (view_height - clip_y - clip_height >= clip_y - 1) && 2605 (view_width - clip_x - clip_width >= clip_x - 1)) { 2606 2607 /* when OS scales up/down to letter box, it may end up 2608 * with few blank pixels on the border due to truncating. 2609 * Add offset margin to account for this 2610 */ 2611 if (clip_x <= 4 || clip_y <= 4) 2612 return true; 2613 } 2614 2615 return false; 2616 } 2617 2618 static enum surface_update_type check_boundary_crossing_for_windowed_mpo_with_odm(struct dc *dc, 2619 struct dc_surface_update *srf_updates, int surface_count, 2620 enum surface_update_type update_type) 2621 { 2622 enum surface_update_type new_update_type = update_type; 2623 int i, j; 2624 struct pipe_ctx *pipe = NULL; 2625 struct dc_stream_state *stream; 2626 2627 /* Check that we are in windowed MPO with ODM 2628 * - look for MPO pipe by scanning pipes for first pipe matching 2629 * surface that has moved ( position change ) 2630 * - MPO pipe will have top pipe 2631 * - check that top pipe has ODM pointer 2632 */ 2633 if ((surface_count > 1) && dc->config.enable_windowed_mpo_odm) { 2634 for (i = 0; i < surface_count; i++) { 2635 if (srf_updates[i].surface && srf_updates[i].scaling_info 2636 && srf_updates[i].surface->update_flags.bits.position_change) { 2637 2638 for (j = 0; j < dc->res_pool->pipe_count; j++) { 2639 if (srf_updates[i].surface == dc->current_state->res_ctx.pipe_ctx[j].plane_state) { 2640 pipe = &dc->current_state->res_ctx.pipe_ctx[j]; 2641 stream = pipe->stream; 2642 break; 2643 } 2644 } 2645 2646 if (pipe && pipe->top_pipe && (get_num_odm_splits(pipe->top_pipe) > 0) && stream 2647 && !dc_check_is_fullscreen_video(stream->src, srf_updates[i].scaling_info->clip_rect)) { 2648 struct rect old_clip_rect, new_clip_rect; 2649 bool old_clip_rect_left, old_clip_rect_right, old_clip_rect_middle; 2650 bool new_clip_rect_left, new_clip_rect_right, new_clip_rect_middle; 2651 2652 old_clip_rect = srf_updates[i].surface->clip_rect; 2653 new_clip_rect = srf_updates[i].scaling_info->clip_rect; 2654 2655 old_clip_rect_left = ((old_clip_rect.x + old_clip_rect.width) <= (stream->src.x + (stream->src.width/2))); 2656 old_clip_rect_right = (old_clip_rect.x >= (stream->src.x + (stream->src.width/2))); 2657 old_clip_rect_middle = !old_clip_rect_left && !old_clip_rect_right; 2658 2659 new_clip_rect_left = ((new_clip_rect.x + new_clip_rect.width) <= (stream->src.x + (stream->src.width/2))); 2660 new_clip_rect_right = (new_clip_rect.x >= (stream->src.x + (stream->src.width/2))); 2661 new_clip_rect_middle = !new_clip_rect_left && !new_clip_rect_right; 2662 2663 if (old_clip_rect_left && new_clip_rect_middle) 2664 new_update_type = UPDATE_TYPE_FULL; 2665 else if (old_clip_rect_middle && new_clip_rect_right) 2666 new_update_type = UPDATE_TYPE_FULL; 2667 else if (old_clip_rect_right && new_clip_rect_middle) 2668 new_update_type = UPDATE_TYPE_FULL; 2669 else if (old_clip_rect_middle && new_clip_rect_left) 2670 new_update_type = UPDATE_TYPE_FULL; 2671 } 2672 } 2673 } 2674 } 2675 return new_update_type; 2676 } 2677 2678 /* 2679 * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full) 2680 * 2681 * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types 2682 */ 2683 enum surface_update_type dc_check_update_surfaces_for_stream( 2684 struct dc *dc, 2685 struct dc_surface_update *updates, 2686 int surface_count, 2687 struct dc_stream_update *stream_update, 2688 const struct dc_stream_status *stream_status) 2689 { 2690 int i; 2691 enum surface_update_type type; 2692 2693 if (stream_update) 2694 stream_update->stream->update_flags.raw = 0; 2695 for (i = 0; i < surface_count; i++) 2696 updates[i].surface->update_flags.raw = 0; 2697 2698 type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status); 2699 if (type == UPDATE_TYPE_FULL) { 2700 if (stream_update) { 2701 uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed; 2702 stream_update->stream->update_flags.raw = 0xFFFFFFFF; 2703 stream_update->stream->update_flags.bits.dsc_changed = dsc_changed; 2704 } 2705 for (i = 0; i < surface_count; i++) 2706 updates[i].surface->update_flags.raw = 0xFFFFFFFF; 2707 } 2708 2709 if (type == UPDATE_TYPE_MED) 2710 type = check_boundary_crossing_for_windowed_mpo_with_odm(dc, 2711 updates, surface_count, type); 2712 2713 if (type == UPDATE_TYPE_FAST) { 2714 // If there's an available clock comparator, we use that. 2715 if (dc->clk_mgr->funcs->are_clock_states_equal) { 2716 if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk)) 2717 dc->optimized_required = true; 2718 // Else we fallback to mem compare. 2719 } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) { 2720 dc->optimized_required = true; 2721 } 2722 2723 dc->optimized_required |= dc->wm_optimized_required; 2724 } 2725 2726 return type; 2727 } 2728 2729 static struct dc_stream_status *stream_get_status( 2730 struct dc_state *ctx, 2731 struct dc_stream_state *stream) 2732 { 2733 uint8_t i; 2734 2735 for (i = 0; i < ctx->stream_count; i++) { 2736 if (stream == ctx->streams[i]) { 2737 return &ctx->stream_status[i]; 2738 } 2739 } 2740 2741 return NULL; 2742 } 2743 2744 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL; 2745 2746 static void copy_surface_update_to_plane( 2747 struct dc_plane_state *surface, 2748 struct dc_surface_update *srf_update) 2749 { 2750 if (srf_update->flip_addr) { 2751 surface->address = srf_update->flip_addr->address; 2752 surface->flip_immediate = 2753 srf_update->flip_addr->flip_immediate; 2754 surface->time.time_elapsed_in_us[surface->time.index] = 2755 srf_update->flip_addr->flip_timestamp_in_us - 2756 surface->time.prev_update_time_in_us; 2757 surface->time.prev_update_time_in_us = 2758 srf_update->flip_addr->flip_timestamp_in_us; 2759 surface->time.index++; 2760 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX) 2761 surface->time.index = 0; 2762 2763 surface->triplebuffer_flips = srf_update->flip_addr->triplebuffer_flips; 2764 } 2765 2766 if (srf_update->scaling_info) { 2767 surface->scaling_quality = 2768 srf_update->scaling_info->scaling_quality; 2769 surface->dst_rect = 2770 srf_update->scaling_info->dst_rect; 2771 surface->src_rect = 2772 srf_update->scaling_info->src_rect; 2773 surface->clip_rect = 2774 srf_update->scaling_info->clip_rect; 2775 } 2776 2777 if (srf_update->plane_info) { 2778 surface->color_space = 2779 srf_update->plane_info->color_space; 2780 surface->format = 2781 srf_update->plane_info->format; 2782 surface->plane_size = 2783 srf_update->plane_info->plane_size; 2784 surface->rotation = 2785 srf_update->plane_info->rotation; 2786 surface->horizontal_mirror = 2787 srf_update->plane_info->horizontal_mirror; 2788 surface->stereo_format = 2789 srf_update->plane_info->stereo_format; 2790 surface->tiling_info = 2791 srf_update->plane_info->tiling_info; 2792 surface->visible = 2793 srf_update->plane_info->visible; 2794 surface->per_pixel_alpha = 2795 srf_update->plane_info->per_pixel_alpha; 2796 surface->global_alpha = 2797 srf_update->plane_info->global_alpha; 2798 surface->global_alpha_value = 2799 srf_update->plane_info->global_alpha_value; 2800 surface->dcc = 2801 srf_update->plane_info->dcc; 2802 surface->layer_index = 2803 srf_update->plane_info->layer_index; 2804 } 2805 2806 if (srf_update->gamma && 2807 (surface->gamma_correction != 2808 srf_update->gamma)) { 2809 memcpy(&surface->gamma_correction->entries, 2810 &srf_update->gamma->entries, 2811 sizeof(struct dc_gamma_entries)); 2812 surface->gamma_correction->is_identity = 2813 srf_update->gamma->is_identity; 2814 surface->gamma_correction->num_entries = 2815 srf_update->gamma->num_entries; 2816 surface->gamma_correction->type = 2817 srf_update->gamma->type; 2818 } 2819 2820 if (srf_update->in_transfer_func && 2821 (surface->in_transfer_func != 2822 srf_update->in_transfer_func)) { 2823 surface->in_transfer_func->sdr_ref_white_level = 2824 srf_update->in_transfer_func->sdr_ref_white_level; 2825 surface->in_transfer_func->tf = 2826 srf_update->in_transfer_func->tf; 2827 surface->in_transfer_func->type = 2828 srf_update->in_transfer_func->type; 2829 memcpy(&surface->in_transfer_func->tf_pts, 2830 &srf_update->in_transfer_func->tf_pts, 2831 sizeof(struct dc_transfer_func_distributed_points)); 2832 } 2833 2834 if (srf_update->func_shaper && 2835 (surface->in_shaper_func != 2836 srf_update->func_shaper)) 2837 memcpy(surface->in_shaper_func, srf_update->func_shaper, 2838 sizeof(*surface->in_shaper_func)); 2839 2840 if (srf_update->lut3d_func && 2841 (surface->lut3d_func != 2842 srf_update->lut3d_func)) 2843 memcpy(surface->lut3d_func, srf_update->lut3d_func, 2844 sizeof(*surface->lut3d_func)); 2845 2846 if (srf_update->hdr_mult.value) 2847 surface->hdr_mult = 2848 srf_update->hdr_mult; 2849 2850 if (srf_update->blend_tf && 2851 (surface->blend_tf != 2852 srf_update->blend_tf)) 2853 memcpy(surface->blend_tf, srf_update->blend_tf, 2854 sizeof(*surface->blend_tf)); 2855 2856 if (srf_update->input_csc_color_matrix) 2857 surface->input_csc_color_matrix = 2858 *srf_update->input_csc_color_matrix; 2859 2860 if (srf_update->coeff_reduction_factor) 2861 surface->coeff_reduction_factor = 2862 *srf_update->coeff_reduction_factor; 2863 2864 if (srf_update->gamut_remap_matrix) 2865 surface->gamut_remap_matrix = 2866 *srf_update->gamut_remap_matrix; 2867 } 2868 2869 static void copy_stream_update_to_stream(struct dc *dc, 2870 struct dc_state *context, 2871 struct dc_stream_state *stream, 2872 struct dc_stream_update *update) 2873 { 2874 struct dc_context *dc_ctx = dc->ctx; 2875 2876 if (update == NULL || stream == NULL) 2877 return; 2878 2879 if (update->src.height && update->src.width) 2880 stream->src = update->src; 2881 2882 if (update->dst.height && update->dst.width) 2883 stream->dst = update->dst; 2884 2885 if (update->out_transfer_func && 2886 stream->out_transfer_func != update->out_transfer_func) { 2887 stream->out_transfer_func->sdr_ref_white_level = 2888 update->out_transfer_func->sdr_ref_white_level; 2889 stream->out_transfer_func->tf = update->out_transfer_func->tf; 2890 stream->out_transfer_func->type = 2891 update->out_transfer_func->type; 2892 memcpy(&stream->out_transfer_func->tf_pts, 2893 &update->out_transfer_func->tf_pts, 2894 sizeof(struct dc_transfer_func_distributed_points)); 2895 } 2896 2897 if (update->hdr_static_metadata) 2898 stream->hdr_static_metadata = *update->hdr_static_metadata; 2899 2900 if (update->abm_level) 2901 stream->abm_level = *update->abm_level; 2902 2903 if (update->periodic_interrupt) 2904 stream->periodic_interrupt = *update->periodic_interrupt; 2905 2906 if (update->gamut_remap) 2907 stream->gamut_remap_matrix = *update->gamut_remap; 2908 2909 /* Note: this being updated after mode set is currently not a use case 2910 * however if it arises OCSC would need to be reprogrammed at the 2911 * minimum 2912 */ 2913 if (update->output_color_space) 2914 stream->output_color_space = *update->output_color_space; 2915 2916 if (update->output_csc_transform) 2917 stream->csc_color_matrix = *update->output_csc_transform; 2918 2919 if (update->vrr_infopacket) 2920 stream->vrr_infopacket = *update->vrr_infopacket; 2921 2922 if (update->allow_freesync) 2923 stream->allow_freesync = *update->allow_freesync; 2924 2925 if (update->vrr_active_variable) 2926 stream->vrr_active_variable = *update->vrr_active_variable; 2927 2928 if (update->crtc_timing_adjust) 2929 stream->adjust = *update->crtc_timing_adjust; 2930 2931 if (update->dpms_off) 2932 stream->dpms_off = *update->dpms_off; 2933 2934 if (update->hfvsif_infopacket) 2935 stream->hfvsif_infopacket = *update->hfvsif_infopacket; 2936 2937 if (update->vtem_infopacket) 2938 stream->vtem_infopacket = *update->vtem_infopacket; 2939 2940 if (update->vsc_infopacket) 2941 stream->vsc_infopacket = *update->vsc_infopacket; 2942 2943 if (update->vsp_infopacket) 2944 stream->vsp_infopacket = *update->vsp_infopacket; 2945 2946 if (update->dither_option) 2947 stream->dither_option = *update->dither_option; 2948 2949 if (update->pending_test_pattern) 2950 stream->test_pattern = *update->pending_test_pattern; 2951 /* update current stream with writeback info */ 2952 if (update->wb_update) { 2953 int i; 2954 2955 stream->num_wb_info = update->wb_update->num_wb_info; 2956 ASSERT(stream->num_wb_info <= MAX_DWB_PIPES); 2957 for (i = 0; i < stream->num_wb_info; i++) 2958 stream->writeback_info[i] = 2959 update->wb_update->writeback_info[i]; 2960 } 2961 if (update->dsc_config) { 2962 struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg; 2963 uint32_t old_dsc_enabled = stream->timing.flags.DSC; 2964 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 && 2965 update->dsc_config->num_slices_v != 0); 2966 2967 /* Use temporarry context for validating new DSC config */ 2968 struct dc_state *dsc_validate_context = dc_create_state(dc); 2969 2970 if (dsc_validate_context) { 2971 dc_resource_state_copy_construct(dc->current_state, dsc_validate_context); 2972 2973 stream->timing.dsc_cfg = *update->dsc_config; 2974 stream->timing.flags.DSC = enable_dsc; 2975 if (!dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true)) { 2976 stream->timing.dsc_cfg = old_dsc_cfg; 2977 stream->timing.flags.DSC = old_dsc_enabled; 2978 update->dsc_config = NULL; 2979 } 2980 2981 dc_release_state(dsc_validate_context); 2982 } else { 2983 DC_ERROR("Failed to allocate new validate context for DSC change\n"); 2984 update->dsc_config = NULL; 2985 } 2986 } 2987 } 2988 2989 static bool update_planes_and_stream_state(struct dc *dc, 2990 struct dc_surface_update *srf_updates, int surface_count, 2991 struct dc_stream_state *stream, 2992 struct dc_stream_update *stream_update, 2993 enum surface_update_type *new_update_type, 2994 struct dc_state **new_context) 2995 { 2996 struct dc_state *context; 2997 int i, j; 2998 enum surface_update_type update_type; 2999 const struct dc_stream_status *stream_status; 3000 struct dc_context *dc_ctx = dc->ctx; 3001 3002 stream_status = dc_stream_get_status(stream); 3003 3004 if (!stream_status) { 3005 if (surface_count) /* Only an error condition if surf_count non-zero*/ 3006 ASSERT(false); 3007 3008 return false; /* Cannot commit surface to stream that is not committed */ 3009 } 3010 3011 context = dc->current_state; 3012 3013 update_type = dc_check_update_surfaces_for_stream( 3014 dc, srf_updates, surface_count, stream_update, stream_status); 3015 3016 /* update current stream with the new updates */ 3017 copy_stream_update_to_stream(dc, context, stream, stream_update); 3018 3019 /* do not perform surface update if surface has invalid dimensions 3020 * (all zero) and no scaling_info is provided 3021 */ 3022 if (surface_count > 0) { 3023 for (i = 0; i < surface_count; i++) { 3024 if ((srf_updates[i].surface->src_rect.width == 0 || 3025 srf_updates[i].surface->src_rect.height == 0 || 3026 srf_updates[i].surface->dst_rect.width == 0 || 3027 srf_updates[i].surface->dst_rect.height == 0) && 3028 (!srf_updates[i].scaling_info || 3029 srf_updates[i].scaling_info->src_rect.width == 0 || 3030 srf_updates[i].scaling_info->src_rect.height == 0 || 3031 srf_updates[i].scaling_info->dst_rect.width == 0 || 3032 srf_updates[i].scaling_info->dst_rect.height == 0)) { 3033 DC_ERROR("Invalid src/dst rects in surface update!\n"); 3034 return false; 3035 } 3036 } 3037 } 3038 3039 if (update_type >= update_surface_trace_level) 3040 update_surface_trace(dc, srf_updates, surface_count); 3041 3042 if (update_type >= UPDATE_TYPE_FULL) { 3043 struct dc_plane_state *new_planes[MAX_SURFACES] = {0}; 3044 3045 for (i = 0; i < surface_count; i++) 3046 new_planes[i] = srf_updates[i].surface; 3047 3048 /* initialize scratch memory for building context */ 3049 context = dc_create_state(dc); 3050 if (context == NULL) { 3051 DC_ERROR("Failed to allocate new validate context!\n"); 3052 return false; 3053 } 3054 3055 dc_resource_state_copy_construct( 3056 dc->current_state, context); 3057 3058 /* For each full update, remove all existing phantom pipes first. 3059 * Ensures that we have enough pipes for newly added MPO planes 3060 */ 3061 if (dc->res_pool->funcs->remove_phantom_pipes) 3062 dc->res_pool->funcs->remove_phantom_pipes(dc, context); 3063 3064 /*remove old surfaces from context */ 3065 if (!dc_rem_all_planes_for_stream(dc, stream, context)) { 3066 3067 BREAK_TO_DEBUGGER(); 3068 goto fail; 3069 } 3070 3071 /* add surface to context */ 3072 if (!dc_add_all_planes_for_stream(dc, stream, new_planes, surface_count, context)) { 3073 3074 BREAK_TO_DEBUGGER(); 3075 goto fail; 3076 } 3077 } 3078 3079 /* save update parameters into surface */ 3080 for (i = 0; i < surface_count; i++) { 3081 struct dc_plane_state *surface = srf_updates[i].surface; 3082 3083 copy_surface_update_to_plane(surface, &srf_updates[i]); 3084 3085 if (update_type >= UPDATE_TYPE_MED) { 3086 for (j = 0; j < dc->res_pool->pipe_count; j++) { 3087 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; 3088 3089 if (pipe_ctx->plane_state != surface) 3090 continue; 3091 3092 resource_build_scaling_params(pipe_ctx); 3093 } 3094 } 3095 } 3096 3097 if (update_type == UPDATE_TYPE_FULL) { 3098 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) { 3099 BREAK_TO_DEBUGGER(); 3100 goto fail; 3101 } 3102 } 3103 3104 *new_context = context; 3105 *new_update_type = update_type; 3106 3107 return true; 3108 3109 fail: 3110 dc_release_state(context); 3111 3112 return false; 3113 3114 } 3115 3116 static void commit_planes_do_stream_update(struct dc *dc, 3117 struct dc_stream_state *stream, 3118 struct dc_stream_update *stream_update, 3119 enum surface_update_type update_type, 3120 struct dc_state *context) 3121 { 3122 int j; 3123 3124 // Stream updates 3125 for (j = 0; j < dc->res_pool->pipe_count; j++) { 3126 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; 3127 3128 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) { 3129 3130 if (stream_update->periodic_interrupt && dc->hwss.setup_periodic_interrupt) 3131 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx); 3132 3133 if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) || 3134 stream_update->vrr_infopacket || 3135 stream_update->vsc_infopacket || 3136 stream_update->vsp_infopacket || 3137 stream_update->hfvsif_infopacket || 3138 stream_update->vtem_infopacket) { 3139 resource_build_info_frame(pipe_ctx); 3140 dc->hwss.update_info_frame(pipe_ctx); 3141 3142 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 3143 dp_source_sequence_trace(pipe_ctx->stream->link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 3144 } 3145 3146 if (stream_update->hdr_static_metadata && 3147 stream->use_dynamic_meta && 3148 dc->hwss.set_dmdata_attributes && 3149 pipe_ctx->stream->dmdata_address.quad_part != 0) 3150 dc->hwss.set_dmdata_attributes(pipe_ctx); 3151 3152 if (stream_update->gamut_remap) 3153 dc_stream_set_gamut_remap(dc, stream); 3154 3155 if (stream_update->output_csc_transform) 3156 dc_stream_program_csc_matrix(dc, stream); 3157 3158 if (stream_update->dither_option) { 3159 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 3160 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 3161 &pipe_ctx->stream->bit_depth_params); 3162 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp, 3163 &stream->bit_depth_params, 3164 &stream->clamping); 3165 while (odm_pipe) { 3166 odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp, 3167 &stream->bit_depth_params, 3168 &stream->clamping); 3169 odm_pipe = odm_pipe->next_odm_pipe; 3170 } 3171 } 3172 3173 3174 /* Full fe update*/ 3175 if (update_type == UPDATE_TYPE_FAST) 3176 continue; 3177 3178 if (stream_update->dsc_config) 3179 dp_update_dsc_config(pipe_ctx); 3180 3181 if (stream_update->mst_bw_update) { 3182 if (stream_update->mst_bw_update->is_increase) 3183 dc_link_increase_mst_payload(pipe_ctx, stream_update->mst_bw_update->mst_stream_bw); 3184 else 3185 dc_link_reduce_mst_payload(pipe_ctx, stream_update->mst_bw_update->mst_stream_bw); 3186 } 3187 3188 if (stream_update->pending_test_pattern) { 3189 dc_link_dp_set_test_pattern(stream->link, 3190 stream->test_pattern.type, 3191 stream->test_pattern.color_space, 3192 stream->test_pattern.p_link_settings, 3193 stream->test_pattern.p_custom_pattern, 3194 stream->test_pattern.cust_pattern_size); 3195 } 3196 3197 if (stream_update->dpms_off) { 3198 if (*stream_update->dpms_off) { 3199 core_link_disable_stream(pipe_ctx); 3200 /* for dpms, keep acquired resources*/ 3201 if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only) 3202 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 3203 3204 dc->optimized_required = true; 3205 3206 } else { 3207 if (get_seamless_boot_stream_count(context) == 0) 3208 dc->hwss.prepare_bandwidth(dc, dc->current_state); 3209 core_link_enable_stream(dc->current_state, pipe_ctx); 3210 } 3211 } 3212 3213 if (stream_update->abm_level && pipe_ctx->stream_res.abm) { 3214 bool should_program_abm = true; 3215 3216 // if otg funcs defined check if blanked before programming 3217 if (pipe_ctx->stream_res.tg->funcs->is_blanked) 3218 if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) 3219 should_program_abm = false; 3220 3221 if (should_program_abm) { 3222 if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) { 3223 dc->hwss.set_abm_immediate_disable(pipe_ctx); 3224 } else { 3225 pipe_ctx->stream_res.abm->funcs->set_abm_level( 3226 pipe_ctx->stream_res.abm, stream->abm_level); 3227 } 3228 } 3229 } 3230 } 3231 } 3232 } 3233 3234 static bool dc_dmub_should_send_dirty_rect_cmd(struct dc *dc, struct dc_stream_state *stream) 3235 { 3236 if ((stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 3237 || stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) 3238 && stream->ctx->dce_version >= DCN_VERSION_3_1) 3239 return true; 3240 3241 return false; 3242 } 3243 3244 void dc_dmub_update_dirty_rect(struct dc *dc, 3245 int surface_count, 3246 struct dc_stream_state *stream, 3247 struct dc_surface_update *srf_updates, 3248 struct dc_state *context) 3249 { 3250 union dmub_rb_cmd cmd; 3251 struct dc_context *dc_ctx = dc->ctx; 3252 struct dmub_cmd_update_dirty_rect_data *update_dirty_rect; 3253 unsigned int i, j; 3254 unsigned int panel_inst = 0; 3255 3256 if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream)) 3257 return; 3258 3259 if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst)) 3260 return; 3261 3262 memset(&cmd, 0x0, sizeof(cmd)); 3263 cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT; 3264 cmd.update_dirty_rect.header.sub_type = 0; 3265 cmd.update_dirty_rect.header.payload_bytes = 3266 sizeof(cmd.update_dirty_rect) - 3267 sizeof(cmd.update_dirty_rect.header); 3268 update_dirty_rect = &cmd.update_dirty_rect.update_dirty_rect_data; 3269 for (i = 0; i < surface_count; i++) { 3270 struct dc_plane_state *plane_state = srf_updates[i].surface; 3271 const struct dc_flip_addrs *flip_addr = srf_updates[i].flip_addr; 3272 3273 if (!srf_updates[i].surface || !flip_addr) 3274 continue; 3275 /* Do not send in immediate flip mode */ 3276 if (srf_updates[i].surface->flip_immediate) 3277 continue; 3278 3279 update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count; 3280 memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects, 3281 sizeof(flip_addr->dirty_rects)); 3282 for (j = 0; j < dc->res_pool->pipe_count; j++) { 3283 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; 3284 3285 if (pipe_ctx->stream != stream) 3286 continue; 3287 if (pipe_ctx->plane_state != plane_state) 3288 continue; 3289 3290 update_dirty_rect->panel_inst = panel_inst; 3291 update_dirty_rect->pipe_idx = j; 3292 dc_dmub_srv_cmd_queue(dc_ctx->dmub_srv, &cmd); 3293 dc_dmub_srv_cmd_execute(dc_ctx->dmub_srv); 3294 } 3295 } 3296 } 3297 3298 static void commit_planes_for_stream(struct dc *dc, 3299 struct dc_surface_update *srf_updates, 3300 int surface_count, 3301 struct dc_stream_state *stream, 3302 struct dc_stream_update *stream_update, 3303 enum surface_update_type update_type, 3304 struct dc_state *context) 3305 { 3306 int i, j; 3307 struct pipe_ctx *top_pipe_to_program = NULL; 3308 bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST); 3309 bool subvp_prev_use = false; 3310 3311 // Once we apply the new subvp context to hardware it won't be in the 3312 // dc->current_state anymore, so we have to cache it before we apply 3313 // the new SubVP context 3314 subvp_prev_use = false; 3315 3316 3317 dc_z10_restore(dc); 3318 3319 if (update_type == UPDATE_TYPE_FULL) { 3320 /* wait for all double-buffer activity to clear on all pipes */ 3321 int pipe_idx; 3322 3323 for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) { 3324 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 3325 3326 if (!pipe_ctx->stream) 3327 continue; 3328 3329 if (pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear) 3330 pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg); 3331 } 3332 } 3333 3334 if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) { 3335 /* Optimize seamless boot flag keeps clocks and watermarks high until 3336 * first flip. After first flip, optimization is required to lower 3337 * bandwidth. Important to note that it is expected UEFI will 3338 * only light up a single display on POST, therefore we only expect 3339 * one stream with seamless boot flag set. 3340 */ 3341 if (stream->apply_seamless_boot_optimization) { 3342 stream->apply_seamless_boot_optimization = false; 3343 3344 if (get_seamless_boot_stream_count(context) == 0) 3345 dc->optimized_required = true; 3346 } 3347 } 3348 3349 if (update_type == UPDATE_TYPE_FULL) { 3350 dc_allow_idle_optimizations(dc, false); 3351 3352 if (get_seamless_boot_stream_count(context) == 0) 3353 dc->hwss.prepare_bandwidth(dc, context); 3354 3355 if (dc->debug.enable_double_buffered_dsc_pg_support) 3356 dc->hwss.update_dsc_pg(dc, context, false); 3357 3358 context_clock_trace(dc, context); 3359 } 3360 3361 for (j = 0; j < dc->res_pool->pipe_count; j++) { 3362 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; 3363 3364 if (!pipe_ctx->top_pipe && 3365 !pipe_ctx->prev_odm_pipe && 3366 pipe_ctx->stream && 3367 pipe_ctx->stream == stream) { 3368 top_pipe_to_program = pipe_ctx; 3369 } 3370 } 3371 3372 for (i = 0; i < dc->res_pool->pipe_count; i++) { 3373 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 3374 3375 // Check old context for SubVP 3376 subvp_prev_use |= (old_pipe->stream && old_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM); 3377 if (subvp_prev_use) 3378 break; 3379 } 3380 3381 if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) { 3382 struct pipe_ctx *mpcc_pipe; 3383 struct pipe_ctx *odm_pipe; 3384 3385 for (mpcc_pipe = top_pipe_to_program; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe) 3386 for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 3387 odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU; 3388 } 3389 3390 if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed) 3391 if (top_pipe_to_program && 3392 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) { 3393 if (should_use_dmub_lock(stream->link)) { 3394 union dmub_hw_lock_flags hw_locks = { 0 }; 3395 struct dmub_hw_lock_inst_flags inst_flags = { 0 }; 3396 3397 hw_locks.bits.lock_dig = 1; 3398 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst; 3399 3400 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, 3401 true, 3402 &hw_locks, 3403 &inst_flags); 3404 } else 3405 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable( 3406 top_pipe_to_program->stream_res.tg); 3407 } 3408 3409 if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) { 3410 if (dc->hwss.subvp_pipe_control_lock) 3411 dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, NULL, subvp_prev_use); 3412 dc->hwss.interdependent_update_lock(dc, context, true); 3413 3414 } else { 3415 if (dc->hwss.subvp_pipe_control_lock) 3416 dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use); 3417 /* Lock the top pipe while updating plane addrs, since freesync requires 3418 * plane addr update event triggers to be synchronized. 3419 * top_pipe_to_program is expected to never be NULL 3420 */ 3421 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true); 3422 } 3423 3424 if (update_type != UPDATE_TYPE_FAST) { 3425 for (i = 0; i < dc->res_pool->pipe_count; i++) { 3426 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; 3427 3428 if ((new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) || 3429 subvp_prev_use) { 3430 // If old context or new context has phantom pipes, apply 3431 // the phantom timings now. We can't change the phantom 3432 // pipe configuration safely without driver acquiring 3433 // the DMCUB lock first. 3434 dc->hwss.apply_ctx_to_hw(dc, context); 3435 break; 3436 } 3437 } 3438 } 3439 3440 dc_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context); 3441 3442 if (update_type != UPDATE_TYPE_FAST) { 3443 for (i = 0; i < dc->res_pool->pipe_count; i++) { 3444 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; 3445 3446 if ((new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) || 3447 subvp_prev_use) { 3448 // If old context or new context has phantom pipes, apply 3449 // the phantom timings now. We can't change the phantom 3450 // pipe configuration safely without driver acquiring 3451 // the DMCUB lock first. 3452 dc->hwss.apply_ctx_to_hw(dc, context); 3453 break; 3454 } 3455 } 3456 } 3457 3458 // Stream updates 3459 if (stream_update) 3460 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context); 3461 3462 if (surface_count == 0) { 3463 /* 3464 * In case of turning off screen, no need to program front end a second time. 3465 * just return after program blank. 3466 */ 3467 if (dc->hwss.apply_ctx_for_surface) 3468 dc->hwss.apply_ctx_for_surface(dc, stream, 0, context); 3469 if (dc->hwss.program_front_end_for_ctx) 3470 dc->hwss.program_front_end_for_ctx(dc, context); 3471 3472 if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) { 3473 dc->hwss.interdependent_update_lock(dc, context, false); 3474 } else { 3475 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false); 3476 } 3477 dc->hwss.post_unlock_program_front_end(dc, context); 3478 3479 if (update_type != UPDATE_TYPE_FAST) 3480 if (dc->hwss.commit_subvp_config) 3481 dc->hwss.commit_subvp_config(dc, context); 3482 3483 /* Since phantom pipe programming is moved to post_unlock_program_front_end, 3484 * move the SubVP lock to after the phantom pipes have been setup 3485 */ 3486 if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) { 3487 if (dc->hwss.subvp_pipe_control_lock) 3488 dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, NULL, subvp_prev_use); 3489 } else { 3490 if (dc->hwss.subvp_pipe_control_lock) 3491 dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, NULL, subvp_prev_use); 3492 } 3493 3494 return; 3495 } 3496 3497 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 3498 for (i = 0; i < surface_count; i++) { 3499 struct dc_plane_state *plane_state = srf_updates[i].surface; 3500 /*set logical flag for lock/unlock use*/ 3501 for (j = 0; j < dc->res_pool->pipe_count; j++) { 3502 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; 3503 if (!pipe_ctx->plane_state) 3504 continue; 3505 if (should_update_pipe_for_plane(context, pipe_ctx, plane_state)) 3506 continue; 3507 pipe_ctx->plane_state->triplebuffer_flips = false; 3508 if (update_type == UPDATE_TYPE_FAST && 3509 dc->hwss.program_triplebuffer != NULL && 3510 !pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) { 3511 /*triple buffer for VUpdate only*/ 3512 pipe_ctx->plane_state->triplebuffer_flips = true; 3513 } 3514 } 3515 if (update_type == UPDATE_TYPE_FULL) { 3516 /* force vsync flip when reconfiguring pipes to prevent underflow */ 3517 plane_state->flip_immediate = false; 3518 } 3519 } 3520 } 3521 3522 // Update Type FULL, Surface updates 3523 for (j = 0; j < dc->res_pool->pipe_count; j++) { 3524 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; 3525 3526 if (!pipe_ctx->top_pipe && 3527 !pipe_ctx->prev_odm_pipe && 3528 should_update_pipe_for_stream(context, pipe_ctx, stream)) { 3529 struct dc_stream_status *stream_status = NULL; 3530 3531 if (!pipe_ctx->plane_state) 3532 continue; 3533 3534 /* Full fe update*/ 3535 if (update_type == UPDATE_TYPE_FAST) 3536 continue; 3537 3538 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips); 3539 3540 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) { 3541 /*turn off triple buffer for full update*/ 3542 dc->hwss.program_triplebuffer( 3543 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips); 3544 } 3545 stream_status = 3546 stream_get_status(context, pipe_ctx->stream); 3547 3548 if (dc->hwss.apply_ctx_for_surface) 3549 dc->hwss.apply_ctx_for_surface( 3550 dc, pipe_ctx->stream, stream_status->plane_count, context); 3551 } 3552 } 3553 if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) { 3554 dc->hwss.program_front_end_for_ctx(dc, context); 3555 if (dc->debug.validate_dml_output) { 3556 for (i = 0; i < dc->res_pool->pipe_count; i++) { 3557 struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i]; 3558 if (cur_pipe->stream == NULL) 3559 continue; 3560 3561 cur_pipe->plane_res.hubp->funcs->validate_dml_output( 3562 cur_pipe->plane_res.hubp, dc->ctx, 3563 &context->res_ctx.pipe_ctx[i].rq_regs, 3564 &context->res_ctx.pipe_ctx[i].dlg_regs, 3565 &context->res_ctx.pipe_ctx[i].ttu_regs); 3566 } 3567 } 3568 } 3569 3570 // Update Type FAST, Surface updates 3571 if (update_type == UPDATE_TYPE_FAST) { 3572 if (dc->hwss.set_flip_control_gsl) 3573 for (i = 0; i < surface_count; i++) { 3574 struct dc_plane_state *plane_state = srf_updates[i].surface; 3575 3576 for (j = 0; j < dc->res_pool->pipe_count; j++) { 3577 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; 3578 3579 if (!should_update_pipe_for_stream(context, pipe_ctx, stream)) 3580 continue; 3581 3582 if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state)) 3583 continue; 3584 3585 // GSL has to be used for flip immediate 3586 dc->hwss.set_flip_control_gsl(pipe_ctx, 3587 pipe_ctx->plane_state->flip_immediate); 3588 } 3589 } 3590 3591 /* Perform requested Updates */ 3592 for (i = 0; i < surface_count; i++) { 3593 struct dc_plane_state *plane_state = srf_updates[i].surface; 3594 3595 for (j = 0; j < dc->res_pool->pipe_count; j++) { 3596 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; 3597 3598 if (!should_update_pipe_for_stream(context, pipe_ctx, stream)) 3599 continue; 3600 3601 if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state)) 3602 continue; 3603 3604 /*program triple buffer after lock based on flip type*/ 3605 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) { 3606 /*only enable triplebuffer for fast_update*/ 3607 dc->hwss.program_triplebuffer( 3608 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips); 3609 } 3610 if (pipe_ctx->plane_state->update_flags.bits.addr_update) 3611 dc->hwss.update_plane_addr(dc, pipe_ctx); 3612 } 3613 } 3614 3615 } 3616 3617 if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) { 3618 dc->hwss.interdependent_update_lock(dc, context, false); 3619 } else { 3620 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false); 3621 } 3622 3623 if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed) 3624 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) { 3625 top_pipe_to_program->stream_res.tg->funcs->wait_for_state( 3626 top_pipe_to_program->stream_res.tg, 3627 CRTC_STATE_VACTIVE); 3628 top_pipe_to_program->stream_res.tg->funcs->wait_for_state( 3629 top_pipe_to_program->stream_res.tg, 3630 CRTC_STATE_VBLANK); 3631 top_pipe_to_program->stream_res.tg->funcs->wait_for_state( 3632 top_pipe_to_program->stream_res.tg, 3633 CRTC_STATE_VACTIVE); 3634 3635 if (should_use_dmub_lock(stream->link)) { 3636 union dmub_hw_lock_flags hw_locks = { 0 }; 3637 struct dmub_hw_lock_inst_flags inst_flags = { 0 }; 3638 3639 hw_locks.bits.lock_dig = 1; 3640 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst; 3641 3642 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, 3643 false, 3644 &hw_locks, 3645 &inst_flags); 3646 } else 3647 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable( 3648 top_pipe_to_program->stream_res.tg); 3649 } 3650 3651 if (update_type != UPDATE_TYPE_FAST) 3652 dc->hwss.post_unlock_program_front_end(dc, context); 3653 if (update_type != UPDATE_TYPE_FAST) 3654 if (dc->hwss.commit_subvp_config) 3655 dc->hwss.commit_subvp_config(dc, context); 3656 3657 if (update_type != UPDATE_TYPE_FAST) 3658 if (dc->hwss.commit_subvp_config) 3659 dc->hwss.commit_subvp_config(dc, context); 3660 3661 /* Since phantom pipe programming is moved to post_unlock_program_front_end, 3662 * move the SubVP lock to after the phantom pipes have been setup 3663 */ 3664 if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) { 3665 if (dc->hwss.subvp_pipe_control_lock) 3666 dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, NULL, subvp_prev_use); 3667 } else { 3668 if (dc->hwss.subvp_pipe_control_lock) 3669 dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use); 3670 } 3671 3672 // Fire manual trigger only when bottom plane is flipped 3673 for (j = 0; j < dc->res_pool->pipe_count; j++) { 3674 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; 3675 3676 if (!pipe_ctx->plane_state) 3677 continue; 3678 3679 if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe || 3680 !pipe_ctx->stream || !should_update_pipe_for_stream(context, pipe_ctx, stream) || 3681 !pipe_ctx->plane_state->update_flags.bits.addr_update || 3682 pipe_ctx->plane_state->skip_manual_trigger) 3683 continue; 3684 3685 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger) 3686 pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg); 3687 } 3688 } 3689 3690 /* Determines if the incoming context requires a applying transition state with unnecessary 3691 * pipe splitting and ODM disabled, due to hardware limitations. In a case where 3692 * the OPP associated with an MPCC might change due to plane additions, this function 3693 * returns true. 3694 */ 3695 static bool could_mpcc_tree_change_for_active_pipes(struct dc *dc, 3696 struct dc_stream_state *stream, 3697 int surface_count, 3698 bool *is_plane_addition) 3699 { 3700 3701 struct dc_stream_status *cur_stream_status = stream_get_status(dc->current_state, stream); 3702 bool force_minimal_pipe_splitting = false; 3703 3704 *is_plane_addition = false; 3705 3706 if (cur_stream_status && 3707 dc->current_state->stream_count > 0 && 3708 dc->debug.pipe_split_policy != MPC_SPLIT_AVOID) { 3709 /* determine if minimal transition is required due to MPC*/ 3710 if (surface_count > 0) { 3711 if (cur_stream_status->plane_count > surface_count) { 3712 force_minimal_pipe_splitting = true; 3713 } else if (cur_stream_status->plane_count < surface_count) { 3714 force_minimal_pipe_splitting = true; 3715 *is_plane_addition = true; 3716 } 3717 } 3718 } 3719 3720 if (cur_stream_status && 3721 dc->current_state->stream_count == 1 && 3722 dc->debug.enable_single_display_2to1_odm_policy) { 3723 /* determine if minimal transition is required due to dynamic ODM*/ 3724 if (surface_count > 0) { 3725 if (cur_stream_status->plane_count > 2 && cur_stream_status->plane_count > surface_count) { 3726 force_minimal_pipe_splitting = true; 3727 } else if (surface_count > 2 && cur_stream_status->plane_count < surface_count) { 3728 force_minimal_pipe_splitting = true; 3729 *is_plane_addition = true; 3730 } 3731 } 3732 } 3733 3734 /* For SubVP when adding MPO video we need to add a minimal transition. 3735 */ 3736 if (cur_stream_status && stream->mall_stream_config.type == SUBVP_MAIN) { 3737 /* determine if minimal transition is required due to SubVP*/ 3738 if (surface_count > 0) { 3739 if (cur_stream_status->plane_count > surface_count) { 3740 force_minimal_pipe_splitting = true; 3741 } else if (cur_stream_status->plane_count < surface_count) { 3742 force_minimal_pipe_splitting = true; 3743 *is_plane_addition = true; 3744 } 3745 } 3746 } 3747 3748 return force_minimal_pipe_splitting; 3749 } 3750 3751 static bool commit_minimal_transition_state(struct dc *dc, 3752 struct dc_state *transition_base_context) 3753 { 3754 struct dc_state *transition_context = dc_create_state(dc); 3755 enum pipe_split_policy tmp_mpc_policy; 3756 bool temp_dynamic_odm_policy; 3757 bool temp_subvp_policy; 3758 enum dc_status ret = DC_ERROR_UNEXPECTED; 3759 unsigned int i, j; 3760 unsigned int pipe_in_use = 0; 3761 3762 if (!transition_context) 3763 return false; 3764 3765 /* check current pipes in use*/ 3766 for (i = 0; i < dc->res_pool->pipe_count; i++) { 3767 struct pipe_ctx *pipe = &transition_base_context->res_ctx.pipe_ctx[i]; 3768 3769 if (pipe->plane_state) 3770 pipe_in_use++; 3771 } 3772 3773 /* When the OS add a new surface if we have been used all of pipes with odm combine 3774 * and mpc split feature, it need use commit_minimal_transition_state to transition safely. 3775 * After OS exit MPO, it will back to use odm and mpc split with all of pipes, we need 3776 * call it again. Otherwise return true to skip. 3777 * 3778 * Reduce the scenarios to use dc_commit_state_no_check in the stage of flip. Especially 3779 * enter/exit MPO when DCN still have enough resources. 3780 */ 3781 if (pipe_in_use != dc->res_pool->pipe_count) { 3782 dc_release_state(transition_context); 3783 return true; 3784 } 3785 3786 if (!dc->config.is_vmin_only_asic) { 3787 tmp_mpc_policy = dc->debug.pipe_split_policy; 3788 dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; 3789 } 3790 3791 temp_dynamic_odm_policy = dc->debug.enable_single_display_2to1_odm_policy; 3792 dc->debug.enable_single_display_2to1_odm_policy = false; 3793 3794 temp_subvp_policy = dc->debug.force_disable_subvp; 3795 dc->debug.force_disable_subvp = true; 3796 3797 dc_resource_state_copy_construct(transition_base_context, transition_context); 3798 3799 //commit minimal state 3800 if (dc->res_pool->funcs->validate_bandwidth(dc, transition_context, false)) { 3801 for (i = 0; i < transition_context->stream_count; i++) { 3802 struct dc_stream_status *stream_status = &transition_context->stream_status[i]; 3803 3804 for (j = 0; j < stream_status->plane_count; j++) { 3805 struct dc_plane_state *plane_state = stream_status->plane_states[j]; 3806 3807 /* force vsync flip when reconfiguring pipes to prevent underflow 3808 * and corruption 3809 */ 3810 plane_state->flip_immediate = false; 3811 } 3812 } 3813 3814 ret = dc_commit_state_no_check(dc, transition_context); 3815 } 3816 3817 /*always release as dc_commit_state_no_check retains in good case*/ 3818 dc_release_state(transition_context); 3819 3820 /*restore previous pipe split and odm policy*/ 3821 if (!dc->config.is_vmin_only_asic) 3822 dc->debug.pipe_split_policy = tmp_mpc_policy; 3823 3824 dc->debug.enable_single_display_2to1_odm_policy = temp_dynamic_odm_policy; 3825 dc->debug.force_disable_subvp = temp_subvp_policy; 3826 3827 if (ret != DC_OK) { 3828 /*this should never happen*/ 3829 BREAK_TO_DEBUGGER(); 3830 return false; 3831 } 3832 3833 /*force full surface update*/ 3834 for (i = 0; i < dc->current_state->stream_count; i++) { 3835 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) { 3836 dc->current_state->stream_status[i].plane_states[j]->update_flags.raw = 0xFFFFFFFF; 3837 } 3838 } 3839 3840 return true; 3841 } 3842 3843 bool dc_update_planes_and_stream(struct dc *dc, 3844 struct dc_surface_update *srf_updates, int surface_count, 3845 struct dc_stream_state *stream, 3846 struct dc_stream_update *stream_update) 3847 { 3848 struct dc_state *context; 3849 enum surface_update_type update_type; 3850 int i; 3851 3852 /* In cases where MPO and split or ODM are used transitions can 3853 * cause underflow. Apply stream configuration with minimal pipe 3854 * split first to avoid unsupported transitions for active pipes. 3855 */ 3856 bool force_minimal_pipe_splitting; 3857 bool is_plane_addition; 3858 3859 force_minimal_pipe_splitting = could_mpcc_tree_change_for_active_pipes( 3860 dc, 3861 stream, 3862 surface_count, 3863 &is_plane_addition); 3864 3865 /* on plane addition, minimal state is the current one */ 3866 if (force_minimal_pipe_splitting && is_plane_addition && 3867 !commit_minimal_transition_state(dc, dc->current_state)) 3868 return false; 3869 3870 if (!update_planes_and_stream_state( 3871 dc, 3872 srf_updates, 3873 surface_count, 3874 stream, 3875 stream_update, 3876 &update_type, 3877 &context)) 3878 return false; 3879 3880 /* on plane removal, minimal state is the new one */ 3881 if (force_minimal_pipe_splitting && !is_plane_addition) { 3882 if (!commit_minimal_transition_state(dc, context)) { 3883 dc_release_state(context); 3884 return false; 3885 } 3886 3887 update_type = UPDATE_TYPE_FULL; 3888 } 3889 3890 commit_planes_for_stream( 3891 dc, 3892 srf_updates, 3893 surface_count, 3894 stream, 3895 stream_update, 3896 update_type, 3897 context); 3898 3899 if (dc->current_state != context) { 3900 3901 /* Since memory free requires elevated IRQL, an interrupt 3902 * request is generated by mem free. If this happens 3903 * between freeing and reassigning the context, our vsync 3904 * interrupt will call into dc and cause a memory 3905 * corruption BSOD. Hence, we first reassign the context, 3906 * then free the old context. 3907 */ 3908 3909 struct dc_state *old = dc->current_state; 3910 3911 dc->current_state = context; 3912 dc_release_state(old); 3913 3914 // clear any forced full updates 3915 for (i = 0; i < dc->res_pool->pipe_count; i++) { 3916 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 3917 3918 if (pipe_ctx->plane_state && pipe_ctx->stream == stream) 3919 pipe_ctx->plane_state->force_full_update = false; 3920 } 3921 } 3922 return true; 3923 } 3924 3925 void dc_commit_updates_for_stream(struct dc *dc, 3926 struct dc_surface_update *srf_updates, 3927 int surface_count, 3928 struct dc_stream_state *stream, 3929 struct dc_stream_update *stream_update, 3930 struct dc_state *state) 3931 { 3932 const struct dc_stream_status *stream_status; 3933 enum surface_update_type update_type; 3934 struct dc_state *context; 3935 struct dc_context *dc_ctx = dc->ctx; 3936 int i, j; 3937 3938 stream_status = dc_stream_get_status(stream); 3939 context = dc->current_state; 3940 3941 update_type = dc_check_update_surfaces_for_stream( 3942 dc, srf_updates, surface_count, stream_update, stream_status); 3943 3944 if (update_type >= update_surface_trace_level) 3945 update_surface_trace(dc, srf_updates, surface_count); 3946 3947 3948 if (update_type >= UPDATE_TYPE_FULL) { 3949 3950 /* initialize scratch memory for building context */ 3951 context = dc_create_state(dc); 3952 if (context == NULL) { 3953 DC_ERROR("Failed to allocate new validate context!\n"); 3954 return; 3955 } 3956 3957 dc_resource_state_copy_construct(state, context); 3958 3959 for (i = 0; i < dc->res_pool->pipe_count; i++) { 3960 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; 3961 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 3962 3963 if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state) 3964 new_pipe->plane_state->force_full_update = true; 3965 } 3966 } else if (update_type == UPDATE_TYPE_FAST) { 3967 /* 3968 * Previous frame finished and HW is ready for optimization. 3969 */ 3970 dc_post_update_surfaces_to_stream(dc); 3971 } 3972 3973 3974 for (i = 0; i < surface_count; i++) { 3975 struct dc_plane_state *surface = srf_updates[i].surface; 3976 3977 copy_surface_update_to_plane(surface, &srf_updates[i]); 3978 3979 if (update_type >= UPDATE_TYPE_MED) { 3980 for (j = 0; j < dc->res_pool->pipe_count; j++) { 3981 struct pipe_ctx *pipe_ctx = 3982 &context->res_ctx.pipe_ctx[j]; 3983 3984 if (pipe_ctx->plane_state != surface) 3985 continue; 3986 3987 resource_build_scaling_params(pipe_ctx); 3988 } 3989 } 3990 } 3991 3992 copy_stream_update_to_stream(dc, context, stream, stream_update); 3993 3994 if (update_type >= UPDATE_TYPE_FULL) { 3995 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) { 3996 DC_ERROR("Mode validation failed for stream update!\n"); 3997 dc_release_state(context); 3998 return; 3999 } 4000 } 4001 4002 TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES); 4003 4004 commit_planes_for_stream( 4005 dc, 4006 srf_updates, 4007 surface_count, 4008 stream, 4009 stream_update, 4010 update_type, 4011 context); 4012 /*update current_State*/ 4013 if (dc->current_state != context) { 4014 4015 struct dc_state *old = dc->current_state; 4016 4017 dc->current_state = context; 4018 dc_release_state(old); 4019 4020 for (i = 0; i < dc->res_pool->pipe_count; i++) { 4021 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 4022 4023 if (pipe_ctx->plane_state && pipe_ctx->stream == stream) 4024 pipe_ctx->plane_state->force_full_update = false; 4025 } 4026 } 4027 4028 /* Legacy optimization path for DCE. */ 4029 if (update_type >= UPDATE_TYPE_FULL && dc_ctx->dce_version < DCE_VERSION_MAX) { 4030 dc_post_update_surfaces_to_stream(dc); 4031 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce); 4032 } 4033 4034 return; 4035 4036 } 4037 4038 uint8_t dc_get_current_stream_count(struct dc *dc) 4039 { 4040 return dc->current_state->stream_count; 4041 } 4042 4043 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i) 4044 { 4045 if (i < dc->current_state->stream_count) 4046 return dc->current_state->streams[i]; 4047 return NULL; 4048 } 4049 4050 enum dc_irq_source dc_interrupt_to_irq_source( 4051 struct dc *dc, 4052 uint32_t src_id, 4053 uint32_t ext_id) 4054 { 4055 return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id); 4056 } 4057 4058 /* 4059 * dc_interrupt_set() - Enable/disable an AMD hw interrupt source 4060 */ 4061 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable) 4062 { 4063 4064 if (dc == NULL) 4065 return false; 4066 4067 return dal_irq_service_set(dc->res_pool->irqs, src, enable); 4068 } 4069 4070 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src) 4071 { 4072 dal_irq_service_ack(dc->res_pool->irqs, src); 4073 } 4074 4075 void dc_power_down_on_boot(struct dc *dc) 4076 { 4077 if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW && 4078 dc->hwss.power_down_on_boot) 4079 dc->hwss.power_down_on_boot(dc); 4080 } 4081 4082 void dc_set_power_state( 4083 struct dc *dc, 4084 enum dc_acpi_cm_power_state power_state) 4085 { 4086 struct kref refcount; 4087 struct display_mode_lib *dml; 4088 4089 if (!dc->current_state) 4090 return; 4091 4092 switch (power_state) { 4093 case DC_ACPI_CM_POWER_STATE_D0: 4094 dc_resource_state_construct(dc, dc->current_state); 4095 4096 dc_z10_restore(dc); 4097 4098 if (dc->ctx->dmub_srv) 4099 dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv); 4100 4101 dc->hwss.init_hw(dc); 4102 4103 if (dc->hwss.init_sys_ctx != NULL && 4104 dc->vm_pa_config.valid) { 4105 dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config); 4106 } 4107 4108 break; 4109 default: 4110 ASSERT(dc->current_state->stream_count == 0); 4111 /* Zero out the current context so that on resume we start with 4112 * clean state, and dc hw programming optimizations will not 4113 * cause any trouble. 4114 */ 4115 dml = kzalloc(sizeof(struct display_mode_lib), 4116 GFP_KERNEL); 4117 4118 ASSERT(dml); 4119 if (!dml) 4120 return; 4121 4122 /* Preserve refcount */ 4123 refcount = dc->current_state->refcount; 4124 /* Preserve display mode lib */ 4125 memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib)); 4126 4127 dc_resource_state_destruct(dc->current_state); 4128 memset(dc->current_state, 0, 4129 sizeof(*dc->current_state)); 4130 4131 dc->current_state->refcount = refcount; 4132 dc->current_state->bw_ctx.dml = *dml; 4133 4134 kfree(dml); 4135 4136 break; 4137 } 4138 } 4139 4140 void dc_resume(struct dc *dc) 4141 { 4142 uint32_t i; 4143 4144 for (i = 0; i < dc->link_count; i++) 4145 core_link_resume(dc->links[i]); 4146 } 4147 4148 bool dc_is_dmcu_initialized(struct dc *dc) 4149 { 4150 struct dmcu *dmcu = dc->res_pool->dmcu; 4151 4152 if (dmcu) 4153 return dmcu->funcs->is_dmcu_initialized(dmcu); 4154 return false; 4155 } 4156 4157 bool dc_is_oem_i2c_device_present( 4158 struct dc *dc, 4159 size_t slave_address) 4160 { 4161 if (dc->res_pool->oem_device) 4162 return dce_i2c_oem_device_present( 4163 dc->res_pool, 4164 dc->res_pool->oem_device, 4165 slave_address); 4166 4167 return false; 4168 } 4169 4170 bool dc_submit_i2c( 4171 struct dc *dc, 4172 uint32_t link_index, 4173 struct i2c_command *cmd) 4174 { 4175 4176 struct dc_link *link = dc->links[link_index]; 4177 struct ddc_service *ddc = link->ddc; 4178 return dce_i2c_submit_command( 4179 dc->res_pool, 4180 ddc->ddc_pin, 4181 cmd); 4182 } 4183 4184 bool dc_submit_i2c_oem( 4185 struct dc *dc, 4186 struct i2c_command *cmd) 4187 { 4188 struct ddc_service *ddc = dc->res_pool->oem_device; 4189 if (ddc) 4190 return dce_i2c_submit_command( 4191 dc->res_pool, 4192 ddc->ddc_pin, 4193 cmd); 4194 4195 return false; 4196 } 4197 4198 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink) 4199 { 4200 if (dc_link->sink_count >= MAX_SINKS_PER_LINK) { 4201 BREAK_TO_DEBUGGER(); 4202 return false; 4203 } 4204 4205 dc_sink_retain(sink); 4206 4207 dc_link->remote_sinks[dc_link->sink_count] = sink; 4208 dc_link->sink_count++; 4209 4210 return true; 4211 } 4212 4213 /* 4214 * dc_link_add_remote_sink() - Create a sink and attach it to an existing link 4215 * 4216 * EDID length is in bytes 4217 */ 4218 struct dc_sink *dc_link_add_remote_sink( 4219 struct dc_link *link, 4220 const uint8_t *edid, 4221 int len, 4222 struct dc_sink_init_data *init_data) 4223 { 4224 struct dc_sink *dc_sink; 4225 enum dc_edid_status edid_status; 4226 4227 if (len > DC_MAX_EDID_BUFFER_SIZE) { 4228 dm_error("Max EDID buffer size breached!\n"); 4229 return NULL; 4230 } 4231 4232 if (!init_data) { 4233 BREAK_TO_DEBUGGER(); 4234 return NULL; 4235 } 4236 4237 if (!init_data->link) { 4238 BREAK_TO_DEBUGGER(); 4239 return NULL; 4240 } 4241 4242 dc_sink = dc_sink_create(init_data); 4243 4244 if (!dc_sink) 4245 return NULL; 4246 4247 memmove(dc_sink->dc_edid.raw_edid, edid, len); 4248 dc_sink->dc_edid.length = len; 4249 4250 if (!link_add_remote_sink_helper( 4251 link, 4252 dc_sink)) 4253 goto fail_add_sink; 4254 4255 edid_status = dm_helpers_parse_edid_caps( 4256 link, 4257 &dc_sink->dc_edid, 4258 &dc_sink->edid_caps); 4259 4260 /* 4261 * Treat device as no EDID device if EDID 4262 * parsing fails 4263 */ 4264 if (edid_status != EDID_OK && edid_status != EDID_PARTIAL_VALID) { 4265 dc_sink->dc_edid.length = 0; 4266 dm_error("Bad EDID, status%d!\n", edid_status); 4267 } 4268 4269 return dc_sink; 4270 4271 fail_add_sink: 4272 dc_sink_release(dc_sink); 4273 return NULL; 4274 } 4275 4276 /* 4277 * dc_link_remove_remote_sink() - Remove a remote sink from a dc_link 4278 * 4279 * Note that this just removes the struct dc_sink - it doesn't 4280 * program hardware or alter other members of dc_link 4281 */ 4282 void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) 4283 { 4284 int i; 4285 4286 if (!link->sink_count) { 4287 BREAK_TO_DEBUGGER(); 4288 return; 4289 } 4290 4291 for (i = 0; i < link->sink_count; i++) { 4292 if (link->remote_sinks[i] == sink) { 4293 dc_sink_release(sink); 4294 link->remote_sinks[i] = NULL; 4295 4296 /* shrink array to remove empty place */ 4297 while (i < link->sink_count - 1) { 4298 link->remote_sinks[i] = link->remote_sinks[i+1]; 4299 i++; 4300 } 4301 link->remote_sinks[i] = NULL; 4302 link->sink_count--; 4303 return; 4304 } 4305 } 4306 } 4307 4308 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info) 4309 { 4310 info->displayClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz; 4311 info->engineClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz; 4312 info->memoryClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz; 4313 info->maxSupportedDppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; 4314 info->dppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz; 4315 info->socClock = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz; 4316 info->dcfClockDeepSleep = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz; 4317 info->fClock = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz; 4318 info->phyClock = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz; 4319 } 4320 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping) 4321 { 4322 if (dc->hwss.set_clock) 4323 return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping); 4324 return DC_ERROR_UNEXPECTED; 4325 } 4326 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg) 4327 { 4328 if (dc->hwss.get_clock) 4329 dc->hwss.get_clock(dc, clock_type, clock_cfg); 4330 } 4331 4332 /* enable/disable eDP PSR without specify stream for eDP */ 4333 bool dc_set_psr_allow_active(struct dc *dc, bool enable) 4334 { 4335 int i; 4336 bool allow_active; 4337 4338 for (i = 0; i < dc->current_state->stream_count ; i++) { 4339 struct dc_link *link; 4340 struct dc_stream_state *stream = dc->current_state->streams[i]; 4341 4342 link = stream->link; 4343 if (!link) 4344 continue; 4345 4346 if (link->psr_settings.psr_feature_enabled) { 4347 if (enable && !link->psr_settings.psr_allow_active) { 4348 allow_active = true; 4349 if (!dc_link_set_psr_allow_active(link, &allow_active, false, false, NULL)) 4350 return false; 4351 } else if (!enable && link->psr_settings.psr_allow_active) { 4352 allow_active = false; 4353 if (!dc_link_set_psr_allow_active(link, &allow_active, true, false, NULL)) 4354 return false; 4355 } 4356 } 4357 } 4358 4359 return true; 4360 } 4361 4362 void dc_allow_idle_optimizations(struct dc *dc, bool allow) 4363 { 4364 if (dc->debug.disable_idle_power_optimizations) 4365 return; 4366 4367 if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->is_smu_present) 4368 if (!dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr)) 4369 return; 4370 4371 if (allow == dc->idle_optimizations_allowed) 4372 return; 4373 4374 if (dc->hwss.apply_idle_power_optimizations && dc->hwss.apply_idle_power_optimizations(dc, allow)) 4375 dc->idle_optimizations_allowed = allow; 4376 } 4377 4378 /* set min and max memory clock to lowest and highest DPM level, respectively */ 4379 void dc_unlock_memory_clock_frequency(struct dc *dc) 4380 { 4381 if (dc->clk_mgr->funcs->set_hard_min_memclk) 4382 dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false); 4383 4384 if (dc->clk_mgr->funcs->set_hard_max_memclk) 4385 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 4386 } 4387 4388 /* set min memory clock to the min required for current mode, max to maxDPM */ 4389 void dc_lock_memory_clock_frequency(struct dc *dc) 4390 { 4391 if (dc->clk_mgr->funcs->get_memclk_states_from_smu) 4392 dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr); 4393 4394 if (dc->clk_mgr->funcs->set_hard_min_memclk) 4395 dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true); 4396 4397 if (dc->clk_mgr->funcs->set_hard_max_memclk) 4398 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 4399 } 4400 4401 static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memclk_mhz) 4402 { 4403 struct dc_state *context = dc->current_state; 4404 struct hubp *hubp; 4405 struct pipe_ctx *pipe; 4406 int i; 4407 4408 for (i = 0; i < dc->res_pool->pipe_count; i++) { 4409 pipe = &context->res_ctx.pipe_ctx[i]; 4410 4411 if (pipe->stream != NULL) { 4412 dc->hwss.disable_pixel_data(dc, pipe, true); 4413 4414 // wait for double buffer 4415 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VACTIVE); 4416 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK); 4417 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VACTIVE); 4418 4419 hubp = pipe->plane_res.hubp; 4420 hubp->funcs->set_blank_regs(hubp, true); 4421 } 4422 } 4423 4424 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, memclk_mhz); 4425 dc->clk_mgr->funcs->set_min_memclk(dc->clk_mgr, memclk_mhz); 4426 4427 for (i = 0; i < dc->res_pool->pipe_count; i++) { 4428 pipe = &context->res_ctx.pipe_ctx[i]; 4429 4430 if (pipe->stream != NULL) { 4431 dc->hwss.disable_pixel_data(dc, pipe, false); 4432 4433 hubp = pipe->plane_res.hubp; 4434 hubp->funcs->set_blank_regs(hubp, false); 4435 } 4436 } 4437 } 4438 4439 4440 /** 4441 * dc_enable_dcmode_clk_limit() - lower clocks in dc (battery) mode 4442 * @dc: pointer to dc of the dm calling this 4443 * @enable: True = transition to DC mode, false = transition back to AC mode 4444 * 4445 * Some SoCs define additional clock limits when in DC mode, DM should 4446 * invoke this function when the platform undergoes a power source transition 4447 * so DC can apply/unapply the limit. This interface may be disruptive to 4448 * the onscreen content. 4449 * 4450 * Context: Triggered by OS through DM interface, or manually by escape calls. 4451 * Need to hold a dclock when doing so. 4452 * 4453 * Return: none (void function) 4454 * 4455 */ 4456 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable) 4457 { 4458 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 4459 unsigned int softMax, maxDPM, funcMin; 4460 bool p_state_change_support; 4461 4462 if (!ASICREV_IS_BEIGE_GOBY_P(hw_internal_rev)) 4463 return; 4464 4465 softMax = dc->clk_mgr->bw_params->dc_mode_softmax_memclk; 4466 maxDPM = dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz; 4467 funcMin = (dc->clk_mgr->clks.dramclk_khz + 999) / 1000; 4468 p_state_change_support = dc->clk_mgr->clks.p_state_change_support; 4469 4470 if (enable && !dc->clk_mgr->dc_mode_softmax_enabled) { 4471 if (p_state_change_support) { 4472 if (funcMin <= softMax) 4473 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, softMax); 4474 // else: No-Op 4475 } else { 4476 if (funcMin <= softMax) 4477 blank_and_force_memclk(dc, true, softMax); 4478 // else: No-Op 4479 } 4480 } else if (!enable && dc->clk_mgr->dc_mode_softmax_enabled) { 4481 if (p_state_change_support) { 4482 if (funcMin <= softMax) 4483 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, maxDPM); 4484 // else: No-Op 4485 } else { 4486 if (funcMin <= softMax) 4487 blank_and_force_memclk(dc, true, maxDPM); 4488 // else: No-Op 4489 } 4490 } 4491 dc->clk_mgr->dc_mode_softmax_enabled = enable; 4492 } 4493 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 4494 struct dc_cursor_attributes *cursor_attr) 4495 { 4496 if (dc->hwss.does_plane_fit_in_mall && dc->hwss.does_plane_fit_in_mall(dc, plane, cursor_attr)) 4497 return true; 4498 return false; 4499 } 4500 4501 /* cleanup on driver unload */ 4502 void dc_hardware_release(struct dc *dc) 4503 { 4504 dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(dc); 4505 4506 if (dc->hwss.hardware_release) 4507 dc->hwss.hardware_release(dc); 4508 } 4509 4510 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc) 4511 { 4512 if (dc->current_state) 4513 dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down = true; 4514 } 4515 4516 /* 4517 ***************************************************************************** 4518 * Function: dc_is_dmub_outbox_supported - 4519 * 4520 * @brief 4521 * Checks whether DMUB FW supports outbox notifications, if supported 4522 * DM should register outbox interrupt prior to actually enabling interrupts 4523 * via dc_enable_dmub_outbox 4524 * 4525 * @param 4526 * [in] dc: dc structure 4527 * 4528 * @return 4529 * True if DMUB FW supports outbox notifications, False otherwise 4530 ***************************************************************************** 4531 */ 4532 bool dc_is_dmub_outbox_supported(struct dc *dc) 4533 { 4534 /* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts */ 4535 if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && 4536 dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 && 4537 !dc->debug.dpia_debug.bits.disable_dpia) 4538 return true; 4539 4540 if (dc->ctx->asic_id.chip_family == AMDGPU_FAMILY_GC_11_0_1 && 4541 !dc->debug.dpia_debug.bits.disable_dpia) 4542 return true; 4543 4544 /* dmub aux needs dmub notifications to be enabled */ 4545 return dc->debug.enable_dmub_aux_for_legacy_ddc; 4546 } 4547 4548 /* 4549 ***************************************************************************** 4550 * Function: dc_enable_dmub_notifications 4551 * 4552 * @brief 4553 * Calls dc_is_dmub_outbox_supported to check if dmub fw supports outbox 4554 * notifications. All DMs shall switch to dc_is_dmub_outbox_supported. 4555 * This API shall be removed after switching. 4556 * 4557 * @param 4558 * [in] dc: dc structure 4559 * 4560 * @return 4561 * True if DMUB FW supports outbox notifications, False otherwise 4562 ***************************************************************************** 4563 */ 4564 bool dc_enable_dmub_notifications(struct dc *dc) 4565 { 4566 return dc_is_dmub_outbox_supported(dc); 4567 } 4568 4569 /** 4570 ***************************************************************************** 4571 * Function: dc_enable_dmub_outbox 4572 * 4573 * @brief 4574 * Enables DMUB unsolicited notifications to x86 via outbox 4575 * 4576 * @param 4577 * [in] dc: dc structure 4578 * 4579 * @return 4580 * None 4581 ***************************************************************************** 4582 */ 4583 void dc_enable_dmub_outbox(struct dc *dc) 4584 { 4585 struct dc_context *dc_ctx = dc->ctx; 4586 4587 dmub_enable_outbox_notification(dc_ctx->dmub_srv); 4588 DC_LOG_DC("%s: dmub outbox notifications enabled\n", __func__); 4589 } 4590 4591 /** 4592 * dc_process_dmub_aux_transfer_async - Submits aux command to dmub via inbox message 4593 * Sets port index appropriately for legacy DDC 4594 * @dc: dc structure 4595 * @link_index: link index 4596 * @payload: aux payload 4597 * 4598 * Returns: True if successful, False if failure 4599 */ 4600 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 4601 uint32_t link_index, 4602 struct aux_payload *payload) 4603 { 4604 uint8_t action; 4605 union dmub_rb_cmd cmd = {0}; 4606 struct dc_dmub_srv *dmub_srv = dc->ctx->dmub_srv; 4607 4608 ASSERT(payload->length <= 16); 4609 4610 cmd.dp_aux_access.header.type = DMUB_CMD__DP_AUX_ACCESS; 4611 cmd.dp_aux_access.header.payload_bytes = 0; 4612 /* For dpia, ddc_pin is set to NULL */ 4613 if (!dc->links[link_index]->ddc->ddc_pin) 4614 cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_DPIA; 4615 else 4616 cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_LEGACY_DDC; 4617 4618 cmd.dp_aux_access.aux_control.instance = dc->links[link_index]->ddc_hw_inst; 4619 cmd.dp_aux_access.aux_control.sw_crc_enabled = 0; 4620 cmd.dp_aux_access.aux_control.timeout = 0; 4621 cmd.dp_aux_access.aux_control.dpaux.address = payload->address; 4622 cmd.dp_aux_access.aux_control.dpaux.is_i2c_over_aux = payload->i2c_over_aux; 4623 cmd.dp_aux_access.aux_control.dpaux.length = payload->length; 4624 4625 /* set aux action */ 4626 if (payload->i2c_over_aux) { 4627 if (payload->write) { 4628 if (payload->mot) 4629 action = DP_AUX_REQ_ACTION_I2C_WRITE_MOT; 4630 else 4631 action = DP_AUX_REQ_ACTION_I2C_WRITE; 4632 } else { 4633 if (payload->mot) 4634 action = DP_AUX_REQ_ACTION_I2C_READ_MOT; 4635 else 4636 action = DP_AUX_REQ_ACTION_I2C_READ; 4637 } 4638 } else { 4639 if (payload->write) 4640 action = DP_AUX_REQ_ACTION_DPCD_WRITE; 4641 else 4642 action = DP_AUX_REQ_ACTION_DPCD_READ; 4643 } 4644 4645 cmd.dp_aux_access.aux_control.dpaux.action = action; 4646 4647 if (payload->length && payload->write) { 4648 memcpy(cmd.dp_aux_access.aux_control.dpaux.data, 4649 payload->data, 4650 payload->length 4651 ); 4652 } 4653 4654 dc_dmub_srv_cmd_queue(dmub_srv, &cmd); 4655 dc_dmub_srv_cmd_execute(dmub_srv); 4656 dc_dmub_srv_wait_idle(dmub_srv); 4657 4658 return true; 4659 } 4660 4661 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 4662 uint8_t dpia_port_index) 4663 { 4664 uint8_t index, link_index = 0xFF; 4665 4666 for (index = 0; index < dc->link_count; index++) { 4667 /* ddc_hw_inst has dpia port index for dpia links 4668 * and ddc instance for legacy links 4669 */ 4670 if (!dc->links[index]->ddc->ddc_pin) { 4671 if (dc->links[index]->ddc_hw_inst == dpia_port_index) { 4672 link_index = index; 4673 break; 4674 } 4675 } 4676 } 4677 ASSERT(link_index != 0xFF); 4678 return link_index; 4679 } 4680 4681 /** 4682 ***************************************************************************** 4683 * Function: dc_process_dmub_set_config_async 4684 * 4685 * @brief 4686 * Submits set_config command to dmub via inbox message 4687 * 4688 * @param 4689 * [in] dc: dc structure 4690 * [in] link_index: link index 4691 * [in] payload: aux payload 4692 * [out] notify: set_config immediate reply 4693 * 4694 * @return 4695 * True if successful, False if failure 4696 ***************************************************************************** 4697 */ 4698 bool dc_process_dmub_set_config_async(struct dc *dc, 4699 uint32_t link_index, 4700 struct set_config_cmd_payload *payload, 4701 struct dmub_notification *notify) 4702 { 4703 union dmub_rb_cmd cmd = {0}; 4704 struct dc_dmub_srv *dmub_srv = dc->ctx->dmub_srv; 4705 bool is_cmd_complete = true; 4706 4707 /* prepare SET_CONFIG command */ 4708 cmd.set_config_access.header.type = DMUB_CMD__DPIA; 4709 cmd.set_config_access.header.sub_type = DMUB_CMD__DPIA_SET_CONFIG_ACCESS; 4710 4711 cmd.set_config_access.set_config_control.instance = dc->links[link_index]->ddc_hw_inst; 4712 cmd.set_config_access.set_config_control.cmd_pkt.msg_type = payload->msg_type; 4713 cmd.set_config_access.set_config_control.cmd_pkt.msg_data = payload->msg_data; 4714 4715 if (!dc_dmub_srv_cmd_with_reply_data(dmub_srv, &cmd)) { 4716 /* command is not processed by dmub */ 4717 notify->sc_status = SET_CONFIG_UNKNOWN_ERROR; 4718 return is_cmd_complete; 4719 } 4720 4721 /* command processed by dmub, if ret_status is 1, it is completed instantly */ 4722 if (cmd.set_config_access.header.ret_status == 1) 4723 notify->sc_status = cmd.set_config_access.set_config_control.immed_status; 4724 else 4725 /* cmd pending, will receive notification via outbox */ 4726 is_cmd_complete = false; 4727 4728 return is_cmd_complete; 4729 } 4730 4731 /** 4732 ***************************************************************************** 4733 * Function: dc_process_dmub_set_mst_slots 4734 * 4735 * @brief 4736 * Submits mst slot allocation command to dmub via inbox message 4737 * 4738 * @param 4739 * [in] dc: dc structure 4740 * [in] link_index: link index 4741 * [in] mst_alloc_slots: mst slots to be allotted 4742 * [out] mst_slots_in_use: mst slots in use returned in failure case 4743 * 4744 * @return 4745 * DC_OK if successful, DC_ERROR if failure 4746 ***************************************************************************** 4747 */ 4748 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 4749 uint32_t link_index, 4750 uint8_t mst_alloc_slots, 4751 uint8_t *mst_slots_in_use) 4752 { 4753 union dmub_rb_cmd cmd = {0}; 4754 struct dc_dmub_srv *dmub_srv = dc->ctx->dmub_srv; 4755 4756 /* prepare MST_ALLOC_SLOTS command */ 4757 cmd.set_mst_alloc_slots.header.type = DMUB_CMD__DPIA; 4758 cmd.set_mst_alloc_slots.header.sub_type = DMUB_CMD__DPIA_MST_ALLOC_SLOTS; 4759 4760 cmd.set_mst_alloc_slots.mst_slots_control.instance = dc->links[link_index]->ddc_hw_inst; 4761 cmd.set_mst_alloc_slots.mst_slots_control.mst_alloc_slots = mst_alloc_slots; 4762 4763 if (!dc_dmub_srv_cmd_with_reply_data(dmub_srv, &cmd)) 4764 /* command is not processed by dmub */ 4765 return DC_ERROR_UNEXPECTED; 4766 4767 /* command processed by dmub, if ret_status is 1 */ 4768 if (cmd.set_config_access.header.ret_status != 1) 4769 /* command processing error */ 4770 return DC_ERROR_UNEXPECTED; 4771 4772 /* command processed and we have a status of 2, mst not enabled in dpia */ 4773 if (cmd.set_mst_alloc_slots.mst_slots_control.immed_status == 2) 4774 return DC_FAIL_UNSUPPORTED_1; 4775 4776 /* previously configured mst alloc and used slots did not match */ 4777 if (cmd.set_mst_alloc_slots.mst_slots_control.immed_status == 3) { 4778 *mst_slots_in_use = cmd.set_mst_alloc_slots.mst_slots_control.mst_slots_in_use; 4779 return DC_NOT_SUPPORTED; 4780 } 4781 4782 return DC_OK; 4783 } 4784 4785 /** 4786 ***************************************************************************** 4787 * Function: dc_process_dmub_dpia_hpd_int_enable 4788 * 4789 * @brief 4790 * Submits dpia hpd int enable command to dmub via inbox message 4791 * 4792 * @param 4793 * [in] dc: dc structure 4794 * [in] hpd_int_enable: 1 for hpd int enable, 0 to disable 4795 * 4796 * @return 4797 * None 4798 ***************************************************************************** 4799 */ 4800 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 4801 uint32_t hpd_int_enable) 4802 { 4803 union dmub_rb_cmd cmd = {0}; 4804 struct dc_dmub_srv *dmub_srv = dc->ctx->dmub_srv; 4805 4806 cmd.dpia_hpd_int_enable.header.type = DMUB_CMD__DPIA_HPD_INT_ENABLE; 4807 cmd.dpia_hpd_int_enable.enable = hpd_int_enable; 4808 4809 dc_dmub_srv_cmd_queue(dmub_srv, &cmd); 4810 dc_dmub_srv_cmd_execute(dmub_srv); 4811 dc_dmub_srv_wait_idle(dmub_srv); 4812 4813 DC_LOG_DEBUG("%s: hpd_int_enable(%d)\n", __func__, hpd_int_enable); 4814 } 4815 4816 /** 4817 * dc_disable_accelerated_mode - disable accelerated mode 4818 * @dc: dc structure 4819 */ 4820 void dc_disable_accelerated_mode(struct dc *dc) 4821 { 4822 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 0); 4823 } 4824 4825 4826 /** 4827 ***************************************************************************** 4828 * dc_notify_vsync_int_state() - notifies vsync enable/disable state 4829 * @dc: dc structure 4830 * @stream: stream where vsync int state changed 4831 * @enable: whether vsync is enabled or disabled 4832 * 4833 * Called when vsync is enabled/disabled 4834 * Will notify DMUB to start/stop ABM interrupts after steady state is reached 4835 * 4836 ***************************************************************************** 4837 */ 4838 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable) 4839 { 4840 int i; 4841 int edp_num; 4842 struct pipe_ctx *pipe = NULL; 4843 struct dc_link *link = stream->sink->link; 4844 struct dc_link *edp_links[MAX_NUM_EDP]; 4845 4846 4847 if (link->psr_settings.psr_feature_enabled) 4848 return; 4849 4850 /*find primary pipe associated with stream*/ 4851 for (i = 0; i < MAX_PIPES; i++) { 4852 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 4853 4854 if (pipe->stream == stream && pipe->stream_res.tg) 4855 break; 4856 } 4857 4858 if (i == MAX_PIPES) { 4859 ASSERT(0); 4860 return; 4861 } 4862 4863 get_edp_links(dc, edp_links, &edp_num); 4864 4865 /* Determine panel inst */ 4866 for (i = 0; i < edp_num; i++) { 4867 if (edp_links[i] == link) 4868 break; 4869 } 4870 4871 if (i == edp_num) { 4872 return; 4873 } 4874 4875 if (pipe->stream_res.abm && pipe->stream_res.abm->funcs->set_abm_pause) 4876 pipe->stream_res.abm->funcs->set_abm_pause(pipe->stream_res.abm, !enable, i, pipe->stream_res.tg->inst); 4877 } 4878 /* 4879 * dc_extended_blank_supported: Decide whether extended blank is supported 4880 * 4881 * Extended blank is a freesync optimization feature to be enabled in the future. 4882 * During the extra vblank period gained from freesync, we have the ability to enter z9/z10. 4883 * 4884 * @param [in] dc: Current DC state 4885 * @return: Indicate whether extended blank is supported (true or false) 4886 */ 4887 bool dc_extended_blank_supported(struct dc *dc) 4888 { 4889 return dc->debug.extended_blank_optimization && !dc->debug.disable_z10 4890 && dc->caps.zstate_support && dc->caps.is_apu; 4891 } 4892