1fb4d8502Sjsg /* 2fb4d8502Sjsg * Copyright 2012-16 Advanced Micro Devices, Inc. 3fb4d8502Sjsg * 4fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"), 6fb4d8502Sjsg * to deal in the Software without restriction, including without limitation 7fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions: 10fb4d8502Sjsg * 11fb4d8502Sjsg * The above copyright notice and this permission notice shall be included in 12fb4d8502Sjsg * all copies or substantial portions of the Software. 13fb4d8502Sjsg * 14fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15fb4d8502Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18fb4d8502Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19fb4d8502Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20fb4d8502Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21fb4d8502Sjsg * 22fb4d8502Sjsg * Authors: AMD 23fb4d8502Sjsg * 24fb4d8502Sjsg */ 25fb4d8502Sjsg 26fb4d8502Sjsg 27fb4d8502Sjsg #ifndef _DCE_ABM_H_ 28fb4d8502Sjsg #define _DCE_ABM_H_ 29fb4d8502Sjsg 30fb4d8502Sjsg #include "abm.h" 31fb4d8502Sjsg 32fb4d8502Sjsg #define ABM_COMMON_REG_LIST_DCE_BASE() \ 33fb4d8502Sjsg SR(MASTER_COMM_CNTL_REG), \ 34fb4d8502Sjsg SR(MASTER_COMM_CMD_REG), \ 35fb4d8502Sjsg SR(MASTER_COMM_DATA_REG1) 36fb4d8502Sjsg 37fb4d8502Sjsg #define ABM_DCE110_COMMON_REG_LIST() \ 38fb4d8502Sjsg ABM_COMMON_REG_LIST_DCE_BASE(), \ 39fb4d8502Sjsg SR(DC_ABM1_HG_SAMPLE_RATE), \ 40fb4d8502Sjsg SR(DC_ABM1_LS_SAMPLE_RATE), \ 41fb4d8502Sjsg SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \ 42fb4d8502Sjsg SR(DC_ABM1_HG_MISC_CTRL), \ 43fb4d8502Sjsg SR(DC_ABM1_IPCSC_COEFF_SEL), \ 44fb4d8502Sjsg SR(BL1_PWM_CURRENT_ABM_LEVEL), \ 45fb4d8502Sjsg SR(BL1_PWM_TARGET_ABM_LEVEL), \ 46fb4d8502Sjsg SR(BL1_PWM_USER_LEVEL), \ 47fb4d8502Sjsg SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \ 48fb4d8502Sjsg SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \ 49ad8b1aafSjsg SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \ 50ad8b1aafSjsg SR(DC_ABM1_ACE_THRES_12), \ 51fb4d8502Sjsg SR(BIOS_SCRATCH_2) 52fb4d8502Sjsg 53fb4d8502Sjsg #define ABM_DCN10_REG_LIST(id)\ 54fb4d8502Sjsg ABM_COMMON_REG_LIST_DCE_BASE(), \ 55fb4d8502Sjsg SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ 56fb4d8502Sjsg SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ 57fb4d8502Sjsg SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ 58fb4d8502Sjsg SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \ 59fb4d8502Sjsg SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ 60fb4d8502Sjsg SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ 61fb4d8502Sjsg SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ 62fb4d8502Sjsg SRI(BL1_PWM_USER_LEVEL, ABM, id), \ 63fb4d8502Sjsg SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ 64fb4d8502Sjsg SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ 65ad8b1aafSjsg SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \ 66ad8b1aafSjsg SRI(DC_ABM1_ACE_THRES_12, ABM, id), \ 67fb4d8502Sjsg NBIO_SR(BIOS_SCRATCH_2) 68fb4d8502Sjsg 69c349dbc7Sjsg #define ABM_DCN20_REG_LIST() \ 70c349dbc7Sjsg ABM_COMMON_REG_LIST_DCE_BASE(), \ 71c349dbc7Sjsg SR(DC_ABM1_HG_SAMPLE_RATE), \ 72c349dbc7Sjsg SR(DC_ABM1_LS_SAMPLE_RATE), \ 73c349dbc7Sjsg SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \ 74c349dbc7Sjsg SR(DC_ABM1_HG_MISC_CTRL), \ 75c349dbc7Sjsg SR(DC_ABM1_IPCSC_COEFF_SEL), \ 76c349dbc7Sjsg SR(BL1_PWM_CURRENT_ABM_LEVEL), \ 77c349dbc7Sjsg SR(BL1_PWM_TARGET_ABM_LEVEL), \ 78c349dbc7Sjsg SR(BL1_PWM_USER_LEVEL), \ 79c349dbc7Sjsg SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \ 80c349dbc7Sjsg SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \ 81ad8b1aafSjsg SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \ 82ad8b1aafSjsg SR(DC_ABM1_ACE_THRES_12), \ 83c349dbc7Sjsg NBIO_SR(BIOS_SCRATCH_2) 84c349dbc7Sjsg 855ca02815Sjsg #define ABM_DCN301_REG_LIST(id)\ 865ca02815Sjsg ABM_COMMON_REG_LIST_DCE_BASE(), \ 875ca02815Sjsg SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ 885ca02815Sjsg SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ 895ca02815Sjsg SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ 905ca02815Sjsg SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \ 915ca02815Sjsg SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ 925ca02815Sjsg SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ 935ca02815Sjsg SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ 945ca02815Sjsg SRI(BL1_PWM_USER_LEVEL, ABM, id), \ 955ca02815Sjsg SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ 965ca02815Sjsg SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ 975ca02815Sjsg NBIO_SR(BIOS_SCRATCH_2) 985ca02815Sjsg 991bb76ff1Sjsg #define ABM_DCN302_REG_LIST(id)\ 1001bb76ff1Sjsg ABM_COMMON_REG_LIST_DCE_BASE(), \ 1011bb76ff1Sjsg SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ 1021bb76ff1Sjsg SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ 1031bb76ff1Sjsg SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ 1041bb76ff1Sjsg SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \ 1051bb76ff1Sjsg SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ 1061bb76ff1Sjsg SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ 1071bb76ff1Sjsg SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ 1081bb76ff1Sjsg SRI(BL1_PWM_USER_LEVEL, ABM, id), \ 1091bb76ff1Sjsg SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ 1101bb76ff1Sjsg SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ 1111bb76ff1Sjsg SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \ 1121bb76ff1Sjsg SRI(DC_ABM1_ACE_THRES_12, ABM, id), \ 1131bb76ff1Sjsg NBIO_SR(BIOS_SCRATCH_2) 1141bb76ff1Sjsg 115ad8b1aafSjsg #define ABM_DCN30_REG_LIST(id)\ 116ad8b1aafSjsg ABM_COMMON_REG_LIST_DCE_BASE(), \ 117ad8b1aafSjsg SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ 118ad8b1aafSjsg SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ 119ad8b1aafSjsg SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ 120ad8b1aafSjsg SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \ 121ad8b1aafSjsg SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ 122ad8b1aafSjsg SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ 123ad8b1aafSjsg SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ 124ad8b1aafSjsg SRI(BL1_PWM_USER_LEVEL, ABM, id), \ 125ad8b1aafSjsg SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ 126ad8b1aafSjsg SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ 127ad8b1aafSjsg SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \ 128ad8b1aafSjsg SRI(DC_ABM1_ACE_THRES_12, ABM, id), \ 129ad8b1aafSjsg NBIO_SR(BIOS_SCRATCH_2) 130ad8b1aafSjsg 1311bb76ff1Sjsg #define ABM_DCN32_REG_LIST(id)\ 1321bb76ff1Sjsg SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ 1331bb76ff1Sjsg SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ 1341bb76ff1Sjsg SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ 1351bb76ff1Sjsg SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \ 1361bb76ff1Sjsg SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ 1371bb76ff1Sjsg SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ 1381bb76ff1Sjsg SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ 1391bb76ff1Sjsg SRI(BL1_PWM_USER_LEVEL, ABM, id), \ 1401bb76ff1Sjsg SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ 1411bb76ff1Sjsg SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ 1421bb76ff1Sjsg SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \ 1431bb76ff1Sjsg SRI(DC_ABM1_ACE_THRES_12, ABM, id), \ 1441bb76ff1Sjsg NBIO_SR(BIOS_SCRATCH_2) 1451bb76ff1Sjsg 146fb4d8502Sjsg #define ABM_SF(reg_name, field_name, post_fix)\ 147fb4d8502Sjsg .field_name = reg_name ## __ ## field_name ## post_fix 148fb4d8502Sjsg 149fb4d8502Sjsg #define ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ 150fb4d8502Sjsg ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ 151fb4d8502Sjsg ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ 152fb4d8502Sjsg ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \ 153fb4d8502Sjsg ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh) 154fb4d8502Sjsg 155fb4d8502Sjsg #define ABM_MASK_SH_LIST_DCE110(mask_sh) \ 156fb4d8502Sjsg ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ 157fb4d8502Sjsg ABM_SF(DC_ABM1_HG_MISC_CTRL, \ 158fb4d8502Sjsg ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ 159fb4d8502Sjsg ABM_SF(DC_ABM1_HG_MISC_CTRL, \ 160fb4d8502Sjsg ABM1_HG_VMAX_SEL, mask_sh), \ 161fb4d8502Sjsg ABM_SF(DC_ABM1_HG_MISC_CTRL, \ 162fb4d8502Sjsg ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ 163fb4d8502Sjsg ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \ 164fb4d8502Sjsg ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ 165fb4d8502Sjsg ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \ 166fb4d8502Sjsg ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ 167fb4d8502Sjsg ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \ 168fb4d8502Sjsg ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ 169fb4d8502Sjsg ABM_SF(BL1_PWM_CURRENT_ABM_LEVEL, \ 170fb4d8502Sjsg BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ 171fb4d8502Sjsg ABM_SF(BL1_PWM_TARGET_ABM_LEVEL, \ 172fb4d8502Sjsg BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ 173fb4d8502Sjsg ABM_SF(BL1_PWM_USER_LEVEL, \ 174fb4d8502Sjsg BL1_PWM_USER_LEVEL, mask_sh), \ 175fb4d8502Sjsg ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ 176fb4d8502Sjsg ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ 177fb4d8502Sjsg ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ 178fb4d8502Sjsg ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ 179fb4d8502Sjsg ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ 180fb4d8502Sjsg ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ 181fb4d8502Sjsg ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ 182fb4d8502Sjsg ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ 183fb4d8502Sjsg ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ 184fb4d8502Sjsg ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) 185fb4d8502Sjsg 186fb4d8502Sjsg #define ABM_MASK_SH_LIST_DCN10(mask_sh) \ 187fb4d8502Sjsg ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ 188fb4d8502Sjsg ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ 189fb4d8502Sjsg ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ 190fb4d8502Sjsg ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ 191fb4d8502Sjsg ABM1_HG_VMAX_SEL, mask_sh), \ 192fb4d8502Sjsg ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ 193fb4d8502Sjsg ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ 194fb4d8502Sjsg ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ 195fb4d8502Sjsg ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ 196fb4d8502Sjsg ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ 197fb4d8502Sjsg ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ 198fb4d8502Sjsg ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ 199fb4d8502Sjsg ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ 200fb4d8502Sjsg ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \ 201fb4d8502Sjsg BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ 202fb4d8502Sjsg ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \ 203fb4d8502Sjsg BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ 204fb4d8502Sjsg ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \ 205fb4d8502Sjsg BL1_PWM_USER_LEVEL, mask_sh), \ 206fb4d8502Sjsg ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ 207fb4d8502Sjsg ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ 208fb4d8502Sjsg ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ 209fb4d8502Sjsg ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ 210fb4d8502Sjsg ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ 211fb4d8502Sjsg ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ 212fb4d8502Sjsg ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ 213fb4d8502Sjsg ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ 214fb4d8502Sjsg ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ 215fb4d8502Sjsg ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) 216fb4d8502Sjsg 217c349dbc7Sjsg #define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh) 218c349dbc7Sjsg 2195ca02815Sjsg #define ABM_MASK_SH_LIST_DCN30(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh) 220ad8b1aafSjsg 2211bb76ff1Sjsg #define ABM_MASK_SH_LIST_DCN32(mask_sh) \ 2221bb76ff1Sjsg ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ 2231bb76ff1Sjsg ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ 2241bb76ff1Sjsg ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ 2251bb76ff1Sjsg ABM1_HG_VMAX_SEL, mask_sh), \ 2261bb76ff1Sjsg ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ 2271bb76ff1Sjsg ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ 2281bb76ff1Sjsg ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ 2291bb76ff1Sjsg ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ 2301bb76ff1Sjsg ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ 2311bb76ff1Sjsg ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ 2321bb76ff1Sjsg ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ 2331bb76ff1Sjsg ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ 2341bb76ff1Sjsg ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \ 2351bb76ff1Sjsg BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ 2361bb76ff1Sjsg ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \ 2371bb76ff1Sjsg BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ 2381bb76ff1Sjsg ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \ 2391bb76ff1Sjsg BL1_PWM_USER_LEVEL, mask_sh), \ 2401bb76ff1Sjsg ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ 2411bb76ff1Sjsg ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ 2421bb76ff1Sjsg ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ 2431bb76ff1Sjsg ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ 2441bb76ff1Sjsg ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ 2451bb76ff1Sjsg ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ 2461bb76ff1Sjsg ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ 2471bb76ff1Sjsg ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ 2481bb76ff1Sjsg ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ 2491bb76ff1Sjsg ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) 2501bb76ff1Sjsg 251fb4d8502Sjsg #define ABM_REG_FIELD_LIST(type) \ 252fb4d8502Sjsg type ABM1_HG_NUM_OF_BINS_SEL; \ 253fb4d8502Sjsg type ABM1_HG_VMAX_SEL; \ 254fb4d8502Sjsg type ABM1_HG_BIN_BITWIDTH_SIZE_SEL; \ 255fb4d8502Sjsg type ABM1_IPCSC_COEFF_SEL_R; \ 256fb4d8502Sjsg type ABM1_IPCSC_COEFF_SEL_G; \ 257fb4d8502Sjsg type ABM1_IPCSC_COEFF_SEL_B; \ 258fb4d8502Sjsg type BL1_PWM_CURRENT_ABM_LEVEL; \ 259fb4d8502Sjsg type BL1_PWM_TARGET_ABM_LEVEL; \ 260fb4d8502Sjsg type BL1_PWM_USER_LEVEL; \ 261fb4d8502Sjsg type ABM1_LS_MIN_PIXEL_VALUE_THRES; \ 262fb4d8502Sjsg type ABM1_LS_MAX_PIXEL_VALUE_THRES; \ 263fb4d8502Sjsg type ABM1_HG_REG_READ_MISSED_FRAME_CLEAR; \ 264fb4d8502Sjsg type ABM1_LS_REG_READ_MISSED_FRAME_CLEAR; \ 265fb4d8502Sjsg type ABM1_BL_REG_READ_MISSED_FRAME_CLEAR; \ 266fb4d8502Sjsg type MASTER_COMM_INTERRUPT; \ 267fb4d8502Sjsg type MASTER_COMM_CMD_REG_BYTE0; \ 268fb4d8502Sjsg type MASTER_COMM_CMD_REG_BYTE1; \ 269*f005ef32Sjsg type MASTER_COMM_CMD_REG_BYTE2; \ 270*f005ef32Sjsg type ABM1_HG_BIN_33_40_SHIFT_INDEX; \ 271*f005ef32Sjsg type ABM1_HG_BIN_33_64_SHIFT_FLAG; \ 272*f005ef32Sjsg type ABM1_HG_BIN_41_48_SHIFT_INDEX; \ 273*f005ef32Sjsg type ABM1_HG_BIN_49_56_SHIFT_INDEX; \ 274*f005ef32Sjsg type ABM1_HG_BIN_57_64_SHIFT_INDEX; \ 275*f005ef32Sjsg type ABM1_HG_RESULT_DATA; \ 276*f005ef32Sjsg type ABM1_HG_RESULT_INDEX; \ 277*f005ef32Sjsg type ABM1_ACE_SLOPE_DATA; \ 278*f005ef32Sjsg type ABM1_ACE_OFFSET_DATA; \ 279*f005ef32Sjsg type ABM1_ACE_OFFSET_SLOPE_INDEX; \ 280*f005ef32Sjsg type ABM1_ACE_THRES_INDEX; \ 281*f005ef32Sjsg type ABM1_ACE_IGNORE_MASTER_LOCK_EN; \ 282*f005ef32Sjsg type ABM1_ACE_READBACK_DB_REG_VALUE_EN; \ 283*f005ef32Sjsg type ABM1_ACE_DBUF_REG_UPDATE_PENDING; \ 284*f005ef32Sjsg type ABM1_ACE_LOCK; \ 285*f005ef32Sjsg type ABM1_ACE_THRES_DATA_1; \ 286*f005ef32Sjsg type ABM1_ACE_THRES_DATA_2 287fb4d8502Sjsg 288fb4d8502Sjsg struct dce_abm_shift { 289fb4d8502Sjsg ABM_REG_FIELD_LIST(uint8_t); 290fb4d8502Sjsg }; 291fb4d8502Sjsg 292fb4d8502Sjsg struct dce_abm_mask { 293fb4d8502Sjsg ABM_REG_FIELD_LIST(uint32_t); 294fb4d8502Sjsg }; 295fb4d8502Sjsg 296fb4d8502Sjsg struct dce_abm_registers { 297fb4d8502Sjsg uint32_t DC_ABM1_HG_SAMPLE_RATE; 298fb4d8502Sjsg uint32_t DC_ABM1_LS_SAMPLE_RATE; 299fb4d8502Sjsg uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE; 300fb4d8502Sjsg uint32_t DC_ABM1_HG_MISC_CTRL; 301fb4d8502Sjsg uint32_t DC_ABM1_IPCSC_COEFF_SEL; 302fb4d8502Sjsg uint32_t BL1_PWM_CURRENT_ABM_LEVEL; 303fb4d8502Sjsg uint32_t BL1_PWM_TARGET_ABM_LEVEL; 304fb4d8502Sjsg uint32_t BL1_PWM_USER_LEVEL; 305fb4d8502Sjsg uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES; 306fb4d8502Sjsg uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS; 307ad8b1aafSjsg uint32_t DC_ABM1_ACE_OFFSET_SLOPE_0; 308*f005ef32Sjsg uint32_t DC_ABM1_ACE_OFFSET_SLOPE_DATA; 309*f005ef32Sjsg uint32_t DC_ABM1_ACE_PWL_CNTL; 310*f005ef32Sjsg uint32_t DC_ABM1_HG_BIN_33_40_SHIFT_INDEX; 311*f005ef32Sjsg uint32_t DC_ABM1_HG_BIN_33_64_SHIFT_FLAG; 312*f005ef32Sjsg uint32_t DC_ABM1_HG_BIN_41_48_SHIFT_INDEX; 313*f005ef32Sjsg uint32_t DC_ABM1_HG_BIN_49_56_SHIFT_INDEX; 314*f005ef32Sjsg uint32_t DC_ABM1_HG_BIN_57_64_SHIFT_INDEX; 315*f005ef32Sjsg uint32_t DC_ABM1_HG_RESULT_DATA; 316*f005ef32Sjsg uint32_t DC_ABM1_HG_RESULT_INDEX; 317*f005ef32Sjsg uint32_t DC_ABM1_ACE_THRES_DATA; 318ad8b1aafSjsg uint32_t DC_ABM1_ACE_THRES_12; 319fb4d8502Sjsg uint32_t MASTER_COMM_CNTL_REG; 320fb4d8502Sjsg uint32_t MASTER_COMM_CMD_REG; 321fb4d8502Sjsg uint32_t MASTER_COMM_DATA_REG1; 322fb4d8502Sjsg uint32_t BIOS_SCRATCH_2; 323fb4d8502Sjsg }; 324fb4d8502Sjsg 325fb4d8502Sjsg struct dce_abm { 326fb4d8502Sjsg struct abm base; 327fb4d8502Sjsg const struct dce_abm_registers *regs; 328fb4d8502Sjsg const struct dce_abm_shift *abm_shift; 329fb4d8502Sjsg const struct dce_abm_mask *abm_mask; 330fb4d8502Sjsg }; 331fb4d8502Sjsg 332fb4d8502Sjsg struct abm *dce_abm_create( 333fb4d8502Sjsg struct dc_context *ctx, 334fb4d8502Sjsg const struct dce_abm_registers *regs, 335fb4d8502Sjsg const struct dce_abm_shift *abm_shift, 336fb4d8502Sjsg const struct dce_abm_mask *abm_mask); 337fb4d8502Sjsg 338fb4d8502Sjsg void dce_abm_destroy(struct abm **abm); 339fb4d8502Sjsg 340fb4d8502Sjsg #endif /* _DCE_ABM_H_ */ 341